SY89112U 2.5/3.3V Low-Jitter, Low-Skew 1:12 LVPECL Fanout Buffer with 2:1 Input MUX and Internal Termination General Description The SY89112U is a low-jitter, low-skew, high-speed LVPECL 1:12 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. The input includes a 2:1 MUX for clock switchover application. Unlike other multiplexers, this input includes a unique isolation design to minimize channel-tochannel crosstalk. The SY89112U distributes clock frequencies from DC to >2GHz guaranteed over temperature and voltage. The SY89112U incorporates a synchronous output enable (EN) so that the outputs will only be enabled/disabled when they are already in the LOW state. This reduces the chance of generating “runt” clock pulses. The SY89112U differential input includes Micrel’s unique, patent-pending 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DCcoupled) as small as 100mV (200mVpp) without any level shifting or termination resistor networks in the signal path. For AC-coupled input interface, an on-board output reference voltage (VREF-AC) is provided to bias the center-tap (VT) pin. The outputs are 800mV, 100Kcompatible LVPECL with fast rise/fall times guaranteed to be less than 220ps. The SY89112U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of –40°C to +85°C. The SY89112U is part of Micrel’s high-speed, Precision Edge® product line. All support documentation can be found on Micrel’s web site at www.micrel.com. Precision Edge Features • Selects between 1 of 2 inputs, and provides 12 precision, low skew LVPECL output copies • Guaranteed AC performance over temperature and voltage: – DC to >2GHz throughput – <550ps propagation delay CLK-to-Q – <220ps rise/fall time – <25ps output-to-output skew • Ultra-low jitter design: – 109fsRMS phase jitter (typ.) – <0.7psRMS crosstalk induced jitter • Unique, patent-pending input termination and VT pin accepts DC-coupled and AC-coupled differential inputs • Unique, patent-pending 2:1 input MUX provides superior isolation to minimize channel-to-channel crosstalk • 800mV, 100K LVPECL output swing • Power supply 2.5V +5% or 3.3V +10% • Industrial temperature range –40°C to +85°C • Available in 44-pin (7mm x 7mm) QFN package Applications • • • • Multi-processor server SONET/SDH clock/data distribution Fibre Channel distribution Gigabit Ethernet clock distribution Precision Edge is a registered trademark of Micrel, Inc Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com March 2011 M9999-030211-E [email protected] or (408) 955-1690 ® Micrel, Inc. SY89112U Functional Block Diagram March 2011 2 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish QFN-44 Industrial SY89112U Sn-Pb QFN-44 Industrial SY89112U Sn-Pb Matte-Sn Pb-Free Matte-Sn Pb-Free SY89112UMI (2) SY89112UMITR SY89112UMY QFN-44 Industrial SY89112U with Pb-Free bar-line indicator SY89112UMYTR(2) QFN-44 Industrial SY89112U with Pb-Free bar-line indicator Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. Pin Configuration 44-Pin QFN March 2011 3 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Pin Description Pin Number Pin Name Pin Function 2, 5 7, 10 CLK0, /CLK0 CLK1, /CLK1 Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50Ω. Note that these inputs will default to an indeterminate state if left open. Please refer to the “Input Interface Applications” section for more details. 3, 8 VT0, VT1 Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details. 4, 9 VREF-AC0 VREF-AC1 Reference Voltage: These outputs bias to VCC–1.2V. They are used when AC coupling the inputs (CLK, /CLK). For AC-coupled applications, connect VREF-AC to the VT pin and bypass with a 0.01μF low ESR capacitor to VCC. See “Input Interface Applications” section for more details. Maximum sink/source current is ±1.5mA. Due to the limited drive capability, each VREF-AC pin is only intended to drive its respective VT pin. 44 CLK_SEL This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to a logic HIGH state if left open. This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. Note that this input is internally connected to a 25kΩ pull-up resistor and will default to logic HIGH state (enabled) if left open. 12 EN 13,22,23,28, 33,34,43 VCC 42, 41 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 15, 14 Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 Q6, /Q6 Q7, /Q7 Q8, /Q8 Q9, /Q9 Q10, /Q10 Q11, /Q11 Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies of the inputs. Please refer to the truth table below for details. Unused output pairs may be left open. Terminate with 50Ω to VCC–2V. See “LVPECL Output Interface Applications” section for more details. 1, 6, 11 GND, Exposed Pad Ground. GND pins and exposed pad must both be connected to the most negative potential of chip the ground. Positive power supply. Bypass with 0.1μF//0.01μF low ESR capacitors and place as close to each VCC pin as possible. Truth Table EN CLK_SEL Q /Q H L CLK0 /CLK0 H H CLK1 /CLK1 L X L(1) H(1) Notes: 1. Transition occurs on next negative transition of the non-inverted input. March 2011 4 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Absolute Maximum Ratings(1) Operating Rating(2) Supply Voltage (VCC).................................... −0.5V to +4.0V Input Voltage (VIN) .......................................... −0.5V to VCC LVPECL Output Current (IOUT) Continuous............................................................50mA Surge ..................................................................100mA Termination Current Source or sink current on VT............................±100mA Input Current Source or sink current on CLK, /CLK .................±50mA VREF-AC Current Source or sink current...........................................±2mA Lead Temperature (soldering, 20sec)...................... +260°C Storage Temperature (TS) ........................ −65°C to +150°C Supply Voltage (VCC)......................... +2.375V to +2.625V +3.0V to +3.6V Ambient Temperature (TA)....................... −40°C to +85°C Package Thermal Resistance(3) QFN (θJA) Still-Air......................................................42°C/W QFN (ψJB) Junction-to-Board ....................................20°C/W DC Electrical Characteristics(4) TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter Condition Min. Typ. VCC Power Supply ICC Power Supply Current RIN Input Resistance (IN-to-VT) 45 50 55 Ω RDIFF_IN Differential Input Resistance (IN-to-/IN) 90 100 110 Ω VIH Input High Voltage (IN, /IN) 1.2 VCC V 2.375 3.0 No load, max. VCC 95 Max. Units 2.625 3.6 V V 130 mA VIL Input Low Voltage (IN, /IN) 0 VIH –0.1 V VIN Input Voltage Swing (IN, /IN) See Figure 1a. 0.1 1.7 V VDIFF_IN Differential Input Voltage Swing |IN–/IN| See Figure 1b. 0.2 VT_IN IN-to-VT (IN, /IN) VREF-AC Output Reference Voltage VCC – 1.3 V VCC – 1.2 1.28 V VCC–1.1 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. θJA and ΨJB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. March 2011 5 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U LVPECL Outputs DC Electrical Characteristics(5) VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to +85°C; RL = 50Ω to VCC – 2V, unless otherwise stated. Symbol Parameter Condition Min. Typ. VOH Output HIGH Voltage (Q, /Q) VOL Output LOW Voltage (Q, /Q) VOUT Output Voltage Swing (Q, /Q) See Figure 1a 550 800 mV VDIFF-OUT Differential Output Voltage Swing (Q, /Q) See Figure 1b 1100 1600 mV Min. Typ. VCC – 1.145 VCC – 1.945 Max. Units VCC – 0.895 V VCC – 1.695 V LVTTL/CMOS DC Electrical Characteristics(5) VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to +85°C, unless otherwise stated. Symbol Parameter VIH Input HIGH Voltage Condition 2.0 VIL Input LOW Voltage IIH Input HIGH Current –125 IIL Input LOW Current –300 Max. Units VCC V 0.8 V 30 µA µA Note: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. March 2011 6 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U AC Electrical Characteristics(6) VCC = +2.5V ±5% or +3.3V ±10%; TA = –40°C to + 85°C, RL = 50Ω to VCC – 2V, unless otherwise stated. Symbol Parameter Condition fMAX Maximum Operating Frequency VOUT ≥ 400mV tPD Propagation Delay CLK to Q Propagation Delay CLK_SEL to Q VIN ≥ 100mV Min. Typ. Max. Units 2 3 300 400 550 ps 200 350 600 ps GHz tPD Tempco Differential Propagation Delay Temperature Coefficient tS Set-up Time EN-to-CLK Note 7 0 ps tH Hold Time CLK-to-EN Note 7 500 ps tSKEW tJITTER tr, tf fs/oC 150 Output-to-Output Skew Note 8 25 Part-to-Part Skew Note 9 200 RMS Phase Jitter Output = 622MHz, Integration Range: 12kHz − 20MHz Adjacent Channel Crosstalk-induced Jitter Note 10 Output Rise/Fall Time (20% to 80%) At full output swing. 109 70 140 ps fsRMS 0.7 ps(rms) 220 ps Notes: 6. High-frequency AC-parameters are guaranteed by design and characterization. 7. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply. 8. Output-to-output skew is measured between two different outputs under identical input transitions. 9. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. Crosstalk is measured at the output while applying two similar differential clock frequencies that are asynchronous with respect to each other at the inputs. March 2011 7 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Phase Noise Characteristics VCC = +3.3V, GND = 0, VIN = 100mV, RL = 50Ω to VCC–2V, TA = 25°C, unless otherwise stated. March 2011 8 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Operating Characteristics VCC = +3.3V, GND = 0, VIN = 100mV, RL = 50Ω to VCC–2V, TA = 25°C, unless otherwise stated. March 2011 9 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Functional Characteristics VCC = +3.3V, GND = 0, VIN = 100mV, RL = 50Ω to VCC–2V, TA = 25°C, unless otherwise stated. March 2011 10 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Single-Ended and Differential Swings Figure 1a. Single-Ended Voltage Swing Figure 1b. Differential Voltage Swing Timing Diagrams tPD − Differential In-to-Differential Out tPD − CLK_SEL-to-Differential Out tPD − Set-Up and Hold Time EN-to-Differential Out March 2011 11 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Input and Output Stages Figure 2a. Simplified Differential Input Stage Figure 2b. Simplified LVPECL Output Stage Input Interface Applications Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface March 2011 12 Figure 3c. CML Interface (DC-Coupled) M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Parallel Termination-Thevenin Equivalent, Parallel Termination (3-Resistor), and AC-Coupled Termination. Unused output pairs may be left floating. However, singleended outputs must be terminated or balanced. LVPECL Output Interface Applications LVPECL has high-input impedance, very-low output (open emitter) impedance, and small signal swing, which result in low EMI. LVPECL is ideal for driving 50Ω and 100Ω controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Figure 4a. Parallel Thevenin-Equivalent Termination Figure 4b. Parallel Termination (3-Resistor) Related Product and Support Documentation Part Number Function Datasheet Link SY89113U 2.5V/3.3V Low-Jitter, Low-Skew, 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination www.micrel.com/product-info/products/sy89113u.shtml HBW Solutions New Products and Applications www.micrel.com/product-info/products/solutions.shtml March 2011 13 M9999-030211-E [email protected] or (408) 955-1690 Micrel, Inc. SY89112U Package Information 44-Pin QFN MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. March 2011 14 M9999-030211-E [email protected] or (408) 955-1690