ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS87421I is a high perfor mance ÷1/÷2 ICS Differential-to-LVDS Clock Generator and a memHiPerClockS™ ber of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The ICS87421I is characterized to operate from a 3.3V power supply. Guaranteed part-to-part skew characteristics make the ICS87421I ideal for those clock distribution applications demanding well defined performance and repeatability. • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS levels with resistor bias on nCLK input • Part-to-part skew: 500ps (maximum) • Propagation delay: 1.7ns (maximum) • Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical) • Full 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT ÷1 0 R ÷2 1 CLK nCLK MR F_SEL Q nQ 8 7 6 5 VDD Q nQ GND ICS87421I MR 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View F_SEL IDT ™ / ICS™ LVDS CLOCK GENERATOR 1 2 3 4 1 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 CLK Input Pulldown Non-inver ting differential clock input. 2 nCLK Input 3 MR Input 4 F_SEL Input Inver ting differential clock input. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true output (Q) to go low and the inver ted output Pulldown (nQ) to go high. When logic LOW, the internal dividers and the output are enabled. LVCMOS / LVTTL interface levels. See Table 3. Selects divider value for Q, nQ outputs as described in Table 3. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. Pullup 5 GND Power 6, 7 Q, nQ Output Differential output pair. LVDS interface levels. 8 VDD Power Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ TABLE 3. FUNCTION TABLE MR F_SEL Divide Value 1 X Reset: Q output low, nQ output high 0 0 ÷1 0 1 ÷2 CLK MR Q FIGURE 1A. ÷1 CONFIGURATION TIMING DIAGRAM FIGURE 1B. ÷2 CONFIGURATION TIMING DIAGRAM IDT ™ / ICS™ LVDS CLOCK GENERATOR 2 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO Continuous Current Surge Current 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 96°C/W (0 mps) -65°C to 150°C Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 55 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Test Conditions Minimum Input High Voltage Typical 1.37 VIL Input Low Voltage IIH Input High Current MR, F_SEL VDD = VIN = 3.465V -0.3 IIL Input Low Current MR, F_SEL VDD = 3.465V, VIN = 0V Maximum Units VDD + 0.3 V 0.7 V 15 0 µA -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter IIH Input High Current IIL Input Low Current Test Conditions CLK Minimum VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V CLK VDD = 3.465V, VIN = 0V -5 nCLK VDD= 3.465V, VIN = 0V -150 Peak-to-Peak Input Voltage Common Mode Input Voltage; VCMR NOTE 1 NOTE 1: Common mode voltage is defined as VIH. VPP IDT ™ / ICS™ LVDS CLOCK GENERATOR 3 Typical Maximum Units 150 µA 5 µA µA µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Δ VOS VOS Magnitude Change Test Conditions Minimum Typical Maximum Units 350 470 540 mV 50 mV 1.1 1.25 1.4 V 50 mV Maximum Units 1 GHz 1.7 ns 500 ps TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter fCLK Clock Input Frequency Propagation Delay; CLK to Q (Dif) NOTE 1 Par t-to-Par t Skew; NOTE 2, 3 Additive Phase Noise, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time tPD t sk(pp) t JIT t R / tF Test Conditions Minimum Typical 1.0 155.52MHz, Integration Range: 12kHz – 20MHz 20% to 80% 0.17 150 odc Output Duty Cycle fIN < 500MHz 43 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ LVDS CLOCK GENERATOR 4 ps 500 ps 57 % ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz SSB PHASE NOISE dBc/HZ Additive Phase Jitter @ 155.52MHz (12kHz to 20MHz) = 0.17ps typical OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDT ™ / ICS™ LVDS CLOCK GENERATOR meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 5 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION VDD 3.3V SCOPE 3.3V±5% POWER SUPPLY + Float GND – nCLK Qx VDD V V Cross Points PP LVDS CMR CLK nQx GND DIFFERENTIAL INPUT LEVEL 3.3V OUTPUT LOAD AC TEST CIRCUIT PART 1 nQx nCLK CLK Qx PART 2 nQy nQ Q Qy tPD tsk(pp) PART-TO-PART SKEW PROPAGATION DELAY nQ 80% 80% Q VSW I N G Clock Outputs t PW t 20% 20% tR tF odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME VDD VDD out ➤ DC Input ➤ DC Input LVDS 100 LVDS ➤ out VOD/Δ VOD ➤ out ➤ out VOS/Δ VOS ➤ OFFSET VOLTAGE SETUP DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVDS CLOCK GENERATOR 6 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ LVDS CLOCK GENERATOR 7 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER IDT ™ / ICS™ LVDS CLOCK GENERATOR 8 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR LVDS DRIVER TERMINATION input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. A general LVDS interface is shown in Figure 4. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver 3.3V 50Ω 3.3V LVDS Driver + R1 100Ω – 50Ω 100Ω Differential Transmission Line FIGURE 4. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ LVDS CLOCK GENERATOR 9 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS87421I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS87421I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power_MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 198.58mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 96°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.199W * 96°C/W = 104.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 8-PIN SOIC, FORCED CONVECTION θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS CLOCK GENERATOR 96°C/W 10 1 87°C/W 2.5 82°C/W ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 96°C/W 1 87°C/W 2.5 82°C/W TRANSISTOR COUNT The transistor count for ICS87421I is: 417 IDT ™ / ICS™ LVDS CLOCK GENERATOR 11 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e 4.00 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 IDT ™ / ICS™ LVDS CLOCK GENERATOR 12 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS87421AMI 87421AMI 8 lead SOIC tube -40°C to 85°C ICS87421AMI 87421AMI 8 lead SOIC 2500 tape & reel -40°C to 85°C ICS87421AMILF 87421AIL 8 lead "Lead-Free" SOIC tube -40°C to 85°C ICS87421AMIFT 87421AIL 8 lead "Lead-Free" SOIC 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS CLOCK GENERATOR 13 ICS87421AMI REV. A OCTOBER 3, 2007 ICS87421I ÷1/÷2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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