THC63LVDR84C

THC63LVDR84C_Rev.1.03E
THC63LVDR84C
24bit COLOR LVDS RECEIVER (Rising Edge Clock)
General Description
Features
The THC63LVDR84C receiver supports wide temperature
range as -40 to +85C, and wide frequency range as 8 to
112MHz.
The THC63FVDR84C converts the four LVDS data streams
back into 24bits of CMOS/TTL data with rising edge clock.
At a transmit clock frequency of 112MHz, 24bits of RGB data
and 4bits of timing and control data (HSYNC, VSYNC, DE,
etc.) are transmitted at an effective rate of 3.1Gbps.
・1:7 LVDS to CMOS De-Serializer
・Operating Temperature Range : -40 to +85C
・No Special Start-up Sequence Required
・Spread Spectrum Clocking Tolerant up to 100kHz Frequency
Modulation and +/-2.5% Deviations
・Dot Clock Range: 8 to 112MHz Suited for VGA, SVGA,
XGA, WXGA, and SXGA
・56pin TSSOP Package
・PLL requires no external components
・Power Down Mode
・Rising Edge Clock
・EU RoHS Compliant
Application
・Medium and Small Size Panel
・Security Camera / Industrial Camera
・Multi Function Printer
・Industrial Equipment
・Medical Equipment Monitor
LVDS TO LVCMOS/TTL
PARALLEL
Block Diagram
Figure 1. Block Diagram
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Pin Diagram
RC3
RD6
RC4
GND
RC5
RC6
RD0
LVDS GND
RARA+
RBRB+
LVDS VCC
LVDS GND
RCRC+
RCLKRCLK+
RDRD+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
GND
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
●
22
23
24
25
26
27
28
VCC
RC2
RC1
RC0
GND
RB6
RD5
RD4
VCC
RB5
RB4
RB3
GND
RB2
RD3
RD2
VCC
RB1
RB0
RA6
GND
RA5
RD1
RA4
RA3
VCC
RA2
RA1
Figure 2. Pin Diagram
Pin Description
Pin Name
RA+, RARB+, RBRC+, RCRD+, RDRCLK+,
RCLKRA0 ~ RA6
RB0 ~ RB6
RC0 ~ RC6
RD0 ~ RD6
CLKOUT
Pin #
10, 9
12, 11
16, 15
20, 19
18, 17
Direction
27, 29, 30, 32, 33, 35, 37
38, 39, 43, 45, 46, 47, 51
53, 54, 55, 1, 3, 5, 6
7, 34, 41, 42, 49, 50, 2
26
Output
/PDWN
25
Input
VCC
31, 40, 48, 56
GND
LVDS VCC
LVDS GND
PLL VCC
PLL GND
4, 28, 36, 44, 52
13
8, 14, 21
23
22, 24
Type
Description
LVDS Data Inputs
Input
LVDS
LVDS Clock Inputs
Pixel Data Outputs
CMOS
/ TTL
Power
-
Pixel Clock Output
H : Normal Operation
L : Power Down (all outputs are pulled to ground)
Power Supply Pins for TTL outputs and digital
circuitry
Ground Pins for TTL outputs and digital circuitry
Power Supply Pins for LVDS inputs
Ground Pins for LVDS inputs
Power Supply Pins for PLL circuitry
Ground Pins for PLL circuitry
Table 1. Pin Description
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Absolute Maximum Ratings
Parameter
Supply Voltage (VCC)
CMOS/TTL Input Voltage
CMOS/TTL Output Voltage
LVDS Input Pin
Junction Temperature
Storage Temperature
Reflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25C
Min
-0.3
-0.3
-0.3
-0.3
-55
-
Max
+4.0
VCC + 0.3
VCC + 0.3
VCC + 0.3
+125
+150
+260
10
1.9
Unit
V
V
V
V
C
C
C
sec
W
Table 2. Absolute Maximum Ratings
Recommended Operating Conditions
Symbol
Ta
-
Parameter
Min
Typ
All Supply Voltage
3.0
Operating Ambient Temperature
-40
+25
Clock Frequency
8
Table 3. Recommended Operating Conditions
Max
3.6
+85
112
Unit
V
C
MHz
“Absolute Maximum Ratings” are those values beyond which the safety of the device can not be guaranteed.
They are not meant to imply that the device should be operated at these limits. The tables of “Electrical
Characteristics Table4, 5, 6, 7” specify conditions for device operation.
“Absolute Maximum Rating” value also includes behavior of overshooting and undershooting.
Equivalent LVDS Input Schematic Diagram
LVDS_InP
AMP
LVDS_InN
Figure 3. LVDS Input Schematic Diagram
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Power Consumption
Over recommended operating supply and temperature range unless otherwise specified
Symbol
Parameter
Conditions
Typ*
Max
Unit
LVDS Receiver
CL=8pF, f=65MHz, VCC=3.3V
55
70
mA
Operating Current
IRCCG
Gray Scale Pattern 16
CL=8pF, f=112MHz, VCC=3.3V
90
110
mA
(Fig.4)
LVDS Receiver
CL=8pF, f=65MHz, VCC=3.3V
90
110
mA
Operating Current
IRCCW
Worst Case Pattern
CL=8pF, f=112MHz, VCC=3.3V
130
160
mA
(Fig.5)
LVDS Receiver
IRCCS
/PDWN=L
500
µA
Power Down Current
*Typ values are at the conditions of Ta = +25ºC
Table 4. Power Consumption
16 Grayscale Pattern
CLKIN
f
TA0, TB1, TC2
f/16
TA1, TB2, TC3
f/8
TA2, TB3, TC4
f/4
TA3, TB4, TC5
f/2
TA4-6, TB0,5,6
TC0,1,6, TD0-2
Steady State Low
TD3-6
Steady State High
Figure 4. 16 Grayscale Pattern
Worst Case Pattern
CLKIN
Tx0-6
x=A,B,C,D
Figure 5. Worst Case Pattern
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Electrical Characteristics
CMOS/TTL DC Specifications
Symbol
VIH
VIL
VOH
VOL
IIN
Over recommended operating supply and temperature range unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Unit
High Level Input Voltage
2.0
VCC
V
Low Level Input Voltage
GND
0.8
V
IOH = -4mA (Data)
High Level Output Voltage
2.4
V
IOH = -8mA (Clock)
IOL = 4mA (Data)
Low Level Output Voltage
0.4
V
IOL = 8mA (Clock)
Input Current
10
A
GND  VIN  VCC
Table 5. CMOS/TTL DC Specifications
LVDS Receiver DC Specifications
Symbol
VTH
VTL
IIN
Over recommended operating supply and temperature range unless otherwise specified
Parameter
Conditions
Min
Typ*
Max
Unit
Differential Input High Threshold
100
mV
RL=100Ω,
VIC=+1.2V
Differential Input Low Threshold
-100
mV
VIN = +2.4 / 0V
Input Current
30
A
VCC = 3.6V
Table 6. LVDS Transmitter DC Specifications
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CMOS/TTL & LVDS Receiver AC Specifications
Over recommended operating supply and temperature range unless otherwise specified
Parameter
Min
Typ*
Max
Unit
CLKOUT Transition Time
8.92
T
125
ns
CLKOUT High Time
T/2
ns
CLKOUT Low Time
T/2
ns
RCLK IN to CLKOUT +/- Delay
(3/14+3)T
ns
CMOS/TTL Data Setup to CLKOUT
0.35T - 0.3
ns
CMOS/TTL Data Hold from CLKOUT
0.45T - 1.6
ns
CMOS/TTL Low to High Transition Time
0.7
1.0
ns
CMOS/TTL High to Low Transition Time
0.7
1.0
ns
f=65MHz
-0.55
0.55
Receiver
ns
Skew Margin f=112MHz
-0.25
0.25
tRIP1
Input Data Position0
- tSK
0.0
+ tSK
ns
tRIP0
Input Data Position1
T/7- tSK
T/7
T/7+ tSK
ns
tRIP6
Input Data Position2
2T/7- tSK
2T/7
2T/7+ tSK
ns
tRIP5
Input Data Position3
3T/7- tSK
3T/7
3T/7+ tSK
ns
tRIP4
Input Data Position4
4T/7- tSK
4T/7
4T/7+ tSK
ns
tRIP3
Input Data Position5
5T/7- tSK
5T/7
5T/7+ tSK
ns
tRIP2
Input Data Position6
6T/7- tSK
6T/7
6T/7+ tSK
ns
tRPLL
Phase Lock Loop Set
10.0
ms
*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
Table 7. CMOS/TTL & LVDS Transmitter AC Specifications
Symbol
tRCP
tRCH
tRCL
tRCD
tRS
tRH
tTLH
tTHL
tSK
CMOS/TTL Output
Figure 6. CLKIN Transmission Time
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AC Timing Diagrams
LVDS Input Data Position
Figure 7. LVDS Input Data Position
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Phase Lock Loop Set Time
Figure 8. PLL Lock Loop Set Time
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LVDS Data Timing Diagram
Figure 9. LVDS Data Timing Diagram
Pixel Data Mapping for JEIDA Format (6bit, 8bit Application)
TX Pin
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
6bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
-
8bit
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
Hsync
Vsync
DE
R0
R1
G0
G1
B0
B1
N/A
RX Pin
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
Note : Use TA to TC channels and open TD channel for 6bit application.
Table 8. Data Mapping for JEIDA Format
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Pixel Data Mapping for VESA Format (6bit, 8bit Application)
TX Pin
TA0
TA1
TA2
TA3
TA4
TA5
TA6
TB0
TB1
TB2
TB3
TB4
TB5
TB6
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TD0
TD1
TD2
TD3
TD4
TD5
TD6
6bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
Hsync
Vsync
DE
-
8bit
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
Hsync
Vsync
DE
R6
R7
G6
G7
B6
B7
N/A
RX Pin
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RD0
RD1
RD2
RD3
RD4
RD5
RD6
Note : Use TA to TC channels and open TD channel for 6bit application.
Table 9. Data Mapping for VESA Format
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Normal Connection with JEIDA Format
THC63LVDF(R)84C
Figure 10. Typical Connection Diagram
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Notes
1) Cable Connection and Disconnection
Do not connect and disconnect the LVDS cable, when the power is supplied to the system.
2) GND Connection
Connect each GND of the PCB which THC63LVDM83D and LVDS-Rx on it.
reduction to place GND cable as close to LVDS cable as possible.
It is better for EMI
3) Multi Drop Connection
Multi drop connection is not recommended.
TCLK+
LVDS-Tx
THC63LVDR84C
TCLKTHC63LVDR84C
Figure 11. Multi Drop Connection
4) Asynchronous use
Asynchronous using such as following systems is not recommended.
Figure 12. Asynchronous Use
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Package
Figure 13. Package Diagram
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Reference Land Pattern
CY1=
9.44
HE=
e=
8.100
0.500
E=
6.10
Package
Land pattern
Ttyp.=
0.60
Gmin=
6.60
1.05
b=
0.200
Zmax=
Xmax=
0.370
8.70
Zmax/2
Unit : [mm]
Figure 14. Reference of Land Pattern
The recommendation mounting method of THine device is reflow soldering.
The reference pattern is using the calculation result on condition of reflow soldering.
Notes
This land pattern design is a calculated value based on JEITA ET-7501.
Please take into consideration in an actual substrate design about enough the ease of mounting, the intensity of
connection, the density of mounting, and the solder paste used, etc…
The optimal land pattern size changes
with these parameters. Please use the value shown by the land pattern as reference data.
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to
the customer's design. We are not responsible for possible errors and omissions in this material. Please note if
errors or omissions should be found in this material, we may not be able to correct them immediately.
3. This material contains our copyright, know-how or other proprietary. Copying or disclosing to third parties
the contents of this material without our prior permission is prohibited.
4. Note that if infringement of any third party's industrial ownership should occur by using this product, we will
be exempted from the responsibility unless it directly relates to the production process or functions of the
product.
5. This product is presumed to be used for general electric equipment, not for the applications which require
very high reliability (including medical equipment directly concerning people's life, aerospace equipment, or
nuclear control equipment). Also, when using this product for the equipment concerned with the control and
safety of the transportation means, the traffic signal equipment, or various Types of safety equipment, please
do it after applying appropriate measures to the product.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain
small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have
sufficiently redundant or error preventive design applied to the use of the product so as not to have our
product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic
goods under the Foreign Exchange and Foreign Trade Control Law.
THine Electronics, Inc.
[email protected]
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