FREESCALE MC68HC05V12CFN

Freescale Semiconductor, Inc.
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General Release Specification
CSIC System Design Group
Austin, Texas
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R E Q U I R E D
December 10, 1996
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
68HC05V12
A G R E E M E N T
CT
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C.2
006
HC05V12GRS/D
Rev. 1.0
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc...
A G R E E M E N T
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R E Q U I R E D
General Release Specification
© Motorola, Inc., 1996
2
MC68HC05V12 — Rev.
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1.0
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General Release Specification — MC68HC05V12
List of Sections
Section 1. General Description ......................................21
R E Q U I R E D
Freescale Semiconductor, Inc.
DU
Section 3. Central Processing Unit (CPU) .......................45
Section 4. Interrupts .........................................................51
ON
Section 5. Resets ..............................................................63
MIC
Section 6. Low-Power Modes .........................................71
SE
Section 7. Parallel Input/Output (I/O) ............................77
Section 8. Core Timer ......................................................83
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Section 9. 16-Bit Timer .....................................................89
A G R E E M E N T
Freescale Semiconductor, Inc...
Section 2. Memory Map ..................................................35
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Section 11. Pulse Width Modulators (PWMs) ...............109
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Section 12. EEPROM .......................................................117
Section 13. A/D Converter ............................................123
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Section 14. Byte Data Link Controller-Digital
(BDLC-D) ...................................................129
Section 15. Gauge Drivers ............................................173
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Section 16. Instruction Set .............................................201
CH
Section 17. Electrical Specifications ............................219
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Section 18. Mechanical Specifications .......................233
Section 19. Ordering Information .................................235
MC68HC05V12 — Rev. 1.0
General Release Specification
List of Sections
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N O N - D I S C L O S U R E
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Section 10. Serial Peripheral Interface (SPI) ..................97
Freescale Semiconductor, Inc.
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Freescale Semiconductor, Inc...
A G R E E M E N T
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R E Q U I R E D
List of Sections
General Release Specification
MC68HC05V12 — Rev. 1.0
List of Sections
For More Information On This Product,
Go to: www.freescale.com
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5
Selectable Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6
Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.6.1
VDD and VSSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.2
VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.3
VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.4
VREFH and VREFL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.5
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.5.1
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.5.2
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .27
1.6.5.3
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.6.6
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.6.7
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .28
1.6.8
PA0–PA6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.6.9
PB0–PB3 (SPI Pins), PB4/PWMA, PB5/PWMB,
PB6/TCMP, and PB7/TCAP . . . . . . . . . . . . . . . . . . . . . .29
1.6.10
PC0–PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.11
PD0–PD4/AD0–AD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.12
TXP and RXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.13
IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.14
VPGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.15
VGSUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.6.16
VSSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.6.17
VGVREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.6.18
MAJA(B)1+, MAJA(B)1−, MAJA(B)2+, and MAJA(B)2− . . .31
1.6.19
MINA(B,C,D)1, MINA(B,C,D)2+, and MINA(B,C,D)2− . . . .31
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Freescale Semiconductor, Inc...
Section 1. General Description
MC68HC05V12 — Rev. 1.0
General Release Specification
Table of Contents
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A G R E E M E N T
Table of Contents
N O N - D I S C L O S U R E
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General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
R E Q U I R E D
Table of Contents
Section 2. Memory Map
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
USER ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Miscellaneous Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
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A G R E E M E N T
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Freescale Semiconductor, Inc...
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Section 4. Interrupts
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . .58
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .60
16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
CH
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4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.7.1
4.7.2
4.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
RE
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
MIC
Section 3. Central Processing Unit (CPU)
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N O N - D I S C L O S U R E
Power Supply Pin Connections . . . . . . . . . . . . . . . . . . . . . . . .32
Decoupling Recommendations. . . . . . . . . . . . . . . . . . . . . . . . .32
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1.7
1.8
General Release Specification
MC68HC05V12 — Rev. 1.0
Table of Contents
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Freescale Semiconductor, Inc.
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
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6.1
6.2
6.3
6.4
6.5
Section 6. Low-Power Modes
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Freescale Semiconductor, Inc...
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.4.1
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.4.2
Computer Operating Properly Reset (COPR) . . . . . . . . . . .66
5.4.2.1
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.2.2
COP during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.2.3
COP during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.2.4
COP Watchdog Timer Considerations . . . . . . . . . . . . . . .67
5.4.2.5
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5.4.3
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.4
Disabled STOP Instruction Reset . . . . . . . . . . . . . . . . . . . .69
5.4.5
Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.6
LVR Operation in Stop and Wait Modes . . . . . . . . . . . . . . .70
Section 7. Parallel Input/Output (I/O)
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7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.2
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . .79
MC68HC05V12 — Rev. 1.0
General Release Specification
Table of Contents
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A G R E E M E N T
Secton 5. Resets
N O N - D I S C L O S U R E
BDLC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Gauge Synchronize Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .62
Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
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4.9
4.10
4.11
4.12
4.13
R E Q U I R E D
Table of Contents
Freescale Semiconductor, Inc.
R E Q U I R E D
Table of Contents
Section 8. Core Timer
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Section 9. 16-Bit Timer
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Timer Counter Registers $18−$19 and $1A−$1B. . . . . . . . . . .90
Output Compare Register $16−$17 . . . . . . . . . . . . . . . . . . . . .92
Input Capture Register $14−$15. . . . . . . . . . . . . . . . . . . . . . . .92
16-Bit Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .94
16-Bit Timer Status Register (TMRSR) . . . . . . . . . . . . . . . . . .95
16-Bit Timer during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . .96
16-Bit Timer during Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . .96
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9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Core Timer Status and Control Register. . . . . . . . . . . . . . . . . .85
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .87
Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .88
Core Timer during Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . .88
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
ES
8.1
8.2
8.3
8.4
8.5
8.6
9.1
RE
Freescale Semiconductor, Inc...
Section 10. Serial Peripheral Interface (SPI)
IVE
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
10.4.1
Slave Select (SS/PB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.4.2
Serial Clock (SCK/PB1). . . . . . . . . . . . . . . . . . . . . . . . . . .100
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7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.4.2
Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . .80
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.5.2
Port C Data Direction Register . . . . . . . . . . . . . . . . . . . . . .81
7.5.3
Port C I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
General Release Specification
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Section 12. EEPROM
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . .118
EEPROM Programming/Erasing Procedure. . . . . . . . . . . . . .120
Operation in Stop and Wait Modes. . . . . . . . . . . . . . . . . . . . .121
IVE
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12.1
12.2
12.3
12.4
12.5
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11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.3 PWM Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .110
11.4 PWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.4.1
PWMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .113
11.4.2
PWMB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .114
11.4.3
PWMA Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.4.4
PWMB Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.5 PWMs during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.6 PWMs during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.7 PWMs during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
AR
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13.1
13.2
Section 13. A/D Converter
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
DU
Section 11. Pulse Width Modulators (PWMs)
N O N - D I S C L O S U R E
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10.4.3
Master In Slave Out (MISO/PB2) . . . . . . . . . . . . . . . . . . .100
10.4.4
Master Out Slave In (MOSI/PB3) . . . . . . . . . . . . . . . . . . .100
10.5 SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .101
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
10.6.1
Serial Peripheral Control Register. . . . . . . . . . . . . . . . . . .103
10.6.2
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . .104
10.6.3
Serial Peripheral Data Register. . . . . . . . . . . . . . . . . . . . .106
10.7 SPI in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.8 SPI in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
R E Q U I R E D
Table of Contents
Freescale Semiconductor, Inc.
R E Q U I R E D
Table of Contents
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14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
14.5 BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
14.5.1
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
14.5.2
Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
14.5.3
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
14.5.4
BDLC Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.5.5
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.5.6
Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.6 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.6.1
BDLC Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . .136
14.6.2
BDLC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . .138
14.6.3
BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . . .144
14.6.4
BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
14.6.5
BDLC Analog and Roundtrip Delay. . . . . . . . . . . . . . . . . .147
14.7 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
14.7.1
Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
14.7.2
Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . .151
14.7.3
Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . .151
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13.3 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.1
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.2
VREFH and VREFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.3
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.4
Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.4 Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.4.1
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.4.2
Internal and Master Oscillators . . . . . . . . . . . . . . . . . . . . .125
13.4.3
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . .126
13.5 A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . .126
13.6 A/D Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.7 A/D during Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.8 A/D during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
General Release Specification
MC68HC05V12 — Rev. 1.0
Table of Contents
For More Information On This Product,
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Freescale Semiconductor, Inc.
MC68HC05V12 — Rev. 1.0
General Release Specification
Table of Contents
For More Information On This Product,
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A G R E E M E N T
N O N - D I S C L O S U R E
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14.7.4
Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . .151
14.7.5
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
14.7.5.1
4X Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
14.7.5.2
Receiving a Message in Block Mode . . . . . . . . . . . . . . .152
14.7.5.3
Transmitting a Message in Block Mode . . . . . . . . . . . . .152
14.7.6
J1850 Bus Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
14.7.6.1
CRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
14.7.6.2
Symbol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
14.7.6.3
Framing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
14.7.6.4
Bus Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
14.7.6.5
Break (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
14.8 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.8.1
Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.8.1.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
14.8.1.2
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
14.8.2
J1850 Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
14.8.3
J1850 VPW Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.8.3.1
Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.8.3.2
Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
14.8.3.3
Normalization Bit (NB) . . . . . . . . . . . . . . . . . . . . . . . . . .163
14.8.3.4
Start of Frame Symbol (SOF) . . . . . . . . . . . . . . . . . . . .163
14.8.4
EOD − End of Data Symbol. . . . . . . . . . . . . . . . . . . . . . . .163
14.8.4.1
End of Frame Symbol (EOF) . . . . . . . . . . . . . . . . . . . . .163
14.8.4.2
Inter-Frame Separation Symbol (IFS) . . . . . . . . . . . . . .163
14.8.4.3
Break Signal (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . .163
14.8.5
J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . .164
14.8.5.1
Invalid Passive Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
14.8.5.2
Valid Passive Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .165
14.8.5.3
Valid Passive Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .166
14.8.5.4
Valid EOD Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
14.8.5.5
Valid EOF and IFS Symbol . . . . . . . . . . . . . . . . . . . . . .167
14.8.5.6
Idle Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
14.8.5.7
Invalid Active Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.8
Valid Active Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.9
Valid Active Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.10 Valid SOF Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.11 Valid BREAK Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . .169
14.8.6
Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
R E Q U I R E D
Table of Contents
Freescale Semiconductor, Inc.
R E Q U I R E D
Table of Contents
A G R E E M E N T
Section 15. Gauge Drivers
15.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
15.3
Gauge System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
15.4
Coil Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
15.5
Technical Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
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15.8
Mechanism Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
Gauge Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
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15.6 Gauge Driver Control Registers . . . . . . . . . . . . . . . . . . . . . . .179
15.6.1
Gauge Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . .179
15.6.2
Current Magnitude Registers . . . . . . . . . . . . . . . . . . . . . .181
15.6.3
Current Direction Registers . . . . . . . . . . . . . . . . . . . . . . . .183
15.6.3.1
Current Direction Register for Major A . . . . . . . . . . . . . .183
15.6.3.2
Current Direction Register for Major B . . . . . . . . . . . . . .184
15.6.3.3
Current Direction Register for Minor A . . . . . . . . . . . . . .184
15.6.3.4
Current Direction Register for Minor B . . . . . . . . . . . . . .185
15.6.3.5
Current Direction Register for Minor C. . . . . . . . . . . . . .185
15.6.3.6
Current Direction Register for Minor D. . . . . . . . . . . . . .186
15.7 Coil Sequencer and Control . . . . . . . . . . . . . . . . . . . . . . . . . .186
15.7.1
Scanning Sequence Description . . . . . . . . . . . . . . . . . . . .186
15.7.1.1
Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.7.1.2
Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.7.2
Scan Status and Control Register . . . . . . . . . . . . . . . . . . .189
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15.10 Gauge Regulator Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . .194
15.11 Coil Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
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15.12 External Component Considerations . . . . . . . . . . . . . . . . . . .195
15.12.1 Minimum Voltage Operation . . . . . . . . . . . . . . . . . . . . . . .196
15.12.2 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15.12.3 Coil Inductance Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15.13 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
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14.9 BDLC Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.9.1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.9.2
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.9.3
BDLC Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
15.14 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
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16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
16.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
16.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
16.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
16.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .206
16.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .207
16.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .208
16.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .210
16.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
16.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
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R E Q U I R E D
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17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
17.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.3 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .221
17.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.5 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
17.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .223
17.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
17.8 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .226
17.9 LVR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
17.10 Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . .228
17.11 Gauge Driver Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
17.12 BDLC Electricals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
17.12.1 Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . . .231
17.12.2 Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . . .231
MC68HC05V12 — Rev. 1.0
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Secton 17. Electrical Specifications
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R E Q U I R E D
Table of Contents
18.1
18.2
18.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
68-Lead Plastic Leaded Chip Carrier (PLCC). . . . . . . . . . . . .234
Section 19. Ordering Information
DU
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .236
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .237
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .238
MC Order Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
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19.1
19.2
19.3
19.4
19.5
19.6
19.7
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Section 18. Mechanical Specifications
General Release Specification
MC68HC05V12 — Rev. 1.0
Table of Contents
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Page
MC68HC05V12 Block Diagram . . . . . . . . . . . . . . . . . . . . . .24
MC68HC05V12 Pin Assignments (68-Pin PLCC Package) .25
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Supply Decoupling Diagram. . . . . . . . . . . . . . . . . . . . . . . . .32
Single-Sided PCB Example . . . . . . . . . . . . . . . . . . . . . . . . .33
2-1
2-2
2-3
2-4
2-5
2-6
2-7
MC68HC05V12 Single-Chip Mode Memory Map. . . . . . . . .36
MC68HC05V12 I/O Registers Memory Map . . . . . . . . . . . .37
I/O Registers $0000–$000F . . . . . . . . . . . . . . . . . . . . . . . . .39
I/O Registers $0010–$001F . . . . . . . . . . . . . . . . . . . . . . . . .40
I/O Registers $0020–$002F . . . . . . . . . . . . . . . . . . . . . . . . .41
I/O Registers $0030–$003F . . . . . . . . . . . . . . . . . . . . . . . . .42
Miscellaneous Register (MISC) . . . . . . . . . . . . . . . . . . . . . .43
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .48
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DU
1-1
1-2
1-3
1-4
1-5
DB
AR
CH
IVE
4-1
4-2
4-3
4-4
5-1
5-2
5-3
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .54
IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .56
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . .58
External Interrupts Timing Diagram . . . . . . . . . . . . . . . . . . .60
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . .66
COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .68
MC68HC05V12 — Rev. 1.0
General Release Specification
List of Figures
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Title
YF
Freescale Semiconductor, Inc...
Figure
List of Figures
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
R E Q U I R E D
List of Figures
Page
CT
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Title
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .73
Stop/Wait Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7-1
7-2
7-3
7-4
Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Port D Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
8-1
8-2
8-3
Core Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .84
Core Timer Status and Control Register (CTSCR) . . . . . . .85
Core Timer Counter Register (CTCR) . . . . . . . . . . . . . . . . .88
9-1
9-2
9-3
9-4
16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .90
TCAP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Timer Control Register (TMRCR) . . . . . . . . . . . . . . . . . . . . .94
Timer Status Register (TMRSR) . . . . . . . . . . . . . . . . . . . . .95
10-1
10-2
10-3
10-4
10-5
10-6
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . .99
Serial Peripheral Interface Block Diagram . . . . . . . . . . . . .102
Serial Peripheral Interface Master-Slave Interconnection .102
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . .103
SPI Status Register (SPSR). . . . . . . . . . . . . . . . . . . . . . . .104
SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . .106
ON
MIC
SE
LE
CA
ES
RE
PWM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
PWM Waveform Examples (POL = 1) . . . . . . . . . . . . . . . .111
PWM Waveform Examples (POL = 0) . . . . . . . . . . . . . . . .111
PWM Write Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . .112
PWMA Control Register (PWMAC) . . . . . . . . . . . . . . . . . .113
PWMB Control Register (PWMBC) . . . . . . . . . . . . . . . . . .114
PWMA Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
PWMB Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
CH
IVE
DB
YF
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
DU
6-1
6-2
12-1
EEPROM Programming Register (EEPROG) . . . . . . . . . .118
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Figure
General Release Specification
MC68HC05V12 — Rev. 1.0
List of Figures
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
14-1
14-2
14-3
14-4
14-5
14-6
14-7
14-8
14-9
14-10
14-11
14-12
14-13
14-14
14-15
14-16
14-17
BDLC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
BDLC Operating Modes State Diagram . . . . . . . . . . . . . . .133
BDLC Control Register 1 (BCR1) . . . . . . . . . . . . . . . . . . . .136
BDLC Control Register 2 (BCR2) . . . . . . . . . . . . . . . . . . . .138
Types of In-Frame Response. . . . . . . . . . . . . . . . . . . . . . .141
BDLC State Vector Register (BSVR) . . . . . . . . . . . . . . . . .145
BDLC Data Register (BDR) . . . . . . . . . . . . . . . . . . . . . . . .147
BDLC Analog Roundtrip Delay Register (BARD) . . . . . . . .148
BDLC Protocol Handler Outline . . . . . . . . . . . . . . . . . . . . .150
BDLC Rx Digital Filter Block Diagram . . . . . . . . . . . . . . . .156
J1850 Bus Message Format (VPW) . . . . . . . . . . . . . . . . . .158
J1850 VPW Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
J1850 VPW Passive Symbols . . . . . . . . . . . . . . . . . . . . . .165
J1850 VPW EOF and IFS Symbols . . . . . . . . . . . . . . . . . .166
J1850 VPW Active Symbols. . . . . . . . . . . . . . . . . . . . . . . .167
J1850 VPW BREAK Symbol . . . . . . . . . . . . . . . . . . . . . . .168
J1850 VPW Bitwise Arbitrations. . . . . . . . . . . . . . . . . . . . .170
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
Gauge Driver Block Diagram . . . . . . . . . . . . . . . . . . . . . . .175
Full H-Bridge Coil Driver. . . . . . . . . . . . . . . . . . . . . . . . . . .177
Half H-Bridge Coil Driver . . . . . . . . . . . . . . . . . . . . . . . . . .177
Specification for Current Spikes . . . . . . . . . . . . . . . . . . . . .178
Gauge Enable Register (GER). . . . . . . . . . . . . . . . . . . . . .180
Current Magnitude Registers . . . . . . . . . . . . . . . . . . . . . . .181
MAJA Current Direction Register (DMAJA) . . . . . . . . . . . .183
MAJB Current Direction Register (DMAJB) . . . . . . . . . . . .184
MINA Current Direction Register (DMINA) . . . . . . . . . . . . .184
MINB Current Direction Register (DMINB) . . . . . . . . . . . . .185
MINC Current Direction Register (DMINC) . . . . . . . . . . . .185
MIND Current Direction Register (DMIND) . . . . . . . . . . . .186
Scan Status and Control Register (SSCR). . . . . . . . . . . . .190
Sample Gauge Connections to the MC68HC05V12 . . . . .193
Coil Driver Current Path . . . . . . . . . . . . . . . . . . . . . . . . . . .195
ON
MIC
SE
LE
CA
ES
RE
DB
IVE
CH
AR
MC68HC05V12 — Rev. 1.0
General Release Specification
List of Figures
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A G R E E M E N T
A/D Status and Control Register (ADSCR) . . . . . . . . . . . .126
A/D Data Register (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . .127
DU
13-1
13-2
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Title
YF
Freescale Semiconductor, Inc...
Figure
R E Q U I R E D
List of Figures
Freescale Semiconductor, Inc.
R E Q U I R E D
List of Figures
Page
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Title
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . .225
LVR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . .229
SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . .229
BDLC Variable Pulse Width Modulation (VPW)
Symbol Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
18-1
68-Lead PLCC, Case 779-02 . . . . . . . . . . . . . . . . . . . . . . .234
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
17-1
17-2
17-3
17-4
17-5
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Figure
General Release Specification
MC68HC05V12 — Rev. 1.0
List of Figures
For More Information On This Product,
Go to: www.freescale.com
Page
Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . .53
5-1
COP Watchdog Timer Recommendations . . . . . . . . . . . . . . .68
8-1
RTI and COP Rates at 2.1 MHz . . . . . . . . . . . . . . . . . . . . . . .86
10-1
Serial Peripheral Rate Selection. . . . . . . . . . . . . . . . . . . . . .104
11-1
11-2
PWMA Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
PWMB Clock Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
12-1
12-2
Erase Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
EEPROM Write/Erase Cycle Reduction . . . . . . . . . . . . . . . .120
13-1
A/D Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .127
14-1
14-2
14-3
ES
CA
LE
SE
MIC
ON
DU
4-1
15-1
15-2
Coil Scanning Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . .188
Gauge Module Clock Select Bits . . . . . . . . . . . . . . . . . . . . .191
16-1
16-2
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .206
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .207
YF
RE
BDLC Rate Selection for Binary Frequencies . . . . . . . . . . .137
BDLC Rate Selection for Integer Frequencies . . . . . . . . . . .137
Transmit In-Frame Response Control Bit
Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
BARD Offset Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
BDLC J1850 Bus Error Summary. . . . . . . . . . . . . . . . . . . . .155
AR
CH
IVE
14-4
14-5
14-6
MC68HC05V12 — Rev. 1.0
General Release Specification
List of Tables
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Title
DB
Freescale Semiconductor, Inc...
Table
List of Tables
N O N - D I S C L O S U R E
CT
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General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
R E Q U I R E D
List of Tables
Page
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Title
16-3
16-4
16-5
16-6
16-7
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .209
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .210
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
17-1
BDLC Transmitter VPW Symbol Timings
(BARD Bits BO[3:0] = 0111) . . . . . . . . . . . . . . . . . . . . . .231
BDLC Receiver VPW Symbol Timings
(BARD Bits BO[3:0] = 0111) . . . . . . . . . . . . . . . . . . . . . .231
DU
17-2
MC Order Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
19-1
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Table
General Release Specification
MC68HC05V12 — Rev. 1.0
List of Tables
For More Information On This Product,
Go to: www.freescale.com
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.4
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.5
Selectable Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DU
1.2
ON
Freescale Semiconductor, Inc...
1.1 Contents
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
1.6
Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.6.1
VDD and VSSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.2
VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.3
VCCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.4
VREFH and VREFL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.5
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.5.1
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.5.2
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .27
1.6.5.3
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.6.6
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .28
1.6.7
1.6.8
PA0–PA6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
1.6.9
PB0–PB3 (SPI Pins), PB4/PWMA, PB5/PWMB,
PB6/TCMP, and PB7/TCAP . . . . . . . . . . . . . . . . . . . . . .29
1.6.10
PC0–PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.11
PD0–PD4/AD0–AD4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.12
TXP and RXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.13
IMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.14
VPGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6.15
VGSUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.6.16
VSSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.6.17
VGVREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.6.18
MAJA(B)1+, MAJA(B)1−, MAJA(B)2+, and MAJA(B)2− . . .31
1.6.19
MINA(B,C,D)1, MINA(B,C,D)2+, and MINA(B,C,D)2− . . . .31
1.7
Power Supply Pin Connections . . . . . . . . . . . . . . . . . . . . . . . .32
1.8
Decoupling Recommendations. . . . . . . . . . . . . . . . . . . . . . . . .32
MC68HC05V12 — Rev. 1.0
General Release Specification
General Description
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A G R E E M E N T
Section 1. General Description
N O N - D I S C L O S U R E
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General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
The Motorola MC68HC05V12 microcontroller is a custom M68HC05based MCU featuring a byte data link controller (BDLC) module and onchip power regulation for the on-chip gauge drivers. The device is
available packaged in a 68-pin plastic lead chip carrier (PLCC). A
functional block diagram of the MC68HC05V12 is shown in Figure 1-1.
1.3 Features
M68HC05 Core with On-Chip Oscillator for Crystal/Ceramic
Resonator
•
12 Kbytes of User ROM and 384 Bytes of User RAM
•
256 Bytes of Byte, Block, or Bulk Erasable EEPROM
•
Byte Data Link Controller (BDLC) Module
•
5-Channel, 8-Bit Analog-to-Digital (A/D) Converter
•
Serial Peripheral Interface (SPI)
•
8-Bit Timer with Real-Time Interrupt
•
16-Bit Timer with One Input Capture and One Output Compare
•
Two 38-Frequency, 6-Bit Pulse Width Modulators (PWMs)
•
ES
CA
LE
SE
MIC
ON
•
RE
DU
Features of the MC68HC05V12 include the following.
YF
Mask Option Selectable Computer Operating Properly (COP)
Watchdog System
23 General-Purpose Input/Output (I/O) Pins:
– Eight I/O Pins with Interrupt Wakeup Capability
– Eight I/O Pins Multiplexed with Timer, PWMs, and Serial
Peripheral Interface (SPI) Pins
– Seven General-Purpose I/O Pins
CH
IVE
DB
•
•
Five Input-Only Pins Multiplexed with A/D
AR
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1.2 Introduction
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A G R E E M E N T
R E Q U I R E D
General Description
General Release Specification
MC68HC05V12 — Rev. 1.0
General Description
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
•
Power-Saving Stop Mode and Wait Mode Instructions (Mask
Option Selectable STOP Instruction Disable)
1.4 MCU Structure
ON
DU
The overall block diagram of the MC68HC05V12 is shown in
Figure 1-1.
NOTE:
CA
1.5 Selectable Mask Options
LE
SE
MIC
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, or frequency specified in the following sections will refer to the
nominal values. The exact values and their tolerance or limits are
specified in Section 17. Electrical Specifications.
Selectable COP watchdog system enable/disable
YF
•
Sensitivity on IRQ interrupt, edge- and level-sensitive or edgesensitive only
RE
•
ES
The following mask options are selectable.
Selectable low-voltage reset (LVR) to hold CPU in reset
•
Selectable STOP instruction disable
CH
IVE
DB
•
MC68HC05V12 — Rev. 1.0
General Release Specification
General Description
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R E Q U I R E D
Mask Option Selectable Low-Voltage Reset (LVR)
A G R E E M E N T
•
N O N - D I S C L O S U R E
On-Chip H-Bridge Driver Circuitry to Drive Six Gauges
– Four Minor Gauges
– Two Major Gauges
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•
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Freescale Semiconductor, Inc...
General Description
MCU Structure
Freescale Semiconductor, Inc.
PROGRAM COUNTER
COND CODE REG
1 1 1H I NZC
PORT C
PC4 *
PC3 *
PC2 *
PC1 *
PC0 *
PB7/TCAP
PB6/TCMP
DATA DIRECTION REG
0 0 0 0 0 0 0 0 1 1 STACK PTR
MIC
VREFL
INDEX REGISTER
DU
VREFH
CPU REGISTERS
ON
PD4/AD4
PC5 *
PB5/PWMB
PORT B
5-CHANNEL, 8-BIT A/D CONVERTER
PD3/AD3
ACCUMLATOR
PC6 *
DATA DIRECTION REG
68HC05 CPU
PB4/PWMA
PB3/MISO
PB2/MOSI
PB1/SCK
PB0/SS
SE
SRAM — 384 BYTES
USER ROM — 12 KBYTES
8-BIT TIMER WITH RTI
ES
16-BIT TIMER WITH
1 TCAP AND 1 TCMP
RE
VGVREF
VSSG
IMAX
VDD
VSSD
IVE
VGSUP
PA3
PA3
PA1
INTERRUPT
TXP
YF
DB
VPGC
PA4
PA0
2-CHANNEL
38-FREQUENCY, 6-BIT PWM
VCCA
PA5
PORT A
CA
EEPROM — 256 BYTES
VSSA
PA6
DATA DIRECTION REG
LE
IRQ
AR
A G R E E M E N T
ALU
INTERNAL DATA/ADDRESS BUS
CPU CONTROL
PD0/AD0
PC7 *
WATCHDOG
LVR
PD2/AD2
Freescale Semiconductor, Inc...
SPI
VDD
INTERNAL
RESET
PD1/AD1
N O N - D I S C L O S U R E
÷2
OSCILLATOR
OSC 2
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OSC 1
CH
R E Q U I R E D
General Description
BDLC
RXP
GAUGE DRIVERS
CLKIN
VSSG
MAJ/MIN GAUGE PINS (20 PINS)
VDD
VSSD INTERNAL DIGITAL SUPPLIES
* Interrupt Pins
Figure 1-1. MC68HC05V12 Block Diagram
General Release Specification
MC68HC05V12 — Rev. 1.0
General Description
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Freescale Semiconductor, Inc.
SE
MIC
ON
DU
60
59
58
57
56
55
54
53
10
52
51
50
49
48
47
46
45
44
PC3
PC2
PC1
PC0
VREFH
VREFL
PD4/AD4
PD3/AD3
PD2/AD2
PD1/AD1
PD0/AD0
VCCA
VSSA
MIND1
MIND2+
MIND2VSSG
R E Q U I R E D
PA4
1 68 67 66 65 64 63 62 61
PC4
PA5
2
PC5
PA6
3
PC6
RESET
4
PC7
OSC2
5
PA0
OSC1
6
PA1
VDD
7
PA2
VSSD
8
PA3
IRQ
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
LE
PB0/SS
PB1/SCK
PB2/MOSI
PB3/MISO
PB4/PWMA
PB5/PWMB
PB6/TCMP
PB7/TCAP
TXP
RXP
VDD
VSSD
IMAX
MINB1
MINB2+
MINB2VSSG
CH
IVE
DB
YF
Figure 1-2. MC68HC05V12 Pin Assignments (68-Pin PLCC Package)
MC68HC05V12 — Rev. 1.0
General Release Specification
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N O N - D I S C L O S U R E
MINC2-
MINC1
MINC2+
MAJB2-
MAJB2+
MAJB1-
MAJB1+
VGREF
VGSUP
VPGC
MAJA2-
MAJA1-
MAJA2+
MAJA1+
MINA2-
RE
MINA1
MINA2+
ES
CA
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AR
Freescale Semiconductor, Inc...
The pinout for the MC68HC05V12 is shown in Figure 1-2 followed by a
functional description of each pin.
A G R E E M E N T
1.6 Functional Pin Descriptions
CT
OR
, IN
C.2
006
General Description
Functional Pin Descriptions
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
1.6.1 VDD and VSSD
ON
DU
These pins provide power to all the microcontroller’s digital circuits. The
short rise and fall times of the MCU supply current transients place very
high short-duration current demands on the internal power supply. To
prevent noise problems, special care should be taken to provide good
power supply bypassing at the MCU by using bypass capacitors with
good high-frequency characteristics that are positioned as close to the
MCU supply pins as possible. Two sets of VDD and VSS pins are required
to maintain on-chip supply noise within acceptable limits. Each supply
pin pair will require its own decoupling capacitor. These are high-current
pins.
1.6.2 VSSA
LE
SE
MIC
VSSA is a separate ground pad which provides a ground return for the
analog-to-digital (A/D) subsystem and the digital-to-analog (D/A) gauge
subsystem. To prevent digital noise contamination, this pin should be
connected directly to a low-impedance ground reference point.
CA
1.6.3 VCCA
DB
1.6.4 VREFH and VREFL
YF
RE
ES
VCCA is a separate supply pin providing power to the analog subsystems
of the A/D converter and gauge drivers. This pin must be connected to
the VDD pin externally. To prevent contamination from the digital supply,
this pin should be adequately decoupled to a low-impedance ground
reference.
CH
IVE
VREFH is the positive (high) reference voltage for the A/D subsystem.
VREFL is the negative (low) reference voltage for the A/D subsystem.
VREFH and VREFL should be isolated from the digital supplies to prevent
any loss of accuracy from the A/D converter.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
General Description
General Release Specification
MC68HC05V12 — Rev. 1.0
General Description
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Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
1.6.5 OSC1 and OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator.
OSC1 is the input to the oscillator inverter. The output (OSC2) will
always reflect OSC1 inverted except when the device is in stop mode
which forces OSC2 high. The OSC1 and OCS2 pins can accept the
following sets of components:
1. A crystal as shown in Figure 1-3(a)
R E Q U I R E D
General Description
Functional Pin Descriptions
MIC
1.6.5.1 Crystal Oscillator
RE
ES
CA
LE
SE
The circuit in Figure 1-3(a) shows a typical oscillator circuit for an ATcut, parallel resonant crystal. The crystal manufacturer’s
recommendations should be followed, as the crystal parameters
determine the external component values required to provide maximum
stability and reliable startup. The load capacitance values used in the
oscillator circuit design should include all stray capacitances. The crystal
and components should be mounted as close as possible to the pins for
startup stabilization and to minimize output distortion and radiated
emissions.
YF
1.6.5.2 Ceramic Resonator Oscillator
CH
IVE
DB
In cost-sensitive applications, a ceramic resonator can be used in place
of the crystal. The circuit in Figure 1-3(a) can be used for a ceramic
resonator. The resonator manufacturer’s recommendations should be
followed, as the resonator parameters determine the external
component values required for maximum stability and reliable starting.
The load capacitance values used in the oscillator circuit design should
include all stray capacitances. The ceramic resonator and components
should be mounted as close as possible to the pins for startup
stabilization and to minimize output distortion and radiated emissions.
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
ON
The frequency, fOSC, of the oscillator or external clock source is divided
by two to produce the internal operating frequency, fOP.
N O N - D I S C L O S U R E
DU
3. An external clock signal as shown in Figure 1-3(b)
AR
Freescale Semiconductor, Inc...
2. A ceramic resonator as shown in Figure 1-3(a)
Freescale Semiconductor, Inc.
An external clock from another CMOS-compatible device can be
connected to the OSC1 input. The OSC2 pin should be left unconnected,
as shown in Figure 1-3(b).
MCU
OSC2
10 MΩ*
20 pF *
MCU
OSC1
OSC2
UNCONNECTED
20 pF *
ON
4 MHz*
EXTERNAL CLOCK
(b) External Clock
Source Connection
MIC
(a) Crystal or Ceramic
Resonator Connections
*Values shown are typical. For further information, consult the crystal oscillator vendor.
SE
Figure 1-3. Oscillator Connections
LE
1.6.6 RESET
DB
YF
RE
ES
CA
This pin can be used as an input to reset the MCU to a known startup
state by pulling it to the low state. The RESET pin contains an internal
Schmitt trigger to improve its noise immunity as an input. The RESET pin
has an internal pulldown device that pulls the RESET pin low when there
is an internal computer operating properly (COP) watchdog reset,
power-on reset (POR), illegal address reset, a disabled STOP
instruction reset or an internal low-voltage reset. Refer to
Section 5. Resets.
IVE
1.6.7 IRQ (Maskable Interrupt Request)
This input pin drives the asynchronous IRQ interrupt function of the
CPU. The IRQ interrupt function has a programmable mask option to
select either negative edge-sensitive triggering or both negative edgesensitive and low level-sensitive triggering. The IRQ input requires an
external resistor to VDD for wire-OR operation, if desired. If the IRQ pin
is not used, it must be tied to the VDD supply. The IRQ pin contains an
CH
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Freescale Semiconductor, Inc...
A G R E E M E N T
OSC1
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
1.6.5.3 External Clock
DU
R E Q U I R E D
General Description
General Release Specification
MC68HC05V12 — Rev. 1.0
General Description
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Freescale Semiconductor, Inc.
SE
1.6.9 PB0–PB3 (SPI Pins), PB4/PWMA, PB5/PWMB, PB6/TCMP, and PB7/TCAP
CA
LE
These eight I/O lines comprise port B. The state of any pin is software
programmable, and all port B lines are configured as inputs during
power-on or reset. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
RE
ES
PB0–PB3 are shared with serial peripheral interface (SPI) functions. See
Section 10. Serial Peripheral Interface (SPI) for more details
concerning the operation of the SPI and configuration of these pins.
IVE
DB
YF
PB6 and PB7 are also shared with timer functions. The TCAP pin
controls the input capture feature for the on-chip 16-bit timer. The TCMP
pin provides an output for the output compare feature of the on-chip 16bit timer. See Section 9. 16-Bit Timer for more details on the operation
of the timer subsystem.
CH
PB4 and PB5 are shared with the pulse width modulator output pins
(PWMA and PWMB). See Section 11. Pulse Width Modulators
(PWMs) for more details on the operation of the PWMs.
MC68HC05V12 — Rev. 1.0
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General Description
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A G R E E M E N T
MIC
ON
These seven I/O lines comprise port A. The state of any pin is software
programmable, and all port A lines are configured as inputs during
power-on or reset. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
DU
1.6.8 PA0–PA6
AR
Freescale Semiconductor, Inc...
internal Schmitt trigger as part of its input to improve noise immunity.
Each of the PC0 through PC7 I/O pins may be connected as an OR
function with the IRQ interrupt function. This capability allows keyboard
scan applications where the transitions on the I/O pins will behave the
same as the IRQ pin. The edge or level sensitivity selected by a mask
option for the IRQ pin does not apply to the port C input/output (I/O) pin
interrupt. The I/O pin interrupt is always negative edge-sensitive. See
Section 4. Interrupts for more details on the interrupts.
R E Q U I R E D
General Description
Functional Pin Descriptions
Freescale Semiconductor, Inc.
A G R E E M E N T
These eight I/O lines comprise port C. The state of any pin is software
programmable and all port C lines are configured as inputs during
power-on or reset. All eight pins are connected via an internal gate to the
IRQ interrupt function. When the IRQ interrupt function is enabled, all the
port C pins will act as negative edge-sensitive IRQ sources. See
Section 7. Parallel Input/Output (I/O) for more details on the I/O ports.
1.6.11 PD0–PD4/AD0–AD4
1.6.12 TXP and RXP
CA
LE
SE
MIC
ON
DU
When the A/D converter is disabled, PD0–PD4 are general-purpose
input pins. The A/D converter is disabled upon exiting from reset. When
the A/D converter is enabled, one of these pins is the analog input to the
A/D converter. The A/D control register contains control bits to direct
which of the analog inputs are to be converted at any one time. A digital
read of this pin when the A/D converter is enabled results in a read of
logical zero from the selected analog pin. A digital read of the remaining
pins gives their correct (digital) values. See Section 13. A/D Converter
for more details on the operation of the A/D subsystem.
YF
RE
ES
These pins provide the I/O interface for the BDLC subsystem. See
Section 14. Byte Data Link Controller-Digital (BDLC-D) for more
details on the operation of the BDLC.
DB
1.6.13 IMAX
1.6.14 VPGC
CH
IVE
This pin is used to define the maximum coil current in the gauges by
connecting a resistor from this pin (RMAX) to ground as shown in
15.7 Coil Sequencer and Control.
AR
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
1.6.10 PC0–PC7
N O N - D I S C L O S U R E
R E Q U I R E D
General Description
This pin is the gauge power control pin for the external pass device.
Refer to 15.7 Coil Sequencer and Control.
General Release Specification
MC68HC05V12 — Rev. 1.0
General Description
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DU
Two pins are provided for a separate gauge driver ground, VSSG. Used
as the current return only for the coil driver circuitry, it is a high-current
pin.
ON
1.6.17 VGVREF
SE
MIC
This pin is the feedback pin for the gauge power regulator. External
resistors as shown in Figure 15-14 . Sample Gauge Connections to
the MC68HC05V12 are used to set the gauge input voltage at pin
VGSUP.
LE
1.6.18 MAJA(B)1+, MAJA(B)1−, MAJA(B)2+, and MAJA(B)2−
YF
RE
ES
CA
These pins are the full H-bridge coil driver pins. The A or B refer to pins
associated with major gauge A or gauge B, and pin 1+/− or pin 2+/− refer
to coil 1 or coil 2 of that major gauge and the direction of current flow.
Refer to 15.3 Gauge System Overview for more details on the
operation of these pins.
1.6.19 MINA(B,C,D)1, MINA(B,C,D)2+, and MINA(B,C,D)2−
IVE
DB
MINA(B,C,D)2+ and MINA(B,C,D)2− are the full H-bridge driver pins
used with or for the minor gauges. These pins allow the coil current to be
reversed for movement of gauge pointer from 0 to 180 degrees.
MINA(B,C,D)1 is the low-side driver pin used with the minor gauges. The
current flow through the coil is restricted to one direction. Refer to
15.3 Gauge System Overview for more details on the operation of
these pins.
CH
AR
Freescale Semiconductor, Inc...
1.6.16 VSSG
MC68HC05V12 — Rev. 1.0
General Release Specification
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A G R E E M E N T
This pin is the regulated gauge voltage input. Refer to 15.7 Coil
Sequencer and Control.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
1.6.15 VGSUP
R E Q U I R E D
General Description
Functional Pin Descriptions
Freescale Semiconductor, Inc.
1.7 Power Supply Pin Connections
Refer to Figure 1-4 for a supply decoupling diagram.
DIGITAL CIRCUIT SUPPLY
VDD
0.1 µF
DIGITAL CIRCUIT GROUND
ANALOG
GROUND
DU
0.1 µF
ANALOG
SUPPLY
DIGITAL
MODULES
MIC
LE
SE
GAUGE REGISTER
VSSG
0.1 µF
VSSD
ON
VCCA
**
VDD
A/D CONVERTER
VSSA
SINGLE POINT
GROUND
GAUGE DRIVERS
VPGC*
VGSUP*
0.1 µF
ES
CA
* Refer to Section 15. Gauge Drivers for decoupling recommendations.
**Optional supply isolation circuit
RE
Figure 1-4. Supply Decoupling Diagram
YF
1.8 Decoupling Recommendations
IVE
DB
To provide effective decoupling and to reduce radiated RF emissions,
small decoupling capacitors must be located as close to the supply pins
as possible. The self-inductance of these capacitors and the parasitic
inductance and capacitance of the interconnecting traces determine the
self-resonant frequency of the decoupling network. A frequency that is
too low will reduce decoupling effectiveness and could increase radiated
RF emissions from the system. A low value capacitor (470 pF to 0.01 µF)
placed in parallel with the other capacitors will improve the bandwidth
and effectiveness of the network.
CH
AR
Freescale Semiconductor, Inc...
A G R E E M E N T
VSSD
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
R E Q U I R E D
General Description
General Release Specification
MC68HC05V12 — Rev. 1.0
General Description
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CA
V12
BETTER ANALOG GROUNDING
ANX
VSSA
ES
SHIELDED
CABLE
RE
AIN
VSSD
ANX
VSSA
VSSD
SHIELDED CABLE
AIN
AGND
TO SYSTEM GND
GND
IVE
DB
YF
GND
V12
CH
Figure 1-5. Single-Sided PCB Example
MC68HC05V12 — Rev. 1.0
General Release Specification
General Description
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N O N - D I S C L O S U R E
POOR ANALOG GROUNDING
A G R E E M E N T
CT
OR
, IN
C.2
006
LE
SE
MIC
ON
DU
2. VCCA to VSSA: Analog subsystem power supply pins. These
pins are internally isolated from the digital VDD and VSS supplies.
The VSSA pin provides a ground return for the A/D subsystem and
portions of the gauge subsystem. The analog supply pins should
be appropriately filtered to prevent any external noise affecting the
analog subsystems. The VSSA pin should be brought together with
the digital ground at a single point which has a low (HF)
impedance to ground to prevent common mode noise problems. If
this is not practical, then the VSSA PCB traces should be routed in
such a manner that digital ground return current is impeded from
passing through the analog input ground reference as shown in
Figure 1-5.
AR
Freescale Semiconductor, Inc...
1. VDD to VSSD: MCU internal digital power decoupling. Decouple
with a 0.1 µF ceramic or polystyrene cap. If the self-resonance
frequency of the decoupling circuit (assume 4 nH per bond wire)
is too low, add a 0.01 µF or smaller cap in parallel to increase the
bandwidth of the decoupling network. Place the smaller cap
closest to the VDD and VSSD pins.
R E Q U I R E D
General Description
Decoupling Recommendations
Freescale Semiconductor, Inc.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
CT
OR
, IN
C.2
006
R E Q U I R E D
General Description
General Release Specification
MC68HC05V12 — Rev. 1.0
General Description
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3
I/O and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.4
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.5
Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.6
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.7
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.8
Miscellaneous Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
SE
MIC
ON
DU
2.2
LE
2.2 Introduction
CH
IVE
DB
YF
RE
ES
CA
When the MC68HC05V12 is in the single-chip mode, the input/out (I/O)
and peripherals, user RAM, EEPROM, and user ROM are all active as
shown in Figure 2-1.
AR
Freescale Semiconductor, Inc...
2.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Memory Map
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A G R E E M E N T
Section 2. Memory Map
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
$003F
$0040
$00FF
$0100
0255
0256
USER RAM
192 BYTES
0447
UNUSED
DU
$033F
$0340
0576
USER EEPROM
256 BYTES
0831
0832
UNUSED
2496 BYTES
ON
$0240
3327
3328
MIC
$0CFF
$0D00
$3BFF
$3C00
I/O
Registers
16383
$003F
*Gauge Vector (High Byte)/
COP Watchdog Timer
$3FF0
Gauge Vector (Low Byte)
$3FF1
8-Bit Timer Vector (High Byte)
$3FF2
8-Bit Timer Vector (Low Byte)
$3FF3
SPI Vector (High Byte)
$3FF4
SPI Vector (Low Byte)
$3FF5
BDLC Vector (High Byte)
$3FF6
BDLC Vector (Low Byte)
$3FF7
16-Bit Timer Vector (High Byte) $3FF8
16-Bit Timer Vector (Low Byte)
$3FF9
IRQ Vector (High Byte)
$3FFA
IRQ Vector (Low Byte)
$3FFB
SWI Vector (High Byte)
$3FFC
SWI Vector (Low Byte)
$3FFD
Reset Vector (High Byte)
$3FFE
Reset Vector (Low Byte)
$3FFF
ES
USER VECTORS ROM
16 BYTES
16367
16368
LE
15359
15360
BOOTLOADER/ FACTORY
TEST CODE ROM
1008 BYTES
$3FFF
SE
USER ROM
12032 BYTES
$3FEF
$3FF0
$0000
64 Bytes
See Figure 2-2
STACK RAM
64 BYTES
RE
*Reading $3FF0 returns the gauge vector EPROM byte.
Writing a zero to $3FF0, bit 0, resets the COP.
DB
YF
Figure 2-1. MC68HC05V12 Single-Chip Mode Memory Map
2.3 I/O and Control Registers
IVE
The I/O and control registers reside in locations $0000–$003F. The
overall organization of these registers is shown in Figure 2-2. The bit
assignments for each register are shown in Figure 2-3 through
Figure 2-6. Reading from unimplemented bits will return unknown
states, and writing to unimplemented bits will be ignored.
CH
AR
A G R E E M E N T
Freescale Semiconductor, Inc...
0063
0064
USER RAM
128 BYTES
$01BF
N O N - D I S C L O S U R E
0000
I/O
64 BYTES
CT
OR
, IN
C.2
006
$0000
CA
R E Q U I R E D
Memory Map
General Release Specification
MC68HC05V12 — Rev. 1.0
Memory Map
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Freescale Semiconductor, Inc.
$0001
$0002
Port C Data Direction Register
$0006
Unused
$0007
8-Bit Timer Status and Control
$0008
8-Bit Timer Counter Register
$0009
SPI Control Register
$000A
SPI Status Register
$000B
SPI Data Register
$000C
Unimplemented
$000D
Unimplemented
$000E
Unimplemented
$000F
Unimplemented
$0010
Unimplemented
$0011
16-Bit Timer Control Register
$0012
16-Bit Timer Status Register
$0022
Magnitude Register — MAJA2
$0023
Magnitude Register — MAJB1
$0024
Magnitude Register — MAJB2
$0025
Magnitude Register — MINA1
$0026
Magnitude Register — MINA2
$0027
Magnitude Register — MINB1
$0028
Magnitude Register — MINB2
$0029
Magnitude Register — MINC1
$002A
Magnitude Register — MINC2
$002B
Magnitude Register — MIND1
$002C
Magnitude Register — MIND2
$002D
Current Direction Register — DMAJA
$002E
Current Direction Register — DMAJB
$002F
Current Direction Register — DMINA
$0030
Current Direction Register — DMINB
$0031
Current Direction Register — DMINC
$0032
Current Direction Register — DMIND
$0033
$0034
$0014
Reserved
Input Capture Register (Low)
$0015
Miscellaneous Register
$0035
Output Compare Register (High)
$0016
PWMA Data Register
$0036
$0017
PWMA Control Register
$0037
PWMB Data Register
$0038
PWMB Control Register
$0039
$001A
BDLC Control Register 1
$003A
$003B
LE
Input Capture Register (High)
CA
$0013
ON
Port B Data Direction Register
$0005
MIC
$0004
SE
Port A Data Direction Register
DU
$0003
$0021
Magnitude Register — MAJA1
ES
Output Compare Register (Low)
16-Bit Timer Count Register (High)
$0018
$0019
RE
16-Bit Timer Count Register (Low)
Alternate Count Register (High)
Alternate Count Register (Low)
EEPROM Program Register
$001C
BDLC State Vector Register
$003C
A/D Data Register
$001D
BDLC Data Register
$003D
A/D Status and Control Register
$001E
BDLC Analog Roundtrip Delay Register
$003E
$001F
Reserved
$003F
DB
YF
$001B
BDLC Control Register 2
IVE
IRQ Status and Control Register
CH
Figure 2-2. MC68HC05V12 I/O Registers Memory Map
AR
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Port D Data Register
$0020
MC68HC05V12 — Rev. 1.0
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Memory Map
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R E Q U I R E D
Port B Data Register
Port C Data Register
Gauge Enable Register — GER
Scan Status & Control Reg — SSCR
A G R E E M E N T
$0000
N O N - D I S C L O S U R E
Port A Data Register
CT
OR
, IN
C.2
006
Memory Map
I/O and Control Registers
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
2.4 RAM
The total RAM consists of 384 bytes (including the stack). The stack
begins at address $00FF and proceeds down to $00C0 (64 bytes). Using
the stack area for data storage or temporary work locations requires care
to prevent it from being overwritten due to stacking from an interrupt or
subroutine call.
NOTE:
DU
The stack is located in the middle of the RAM address space. Data
written to addresses within the stack address range can be overwritten
during stack activity.
ON
2.5 Boot ROM
SE
MIC
The boot ROM space in the MC68HC05V12 consists of 1008 bytes
including EEPROM test code, burn-in code, and 16 bytes of bootloader
vectors.
LE
2.6 USER ROM
ES
CA
There are 12,032 bytes of user ROM and 16 bytes of ROM for user
vectors and the COP update location.
RE
2.7 EEPROM
CH
IVE
DB
YF
This device contains 256 bytes of EEPROM. Programming the
EEPROM is performed by the user on a single-byte basis by
manipulating the programming register located at address $001C. Refer
to Section 12. EEPROM for programming details.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Memory Map
General Release Specification
MC68HC05V12 — Rev. 1.0
Memory Map
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Freescale Semiconductor, Inc.
Port A Data — PORTA
Bit 7
R
0
6
PA6
W
R
$0001
Port B Data — PORTB
PB7
PB6
PC7
PC6
0
0
W
R
$0002
Port C Data — PORTC
W
R
$0003
Port B Data
Direction — DDRB
W
0
R
DDRB6
DDRC7
DDRC6
W
R
$0007
Unimplemented
W
W
Core Timer
Counter — CTCR
W
CTOF
R
TMR7
SPI Control — SCR
W
R
SPI Status — SSR
PA4
PA3
PA2
PA1
PA0
PB5
PB4
PB3
PB2
PB1
PB0
PC5
PC4
PC3
PC2
PC1
PC0
PD4
PD3
PD2
PD1
PD0
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
TOFE
RTIE
RT1
RT0
TOFC
RTIFC
TMR4
TMR3
TMR2
TMR1
TMR0
CPOL
CPHA
SPR1
SPR0
SPD3
SPD2
SPD1
SPD0
DDRA5
DDRB5
TMR6
TMR5
SPE
MSTR
SPIF
WCOL
MODF
ES
$000B
PA5
SPIE
CA
R
$000A
Bit 0
RTIF
SE
$0009
R
Core Timer Status and
Control — CTSCR
LE
$0008
1
ON
DDRB7
R
Port C Data
Direction — DDRC
2
DU
DDRA6
MIC
$0006
W
3
W
R
SPI Data — SDR
RE
$000C
SPD7
SPD6
SPD5
SPD4
W
R
Unimplemented
YF
$000D
W
R
Unimplemented
CH
IVE
$000F
Unimplemented
DB
$000E
W
R
W
= Unimplemented
R
= Reserved
Figure 2-3. I/O Registers $0000–$000F
AR
Freescale Semiconductor, Inc...
$0005
R
Port A Data
Direction — DDRA
4
0
Port D Data — PORTD
W
$0004
5
MC68HC05V12 — Rev. 1.0
General Release Specification
Memory Map
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A G R E E M E N T
$0000
Read/
Write
N O N - D I S C L O S U R E
Register
CT
OR
, IN
C.2
006
Addr.
R E Q U I R E D
Memory Map
EEPROM
Freescale Semiconductor, Inc.
Register
$0010
Unimplemented
6
5
ICIE
OCIE
ICF
OCF
IC15
IC14
IC7
IC6
OC15
OC14
W
R
$0011
Unimplemented
W
$0019
$001A
$001B
$001C
Input Capture Low — TCAP
(Low)
W
Output Compare
Low — TCMP (Low)
W
W
IC5
IC4
IC3
IC2
IC1
IC0
OC13
OC12
OC11
OC10
OC9
OC8
OC6
OC5
OC4
OC3
OC2
OC1
OC0
CNT14
CNT13
CNT12
CNT11
CNT10
CNT9
CNT8
CNT6
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
AC15
AC14
AC13
AC12
AC11
AC10
AC9
AC8
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
ER1
ER0
EELAT
EERC
EEPGM
CNT15
R
CNT7
R
Alternate Counter
High — ALTCNT (High)
W
Alternate Counter
Low —ALTCNT (Low)
W
R
EEPROM
Programming — EEPROG
OLVL
IC8
R
Timer Counter
Low — TCNT (Low)
IEDG
IC9
OC7
W
TON
IC10
R
Timer Counter
High — TCNT (High)
Bit 0
IC11
R
W
1
IC12
R
Output Compare
High — TCMP (High)
2
TOF
IC13
DU
W
3
TOIE
ON
R
Input Capture High — TCAP
(High)
MIC
$0018
R
SE
$0017
W
LE
$0016
16-Bit Timer
Status — TMRSR
CA
$0015
W
ES
$0014
R
16-Bit Timer
Control — TMRCR
R
RE
$0012
4
CPEN
W
A/D Data — ADDR
YF
R
$001D
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADRC
ADON
CH4
CH3
CH2
CH1
CH0
W
$001E
IRQ Status and
Control — ISCR
R
CH
IVE
$001F
A/D Status and
Control — ADSCR
COCO
W
IRQF
R
IRQE
IPCF
0
IPCE
W
IRQA
= Unimplemented
Figure 2-4. I/O Registers $0010–$001F
AR
A G R E E M E N T
Freescale Semiconductor, Inc...
Bit 7
R
$0013
N O N - D I S C L O S U R E
Read/
Write
CT
OR
, IN
C.2
006
Addr.
DB
R E Q U I R E D
Memory Map
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MC68HC05V12 — Rev. 1.0
Memory Map
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Freescale Semiconductor, Inc.
Gauge Enable — GER
6
5
4
3
2
1
Bit 0
MJAON
MJBON
MIAON
MIBON
MICON
MIDON
CMPS
R
SYNIE
SYNF
R
GCS1
GCS0
SCNS
AUTOS
B5
B4
B3
B2
B1
B0
B5
B4
B3
B2
B1
B0
B5
B4
B3
B2
B1
B0
B5
B3
B2
B1
B0
B3
B2
B1
B0
B4
B3
B2
B1
B0
B6
B5
B4
B3
B2
B1
B0
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
DMJA1
DMJA2
0
0
0
0
0
0
DMJB1
DMJB2
R
W
$0029
$002A
$002B
$002C
$002D
$002E
B6
B7
B6
DU
MAJB2
Magnitude — MAJB2
W
B4
B7
B5
B4
B6
B5
R
R
W
MINA2
Magnitude — MINA2
W
R
B7
R
MINB1
Magnitude — MINB1
W
MINB2
Magnitude — MINB2
W
B7
B6
MIC
MINA1
Magnitude — MINA1
R
B7
R
MINC1
Magnitude — MINC1
W
MINC2
Magnitude — MINC2
W
R
R
MIND1
Magnitude — MIND1
W
R
MAJA Current
Direction — DMAJA
MAJB Current
Direction — DMAJB
W
CH
B7
ON
W
W
R
IVE
$002F
B6
R
MAJB1
Magnitude — MAJB1
MIND2
Magnitude — MIND2
B7
R
SE
$0028
W
B6
LE
$0027
MAJA2
Magnitude — MAJA2
B7
CA
$0026
W
ES
$0025
R
MAJA1
Magnitude — MAJA1
RE
$0024
SYNR
W
R
R
= Reserved
Figure 2-5. I/O Registers $0020–$002F
AR
Freescale Semiconductor, Inc...
$0023
0
W
YF
$0022
R
Scan Status/
Control — SSCR
DB
$0021
MC68HC05V12 — Rev. 1.0
General Release Specification
Memory Map
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A G R E E M E N T
$0020
Bit 7
N O N - D I S C L O S U R E
Register
CT
OR
, IN
C.2
006
Read/
Write
Addr.
R E Q U I R E D
Memory Map
EEPROM
Freescale Semiconductor, Inc.
MINA Current
Direction — DMINA
W
MINB Current
Direction — DMINB
W
$0031
$0032
6
4
3
2
1
Bit 0
0
0
0
0
0
0
0
DMIA
0
0
0
0
0
0
0
DMIB
0
0
0
0
0
0
0
DMIC
0
0
0
0
0
0
0
DMID
R
R
R
R
R
R
R
R
0
OCE
0
0
0
0
0
0
D5
D4
D3
D2
D1
D0
0
0
PSB3A
PSB2A
PSB1A
PSB0A
D3
D2
D1
D0
PSB3B
PSB2B
PSB1B
PSB0B
0
0
IE
WCM
R
R
R
MINC Current
Direction — DMINC
W
MIND Current
Direction — DMIND
W
R
R
$0034
Reserved
W
R
$0035
Miscellaneous — MISCR
ON
W
R
$0036
PWMA Data — PWMAD
POLA
0
R
$0037
PWMA Control — PWMAC
PSA1A
W
R
PWMB Data — PWMBD
POLB
W
R
$0039
PWMB Control — PWMBC
PSA1B
LE
W
R
BDLC Control 1 — BCR1
W
D5
D4
0
0
PSA0B
CLKS
R1
R0
BDLC Control 2 — BCR2
DLBE
RX4XE
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
R
0
0
I3
I2
I1
I0
0
0
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
ATS
RXPOL
0
0
BO3
BO2
BO1
BO0
R
R
R
R
R
R
R
R
ES
ALBE
RE
R
$003B
0
IMSG
CA
$003A
PSA0A
SE
$0038
MIC
W
W
$003C
BDLC State Vector — BSVR
W
BDLC Data — BDATR
YF
R
$003D
W
$003F
BDLC Analog Round Trip
Delay — BARD
Reserved
CH
= One-Time Write
R
DB
$003E
W
R
W
= Unimplemented
R
= Reserved
Figure 2-6. I/O Registers $0030–$003F
AR
A G R E E M E N T
Freescale Semiconductor, Inc...
Bit 7
CT
OR
, IN
C.2
006
$0030
5
DU
Register
$0033
N O N - D I S C L O S U R E
Read/
Write
Addr.
IVE
R E Q U I R E D
Memory Map
General Release Specification
MC68HC05V12 — Rev. 1.0
Memory Map
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The miscellaneous register is located at $0035.
$0035
Bit 7
Read:
0
6
5
0
OCE
Write:
Reset:
0
0
0
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
R E Q U I R E D
2.8 Miscellaneous Register
CT
OR
, IN
C.2
006
Memory Map
Miscellaneous Register
DU
Figure 2-7. Miscellaneous Register (MISC)
OCE — Output Compare Enable
MIC
ON
This bit controls the function of the PB6 pin.
0 = PB6 functions as a normal I/O pin.
1 = PB6 becomes the TCMP output pin for the 16-bit timer.
AR
CH
IVE
DB
YF
RE
ES
N O N - D I S C L O S U R E
CA
LE
SE
See Section 9. 16-Bit Timer for a description of the TCMP function.
MC68HC05V12 — Rev. 1.0
General Release Specification
Memory Map
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A G R E E M E N T
Freescale Semiconductor, Inc...
= Unimplemented
Freescale Semiconductor, Inc.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
CT
OR
, IN
C.2
006
R E Q U I R E D
Memory Map
General Release Specification
MC68HC05V12 — Rev. 1.0
Memory Map
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CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
Section 3. Central Processing Unit (CPU)
3.1 Contents
Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
SE
3.4
MIC
ON
DU
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3.3.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .48
LE
3.2 Introduction
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
RE
3.3 CPU Registers
CH
IVE
DB
YF
Figure 3-1 shows the five CPU registers. CPU registers are not part of
the memory map.
MC68HC05V12 — Rev. 1.0
General Release Specification
Central Processing Unit (CPU)
For More Information On This Product,
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N O N - D I S C L O S U R E
ES
CA
This section describes the CPU registers.
AR
Freescale Semiconductor, Inc...
3.2
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
7
7
0
0
0
0
0
0
0
10
0
1
8
7
0
1
SP
0
PCH
0
PCL
7
1
STACK POINTER (SP)
1
5
4
1
H
I
N
0
Z
C
CONDITION CODE REGISTER (CCR)
MIC
HALF-CARRY FLAG
PROGRAM COUNTER (PC)
DU
0
5
6
INDEX REGISTER (X)
INTERRUPT MASK
NEGATIVE FLAG
SE
ZERO FLAG
LE
CARRY/BORROW FLAG
CA
Figure 3-1. Programming Model
ES
3.3.1 Accumulator
YF
RE
The accumulator (A) is a general-purpose 8-bit register. The CPU uses
the accumulator to hold operands and results of arithmetic and nonarithmetic operations.
6
5
4
3
2
1
Bit 0
DB
Bit 7
Read:
IVE
Write:
CH
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
AR
A G R E E M E N T
Freescale Semiconductor, Inc...
0
X
15
ACCUMULATOR (A)
CT
OR
, IN
C.2
006
A
15
N O N - D I S C L O S U R E
0
ON
R E Q U I R E D
Central Processing Unit (CPU)
General Release Specification
MC68HC05V12 — Rev. 1.0
Central Processing Unit (CPU)
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Freescale Semiconductor, Inc.
The 8-bit index register can also serve as a temporary data storage
location.
Bit 7
6
5
Write:
DU
Reset:
3
2
1
Bit 0
Unaffected by reset
ON
Figure 3-3. Index Register (X)
MIC
3.3.3 Stack Pointer
CA
LE
SE
The stack pointer (SP) is a 16-bit register that contains the address of
the next location on the stack. During a reset or after the reset stack
pointer (RSP) instruction, the stack pointer is preset to $00FF. The
address in the stack pointer decrements as data is pushed onto the
stack and increments as data is pulled from the stack.
YF
RE
ES
The 10 most significant bits of the stack pointer are permanently fixed at
000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations.
An interrupt uses five locations.
14
13
0
0
0
Reset:
CH
Write:
12
IVE
Read:
11
10
9
8
7
6
5
4
3
2
1
Bit
0
0
0
0
0
1
1
1
1
1
1
1
1
DB
Bit
15
0
Figure 3-4. Stack Pointer (SP)
AR
Freescale Semiconductor, Inc...
Read:
4
MC68HC05V12 — Rev. 1.0
General Release Specification
Central Processing Unit (CPU)
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A G R E E M E N T
In the indexed addressingmodes, the CPU uses the byte in the index
register (X) to determine the conditional address of the operand.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
3.3.2 Index Register
R E Q U I R E D
Central Processing Unit (CPU)
CPU Registers
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
3.3.4 Program Counter
The program counter (PC) is a 16-bit register that contains the address
of the next instruction or operand to be fetched. The two most significant
bits of the program counter are ignored internally and appear as 00.
14
0
0
0
0
13
12
11
10
9
Read:
7
6
5
4
3
2
Bit
0
1
5
MIC
Write:
Reset
8
ON
Bit
15
DU
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Loaded with vectors from $3FF3 and $3FFF
LE
SE
Figure 3-5. Program Counter (PC)
CA
3.3.5 Condition Code Register
YF
RE
ES
The condition code register (CCR) is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed. The following paragraphs describe the
functions of the condition code register.
DB
Read:
Bit 7
6
5
1
1
1
4
3
2
1
Bit 0
H
I
N
Z
C
U
1
U
U
U
Write:
CH
IVE
Reset:
1
1
1
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Central Processing Unit (CPU)
General Release Specification
MC68HC05V12 — Rev. 1.0
Central Processing Unit (CPU)
For More Information On This Product,
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Interrupt Mask
ON
DU
Freescale Semiconductor, Inc...
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic zero, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is set, the interrupt request is latched. Normally, the CPU processes
the latched interrupt as soon as the interrupt mask is cleared again.
Negative Flag
SE
MIC
A return from interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After any
reset, the interrupt mask is set and can be cleared only by a software
instruction.
Zero Flag
CA
LE
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result.
RE
ES
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00.
Carry/Borrow Flag
AR
CH
IVE
DB
YF
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
MC68HC05V12 — Rev. 1.0
General Release Specification
Central Processing Unit (CPU)
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A G R E E M E N T
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an ADD or ADC operation. The halfcarry flag is required for binary coded decimal (BCD) arithmetic
operations.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
Half-Carry Flag
R E Q U I R E D
Central Processing Unit (CPU)
CPU Registers
Freescale Semiconductor, Inc.
The arithmetic/logic unit (ALU) performs the arithmetic and logical
operations defined by the instruction set.
The binary arithmetic circuits decode instructions and set up the ALU for
the selected operation. Most binary arithmetic is based on the addition
algorithm, carrying out subtraction as negative addition. Multiplication is
not performed as a discrete operation but as a chain of addition and shift
operations within the ALU. The multiply instruction (MUL) requires 11
internal clock cycles to complete this chain of operations.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
3.4 Arithmetic/Logic Unit
A G R E E M E N T
R E Q U I R E D
Central Processing Unit (CPU)
General Release Specification
MC68HC05V12 — Rev. 1.0
Central Processing Unit (CPU)
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.3
CPU Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.4
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.5
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.6
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
DU
4.2
ON
Freescale Semiconductor, Inc...
4.1 Contents
SE
MIC
4.7
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
4.7.1
IRQ Status and Control Register. . . . . . . . . . . . . . . . . . . . .58
4.7.2
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .60
16-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.9
BDLC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.10
SPI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.11
8-Bit Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.12
Gauge Synchronize Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.13
Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
AR
CH
IVE
DB
YF
RE
ES
CA
LE
4.8
MC68HC05V12 — Rev. 1.0
General Release Specification
Interrupts
For More Information On This Product,
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A G R E E M E N T
Section 4. Interrupts
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
4.2 Introduction
The MCU can be interrupted eight different ways:
1. Non-Maskable Software Interrupt Instruction (SWI)
2. External Asynchronous Interrupt (IRQ)
3. External Interrupt via IRQ on PC0–PC7 (IRQ)
4. Internal 16-Bit Timer Interrupt (TIMER)
5. Internal BDLC Interrupt (BDLC)
DU
6. Internal Serial Peripheral Interface Interrupt (SPI)
7. Internal 8-Bit Timer Interrupt (CTIMER)
MIC
ON
8. Internal Gauge Interrupt (GAUGE)
SE
4.3 CPU Interrupt Processing
CA
LE
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
CH
IVE
DB
YF
RE
ES
If interrupts are not masked (I bit in the CCR is clear) and the
corresponding interrupt enable bit is set, then the processor will proceed
with interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, then stacks the current CPU register states, sets the I bit to
inhibit further interrupts, and finally checks the pending hardware
interrupts. If more than one interrupt is pending after the stacking
operation, the interrupt with the highest vector location shown in
Table 4-1 will be serviced first. The SWI is executed the same as any
other instruction, regardless of the I-bit state.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Interrupts
General Release Specification
MC68HC05V12 — Rev. 1.0
Interrupts
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Freescale Semiconductor, Inc.
Vector
Address
RESET
$3FFE-$3FFF
Software
SWI
$3FFC-$3FFD
IRQF/IPCF
External
(IRQ & Port C)
IRQ
$3FFA-$3FFB
TSR
TOF
Timer Overflow
DU
TIMER
$3FF8-$3FF9
TSR
OCF
Output Compare
TIMER
$3FF8-$3FF9
TSR
ICF
Input Capture
TIMER
$3FF8-$3FF9
BSVR
I3:I0
BDLC
BDLC
$3FF6-$3FF7
SPSR
SPIF
SPI
SPI
$3FF4-$3FF5
CTSCR
CTOF
Core Timer
Overflow
CTIMER
$3FF2-$3FF3
CTSCR
RTIF
LE
Real Time
CTIMER
$3FF2-$3FF3
SYNF
Gauge Synchronize
GAUGE
$3FF0-$3FF1
N/A
N/A
Reset
N/A
N/A
ISCR
MIC
SE
ES
SSCR
Interrupts
ON
Flag Name
YF
RE
Because the M68HC05 CPU does not support interruptible instructions,
the maximum latency to the first instruction of the interrupt service
routine must include the longest instruction execution time plus stacking
overhead.
DB
Latency = (Longest instruction execution time + 10) x tCYC secs
AR
CH
IVE
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the register contents to
be recovered from the stack and normal processing to resume at the
next instruction that was to be executed when the interrupt took place.
Figure 4-1 shows the sequence of events that occur during interrupt
processing.
MC68HC05V12 — Rev. 1.0
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Interrupts
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A G R E E M E N T
CPU
Interrupt
Register
CA
Freescale Semiconductor, Inc...
Table 4-1. Vector Address for Interrupts and Reset
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $3FF0 through $3FFF as defined in Table 4-1.
R E Q U I R E D
Interrupts
CPU Interrupt Processing
Freescale Semiconductor, Inc.
R E Q U I R E D
Interrupts
CT
OR
, IN
C.2
006
FROM
RESET
I BIT
IN CCR
SET?
Y
N
PORT C
OR IRQ
INTERRUPT?
Y
CLEAR IRQ
REQUEST LATCH
N
ON
Y
N
Y
SE
SPI
INTERRUPT?
MIC
BDLC
INTERRUPT?
N
DU
Y
16-BIT TIMER
INTERRUPT?
Y
CA
LE
8-BIT TIMER
INTERRUPT?
STACK
PC, X, A, CCR
Y
ES
N
GAUGE
INTERRUPT?
RE
N
FETCH NEXT INSTRUCTION
DB
YF
SWI
INSTRUCTION
?
CH
IVE
Y
RESTORE REGISTERS
FROM STACK:
CCR, A, X, PC
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
N
SET I BIT IN
CC REGISTER
Y
LOAD PC FROM
APPROPRIATE
VECTOR
N
RTI
INSTRUCTION
?
N
EXECUTE
INSTRUCTION
Figure 4-1. Interrupt Processing Flowchart
General Release Specification
MC68HC05V12 — Rev. 1.0
Interrupts
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LE
SE
MIC
ON
The SWI is an executable instruction and a non-maskable interrupt since
it is executed regardless of the state of the I bit in the CCR. If the I bit is
zero (interrupts enabled), the SWI instruction executes after interrupts
which were pending before the SWI was fetched or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $3FFC and
$3FFD.
CA
4.6 Hardware Interrupts
YF
RE
ES
All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. Two types
of hardware interrupts are explained in the following paragraphs.
DB
4.7 External Interrupt (IRQ)
The BIH and BIL instructions will apply only to the level on the IRQ pin
itself and not to the output of the logic OR function with the port C IRQ
interrupts. The state of the individual port C pins can be checked by
reading the appropriate port C pins as inputs.
CH
NOTE:
IVE
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in Figure 4-2.
MC68HC05V12 — Rev. 1.0
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Interrupts
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A G R E E M E N T
DU
4.5 Software Interrupt (SWI)
AR
Freescale Semiconductor, Inc...
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner as shown in Figure 4-1. A low level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address which is specified by the
contents of memory locations $3FFE and $3FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during this type of reset as described in Section 5. Resets.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
4.4 Reset Interrupt Sequence
R E Q U I R E D
Interrupts
Reset Interrupt Sequence
Freescale Semiconductor, Inc.
IRQ PIN
CT
OR
, IN
C.2
006
R E Q U I R E D
Interrupts
VDD
IRQ
LATCH
IRQ VECTOR FETCH
R
RST
IRQA
IRQF
DU
IRQE
TO IRQ
PROCESSING
IN CPU
ON
PC0
MIC
VDD
DRC0
DDRC0
IPCF
IRQPC
LATCH
SE
DDRC7
DRC0
R
LE
PC7
CA
IPCE
ES
Figure 4-2. IRQ Function Block Diagram
DB
YF
RE
The IRQ pin is one source of an external interrupt. All port C pins (PC0
through PC7) act as other external interrupt sources. These sources
have their own interrupt latch but are combined with IRQ into a single
external interrupt request.
IVE
The port C interrupt sources are negative (falling) edge-sensitive only.
Note that all port C pins are ANDed together to form the negative edge
signal which sets the corresponding flag bits. A high-to-low transition on
any port C pin configured as an interrupt input will, therefore, set the
respective flag bit. If a port C pin is to be used as an interrupt input, the
corresponding data direction and data bits must both be cleared. If either
the pin is configured as an output or the data bit is set, a falling edge on
the pin will not generate an interrupt. The IRQ pin interrupt source may
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
LEVEL
(MASK OPTION)
TO BIH & BIL
INSTRUCTION
SENSING
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MC68HC05V12 — Rev. 1.0
Interrupts
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CT
OR
, IN
C.2
006
be selected to be either edge sensitive or edge and level sensitive
through a mask option. If the edge-sensitive interrupt option is selected
for the IRQ pin, only the IRQ latch output can activate an IRQF flag which
creates an interrupt request to the CPU to generate the external interrupt
sequence.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to
the following cases:
R E Q U I R E D
Interrupts
External Interrupt (IRQ)
ON
If the edge and level mask option is selected, the active low state of the
IRQ pin can also activate an IRQF flag which creates an IRQ request to
the CPU to generate the IRQ interrupt sequence.
MIC
When edge and level sensitivity are selected for the IRQ interrupt, it is
sensitive to the following cases:
SE
1. Low level on the IRQ pin
LE
2. Falling edge on the IRQ pin
CA
3. Falling edge on any port C pin with IRQ enabled
YF
RE
ES
The IRQE enable bit controls whether an active IRQF flag (IRQ pin
interrupt) can generate an IRQ interrupt sequence. The IPCE enable bit
controls whether an active IPCF flag (port C interrupt) can generate an
IRQ interrupt sequence. The IRQ interrupt is serviced by the interrupt
service routine located at the address specified by the contents of
$3FFA and $3FFB.
AR
CH
IVE
DB
The IRQF latch is cleared automatically by entering the interrupt service
routine to maintain compatibility with existing M6805 interrupt servicing
protocol. To allow the user to identify the source of the interrupt, the port
interrupt flag (IPCF) is not cleared automatically. This flag must be
cleared within the interrupt handler prior to exit to prevent repeated reentry. This is achieved by writing a logic one to the IRQA (IRQ
acknowledge) bit, which will clear all pending IRQ interrupts (including a
pending IRQ pin interrupt).
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A G R E E M E N T
DU
2. Falling edge on any port C pin with IRQ enabled
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
1. Falling edge on the IRQ pin
Freescale Semiconductor, Inc.
NOTE:
CT
OR
, IN
C.2
006
The interrupt request flag (IPCF) is read only and cannot be cleared by
writing to it. The acknowledge flag always reads as a logic 0. Together,
these features permit the safe use of read-modify-write instructions (for
instance, BSET and BCLR) on the ISCR.
Although read-modify-write instruction use is allowable on the ISCR,
shift operations should be avoided due to the possibility of inadvertently
setting the IRQA.
DU
4.7.1 IRQ Status and Control Register
Bit 7
6
Read:
0
IRQE
5
4
3
2
1
Bit 0
0
IRQF
0
IPCF
0
0
0
IPCE
SE
Write:
1
0
IRQA
0
0
0
0
LE
Reset:
MIC
$001F
ON
The IRQ interrupt function is controlled by the IRQ status and control
register (ISCR) located at $001F. All unused bits in the ISCR will read as
logic zeros. The IRQF bit is cleared and IRQE bit is set by reset.
= Unimplemented
CA
Figure 4-3. IRQ Status and Control Register (ISCR)
ES
IRQE − IRQ Interrupt Enable
IVE
DB
YF
RE
The IRQE bit controls whether the IRQF flag bit can or cannot initiate
an IRQ interrupt sequence. If the IRQE enable bit is set, the IRQF flag
bit can generate an interrupt sequence. If the IRQE enable bit is
cleared, the IRQF flag bit cannot generate an interrupt sequence.
Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once
the I bit is cleared. Execution of the STOP or WAIT instructions
causes the IRQE bit to be set to allow the external IRQ to exit these
modes. In addition, reset also sets the I bit, which masks all interrupt
sources.
CH
IPCE − Port C IRQ Interrupt Enable
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Interrupts
The IPCE bit controls whether the IPCF flag bit can or cannot initiate
an IRQ interrupt sequence. If the IPCE enable bit is set, the IPCF flag
bit will generate an interrupt sequence. If the IPCE enable bit is
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Interrupts
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The IPCE mask bit must be set prior to entering stop or wait modes if port
IRQ interrupts are to be enabled.
Freescale Semiconductor, Inc...
IRQF − IRQ Interrupt Request
CA
LE
SE
MIC
ON
DU
The IRQF flag bit indicates that an IRQ request is pending. Writing to
the IRQF flag bit will have no effect on it. The IRQF flag bit is cleared
when the IRQ vector is fetched prior to the service routine being
entered. The IRQF flag bit can also be cleared by writing a logic one
to the IRQA acknowledge bit to clear the IRQ latch. In this way any
additional IRQF flag bit that is set while in the service routine can be
ignored by clearing the IRQF flag bit before exiting the service routine.
If the additional IRQF flag bit is not cleared in the IRQ service routine
and the IRQE enable bit remains set, the CPU will re-enter the IRQ
interrupt sequence continuously until either the IRQF flag bit or the
IRQE enable bit is clear. This flag can be set only when the IRQE
enable is set. The IRQ latch is cleared by reset.
IPCF − Port C IRQ Interrupt Request
DB
YF
RE
ES
The IPCF flag bit indicates that a port C IRQ request is pending.
Writing to the IPCF flag bit will have no effect on it. The IPCF flag bit
must be cleared by writing a logic 1 to the IRQA acknowledge bit. If
the IPCF bit is not cleared via IRQA, the CPU will re-enter the IRQ
interrupt sequence continuously until either the IPCF flag bit or the
IPCE enable bit is clear. This bit is operational regardless of the state
of the IPCE bit. The IPCF bit is cleared by reset.
AR
CH
IVE
IRQA − IRQ Interrupt Acknowledge
The IRQA acknowledge bit clears an IRQ interrupt by clearing the
IRQF and IPCF bits. This is achieved by writing a logic 1 to the IRQA
acknowledge bit. Writing a logic 0 to the IRQA acknowledge bit will
have no effect on the any of the IRQ bits. If either the IRQF or IPCF
bit is not cleared within the IRQ service routine, then the CPU will reenter the IRQ interrupt sequence continuously until the IRQ flag bits
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Interrupts
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A G R E E M E N T
NOTE:
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
cleared, the IPCF flag bit will not generate an interrupt sequence.
Reset clears the IPCE enable bit, thereby disabling port C IRQ
interrupts. In addition, reset also sets the I bit, which masks all
interrupt sources. Execution of the STOP or WAIT instructions does
not effect the IPCE bit.
R E Q U I R E D
Interrupts
External Interrupt (IRQ)
Freescale Semiconductor, Inc.
NOTE:
CT
OR
, IN
C.2
006
are all cleared. The IRQA is useful for cancelling unwanted or
spurious interrupts which may have occurred while servicing the initial
IRQ interrupt.
The IRQ flag is cleared automatically during the IRQ vector fetch. The
IRQPC latch is not cleared automatically (to permit interrupt source
differentiation as long as the Interrupt source is present) and must be
cleared from within the IRQ service routine.
DU
4.7.2 External Interrupt Timing
SE
MIC
ON
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
the IRQ source. It is then synchronized internally and serviced as
specified by the contents of $3FFA and $3FFB. The IRQ timing diagram
is shown in Figure 4-4.
CA
tILIL
tILIH
RE
ES
IRQ1 (PORT)
.
.
.
tILIH
LE
IRQ
CH
IVE
DB
YF
IRQn (PORT)
IRQ
(MCU)
Figure 4-4. External Interrupts Timing Diagram
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Interrupts
General Release Specification
MC68HC05V12 — Rev. 1.0
Interrupts
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MIC
4.9 BDLC Interrupt
SE
The interrupt service routine is located at the address specified by the
contents of memory location $3FF6 and $3FF7.
LE
4.10 SPI Interrupt
YF
RE
ES
CA
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory location
$3FF4 and $3FF5.
DB
4.11 8-Bit Timer Interrupt
CH
IVE
This timer can create two types of interrupts. A timer overflow interrupt
will occur whenever the 8-bit timer rolls over from $FF to $00 and the
enable bit TOFE is set. A real-time interrupt will occur whenever the
programmed time elapses and the enable bit RTIE is set. This interrupt
will vector to the interrupt service routine located at the address specified
by the contents of memory location $3FF2 and $3FF3.
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Interrupts
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A G R E E M E N T
ON
DU
Three different timer interrupt flags cause a 16-bit timer interrupt
whenever they are set and enabled. The interrupt flags are in the timer
status register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
location $3FF8 and $3FF9.
AR
Freescale Semiconductor, Inc...
4.8 16-Bit Timer Interrupt
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitiveonly trigger is available as a mask option for the IRQ pin only.
R E Q U I R E D
Interrupts
16-Bit Timer Interrupt
Freescale Semiconductor, Inc.
This interrupt service routine is located at the address specified by the
contents of memory location $3FF0 and $3FF1. See 15.6.2 Current
Magnitude Registers for further details.
4.13 Stop and Wait Modes
All modules which are capable of generating interrupts in stop or wait
mode will be allowed to do so if the module is configured properly. The I
bit is cleared automatically when stop or wait mode is entered. Interrupts
detected on port C are recognized in stop or wait mode if port C
interrupts are enabled.
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
4.12 Gauge Synchronize Interrupt
A G R E E M E N T
R E Q U I R E D
Interrupts
General Release Specification
MC68HC05V12 — Rev. 1.0
Interrupts
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5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
ES
CA
LE
SE
MIC
ON
DU
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.4.1
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.4.2
Computer Operating Properly Reset (COPR) . . . . . . . . . . .66
5.4.2.1
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.2.2
COP during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.2.3
COP during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.4.2.4
COP Watchdog Timer Considerations . . . . . . . . . . . . . . .67
5.4.2.5
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
5.4.3
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.4
Disabled STOP Instruction Reset . . . . . . . . . . . . . . . . . . . .69
5.4.5
Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . .69
5.4.6
LVR Operation in Stop and Wait Modes . . . . . . . . . . . . . . .70
RE
5.2 Introduction
CH
IVE
DB
YF
The MCU can be reset from six sources: one external input and five
internal restart conditions. The RESET pin is an input with a Schmitt
trigger as shown in Figure 5-1. All the internal peripheral modules will be
reset by the internal reset signal (RST). Refer to Figure 5-2 for reset
timing detail.
AR
Freescale Semiconductor, Inc...
5.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Resets
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A G R E E M E N T
Section 5. Resets
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
IRQ
TO IRQ
LOGIC
D
LATCH
RESET
MODE
SELECT
R
(PULSE WIDTH = 3 x tCYC)
CLOCKED
ONE-SHOT
PH2
OSC
DATA
ADDRESS
ADDRESS
ILLEGAL ADDRESS
(ILADDR)
STOPEN
DISABLED STOP
INSTRUCTION
ON
VDD
POWER-ON RESET
(POR)
S
D
LATCH
CPU
RST
TO OTHER
PERIPHERALS
PH2
MIC
LOW-VOLTAGE
RESET (LVR)
SE
VDD
DU
COP WATCHDOG
(COPR)
ES
5.3 External Reset (RESET)
CA
LE
Figure 5-1. Reset Block Diagram
Activation of the RST signal is generally referred to as reset of the
device, unless otherwise specified.
CH
NOTE:
IVE
DB
YF
RE
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the
upper threshold. This active low input will generate the RST signal and
reset the CPU and peripherals.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Resets
The RESET pin can also act as an open drain output. It will be pulled to
a low state by an internal pulldown that is activated by any reset source.
This RESET pulldown device will only be asserted for three to four
General Release Specification
MC68HC05V12 — Rev. 1.0
Resets
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Freescale Semiconductor, Inc.
MIC
5.4.1 Power-On Reset (POR)
LE
SE
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor bus clock
cycles (PH2) after the oscillator becomes active.
ES
CA
The POR will generate the RST signal which will reset the CPU. If any
other reset function is active at the end of this 4064-cycle delay, the RST
signal will remain in the reset condition until the other reset condition(s)
end.
CH
IVE
DB
YF
RE
POR will activate the RESET pin pulldown device connected to the pin.
VDD must drop below VPOR for the internal POR circuit to detect the next
rise of VDD.
MC68HC05V12 — Rev. 1.0
General Release Specification
Resets
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A G R E E M E N T
ON
DU
The five internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, the illegal address detector, the
low-voltage reset, and the disabled STOP instruction. All internal resets
will also assert (pull to logic 0) the external RESET pin for the duration
of the reset or three to four internal clock cycles, whichever is longer.
AR
Freescale Semiconductor, Inc...
5.4 Internal Resets
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
cycles of the internal clock, fOP, or as long as an internal reset source is
asserted. When the external RESET pin is asserted, the pulldown device
will be turned on for only the three to four internal clock cycles.
R E Q U I R E D
Resets
Internal Resets
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
VDD
0V
OSC12
4064 tcyc
3FFF
INTERNAL
DATA
BUS 1
NEW
PCH
NEW
PCL
NEW PC NEW PC
3FFE
ON
3FFE
OP
CODE
MIC
INTERNAL
ADDRESS
1
BUS
DU
tcyc
INTERNAL
PROCESSOR
CLOCK1
3FFE
3FFE
3FFE
3FFF
PCH
PCL
NEW PC NEW PC
OP
CODE
tRL
3
LE
SE
RESET
ES
CA
NOTES:
1.
Internal timing signal and bus information are not available externally.
2.
OSC1 line is not meant to represent frequency. It is only used to represent time.
3.
The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
RE
Figure 5-2. RESET and POR Timing Diagram
YF
5.4.2 Computer Operating Properly Reset (COPR)
CH
IVE
DB
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. Regardless of an internal or external
RESET, the MCU comes out of a COP reset according to the pin
conditions that determine mode selection.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Resets
The COP reset function is enabled or disabled by the COP mask option.
General Release Specification
MC68HC05V12 — Rev. 1.0
Resets
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DU
5.4.2.2 COP during Wait Mode
MIC
ON
The COP will continue to operate normally during wait mode. The
system should be configured to pull the device out of wait mode
periodically and reset the COP by writing to the COPR bit to prevent a
COP reset.
SE
5.4.2.3 COP during Stop Mode
YF
RE
ES
CA
LE
When the STOP enable mask option is selected, stop mode disables the
oscillator circuit and thereby turns the clock off for the entire device. The
COP counter will be reset when stop mode is entered. If a reset is used
to exit stop mode, the COP counter will be held in reset during the 4064
cycles of startup delay. If any operable interrupt is used to exit stop
mode, the COP counter will not be reset during the 4064-cycle startup
delay and will have that many cycles already counted when control is
returned to the program.
DB
5.4.2.4 COP Watchdog Timer Considerations
CH
IVE
The COP watchdog timer is active in user mode if enabled by the COP
mask option. If the COP watchdog timer is selected, any execution of the
STOP instruction (either intentional or inadvertent due to the CPU being
disturbed) will cause the oscillator to halt and prevent the COP watchdog
timer from timing out. Therefore, it is recommended that the STOP
instruction should be disabled if the COP watchdog timer is enabled.
AR
Freescale Semiconductor, Inc...
Preventing a COP reset is done by writing a 0 to the COPR bit. This
action will reset the counter and begin the timeout period again. The
COPR bit is bit 0 of address $3FF0. A read of address $3FF0 will return
user data programmed at that location.
If the COP watchdog timer is selected, the COP will reset the MCU when
it times out. Therefore, it is recommended that the COP watchdog
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
5.4.2.1 Resetting the COP
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
The COP watchdog reset will activate the internal pulldown device
connected to the RESET pin.
R E Q U I R E D
Resets
Internal Resets
Freescale Semiconductor, Inc.
R E Q U I R E D
Resets
CT
OR
, IN
C.2
006
should be disabled for a system that must have intentional uses of the
wait mode for periods longer than the COP timeout period.
The recommended interactions and considerations for the COP
watchdog timer, STOP instruction, and WAIT instruction are
summarized in Table 5-1.
Table 5-1. COP Watchdog Timer Recommendations
THEN the COP Watchdog
Timer should be as follows:
WAIT Time
Converted to Reset
WAIT Time Less Than
COP Timeout
Enable or Disable COP
Converted to Reset
WAIT Time MORE than
COP Timeout
Disable COP
Acts as STOP
Any Length WAIT Time
Disable COP
ON
MIC
SE
5.4.2.5 COP Register
DU
STOP Instruction
ES
CA
LE
The COP register is shared with the MSB of an unimplemented user
interrupt vector as shown in Figure 5-3. Reading this location will return
whatever user data has been programmed at this location. Writing a 0 to
the COPR bit in this location will clear the COP watchdog timer.
Read:
6
5
4
3
2
1
Bit 0
X
X
X
X
X
X
X
X
YF
Write:
BIt 7
RE
$3FF0
X
X
X
X
X
X
X
X
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
CH
IVE
DB
Reset:
COPR
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
IF the following conditions exist:
General Release Specification
MC68HC05V12 — Rev. 1.0
Resets
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5.4.4 Disabled STOP Instruction Reset
MIC
ON
DU
When the mask option is selected to disable the STOP instruction,
execution of a STOP instruction results in an internal reset. This
activates the internal pulldown device connected to the RESET pin.
5.4.5 Low-Voltage Reset (LVR)
YF
RE
ES
CA
LE
SE
The internal low voltage (LVR) reset is generated when VDD falls below
the LVR threshold, VLVRI, and will be released following a POR delay
starting when VDD rises above VLVRR. The LVR threshold is tested to be
above the minimum operating voltage of the microcontroller and is
intended to assure that the CPU will be held in reset when the VDD
supply voltage is below reasonable operating limits. A mask option is
provided to disable the LVR when the device is expected to normally
operate at low voltages. Note that the VDD rise and fall slew rates
(SVDDR and SVDDF) must be within the specification for proper LVR
operation. If the specification is not met, the circuit will operate properly
following a delay of VDD/slew rate.
IVE
DB
The LVR will generate the RST signal which will reset the CPU and other
peripherals. The low-voltage reset will activate the internal pulldown
device connected to the RESET pin.
CH
If any other reset function is active at the end of the LVR reset signal, the
RST signal will remain in the reset condition until the other reset
condition(s) end.
AR
Freescale Semiconductor, Inc...
The illegal address reset will activate the internal pulldown device
connected to the RESET pin.
MC68HC05V12 — Rev. 1.0
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Resets
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A G R E E M E N T
An illegal address reset is generated when the CPU attempts to fetch an
instruction from either unimplemented address space ($01C0 to $023F
and $0340 to $0CFF) or I/O address space ($0000 to $003F).
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
5.4.3 Illegal Address Reset
R E Q U I R E D
Resets
Internal Resets
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
5.4.6 LVR Operation in Stop and Wait Modes
If enabled, the LVR supply voltage sense option is active during stop and
wait modes. Any reset source can bring the MCU out of stop or wait
mode.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Resets
General Release Specification
MC68HC05V12 — Rev. 1.0
Resets
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.3
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
6.4
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
6.5
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
MIC
ON
DU
6.2
6.2 Introduction
YF
6.3 STOP Instruction
RE
ES
CA
LE
SE
The MC68HC705V12 is capable of running in one of several low-power
operational modes. The WAIT and STOP instructions provide two
modes that reduce the power required for the MCU by stopping various
internal clocks and/or the on-chip oscillator. The STOP and WAIT
instructions are not normally used if the COP watchdog timer is enabled.
A programmable mask option is provided to convert the STOP
instruction to an internal reset. The flow of the stop and wait modes is
shown in Figure 6-2.
CH
IVE
DB
The STOP instruction can result in one of two operations depending on
the state of the mask option. If the STOP option is enabled, the STOP
instruction operates like the STOP in normal MC68HC05 Family
members and places the device in the low-power stop mode. If the
STOP option is disabled, the STOP instruction will cause a chip reset
when executed.
AR
Freescale Semiconductor, Inc...
6.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Low-Power Modes
For More Information On This Product,
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A G R E E M E N T
Section 6. Low-Power Modes
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
6.4 Stop Mode
Execution of the STOP instruction with the mask option enabled places
the MCU in its lowest power consumption mode. In stop mode, the
internal oscillator is turned off, halting all internal processing, including
the COP watchdog timer.
During stop mode, the TCR bits are altered to remove any pending timer
interrupt request and to disable any further timer interrupts. The timer
prescaler is cleared. The I bit in the CCR is cleared and the IRQE mask
is set in the ICSR to enable external interrupts. All other registers and
memory remain unaltered. All input/output lines remain unchanged.
DU
ON
The MCU can be brought out of the stop mode only by:
An IRQ pin external interrupt
•
An externally generated reset
•
A falling edge on any port C pin (if enabled) or
•
A rising edge on the BDLC RXP pin
SE
MIC
•
CA
LE
When exiting the stop mode, the internal oscillator will resume after a
4064 internal processor clock cycle oscillator stabilization delay as
shown in Figure 6-1.
NOTE:
CH
IVE
DB
YF
RE
ES
Entering stop mode will cause the oscillator to stop and, therefore,
disable the COP watchdog timer. If the COP watchdog timer is to be
used, stop mode should be disabled by disabling the mask option.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Low-Power Modes
General Release Specification
MC68HC05V12 — Rev. 1.0
Low-Power Modes
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tLIH
IRQ2
tILCH
4064 tcyc
RXP
DU
IDLE
ON
INTERNAL
CLOCK
3FFE
3FFE
3FFE
3FFE
SE
MIC
INTERNAL
ADDRESS
BUS
NOTES:
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive mask option or port C pin
3. IRQ pin level- and edge-sensitive mask option
3FFF
CA
LE
RESET OR INTERRUPT
VECTOR FETCH
(RESET SHOWN)
CH
IVE
DB
YF
RE
ES
Figure 6-1. Stop Recovery Timing Diagram
AR
Freescale Semiconductor, Inc...
IRQ3
MC68HC05V12 — Rev. 1.0
General Release Specification
Low-Power Modes
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A G R E E M E N T
tRL
RESET
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
OSC11
R E Q U I R E D
Low-Power Modes
Stop Mode
Freescale Semiconductor, Inc.
STOP
ENABLED?
CT
OR
, IN
C.2
006
STOP
N
WAIT
RESET CHIP
Y
EXTERNAL OSCILLATOR ACTIVE,
AND INTERNAL
TIMER CLOCK ACTIVE
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
AND RESET STARTUP DELAY
DU
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I BIT IN CCR
ON
Y
EXTERNAL
RESET?
IRQ
EXTERNAL
INTERRRUPT?
MIC
N
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I BIT IN CCR
Y
Y
CA
Y
END
OF STARTUP
DELAY
ES
N
Y
PORT C FALLING
EDGE?
Y
LE
RXP RISING
EDGE?
Y
RE
YF
2.
RESTART
INTERNAL PROCESSOR CLOCK
FETCH RESET VECTOR
OR
SERVICE INTERRUPT
A. STACK
B. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
IVE
DB
1.
TIMER
INTERNAL
INTERRUPT?
N
Y
N
N
IRQ
EXTERNAL
INTERRUPT?
N
RESTART EXTERNAL OSCILLATOR,
AND STABILIZATION DELAY
N
EXTERNAL
RESET?
N
SE
Y
RXP RISING
EDGE?
N
Y
PORT C
FALLING
EDGE?
N
Y
GAUGE
SEQUENCE
INTERRUPT?
N
Y
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Low-Power Modes
SPI
INTERRUPT?
N
Figure 6-2. Stop/Wait Flowcharts
General Release Specification
MC68HC05V12 — Rev. 1.0
Low-Power Modes
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The WAIT instruction places the MCU in a low-power mode, which
consumes more power than stop mode. In wait mode, the internal
processor clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be
generated from the timer or a reset to be generated from the COP
watchdog timer. Execution of the WAIT instruction automatically clears
the I bit in the condition code register. All other registers, memory, and
input/output lines remain in their previous states.
ON
DU
If timer interrupts are enabled, a timer interrupt will cause the processor
to exit the wait mode and resume normal operation. The timer may be
used to generate a periodic exit from the wait mode. The MCU can be
brought out of the wait mode by:
A TIMER interrupt from either timer
•
An SPI interrupt
•
An IRQ pin external interrupt
•
An externally generated RESET
•
A falling edge on any port C pin (if enabled)
•
A rising edge on the BDLC RXP pin or
•
A gauge sequence interrupt
AR
CH
IVE
DB
YF
RE
ES
N O N - D I S C L O S U R E
CA
LE
SE
MIC
•
MC68HC05V12 — Rev. 1.0
General Release Specification
Low-Power Modes
For More Information On This Product,
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A G R E E M E N T
CT
OR
, IN
C.2
006
6.5 WAIT Instruction
R E Q U I R E D
Low-Power Modes
WAIT Instruction
Freescale Semiconductor, Inc.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
CT
OR
, IN
C.2
006
R E Q U I R E D
Low-Power Modes
General Release Specification
MC68HC05V12 — Rev. 1.0
Low-Power Modes
For More Information On This Product,
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CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
Section 7. Parallel Input/Output (I/O)
7.1 Contents
DU
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
7.3.2
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . .79
MIC
ON
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.4.2
Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . .80
ES
7.2 Introduction
CH
IVE
DB
YF
RE
In single-chip mode, 23 bidirectional input/output (I/O) lines are arranged
as two 8-bit I/O ports (ports B and C), and one 7-bit I/O port (port A).
There is one 5-bit input port (port D). The individual bits in the I/O ports
are programmable as either inputs or outputs under software control by
the data direction registers (DDRs). The port C pins also have the
additional property of acting as IRQ interrupt input sources.
MC68HC05V12 — Rev. 1.0
General Release Specification
Parallel Input/Output (I/O)
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N O N - D I S C L O S U R E
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
CA
7.6
LE
SE
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.5.1
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.5.2
Port C Data Direction Register . . . . . . . . . . . . . . . . . . . . . .81
7.5.3
Port C I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .81
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
AR
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7.2
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
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OR
, IN
C.2
006
7.3 Port A
Port A is a 7-bit bidirectional port which functions as shown in
Figure 7-1. Each pin is controlled by the corresponding bit in a data
direction register and a data register. The port A data register is located
at address $0000. The port A data direction register (DDRA) is located
at address $0004. Reset clears DDRA. The port A data register is
unaffected by reset.
WRITE $0004
ON
DATA DIRECTION
REGISTER BIT
WRITE $0000
OUTPUT
I/O
PIN
MIC
DATA
REGISTER BIT
SE
READ $0000
LE
RESET
(RST)
CA
INTERNAL HC05
DATA BUS
DU
READ $0004
RE
7.3.1 Port A Data Register
ES
Figure 7-1. Port A I/O Circuitry
CH
IVE
DB
YF
Each port A I/O pin has a corresponding bit in the port A data register.
When a port A pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port A pin is programmed as an input, any read of the port A data
register will return the logic state of the corresponding I/O pin. The port
A data register is unaffected by reset.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Parallel Input/Output (I/O)
General Release Specification
MC68HC05V12 — Rev. 1.0
Parallel Input/Output (I/O)
For More Information On This Product,
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Freescale Semiconductor, Inc.
ES
CA
LE
SE
MIC
ON
DU
Port B is an 8-bit bidirectional port. Each port B pin is controlled by the
corresponding bits in a data direction register and a data register as
shown in Figure 7-2. PB5 and PB4 are shared with the PWMs as shown
in Section 11. Pulse Width Modulators (PWMs), PB7 and PB6 are
shared with 16-bit timer functions. See Section 9. 16-Bit Timer for timer
description. PB0-PB3 are shared with the SPI as shown in Section 10.
Serial Peripheral Interface (SPI). The port B data register is located at
address $0001. The port B data direction register (DDRB) is located at
address $0005. Reset clears the DDRB register. The port B data register
is unaffected by reset.
READ $0005
RE
WRITE $0005
WRITE $0001
OUTPUT
I/O
PIN
DB
DATA
REGISTER BIT
IVE
READ $0001
RESET
(RST)
CH
INTERNAL HC05
DATA BUS
16-BIT TIMER,
PMWs, AND
SPI MUX LOGIC
YF
DATA DIRECTION
REGISTER BIT
AR
Freescale Semiconductor, Inc...
7.4 Port B
Figure 7-2. Port B I/O Circuitry
MC68HC05V12 — Rev. 1.0
General Release Specification
Parallel Input/Output (I/O)
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A G R E E M E N T
Each port A I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRA or programmed as an output by setting
the corresponding bit in the DDRA. The DDRA can be accessed at
address $0004 and is cleared by reset.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
7.3.2 Port A Data Direction Register
R E Q U I R E D
Parallel Input/Output (I/O)
Port B
Freescale Semiconductor, Inc.
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OR
, IN
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006
7.4.1 Port B Data Register
Each port B I/O pin has a corresponding bit in the port B data register.
When a port B pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port B pin is programmed as an input, any read of the port B data
register will return the logic state of the corresponding I/O pin. The port
B data register is unaffected by reset.
7.4.2 Port B Data Direction Register
MIC
ON
DU
Each port B I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRB or programmed as an output by setting
the corresponding bit in the DDRB. The DDRB can be accessed at
address $0005. The DDRB is cleared by reset.
SE
7.5 Port C
CH
IVE
DB
YF
RE
ES
CA
LE
Port C is an 8-bit bidirectional port shared with the IRQ interrupt
subsystem as shown in Figure 7-3. Each pin is controlled by the
corresponding bits in a data direction register and a data register. The
port C data register is located at address $0002. The port C data
direction register (DDRC) is located at address $0006. Reset clears
DDRC. The port C data register is unaffected by reset.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Parallel Input/Output (I/O)
General Release Specification
MC68HC05V12 — Rev. 1.0
Parallel Input/Output (I/O)
For More Information On This Product,
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Freescale Semiconductor, Inc.
WRITE $0002
DATA
REGISTER BIT
DU
RESET
(RST)
I/O
PIN
TO IRQ SUBSYSTEM
SEE FIGURE 4-2
ON
INTERNAL HC05
DATA BUS
MIC
Figure 7-3. Port C I/O Circuitry
SE
7.5.1 Port C Data Register
RE
ES
CA
LE
Each port C I/O pin has a corresponding bit in the port C data register.
When a port C pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port C pin is programmed as an input, any read of the port C
data register will return the logic state of the corresponding I/O pin. The
port C data register is unaffected by reset.
7.5.2 Port C Data Direction Register
IVE
DB
YF
Each port C I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRC or programmed as an output by setting
the corresponding bit in the DDRC. The DDRC can be accessed at
address $0006 and is cleared by reset.
CH
7.5.3 Port C I/O Pin Interrupts
AR
Freescale Semiconductor, Inc...
RREAD $0002
OUTPUT
The inputs of all eight bits of port C are ANDed into the IRQ input of the
CPU. See Figure 4-2. This port has its own interrupt request latch to
enable the user to differentiate between the IRQ sources. The port IRQ
MC68HC05V12 — Rev. 1.0
General Release Specification
Parallel Input/Output (I/O)
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A G R E E M E N T
DATA DIRECTION
REGISTER BIT
N O N - D I S C L O S U R E
WRITE $0006
CT
OR
, IN
C.2
006
READ $0006
R E Q U I R E D
Parallel Input/Output (I/O)
Port C
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
inputs are falling edge sensitive only. Any port C pin can be disabled as
an interrupt input by setting the corresponding DDR bit or data register
bit. To enable port pin interrupts, the corresponding DDR and data
register bits must both be cleared. Any port C pin that is configured as
an output will not cause a port interrupt when the pin transitions from a
1 to a 0.
The BIH and BIL instructions will apply only to the level on the IRQ pin
itself and not to the internal IRQ input to the CPU. Therefore, BIH and
BIL cannot be used to obtain the result of the logical combination of the
eight pins of port C.
NOTE:
Caution should be exercised when writing to the port C data register and
data direction register due to their interaction with the IRQ subsystem as
depicted in Figure 4-2. Special care should be exercised in using
read/modify/write instructions on these registers.
MIC
ON
DU
NOTE:
SE
7.6 Port D
YF
RE
ES
CA
LE
Port D is a 5-bit input-only port which shares all of its pins with the A/D
converter (AD0 through AD4) as shown in Figure 7-4. The port D data
register is located at address $0003. When the A/D converter is active,
one of these five input ports may be selected by the A/D multiplexer for
conversion. A logical read of a selected input port will always return 0.
VSS
DB
READ $0003/2B
CH
IVE
INTERNAL HC05
DATA BUS
INPUT
PIN
TO A/D CHANNEL SELECT LOGIC
TO A/D SAMPLING CIRCUITRY
Figure 7-4. Port D Circuitry
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Parallel Input/Output (I/O)
General Release Specification
MC68HC05V12 — Rev. 1.0
Parallel Input/Output (I/O)
For More Information On This Product,
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
8.3
Core Timer Status and Control Register. . . . . . . . . . . . . . . . . .85
8.4
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .87
8.5
Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . .88
8.6
Core Timer during Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . .88
MIC
ON
DU
8.2
SE
8.2 Introduction
CA
LE
The core timer for this device is a 12-stage multi-functional ripple
counter. The features include timer overflow, power-on reset (POR),
real-time interrupt (RTI), and computer operating properly (COP)
watchdog timer.
CH
IVE
DB
YF
RE
ES
As seen in Section 8. Core Timer, the internal peripheral clock is
divided by four then drives an 8-bit ripple counter. The value of this 8-bit
ripple counter can be read by the CPU at any time by accessing the core
timer counter register (CTCR) at address $09. A timer overflow function
is implemented on the last stage of this counter, giving a possible
interrupt rate of the internal peripheral clock(E)/1024. This point is then
followed by two more stages, with the resulting clock (E/2048) driving the
real-time interrupt circuit (RTI). The RTI circuit consists of three divider
stages with a 1-of-4 selector. The output of the RTI circuit is further
divided by eight to drive the mask optional COP watchdog timer circuit.
The RTI rate selector bits and the RTI and CTOF enable bits and flags
are located in the timer control and status register at location $08.
AR
Freescale Semiconductor, Inc...
8.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Core Timer
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A G R E E M E N T
Section 8. Core Timer
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
8
CT
OR
, IN
C.2
006
INTERNAL BUS
COP
INTERNAL PERIPHERAL CLOCK (E) CLEAR
8
E/22
CTCR
$09 CORE TIMER COUNTER REGISTER (CTCR)
DU
E / 29
E/210
5-BIT COUNTER
DIVIDE
/4
ON
E / 212
E / 214 E / 213 E / 212 E / 211
SE
RTI SELECT CIRCUIT
TOFE
RTIE
TOFC
CA
RTIF
RTFC
RTIout
RT1
RT0
TIMER CONTROL &
$08
STATUS REGISTER
ES
CTOF
LE
OVERFLOW
DETECT
CIRCUIT
CTSCR
MIC
POR
RE
INTERRUPT CIRCUIT
TIMER (÷ 8)
23
TO RESET
LOGIC
DB
YF
TO INTERRUPT
LOGIC
COP WATCHDOG
CH
IVE
Figure 8-1. Core Timer Block Diagram
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Core Timer
General Release Specification
MC68HC05V12 — Rev. 1.0
Core Timer
For More Information On This Product,
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Freescale Semiconductor, Inc.
$08
Bit 7
6
5
Read:
CTOF
RTIF
TOFE
Freescale Semiconductor, Inc...
Write
0
0
0
3
2
0
0
TOFC
RTFC
0
0
RTIE
0
1
Bit 0
RT1
RT0
1
1
DU
Reset:
4
= Unimplemented
ON
Figure 8-2. Core Timer Status and Control Register (CTSCR)
MIC
CTOF — Core Timer Overflow
SE
CTOF is a read-only status bit set when the 8-bit ripple counter rolls
over from $FF to $00. Clearing the CTOF is done by writing a 1 to
TOFC. Writing to this bit has no effect. Reset clears CTOF.
LE
RTIF — Real Time Interrupt Flag
YF
RE
ES
CA
The real-time interrupt circuit consists of a three-stage divider and a
1-of-4 selector. The clock frequency that drives the RTI circuit is
E/2**11 (or E/2048) with three additional divider stages giving a
maximum interrupt period of 7.8 milliseconds at a bus rate of 2.1 MHz.
RTIF is a clearable, read-only status bit and is set when the output of
the chosen (1-of-4 selection) stage goes active. Clearing the RTIF is
done by writing a 1 to RTFC. Writing has no effect on this bit. Reset
clears RTIF.
DB
TOFE — Timer Overflow Enable
IVE
When this bit is set, a CPU interrupt request is generated when the
CTOF bit is set. Reset clears this bit.
AR
CH
RTIE — Real-Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the
RTIF bit is set. Reset clears this bit.
MC68HC05V12 — Rev. 1.0
General Release Specification
Core Timer
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A G R E E M E N T
The core timer status and control register (CTSCR) contains the timer
interrupt flag, the timer interrupt enable bits, and the real-time interrupt
rate select bits. Figure 8-2 shows the value of each bit in the CTSCR
when coming out of reset.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
8.3 Core Timer Status and Control Register
R E Q U I R E D
Core Timer
Core Timer Status and Control Register
Freescale Semiconductor, Inc.
R E Q U I R E D
Core Timer
CT
OR
, IN
C.2
006
TOFC — Timer Overflow Flag Clear
When a 1 is written to this bit, CTOF is cleared. Writing a 0 has no
effect on the CTOF bit. This bit always reads as zero.
RTFC — Real-Time Interrupt Flag Clear
When a 1 is written to this bit, RTIF is cleared. Writing a 0 has no
effect on the RTIF bit. This bit always reads as zero.
RT1–RT0 — Real-Time Interrupt Rate Select
DU
ON
MIC
SE
LE
CA
Table 8-1. RTI and COP Rates at 2.1 MHz
RTI Rate
1.05 MHz
ES
2.1 MHz
0.97 ms
Minimum COP Rates
RT1–RT0
1.95 ms
2.1 MHz
1.05 MHz
211/E
00
(214–211)/E
6.83 ms
13.65 ms
3.90 ms
212/E
01
(215–212)/E
13.65 ms
27.31 ms
3.90 ms
7.80 ms
213/E
10
(216–213)/E
27.31 ms
54.61 ms
15.60 ms
214/E
11
(217–214)/E
54.61 ms
109.23
ms
YF
RE
1.95 ms
CH
IVE
DB
7.80 ms
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
These two bits select one of four taps from the real-time interrupt
circuit. See Table 8-1 which shows the available interrupt rates with
a 2.1 and 1.05 MHz bus clock. Reset sets bits RT1 and RT0, which
selects the lowest periodic rate, and gives the maximum time in which
to alter these bits if necessary. Care should be taken when altering
RT0 and RT1 if the timeout period is imminent or uncertain. If the
selected tap is modified during a cycle in which the counter is
switching, an RTIF could be missed or an additional one could be
generated. To avoid problems, the COP should be cleared before
changing RTI taps.
General Release Specification
MC68HC05V12 — Rev. 1.0
Core Timer
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Freescale Semiconductor, Inc.
MIC
ON
If the COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. In addition the RESET pin will be pulled low
for a minimum of 3 E clock cycles for emulation purposes. During a chip
reset (regardless of the source), the entire core timer counter chain is
cleared.
LE
SE
The COP will remain enabled after execution of the WAIT instruction and
all associated operations apply. If the STOP instruction is disabled,
execution of STOP instruction will cause an internal reset.
AR
CH
IVE
DB
YF
RE
ES
CA
This COP’s objective is to make it impossible for this part to become
“stuck” or “locked-up” and to be sure the COP is able to “rescue” the part
from any situation where it might entrap itself in an abnormal or
unintended behavior. This function is a mask option.
MC68HC05V12 — Rev. 1.0
General Release Specification
Core Timer
For More Information On This Product,
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A G R E E M E N T
DU
Freescale Semiconductor, Inc...
The COP watchdog timer function is implemented on this device by
using the output of the RTI circuit and further dividing it by eight. The
minimum COP reset rates are listed in Figure 8-1. If the COP circuit
times out, an internal reset is generated and the normal reset vector is
fetched. Preventing a COP timeout, or clearing the COP, is
accomplished by writing a 0 to bit 0 of address $3FF0. When the COP is
cleared, only the final divide-by-eight stage (output of the RTI) is cleared.
The COP time out period will vary depending on when the COP is feed
with respect to the RTI output clock.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
8.4 Computer Operating Properly (COP) Reset
R E Q U I R E D
Core Timer
Computer Operating Properly (COP) Reset
Freescale Semiconductor, Inc.
The core timer counter register (CTCR) is a read-only register which
contains the current value of the 8-bit ripple counter at the beginning of
the timer chain. This counter is clocked by the CPU clock (E/4) and can
be used for various functions including a software input capture.
Extended time periods can be attained using the TOF function to
increment a temporary RAM storage location, thereby simulating a 16bit (or more) counter.
Bit 7
6
5
Read:
TMR7
TMR6
TMR5
0
0
DU
$09
Reset:
ON
Write:
0
4
3
2
1
Bit 0
TMR4
TMR3
TMR2
TMR1
TMR0
0
0
0
0
0
MIC
= Unimplemented
Figure 8-3. Core Timer Counter Register (CTCR)
RE
ES
CA
LE
SE
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 cycles, the power-on reset circuit is released
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer will start
counting up from zero and normal device operation will begin. When
RESET is asserted any time during operation (other than POR), the
counter chain will be cleared.
YF
8.6 Core Timer during Wait Mode
CH
IVE
DB
The CPU clock halts during wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit
wait mode. The COP watchdog timer, derived from the core timer,
remains active in wait mode, if enabled via the MOR.
AR
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
8.5 Core Timer Counter Register
A G R E E M E N T
R E Q U I R E D
Core Timer
General Release Specification
MC68HC05V12 — Rev. 1.0
Core Timer
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Freescale Semiconductor, Inc.
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
9.3
Timer Counter Registers $18−$19 and $1A−$1B. . . . . . . . . . .90
9.4
Output Compare Register $16−$17 . . . . . . . . . . . . . . . . . . . . .92
9.5
Input Capture Register $14−$15. . . . . . . . . . . . . . . . . . . . . . . .92
9.6
16-Bit Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .94
9.7
16-Bit Timer Status Register (TMRSR) . . . . . . . . . . . . . . . . . .95
9.8
16-Bit Timer during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . .96
9.9
16-Bit Timer during Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . .96
LE
SE
MIC
ON
DU
9.2
CA
9.2 Introduction
YF
RE
ES
The timer consists of a 16-bit, free-running counter driven by a fixed
divide-by-four prescaler. This timer can be used for many purposes,
including input waveform measurements while simultaneously
generating an output waveform. Pulse widths can vary from several
microseconds to many seconds. See Figure 9-1.
CH
IVE
DB
Because the timer has a 16-bit architecture, each specific functional
segment (capability) is represented by two registers. These registers
contain the high and low bytes of that functional segment. Access of the
high byte inhibits that specific timer function until the low byte is also
accessed.
NOTE:
AR
Freescale Semiconductor, Inc...
9.1 Contents
The I bit in the CCR should be set while manipulating both the high and
low byte registers of a specific timer function to ensure that an interrupt
does not occur.
MC68HC05V12 — Rev. 1.0
General Release Specification
16-Bit Timer
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R E Q U I R E D
Section 9. 16-Bit Timer
A G R E E M E N T
General Release Specification — MC68HC05V12
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
16-Bit Timer
Contents
Freescale Semiconductor, Inc.
R E Q U I R E D
16-Bit Timer
/4
OUTPUT
COMPARE
REGISTER
8-BIT
BUFFER
HIGH
BYTE
LOW
BYTE
16-BIT FREE$18
RUNNING
$19
COUNTER
HIGH LOW
BYTE BYTE
INPUT
CAPTURE $14
REGISTER $15
$1A
$1B
DU
COUNTER
ALTERNATE
REGISTER
A G R E E M E N T
OUTPUT
COMPARE
CIRCUIT
SE
MIC
ON
OVERFLOW
DETECT
CIRCUIT
TIMER
STATUS ICF OCF TOF $13
REGISTER
EDGE
DETECT
CIRCUIT
D
Q
CLK
OUTPUT
C
LEVEL
REGISTER
RESET
TIMER
ICIE OCIE TOIE IEDG OLVL CONTROL
REGISTER
$12
OUTPUT
LEVEL
(TCMP)
PB6
EDGE
INPUT
(TCAP)
PB7
CA
LE
INTERRUPT
CIRCUIT
ES
Figure 9-1. 16-Bit Timer Block Diagram
RE
9.3 Timer Counter Registers $18−$19 and $1A−$1B
IVE
DB
YF
The key element in the programmable timer is a 16-bit, free-running
counter or counter register preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two
locations, $18-$19 (counter register) or $1A-$1B (counter alternate
register). A read from only the least significant byte (LSB) of the freerunning counter ($19, $1B) receives the count value at the time of the
read. If a read of the free-running counter or counter alternate register
CH
AR
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
INTERNAL
PROCESSOR
CLOCK
HIGH LOW
BYTE BYTE
$16
$17
CT
OR
, IN
C.2
006
INTERNAL BUS
General Release Specification
MC68HC05V12 — Rev. 1.0
16-Bit Timer
For More Information On This Product,
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Freescale Semiconductor, Inc.
ES
CA
NOTE:
CH
IVE
DB
YF
RE
To ensure that an interrupt does not occur, the I bit in the CCR should
be set while manipulating both the high and low byte registers of a
specific timer function.
MC68HC05V12 — Rev. 1.0
General Release Specification
16-Bit Timer
For More Information On This Product,
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A G R E E M E N T
LE
SE
MIC
The free-running counter is configured to $FFFC during reset and is a
read-only register only when the timer is enabled. During a power-on
reset, the counter also is preset to $FFFC and begins running only after
the TON bit in the timer control register is set. Because the free-running
counter is 16 bits preceded by a fixed divided-by-four prescaler, the
value in the free-running counter repeats every 262,144 internal bus
clock cycles. When the counter rolls over from $FFFF to $0000, the TOF
bit is set. When counter roll-over occurs, an interrupt also can be
enabled by setting its interrupt enable bit (TOIE).
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
ON
DU
The counter alternate register differs from the counter register in one
respect: A read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
AR
Freescale Semiconductor, Inc...
first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19,
$1B) is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or counter alternate
register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter
alternate register, if the MSB is read, the LSB also must be read to
complete the sequence.
R E Q U I R E D
16-Bit Timer
Timer Counter Registers $18−$19 and $1A−$1B
Freescale Semiconductor, Inc.
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The output compare register is
used for several purposes, such as indicating when a period of time has
elapsed. All bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not needed, the two
bytes of the output compare register can be used as storage locations.
The output compare register contents are continually compared with the
contents of the free-running counter. If a match is found, the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level
register. The output compare register values and the output level bit
should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt can also accompany a successful output
compare provided the corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is also written. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the
compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the
output compare register is a function of the program rather than the
internal hardware.
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
DB
YF
RE
The processor can write to either byte of the output compare register
without affecting the other byte. The output level (OLVL) bit is clocked to
the output level register regardless of whether the output compare flag
(OCF) is set or clear.
IVE
9.5 Input Capture Register $14−$15
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
CH
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
9.4 Output Compare Register $16−$17
A G R E E M E N T
R E Q U I R E D
16-Bit Timer
General Release Specification
MC68HC05V12 — Rev. 1.0
16-Bit Timer
For More Information On This Product,
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Freescale Semiconductor, Inc.
ON
DU
Freescale Semiconductor, Inc...
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
tTLTL
tTL
tTH
ES
CA
LE
SE
MIC
After a read of the input capture register MSB ($14), the counter transfer
is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction
with the main program to determine the minimum pulse period. A read
of the input capture register LSB ($15) does not inhibit the free-running
counter transfer since they occur on opposite edges of the internal bus
clock.
YF
RE
TCAP
Figure 9-2. TCAP Timing
IVE
The input capture pin (TCAP) and the output compare pin (TCMP) are
shared with PB7 and PB6 respectively. The timer’s TCAP input always
is connected to PB7. PB6 is the timer’s TCMP pin if the OCE bit in the
miscellaneous control register is set.
AR
CH
NOTE:
DB
See control timing specifications for TCAP timing requirements.
MC68HC05V12 — Rev. 1.0
General Release Specification
16-Bit Timer
For More Information On This Product,
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A G R E E M E N T
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register.
R E Q U I R E D
16-Bit Timer
Input Capture Register $14−$15
Freescale Semiconductor, Inc.
9.6 16-Bit Timer Control Register
The 16-bit timer control register (TMRCR) is a read/write register
containing six control bits. Three bits control interrupts associated with
the timer status register flags ICF, OCF, and TOF.
$12
Bit 7
6
5
ICIE
OCIE
TOIE
0
0
0
Read:
Write:
A G R E E M E N T
Reset:
Freescale Semiconductor, Inc...
4
3
0
0
0
0
2
1
Bit 0
TON
IEDG
OLVL
0
0
0
DU
= Unimplemented
ON
Figure 9-3. Timer Control Register (TMRCR)
MIC
ICIE – Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
LE
SE
OCIE – Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
ES
CA
TOIE – Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
RE
TON – Timer On
YF
When disabled, the timer is initialized to the reset condition.
1 = Timer enabled
0 = Timer disabled
DB
IEDG – Input Edge
CH
IVE
Value of input edge determines which level transition on TCAP pin will
trigger free-running counter transfer to the input capture register.
Reset clears this bit.
1 = Positive edge
0 = Negative edge
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
R E Q U I R E D
16-Bit Timer
General Release Specification
MC68HC05V12 — Rev. 1.0
16-Bit Timer
For More Information On This Product,
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Freescale Semiconductor, Inc.
9.7 16-Bit Timer Status Register (TMRSR)
Bit 7
6
Read:
ICF
OCF
0
0
Reset:
5
4
3
2
1
Bit 0
TOF
0
0
0
0
0
0
0
0
0
0
MIC
Write:
DU
$13
ON
Freescale Semiconductor, Inc...
The 16-bit timer status register (TMRSR) is a read-only register
containing three status flag bits.
0
SE
= Unimplemented
Figure 9-4. Timer Status Register (TMRSR)
ES
CA
LE
ICF – Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TMRSR and input capture low register ($15)
are accessed
DB
YF
RE
OCF – Output Compare Flag
1 = Flag set when output compare register contents match the freerunning counter contents
0 = Flag cleared when TMRSR and output compare low register
($17) are accessed
AR
CH
IVE
TOF – Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to
$0000 occurs
0 = Flag cleared when TMRSR and counter low register ($19) are
accessed
MC68HC05V12 — Rev. 1.0
General Release Specification
16-Bit Timer
For More Information On This Product,
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A G R E E M E N T
Value of output level is clocked into output level register by the next
successful output compare and will appear on the TCMP pin.
1 = High output
0 = Low output
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
OLVL − Output Level
R E Q U I R E D
16-Bit Timer
16-Bit Timer Status Register (TMRSR)
Freescale Semiconductor, Inc.
R E Q U I R E D
16-Bit Timer
CT
OR
, IN
C.2
006
Accessing the timer status register satisfies the first condition required
to clear status bits. The remaining step is to access the register
corresponding to the status bit.
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
DU
2. The MSB of the free-running counter is read but not for the
purpose of servicing the flag.
SE
MIC
ON
The counter alternate register at address $1A and $1B contains the
same value as the free-running counter (at address $18 and $19);
therefore, this alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
LE
9.8 16-Bit Timer during Wait Mode
ES
CA
The CPU clock halts during wait mode, but the timer remains active if
turned on prior to entering wait mode. If interrupts are enabled, a timer
interrupt will cause the processor to exit wait mode.
RE
9.9 16-Bit Timer during Stop Mode
CH
IVE
DB
YF
In stop mode, the timer stops counting and holds the last count value if
stop mode is exited by an interrupt. If RESET is used, the counter is
forced to $FFFC. During STOP, if the timer is on and at least one valid
input capture edge occurs at the TCAP pin, the input capture detect
circuit is armed. This does not set any timer flags or wake up the MCU,
but when the MCU does wake up, there is an active input capture flag
and data from the first valid edge that occurred during stop mode. If
RESET is used to exit stop mode, then no input capture flag or data
remains, even if a valid input capture edge occurred.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
1. The timer status register is read or written when TOF is set, and
General Release Specification
MC68HC05V12 — Rev. 1.0
16-Bit Timer
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10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
10.5
MIC
ON
DU
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
10.4.1
Slave Select (SS/PB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.4.2
Serial Clock (SCK/PB1). . . . . . . . . . . . . . . . . . . . . . . . . . .100
10.4.3
Master In Slave Out (MISO/PB2) . . . . . . . . . . . . . . . . . . .100
10.4.4
Master Out Slave In (MOSI/PB3) . . . . . . . . . . . . . . . . . . .100
SPI Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .101
CA
LE
SE
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
10.6.1
Serial Peripheral Control Register. . . . . . . . . . . . . . . . . . .103
10.6.2
Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . .104
10.6.3
Serial Peripheral Data Register. . . . . . . . . . . . . . . . . . . . .106
SPI in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.8
SPI in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
RE
ES
10.7
YF
10.2 Introduction
CH
IVE
DB
The serial peripheral interface (SPI) allows several MC68HC05 MCUs or
an MC68HC05 MCU plus peripheral devices to be interconnected within
a single printed circuit board. In an SPI, separate wires are required for
data and clock. In the SPI format, the clock is not included in the data
stream and must be furnished as a separate signal.
AR
Freescale Semiconductor, Inc...
10.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 10. Serial Peripheral Interface (SPI)
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
10.3 Features
Full Duplex, 3-Wire Synchronous Transfers
•
Master or Slave Operation
•
Internal MCU Clock Divided by Two (Maximum) Master Bit
Frequency
•
Internal MCU Clock (Maximum) Slave Bit Frequency
•
Four Programmable Master Bit Rates
•
Programmable Clock Polarity and Phase
•
End of Transmission Interrupt Flag
•
Write Collision Flag Protection
•
Master-Master Mode Fault Protection Capability
MIC
ON
DU
•
SE
10.4 SPI Signal Description
CA
LE
The four pins (MOSI, MISO, SCK, and SS) are described in the following
paragraphs. Each signal function is described for both the master and
slave modes.
CH
IVE
DB
YF
RE
ES
To function properly, the SPI forces the direction on some of the pins to
output.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
General Release Specification
MC68HC05V12 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
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Freescale Semiconductor, Inc.
SCK
(CPOL = 0, CPHA = 1)
SCK
(CPOL = 1, CPHA = 0)
DU
SCK
(CPOL = 1, CPHA = 1)
6
5
4
3
2
1
0
MIC
MSB
ON
MISO/MOSI
SE
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
LE
Figure 10-1. Data Clock Timing Diagram
CA
10.4.1 Slave Select (SS/PB0)
YF
RE
ES
The slave select (SS) pin is used to select the MCU as a slave device. It
has to be low prior to data transactions and must stay low for the duration
of the transaction. The SS pin on the master must be set high. If it goes
low, a mode fault error flag (MODF) is set in the SPSR.
If the SPI is in master mode, this pin can be used as a general-purpose
output pin. If configured as an input pin while in master mode, it must be
set high.
AR
CH
NOTE:
IVE
DB
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS pin
could be set low as long as CPHA = 1 clock modes are used.
MC68HC05V12 — Rev. 1.0
General Release Specification
Serial Peripheral Interface (SPI)
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A G R E E M E N T
SCK
(CPOL = 0, CPHA = 0)
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
SS
Freescale Semiconductor, Inc...
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI Signal Description
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
10.4.2 Serial Clock (SCK/PB1)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
ON
DU
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line a half cycle before the clock edge (SCK) for the slave device
to latch the data.
SE
MIC
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the
operation of the SPI.
LE
10.4.3 Master In Slave Out (MISO/PB2)
RE
ES
CA
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
YF
10.4.4 Master Out Slave In (MOSI/PB3)
CH
IVE
DB
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit sent first.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Serial Peripheral Interface (SPI)
General Release Specification
MC68HC05V12 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MIC
ON
The SPI is double buffered on read, but not on write. If a write is
performed during data transfer, the transfer occurs uninterrupted, and
the write will be unsuccessful. This condition will cause the write collision
(WCOL) status bit in the SPSR to be set. After a data byte is shifted, the
SPIF flag of the SPSR is set.
CA
LE
SE
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
YF
RE
ES
In a slave mode, the slave select start logic receives a logic low from the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
AR
CH
IVE
DB
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
MC68HC05V12 — Rev. 1.0
General Release Specification
Serial Peripheral Interface (SPI)
For More Information On This Product,
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A G R E E M E N T
DU
Freescale Semiconductor, Inc...
Figure 10-2 shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the I/O operation has been
completed.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
10.5 SPI Functional Description
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI Functional Description
Freescale Semiconductor, Inc.
MSB
DIVIDER
READ DATA BUFF
÷2 ÷4 ÷16 ÷32
CLOCK
SPI CLOCK
(MASTER)
PB3/
MOSI
PB1/
SCK
M
PB0/
SS
SPR0
SPR1
CPOL
MSTR
SPE
SPIE
SE
MODF
WCOL
MIC
SPE
SPI CONTROL
CPHA
ON
DU
SPR0
SPR1
S
CLOCK
LOGIC
MSTR
SPIF
SPI CONTROL REGISTER
LE
SPI STATUS REGISTER
SPI INTERRUPT
REQUEST
INTERNAL
DATA BUS
YF
RE
ES
Figure 10-2. Serial Peripheral Interface Block Diagram
MASTER
IVE
DB
8-BIT SHIFT REGISTER
MISO
MISO
MOSI
MOSI
SCK
SCK
8-BIT SHIFT REGISTER
CH
SPI CLOCK
GENERATOR
SLAVE
AR
A G R E E M E N T
Freescale Semiconductor, Inc...
M
S
8-BIT SHIFT REG
SELECT
N O N - D I S C L O S U R E
LSB
PB2/
MISO
PIN CONTROL LOGIC
INTERNAL
MCU CLOCK
CT
OR
, IN
C.2
006
S
M
CA
R E Q U I R E D
Serial Peripheral Interface (SPI)
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
General Release Specification
MC68HC05V12 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
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Freescale Semiconductor, Inc.
$0A
Bit 7
6
5
SPIE
SPE
0
0
DU
Freescale Semiconductor, Inc...
3
2
1
Bit 0
MSTR
CPOL
CPHA
SPR1
SPR0
0
0
1
U
U
0
Write:
0
MIC
Reset:
ON
Read:
4
= Unimplemented
U = Unaffected
SE
Figure 10-4. SPI Control Register (SPCR)
CA
LE
SPIE − Serial Peripheral Interrupt Enable
1 = SPI interrupt if SPIF = 1
0 = SPIF interrupts disabled
RE
ES
SPE − Serial Peripheral System Enable
1 = SPI system on; port B becomes SPI pins.
0 = SPI system off
YF
MSTR − Master Mode Select
1 = Master mode
0 = Slave mode
DB
CPOL − Clock Polarity
AR
CH
IVE
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit is also used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
MC68HC05V12 — Rev. 1.0
General Release Specification
Serial Peripheral Interface (SPI)
For More Information On This Product,
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R E Q U I R E D
10.6.1 Serial Peripheral Control Register
A G R E E M E N T
Three registers in the SPI provide control, status, and data storage
functions. These registers are called the serial peripheral control register
(SPCR), serial peripheral status register (SPSR), and serial peripheral
data I/O register (SPDR) and are described in the following paragraphs.
N O N - D I S C L O S U R E
10.6 SPI Registers
CT
OR
, IN
C.2
006
Serial Peripheral Interface (SPI)
SPI Registers
Freescale Semiconductor, Inc.
R E Q U I R E D
Serial Peripheral Interface (SPI)
CT
OR
, IN
C.2
006
CPHA − Clock Phase
DU
SPR1 and SPR0 − SPI Clock Rate Selects
MIC
ON
These two bits select one of four baud rates (see Table 10-1) to be
used as SCK if the device is a master; however, they have no effect
in slave mode.
SPR0
Internal MCU Clock
Divided by
0
2
LE
Table 10-1. Serial Peripheral Rate Selection
0
1
4
1
0
16
1
1
32
ES
CA
0
SE
SPR1
$0B
Bit 7
6
5
4
3
2
1
Bit 0
DB
YF
RE
10.6.2 Serial Peripheral Status Register
SPIF
WCOL
0
MODF
0
0
0
0
0
0
0
0
0
0
0
0
Read:
IVE
Write:
CH
Reset:
= Unimplemented
Figure 10-5. SPI Status Register (SPSR)
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, SS may be
thought of as a simple output enable control. See Figure 10-1.
General Release Specification
MC68HC05V12 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
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Freescale Semiconductor, Inc.
WCOL − Write Collision
MIC
ON
DU
Freescale Semiconductor, Inc...
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is zero, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is one, a transfer is said to begin the first time SCK
becomes active while SS is low and the transfer ends when the SPIF
flag gets set. Clearing the WCOL bit is accomplished by reading the
SPSR (with WCOL set) followed by an access to SPDR.
SE
MODF − Mode Fault
RE
ES
CA
LE
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear, and is set only when the master device has its SS pin set low.
Setting the MODF bit affects the internal serial peripheral interface
system in these ways:
1.
An SPI interrupt is generated if SPIE = 1.
YF
2.
DB
3.
The SPE bit is cleared, disabling the SPI.
The MSTR bit is cleared, thus forcing the device into the slave
mode.
AR
CH
IVE
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state after
the MODF bit has been cleared. It is also necessary to restore the port
B DDR bits after a mode fault.
MC68HC05V12 — Rev. 1.0
General Release Specification
Serial Peripheral Interface (SPI)
For More Information On This Product,
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A G R E E M E N T
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
SPIF − SPI Transfer Complete Flag
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI Registers
Freescale Semiconductor, Inc.
10.6.3 Serial Peripheral Data Register
$0C
CT
OR
, IN
C.2
006
R E Q U I R E D
Serial Peripheral Interface (SPI)
Bit 7
6
5
SPD7
SPD6
SPD5
Read:
Write:
Reset:
4
3
2
1
Bit 0
SPD4
SPD3
SPD2
SPD1
SPD0
Unaffected by reset
MIC
ON
DU
The serial peripheral data I/O register is used to transmit and receive
data on the serial bus. Only a write to this register will initiate
transmission/reception of another byte, and this will only occur in the
master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
LE
SE
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
CH
IVE
DB
YF
RE
ES
CA
A write to the serial peripheral data I/O register is not buffered and
places data directly into the shift register for transmission.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Figure 10-6. SPI Data Register (SPDR)
General Release Specification
MC68HC05V12 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
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Freescale Semiconductor, Inc.
CA
LE
SE
Also note that when the MCU enters stop mode, all enabled output
drivers (MISO, MOSI, and SCLK ports) remain active and any sourcing
currents from these outputs will be part of the total supply current
required by the device.
ES
10.8 SPI in Wait Mode
CH
IVE
DB
YF
RE
The SPI subsystem remains active in wait mode. Therefore, it is
consuming power. Before reducing power, the SPI should be shut off
prior to entering wait mode. A non-reset exit from wait mode will result in
the state of the SPI being unchanged. A reset exit will return the SPI to
its reset state, which is disabled.
MC68HC05V12 — Rev. 1.0
General Release Specification
Serial Peripheral Interface (SPI)
For More Information On This Product,
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A G R E E M E N T
MIC
ON
At the end of a possible transmission with a slave SPI in stop mode, no
flags are set until a viable interrupt results in an MCU wake up. Be
cautious when operating the SPI (as a slave) during stop mode because
none of the protection circuitry (write collision, mode fault, etc.) is active.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
DU
When the MCU enters stop mode, the baud rate generator driving the
SPI shuts down. This essentially stops all master mode SPI operation;
thus, the master SPI is unable to transmit or receive any data. If the
STOP instruction is executed during an SPI transfer, that transfer is
halted until the MCU exits stop mode (provided it is an exit resulting from
a viable interrupt source). If the stop mode is exited by a reset, then the
appropriate control/status bits are cleared and the SPI is disabled. If the
device is in slave mode when the STOP instruction is executed, the
slave SPI will still operate. It can still accept data and clock information
in addition to transmitting its own data back to a master device.
AR
Freescale Semiconductor, Inc...
10.7 SPI in Stop Mode
R E Q U I R E D
Serial Peripheral Interface (SPI)
SPI in Stop Mode
Freescale Semiconductor, Inc.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
CT
OR
, IN
C.2
006
R E Q U I R E D
Serial Peripheral Interface (SPI)
General Release Specification
MC68HC05V12 — Rev. 1.0
Serial Peripheral Interface (SPI)
For More Information On This Product,
Go to: www.freescale.com
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
11.3
PWM Functional Description . . . . . . . . . . . . . . . . . . . . . . . . .110
MIC
ON
DU
11.4 PWM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.4.1
PWMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .113
11.4.2
PWMB Control Register . . . . . . . . . . . . . . . . . . . . . . . . . .114
11.4.3
PWMA Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.4.4
PWMB Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
PWMs during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.6
PWMs during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.7
PWMs during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
CA
LE
SE
11.5
11.2 Introduction
CH
IVE
DB
YF
RE
ES
The pulse width modulator (PWM) system has two 6-bit PWMs (PWMA
and PWMB). Preceding the 6-bit (÷64) counters are two programmable
prescalers.The PWM frequency is selected by choosing the desired
divide option from the programmable prescalers. Note that the PWM
clock input is fOP. The PWM frequency will be fOP/(PSA*(PSB-1)*64)
where PSA and PSB are the values selected by the A and B prescaler
and 64 comes from the 6-bit modulus counter. See Table 11-1 for
precise values. The fOP is the internal bus frequency fixed to half of the
external oscillator frequency.
AR
Freescale Semiconductor, Inc...
11.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 11. Pulse Width Modulators (PWMs)
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
fOP (CPU BUS CLOCK)
RCLK
SCLK
INTEGER DIVIDE
÷1, ÷8, ÷16
÷1–16
HC05 DATA BUS
6-BIT COUNTER
(÷64)
MODULUS AND
COMPARATOR
PWMx
PIN LOGIC
PWMx
PWM DATA
REGISTER
POLx
DU
ON
PSB3x
PSB1x
PSB2x
PSB0x
PSA1x
PSA0x
PWM DATA
BUFFER
SE
MIC
PWM CONTROL REGISTERS AND BUFFERS
LE
Figure 11-1. PWM Block Diagram
CA
11.3 PWM Functional Description
RE
ES
The PWM is capable of generating signals from 0% to 100% duty cycle.
A $00 in the PWM data register yields a low output (0%), but a $3F yields
a duty of 63/64. To achieve the 100% duty (high output), the polarity
control bit is set to zero while the data register has $00 in it.
DB
YF
When not in use, the PWM system can be shut off to save power by
clearing the clock rate select bits PSA0x and PSA1x in PWM control
registers.
CH
IVE
Writes to the PWM data registers are buffered and can, therefore, be
performed at any time without affecting the output signal. When the
PWM subsystem is enabled, a write to the PWM control register will
become effective immediately.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Pulse Width Modulators (PWMs)
When the PWM subsystem is enabled, a write to the PWM data register
will not become effective until the end of the current PWM period has
General Release Specification
MC68HC05V12 — Rev. 1.0
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
However, should a write to the registers be performed when the PWM
subsystem is disabled, the data is transferred immediately. All registers
are updated after the PWM data register is written to and the end of a
PWM cycle occurs.
DU
ON
T
$3F
SE
MIC
$05
CA
LE
$1F
PWM REGISTER = $00
T
$05
AR
CH
IVE
DB
YF
RE
ES
Figure 11-2. PWM Waveform Examples (POL = 1)
$3F
$1F
PWM REGISTER = $00
Figure 11-3. PWM Waveform Examples (POL = 0)
MC68HC05V12 — Rev. 1.0
General Release Specification
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
The PWM output can have an active high or an active low pulse under
software control using the POL (polarity) bit as shown in Figure 11-2
and Figure 11-3.
A G R E E M E N T
CT
OR
, IN
C.2
006
occurred, at which time the new data value is loaded into the PWM data
register.
R E Q U I R E D
Pulse Width Modulators (PWMs)
PWM Functional Description
Freescale Semiconductor, Inc.
Associated with each PWM system, there is a PWM data register and a
control register. These registers can be written to and read at any time.
Data written to the data register is held in a buffer and transferred to the
PWM data register at the end of a PWM cycle. Reads of this register will
always result in the read of the PWM data register and not the buffer.
Upon RESET the user should write to the data register prior to enabling
the PWM system (for example, prior to setting the PSAx and PSBx bits
for PWM input clock rate). This will avoid an erroneous duty cycle from
being driven. During user mode, the user should write to the PWM data
register after writing the PWM control register.
POR
OR RESET
SE
MIC
Y
ON
DU
Freescale Semiconductor, Inc...
LE
INITIALIZE PWM DATA 0
WRITE PWM CONTROL
WRITE PWM DATA 1
Figure 11-4. PWM Write Sequences
CH
IVE
DB
YF
RE
ES
CA
WRITE PWM CONTROL
N
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
11.4 PWM Registers
A G R E E M E N T
R E Q U I R E D
Pulse Width Modulators (PWMs)
General Release Specification
MC68HC05V12 — Rev. 1.0
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
$37
Bit 7
6
5
PSA1A
PSA0A
0
0
Read:
0
Write:
Reset:
0
CT
OR
, IN
C.2
006
11.4.1 PWMA Control Register
4
3
2
1
Bit 0
PSB3A
PSB2A
PSB1A
PSB0A
0
0
0
0
0
0
= Unimplemented
R E Q U I R E D
Pulse Width Modulators (PWMs)
PWM Registers
MIC
ON
DU
These bits select the input clock rate and determine the period as
shown in Table 11-1. Note that some output frequencies can be
obtained with more than one combination of PSA and PSB values.
For instance, a PWMA output of fOP/512 can be obtained with either
Table 11-1. PWMA Clock Rates
CA
LE
SE
PSA−PSA0 = 10 and PSB3−PSB0 = $0 or PSA1−PSA0 = 01 and
PSB3−PSB0 = $07. The frequency division provided by the PSB
values will be one more that the value written to the register. For
example, a $0 written to the PSB bits provides a ÷1 and a $1 provides
a ÷2, etc.
PSB3A–
PSB0A
RCLKA
SCLKA
PWMA OUT
00
xxxx
off
off
off
01
0000–1111
fOP/1
fOP/1–fOP/16
fOP/64–fOP/1024
10
0000–1111
fOP/8
fOP/8–fOP/128
fOP/512–fOP/8192
11
0000–1111
fOP/16
fOP/16–fOP/256
fOP/1024–fOP/16384
YF
RE
ES
PSA1A–
PSA0A
DB
This scheme allows for 38 unique frequency selections.
Any non-zero value of PSA1A−PSA0A forces PB4 to the PWMA output
state. If PSA1A:PSA0A = 00, PB4 is determined by the port B data and
data direction registers as described in Section 7. Parallel
Input/Output (I/O).
AR
CH
IVE
NOTE:
A G R E E M E N T
PSA1A, PSA0A, PSB3A−PSB0A — PWMA Clock Rate Bits
MC68HC05V12 — Rev. 1.0
General Release Specification
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Figure 11-5. PWMA Control Register (PWMAC)
Freescale Semiconductor, Inc.
11.4.2 PWMB Control Register
$39
Bit 7
6
5
PSA1B
PSA0B
0
0
Read:
0
Write:
Reset:
0
CT
OR
, IN
C.2
006
R E Q U I R E D
Pulse Width Modulators (PWMs)
4
3
2
1
Bit 0
PSB3B
PSB2B
PSB1B
PSB0B
0
0
0
0
0
0
= Unimplemented
PSA1B, PSA0B, and PSB3B−PSB0B — PWM Clock Rate
MIC
ON
DU
These bits select the input clock rate for PWMB and determine the
period as shown in Table 11-2. These bits function exactly the same
as the corresponding bits in the PWMA control register except they
affect the PWMB output pin.
Table 11-2. PWMB Clock Rates
PSB3B–
PSB0B
RCLKB
SCLKB
PWMB OUT
00
xxxx
off
off
off
0000–1111
fOP/1
fOP/1–fOP/16
fOP/64–fOP/1024
0000–1111
fOP/8
fOP/8–fOP/128
fOP/512–fOP/8192
0000–1111
fOP/16
fOP/16–fOP/256
fOP/1024–fOP/16384
LE
ES
11
CA
01
10
SE
PSA1B–
PSA0B
Any non-zero value of PSA1B−PSA0B forces PB5 to the PWMB output
state. If PSA1B−PSA0B = 00, PB5 is determined by the port B data and
data direction registers as described in Section 7. Parallel
Input/Output (I/O).
CH
IVE
DB
YF
RE
NOTE:
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Figure 11-6. PWMB Control Register (PWMBC)
General Release Specification
MC68HC05V12 — Rev. 1.0
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
$36
Bit 7
6
0
POLA
D5
Reset:
0
DU
Write:
0
U
4
3
2
1
Bit 0
D4
D3
D2
D1
D0
U
U
U
U
U
U = Unaffected
ON
= Unimplemented
MIC
Figure 11-7. PWMA Data Register
LE
SE
POLA — PWMA Polarity
1 = PWMA pulse is active high.
0 = PWMA pulse is active low.
CA
11.4.4 PWMB Data Register
Bit 7
YF
$38
RE
ES
The PWMB system has one 6-bit data register which holds the duty
cycle information. These bits work the same way as the data bits in the
PWMA data register except they affect the PWMB output pin. The data
bits in this register are unaffected by reset.
Read:
6
5
4
3
2
1
Bit 0
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
0
POLB
DB
Write:
0
0
= Unimplemented
U = Unaffected
Figure 11-8. PWMB Data Register
CH
IVE
Reset:
AR
Freescale Semiconductor, Inc...
Read:
5
POLB — PWMB Polarity
1 = PWMB pulse is active high.
0 = PWMB pulse is active low.
MC68HC05V12 — Rev. 1.0
General Release Specification
Pulse Width Modulators (PWMs)
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
The PWMA system has one 6-bit data register which holds the duty
cycle information. The data bits in this register are unaffected by reset.
A value of $00 in this register corresponds to a steady state output level
(0% duty cycle) on the PWMA pin. The logic level of the output will
depend on the value of the POLA bit in the PWMA control register.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
11.4.3 PWMA Data Register
R E Q U I R E D
Pulse Width Modulators (PWMs)
PWM Registers
Freescale Semiconductor, Inc.
11.5 PWMs during Wait Mode
CT
OR
, IN
C.2
006
R E Q U I R E D
Pulse Width Modulators (PWMs)
The PWM continues normal operation during wait mode. To decrease
power consumption during wait mode, it is recommended that the rate
select bits in the PWM control registers be cleared if the PWM is not
being used.
ON
DU
In stop mode, the oscillator is stopped causing the PWM to cease
functioning. Any signal in process is aborted in whatever phase the
signal happens to be in.
MIC
11.7 PWMs during Reset
CH
IVE
DB
YF
RE
ES
CA
LE
SE
Upon reset the PSA0X and PSA1X bits in PWMX control registers are
cleared. This disables the PWM system and sets the PWM outputs low.
The user should write to the data registers prior to enabling the PWM
system (for example, prior to setting PSA1X or PSA0X). This will avoid
an erroneous duty cycle from being driven.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
11.6 PWMs during Stop Mode
General Release Specification
MC68HC05V12 — Rev. 1.0
Pulse Width Modulators (PWMs)
For More Information On This Product,
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Section 12. EEPROM
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
12.3
EEPROM Programming Register . . . . . . . . . . . . . . . . . . . . . .118
12.4
EEPROM Programming/Erasing Procedure. . . . . . . . . . . . . .120
12.5
Operation in Stop and Wait Modes. . . . . . . . . . . . . . . . . . . . .121
MIC
ON
DU
12.2
12.2 Introduction
CH
IVE
DB
YF
RE
ES
N O N - D I S C L O S U R E
CA
LE
SE
The MC68HC05V12 contains EEPROM memory. This section describes
the programming mechanisms for EEPROM memory.
AR
Freescale Semiconductor, Inc...
12.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
EEPROM
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
12.3 EEPROM Programming Register
CT
OR
, IN
C.2
006
R E Q U I R E D
EEPROM
The contents and use of the programming register are discussed here.
$1C
Bit 7
Read:
6
5
0
0
CPEN
Write:
Reset:
0
0
0
4
3
2
1
Bit 0
ER1
ER0
EELAT
EERC
EEPGM
0
0
0
0
0
DU
Figure 12-1. EEPROM Programming Register (EEPROG)
NOTE:
ON
Any reset including LVR will abort any write in progress when it is
asserted. Data written to the addressed byte will, therefore, be
indeterminate.
MIC
CPEN — Charge Pump Enable
CA
LE
SE
When set, CPEN enables the charge pump which produces the
internal programming voltage. This bit should be set with the EELAT
bit. The programming voltage will not be available until EEPGM is set.
The charge pump should be disabled when not in use. CPEN is
readable and writable and is cleared by reset.
ER1−ER0 — Erase Select Bits
YF
RE
ES
ER1 and ER0 form a 2-bit field which is used to select one of three
erase modes: byte, block, or bulk. Table 12-1 shows the modes
selected for each bit configuration. These bits are readable and
writable and are cleared by reset.
CH
IVE
DB
In byte erase mode, only the selected byte is erased. In block mode,
a 64-byte block of EEPROM is erased. The EEPROM memory space
is divided into four 64-byte blocks ($0240-$027F, $0280-$02BF,
$02C0-$02FF, and $0300-$033F), and doing a block erase to any
address within a block will erase the entire block. In bulk erase mode,
the entire 256 byte EEPROM section is erased.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
= Unimplemented
General Release Specification
MC68HC05V12 — Rev. 1.0
EEPROM
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
Table 12-1. Erase Mode Select
ER1
ER0
0
0
No Erase
1
Byte Erase
0
Block Erase
1
Bulk Erase
0
1
1
Mode
R E Q U I R E D
EEPROM
EEPROM Programming Register
SE
EERC — EEPROM RC Oscillator Control
CA
LE
When this bit is set, the EEPROM section uses the internal RC
oscillator instead of the CPU clock. After setting the EERC bit, delay
a time, tRCON, to allow the RC oscillator to stabilize. This bit is
ES
readable and writable and should be set by the user when the internal
bus frequency falls below 1.5 MHz. Reset clears this bit.
RE
EEPGM — EEPROM Programming Power Enable
AR
CH
IVE
DB
YF
EEPGM must be written to enable (or disable) the EEPGM function.
When set, EEPGM turns on the charge pump and enables the
programming (or erasing) power to the EEPROM array. When clear,
this power is switched off. This will enable pulsing of the programming
voltage to be controlled internally. This bit can be read at any time, but
can only be written to if EELAT = 1. If EELAT is not set, then EEPGM
cannot be set. Reset clears this bit.
MC68HC05V12 — Rev. 1.0
General Release Specification
EEPROM
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
MIC
ON
DU
When set, EELAT configures the EEPROM address and data bus for
programming. When EELAT is set, writes to the EEPROM array
cause the data bus and the address bus to be latched. This bit is
readable and writable, but reads from the array are inhibited if the
EELAT bit is set and a write to the EEPROM space has taken place.
When clear, address and data buses are configured for normal
operation. Reset clears this bit.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
EELAT — EEPROM Programming Latch
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
12.4 EEPROM Programming/Erasing Procedure
To program a byte of EEPROM, set EELAT = CPEN = 1,
set ER1 = ER0 = 0, write data to the desired address, and then set
EEPGM for a time, tEEPGM.
In general, all bits should be erased before being programmed.
However, if write/erase cycling is a concern, a procedure can be
followed to minimize the cycling of each bit in each EEPROM byte. The
erased state is 1; therefore, if any bits within the byte need to be changed
from a 0 to a 1, the byte must be erased before programming. The
decision whether to erase a byte before programming is summarized in
Table 12-2.
DU
MIC
EEPROM Data
To Be Programed
0
SE
0
EEPROM Data
Before Programming
Erase Before
Programming?
0
No
1
No
0
Yes
1
No
CA
LE
1
1
ON
Table 12-2. EEPROM Write/Erase Cycle Reduction
RE
ES
To erase a byte of EEPROM, set EELAT = 1, CPEN = 1, ER1 = 0 and
ER0 = 1, write to the address to be erased, and set EEPGM for a time,
tEBYT.
YF
To erase a block of EEPROM, set EELAT = 1, CPEN = 1, ER1 = 1 and
ER0 = 0, write to any address in the block, and set EEPGM for a time,
tEBLOCK.
IVE
DB
For a bulk erase, set EELAT = 1, CPEN = 1, ER1 = 1, and ER0 = 1, write
to any address in the array, and set EEPGM for a time, tEBULK.
CH
To terminate the programming or erase sequence, clear EEPGM, delay
for a time, tFPV, to allow the programming voltage to fall, and then clear
EELAT and CPEN to free up the buses. Following each erase or
programming sequence, clear all programming control bits.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
EEPROM
General Release Specification
MC68HC05V12 — Rev. 1.0
EEPROM
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
MC68HC05V12 — Rev. 1.0
General Release Specification
EEPROM
For More Information On This Product,
Go to: www.freescale.com
R E Q U I R E D
N O N - D I S C L O S U R E
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
The RC oscillator for the EEPROM is disabled automatically when
entering stop mode. To help conserve power, the user should disable
the RC oscillator before entering wait mode.
A G R E E M E N T
12.5 Operation in Stop and Wait Modes
CT
OR
, IN
C.2
006
EEPROM
Operation in Stop and Wait Modes
Freescale Semiconductor, Inc.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
CT
OR
, IN
C.2
006
R E Q U I R E D
EEPROM
General Release Specification
MC68HC05V12 — Rev. 1.0
EEPROM
For More Information On This Product,
Go to: www.freescale.com
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
Section 13. A/D Converter
13.1 Contents
SE
MIC
13.4 Digital Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.4.1
Conversion Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
13.4.2
Internal and Master Oscillators . . . . . . . . . . . . . . . . . . . . .125
13.4.3
Multi-Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . .126
A/D Status and Control Register. . . . . . . . . . . . . . . . . . . . . . .126
13.6
A/D Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.7
A/D during Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.8
A/D during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
RE
ES
CA
LE
13.5
YF
13.2 Introduction
CH
IVE
DB
The MC68HC05V12 includes a 5-channel, 8-bit, multiplexed input, and
a successive approximation analog-to-digital (A/D) converter.
MC68HC05V12 — Rev. 1.0
General Release Specification
A/D Converter
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
ON
DU
13.3 Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.1
Ratiometric Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.2
VREFH and VREFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.3
Accuracy and Precision. . . . . . . . . . . . . . . . . . . . . . . . . . .124
13.3.4
Conversion Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
AR
Freescale Semiconductor, Inc...
13.2
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
13.3 Analog Section
The following paragraphs describe the analog section.
13.3.1 Ratiometric Conversion
ON
DU
The A/D is ratiometric, with two dedicated pins supplying the reference
voltages (VREFH and VREFL). An input voltage equal to VREFH converts
to $FF (full scale) and an input voltage equal to VREFL converts to $00.
An input voltage greater than VREFH will convert to $FF with no overflow
indication. For ratiometric conversions, the source of each analog input
should use VREFH as the supply voltage and be referenced to VREFL.
MIC
13.3.2 VREFH and VREFL
ES
CA
LE
SE
The reference supply for the A/D is two dedicated pins rather than being
driven by the system power supply lines. The voltage drops in the
bonding wires of the heavily loaded system power pins would degrade
the accuracy of the A/D conversion. VREFH and VREFL can be any
voltage between VSSA and VCCA, as long as VREFH > VREFL; however,
the accuracy of conversions is tested and guaranteed only for VREFL =
VSSA and VREFH = VCCA.
RE
13.3.3 Accuracy and Precision
DB
YF
The 8-bit conversions shall be accurate to within ± 1 LSB including
quantization.
13.3.4 Conversion Process
IVE
The A/D reference inputs are applied to a precision internal digital-toanalog (D/A) converter. Control logic drives this D/A and the analog
output is successively compared to the selected analog input which was
sampled at the beginning of the conversion time. The conversion
process is monotonic and has no missing codes.
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
A/D Converter
General Release Specification
MC68HC05V12 — Rev. 1.0
A/D Converter
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
13.4.1 Conversion Times
DU
13.4.2 Internal and Master Oscillators
SE
MIC
ON
If the MCU bus (fOP) frequency is less than 1.0 MHz, an internal RC
oscillator (nominally 1.5 MHz) must be used for the A/D conversion
clock. This selection is made by setting the ADRC bit in the A/D status
and control registers to 1. In stop mode, the internal RC oscillator is
turned off automatically, although the A/D subsystem remains enabled
(ADON remains set). In wait mode the A/D subsystem remains
functional. See 13.7 A/D during Wait Mode.
CA
LE
When the internal RC oscillator is being used as the conversion clock,
three limitations apply:
RE
ES
1. The conversion complete flag (COCO) must be used to determine
when a conversion sequence has been completed, due to the
frequency tolerance of the RC oscillator and its asynchronism with
regard to the MCU bus clock.
DB
YF
2. The conversion process runs at the nominal 1.5 MHz rate, but the
conversion results must be transferred to the MCU result registers
synchronously with the MCU bus clock so conversion time is
limited to a maximum of one channel per bus cycle.
CH
IVE
3. If the system clock is running faster than the RC oscillator, the RC
oscillator should be turned off and the system clock used as the
conversion clock.
AR
Freescale Semiconductor, Inc...
Each channel of conversion takes 32 clock cycles, which must be at a
frequency equal to or greater than 1 MHz.
MC68HC05V12 — Rev. 1.0
General Release Specification
A/D Converter
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
The following paragraphs describe the digital section.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
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13.4 Digital Section
R E Q U I R E D
A/D Converter
Digital Section
Freescale Semiconductor, Inc.
A multiplexer allows the A/D converter to select one of five external
analog signals and four internal reference sources.
13.5 A/D Status and Control Register
The following paragraphs describe the function of the A/D status and
control register.
$1E
Bit 7
Read:
6
5
ADRC
ADON
DU
Freescale Semiconductor, Inc...
COCO
0
2
1
Bit 0
CH4
CH3
CH2
CH1
CH0
0
0
0
0
0
0
0
MIC
Reset:
3
ON
Write:
4
= Unimplemented
SE
Figure 13-1. A/D Status and Control Register (ADSCR)
COCO — Conversions Complete
DB
YF
RE
ES
CA
LE
This read-only status bit is set when a conversion is completed,
indicating that the A/D data register contains valid results. This bit is
cleared whenever the A/D status and control register is written and a
new conversion automatically started, or whenever the A/D data
register is read. Once a conversion has been started by writing to the
A/D status and control register, conversions of the selected channel
will continue every 32 cycles until the A/D status and control register
is written again. In this continuous conversion mode the A/D data
register will be filled with new data, and the COCO bit set, every 32
cycles. Data from the previous conversion will be overwritten
regardless of the state of the COCO bit prior to writing.
CH
IVE
ADRC — RC Oscillator Control
When ADRC is set, the A/D section runs on the internal RC oscillator
instead of the CPU clock. The RC oscillator requires a time, tRCON, to
stabilize, and results can be inaccurate during this time.
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
13.4.3 Multi-Channel Operation
A G R E E M E N T
R E Q U I R E D
A/D Converter
General Release Specification
MC68HC05V12 — Rev. 1.0
A/D Converter
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
the current sources to stabilize, and results can be inaccurate during
this time. This bit turns on the charge pump.
DU
CN4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to
select one of nine A/D channels, including four internal references.
Channels $0−4 correspond to port D input pins on the MCU. Channels
$10−$13 are used for internal reference points. In single-chip mode,
channel $13 is reserved and converts to $00. Table 13-1 shows the
signals selected by the channel select field.
ON
Table 13-1. A/D Channel Assignments
Signal
MIC
CH4–CH0
AD0–AD4
$10
VREFH
SE
00–04
(VREFH–VREFL)/2
$12
VREFL
$13
Factory Test
$05−$0F, $14−$1F
Unused
ES
CA
LE
$11
RE
13.6 A/D Data Register
DB
YF
An 8-bit result register is provided. This register is updated each time the
COCO bit is set.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
D7
D6
D5
D4
D3
D2
D1
D0
IVE
$1D
Write:
CH
Reset:
AR
Freescale Semiconductor, Inc...
CH4–CH0 — Channel Select Bits
Unaffected by reset
= Unimplemented
Figure 13-2. A/D Data Register (ADDR)
MC68HC05V12 — Rev. 1.0
General Release Specification
A/D Converter
For More Information On This Product,
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A G R E E M E N T
When the A/D is turned on (ADON = 1), it requires a time, tADON, for
N O N - D I S C L O S U R E
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OR
, IN
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ADON — A/D On
R E Q U I R E D
A/D Converter
A/D Data Register
Freescale Semiconductor, Inc.
The A/D converter continues normal operation during wait mode. To
decrease power consumption during wait mode, it is recommended that
both the ADON and ADRC bits in the A/D status and control registers be
cleared if the A/D converter is not being used. If the A/D converter is in
use and the system clock rate is above 1.0 MHz, it is recommended that
the ADRC bit be cleared.
DU
As the A/D converter continues to function normally in wait mode, the
COCO bit is not cleared.
13.8 A/D during Stop Mode
CA
LE
SE
MIC
In stop mode, the comparator and charge pump are turned off and the
A/D ceases to function. Any pending conversion is aborted. When the
clocks begin oscillation upon leaving stop mode, a finite amount of time
passes before the A/D circuits stabilize enough to provide conversions
to the specified accuracy. Normally, the delays built into the device when
coming out of stop mode are sufficient for this purpose so that no explicit
delays need to be built into the software.
NOTE:
CH
IVE
DB
YF
RE
ES
Although the comparator and charge pump are disabled in stop mode,
the A/D data and status/control registers are not modified. Disabling the
A/D prior to entering stop mode will not affect the stop mode current
consumption.
AR
Freescale Semiconductor, Inc...
A G R E E M E N T
NOTE:
N O N - D I S C L O S U R E
CT
OR
, IN
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13.7 A/D during Wait Mode
ON
R E Q U I R E D
A/D Converter
General Release Specification
MC68HC05V12 — Rev. 1.0
A/D Converter
For More Information On This Product,
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14.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
14.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
14.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
DU
Freescale Semiconductor, Inc...
14.1 Contents
SE
MIC
ON
14.5 BDLC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
14.5.1
Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
14.5.2
Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
14.5.3
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
14.5.4
BDLC Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.5.5
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.5.6
Digital Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .135
RE
ES
CA
LE
14.6 BDLC CPU Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.6.1
BDLC Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . .136
14.6.2
BDLC Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . .138
14.6.3
BDLC State Vector Register . . . . . . . . . . . . . . . . . . . . . . .144
14.6.4
BDLC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
14.6.5
BDLC Analog and Roundtrip Delay. . . . . . . . . . . . . . . . . .147
AR
CH
IVE
DB
YF
14.7 BDLC Protocol Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
14.7.1
Protocol Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
14.7.2
Rx and Tx Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . .151
14.7.3
Rx and Tx Shadow Registers . . . . . . . . . . . . . . . . . . . . . .151
14.7.4
Digital Loopback Multiplexer . . . . . . . . . . . . . . . . . . . . . . .151
14.7.5
State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
14.7.5.1
4X Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
14.7.5.2
Receiving a Message in Block Mode . . . . . . . . . . . . . . .152
14.7.5.3
Transmitting a Message in Block Mode . . . . . . . . . . . . .152
14.7.6
J1850 Bus Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
14.7.6.1
CRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
14.7.6.2
Symbol Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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A G R E E M E N T
Section 14. Byte Data Link Controller-Digital (BDLC-D)
N O N - D I S C L O S U R E
CT
OR
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C.2
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General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
R E Q U I R E D
Byte Data Link Controller-Digital
A G R E E M E N T
14.8 BDLC MUX Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.8.1
Rx Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
14.8.1.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
14.8.1.2
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
14.8.2
J1850 Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
14.8.3
J1850 VPW Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.8.3.1
Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
14.8.3.2
Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
14.8.3.3
Normalization Bit (NB) . . . . . . . . . . . . . . . . . . . . . . . . . .163
14.8.3.4
Start of Frame Symbol (SOF) . . . . . . . . . . . . . . . . . . . .163
14.8.4
EOD − End of Data Symbol. . . . . . . . . . . . . . . . . . . . . . . .163
14.8.4.1
End of Frame Symbol (EOF) . . . . . . . . . . . . . . . . . . . . .163
14.8.4.2
Inter-Frame Separation Symbol (IFS) . . . . . . . . . . . . . .163
14.8.4.3
Break Signal (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . .163
14.8.5
J1850 VPW Valid/Invalid Bits and Symbols . . . . . . . . . . .164
14.8.5.1
Invalid Passive Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
14.8.5.2
Valid Passive Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .165
14.8.5.3
Valid Passive Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .166
14.8.5.4
Valid EOD Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
14.8.5.5
Valid EOF and IFS Symbol . . . . . . . . . . . . . . . . . . . . . .167
14.8.5.6
Idle Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
14.8.5.7
Invalid Active Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.8
Valid Active Logic 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.9
Valid Active Logic 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.10 Valid SOF Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
14.8.5.11 Valid BREAK Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . .169
14.8.6
Message Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
CH
IVE
14.9 BDLC Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.9.1
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.9.2
BDLC Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
14.9.3
BDLC Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
AR
N O N - D I S C L O S U R E
Framing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Bus Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
Break (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
CT
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, IN
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14.7.6.3
14.7.6.4
14.7.6.5
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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OR
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14.2 Introduction
The byte data link controller (BDLC) provides access to an external
serial communication multiplex bus, operating according to the SAE
J1850 protocol.
14.3 Features
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
Introduction
10.4 kbps Variable Pulse Width (VPW) Bit Format
•
Digital Noise Filter
•
Collision Detection
•
Hardware Cyclical Redundancy Check (CRC) Generation and
Checking
•
Two Power-Saving Modes with Automatic Wakeup on Network
Activity
•
Polling and CPU Interrupts
•
Receive and Transmit Block Modes Supported
•
Supports 4X Receive Mode (41.6 kbps)
•
•
RE
•
In-Frame Response (IFR) Types 0, 1, 2, and 3 Supported
ON
MIC
SE
LE
CA
ES
Digital Loopback Mode
Analog Loopback Mode
DB
IVE
CH
AR
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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A G R E E M E N T
•
N O N - D I S C L O S U R E
SAE J1850 Class B Data Communications Network Interface
Compatible
DU
•
YF
Freescale Semiconductor, Inc...
BDLC module features include:
Freescale Semiconductor, Inc.
TO J1850 TRANSCEIVER
MUX INTERFACE
PROTOCOL HANDLER
Freescale Semiconductor, Inc...
DU
Rx/Tx BUFFERS
BDLC
TO CPU
MIC
ON
CPU INTERFACE
SE
Figure 14-1. BDLC Block Diagram
RE
ES
CA
LE
The CPU interface contains the software addressable registers and
provides the link between the CPU and the buffers. The buffers provide
storage for data received and data to be transmitted onto the J1850 bus.
The protocol handler is responsible for the encoding and decoding of
data bits and special message symbols during transmission and
reception. The MUX interface provides the link between the BDLC digital
section and the analog physical interface. The wave shaping, driving,
and digitizing of data is performed by the physical interface.
CH
IVE
DB
YF
Use of the BDLC module in message networking fully implements the
SAE Standard J1850 Class B Data Communication Network Interface
Specification.
AR
N O N - D I S C L O S U R E
CT
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, IN
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14.4 Functional Description
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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Freescale Semiconductor, Inc.
VDD > VDD (MIN) AND
ANY MCU RESET SOURCE ASSERTED
ON
DU
VDD ≤ VDD (MIN)
MIC
Reset
NO MCU RESET SOURCE ASSERTED
CA
LE
SE
ANY MCU RESET SOURCE ASSERTED
FROM ANY MODE
(COP, ILLADDR, PU, RESET, LVR, POR)
Run
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
YF
RE
ES
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
BDLC Stop
WAIT INSTRUCTION AND WCM = 0
BDLC Wait
IVE
DB
STOP INSTRUCTIONOR
WAIT INSTRUCTION AND WCM = 1
CH
Figure 14-2. BDLC Operating Modes State Diagram
AR
Freescale Semiconductor, Inc...
Power Off
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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A G R E E M E N T
The BDLC has five main modes of operation which interact with the
power supplies, pins, and the rest of the MCU as shown in Figure 14-2.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
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14.5 BDLC Operating Modes
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC Operating Modes
Freescale Semiconductor, Inc.
14.5.1 Power Off Mode
CT
OR
, IN
C.2
006
R E Q U I R E D
Byte Data Link Controller-Digital
Power off mode is entered from the reset mode whenever the BDLC
supply voltage VDD drops below its minimum specified value for the
BDLC to guarantee operation. The BDLC will be placed in the reset
mode by low-voltage reset (LVR) before being powered down. In this
mode, the pin input and output specifications are not guaranteed.
SE
MIC
ON
DU
This mode is entered from the power off mode whenever the BDLC
supply voltage VDD rises above its minimum specified value (VDD(MIN))
and some MCU reset source is asserted. To prevent the BDLC from
entering an unknown state, the internal MCU reset is asserted while
powering up the BDLC. BDLC reset mode also is entered from any other
mode as soon as one of the MCU’s possible reset sources (such as LVR,
POR, COP watchdog, reset pin, etc.) is asserted.
ES
CA
LE
In this mode, the internal BDLC voltage references are operative, VDD is
supplied to the internal circuits, which are held in their reset state, and
the internal BDLC system clock is running. Registers will assume their
reset condition. Outputs are held in their programmed reset state and
inputs and network activity are ignored.
RE
14.5.3 Run Mode
DB
YF
This mode is entered from reset mode after all MCU reset sources are
no longer asserted. It is entered from BDLC wait mode whenever activity
is sensed on the J1850 bus.
IVE
Run mode is entered from BDLC stop mode whenever network activity
is sensed, although messages will not be received properly until the
clocks have stabilized and the CPU is in the run mode also.
In this mode, normal network operation takes place. The user should
ensure that all BDLC transmissions have ceased before exiting this
mode.
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
14.5.2 Reset Mode
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
ON
14.5.5 BDLC Stop Mode
MIC
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR register is set previously.
ES
14.5.6 Digital Loopback Mode
CA
LE
SE
In this mode, the BDLC internal clocks are stopped, but the physical
interface circuitry is placed in a low-power mode and awaits network
activity. If network activity is sensed, then a CPU interrupt request will be
generated, restarting the BDLC internal clocks.
IVE
DB
YF
RE
When a bus fault has been detected, the digital loopback mode is used
to determine if the fault condition is caused by failure in the node’s
internal circuits or elsewhere in the network, including the node’s analog
physical interface. In this mode, the receive digital input (RxPD) is
connected to the transmit digital output (TxPD) to form the loopback
connection. TxPD is not observable at the output pin.
CH
14.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the
BDLC. It consists of five user registers. A full description of each register
follows.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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A G R E E M E N T
DU
In this mode, the BDLC internal clocks continue to run, but the physical
interface circuitry is placed in a low-power mode and waits for any
activity on the bus. The first passive-to-active transition of the bus wakes
up the BDLC and the CPU. If a valid byte is successfully received, a CPU
interrupt request will be generated.
AR
Freescale Semiconductor, Inc...
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and if the WCM bit in
the BCR register is cleared previously.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.5.4 BDLC Wait Mode
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
Freescale Semiconductor, Inc.
14.6.1 BDLC Control Register 1
CT
OR
, IN
C.2
006
R E Q U I R E D
Byte Data Link Controller-Digital
This register is used to configure and control the BDLC.
$003A
Bit 7
6
5
IMSG
CLKS
R1
1
1
1
Read:
Write:
Reset:
4
3
2
0
0
R0
0
0
0
1
Bit 0
IE
WCM
0
0
DU
Figure 14-3. BDLC Control Register 1 (BCR1)
IMSG — Ignore Message
ES
CA
LE
SE
MIC
ON
This bit is used to disable the receiver until a new start of frame (SOF)
is detected.
1 = Disable receiver. When set, all BDLC interrupt requests will be
masked and the status bits will be held in their reset state. If
this bit is set while the BDLC is receiving a message, the rest
of the incoming message will be ignored.
0 = Enable receiver. This bit is cleared automatically by the
reception of an SOF symbol or a BREAK symbol. It will then
generate interrupt requests and will allow changes of the
status register to occur. However, these interrupts may still be
masked by the interrupt enable (IE) bit.
RE
CLKS — Clock select
The nominal BDLC operating frequency (fBDLC) must always be
IVE
DB
YF
1.048576 MHz or 1 MHz for J1850 bus communications to take place.
The CLKS register bit is provided to allow the user to indicate to the
BDLC which frequency (1.048576 MHz or 1 MHz) is used so that each
symbol time can be adjusted automatically.
1 = Binary frequency (1.048576 MHz) is used for fBDLC.
0 = Integer frequency (1 MHz) is used. for fBDLC.
CH
R1 and R0 — Rate Select
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
= Unimplemented
These bits determine the amount by which the frequency of the MCU
system clock signal (fOP) is divided to form the MUX interface clock
(fBDLC) which defines the basic timing resolution of the MUX interface.
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table 14-1. BDLC Rate Selection for Binary Frequencies
Clock Frequency
fOP =1.048576 MHz
Freescale Semiconductor, Inc...
fOP = 2.09715 MHz
DU
fOP = 4.19430 MHz (see Note)
fOP = 8.38861 MHz (see Note)
R1
R0
Division
fBDLC
0
0
1
1.048576 MHz
0
1
2
1.048576 MHz
1
0
4
1.048576 MHz
1
1
8
1.048576 MHz
ON
NOTE: Invalid option on this MCU
R1
R0
Division
fBDLC
0
0
1
1.000000 MHz
fOP = 2.00000 MHz
5
1
2
1.000000 MHz
fOP = 4.00000 MHz (see Note)
1
0
4
1.000000 MHz
LE
MIC
Table 14-2. BDLC Rate Selection for Integer Frequencies
1
1
8
1.000000 MHz
Clock Frequency
SE
fOP = 1.00000 MHz
fOP = 8.00000 MHz (see Note)
A G R E E M E N T
CT
OR
, IN
C.2
006
They may be written only once after reset and then they become readonly bits. The value programmed into these bits is dependent on the
chosen MCU system clock frequency per Table 14-1 and
Table 14-2.
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
ES
IE — Interrupt Enable
AR
CH
IVE
DB
YF
RE
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting BDLC stop or wait modes. By performing the specified actions
upon the BDLC’s registers, interrupt requests will be maintained until
all interrupt request sources are cleared. By performing the specified
actions upon the BDLC’s registers, interrupts pending at the time that
this bit is cleared may be lost.
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
If the programmer does not want to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. Refer to
14.6.3 BDLC State Vector Register for a description of BSVR
register.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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N O N - D I S C L O S U R E
CA
NOTE: Invalid option on this MCU
Freescale Semiconductor, Inc.
R E Q U I R E D
Byte Data Link Controller-Digital
CT
OR
, IN
C.2
006
WCM — Wait Clock Mode
This bit determines the operation of the BDLC during CPU wait mode.
See 14.5.5 BDLC Stop Mode and 14.5.4 BDLC Wait Mode for more
details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
Bit 7
6
5
ALBE
DLBE
1
1
Read:
Reset:
RX4XE
4
3
2
1
Bit 0
NBFS
TEOD
TSIFR
TMIFR1
TMIFR0
0
0
0
0
0
MIC
Write:
ON
$003B
DU
This register controls transmitter operations of the BDLC.
0
SE
Figure 14-4. BDLC Control Register 2 (BCR2)
ALBE — Analog Loopback Mode
IVE
DB
YF
RE
ES
CA
LE
This bit is used to reset the BDLC state machine to a known state after
the user has put the off-chip analog transceiver in loopback mode.
When the user clears ALBE to indicate that the off-chip analog
transceiver is no longer in loopback mode, the BDLC waits for an EOF
symbol before attempting to transmit.
1 = Indicates to the BDLC that the off-chip analog transceiver is
being put in analog loopback mode.
0 = When ALBE is cleared, the BDLC requires the bus to be idle for
a minimum of end-of-frame symbol (Ttv4) time before allowing
a reception of a message. The BDLC requires the bus to be
idle for a minimum of inter-frame separator symbol (Ttv6) time
before allowing any message to be transmitted.
CH
DLBE — Digital Loopback Mode
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
14.6.2 BDLC Control Register 2
This bit determines the source to which the digital receive input is
connected to and can be used to isolate the bus fault condition. If a
fault condition has been detected on the bus, this control bit allows the
programmer to connect the digital transmit output to the digital receive
input. In this configuration, data sent from the transmit buffer should
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
CA
LE
SE
MIC
ON
This bit determines if the BDLC operates at normal transmit and
receive speed (10.4 kbps) or receive only at 41.6 kbps. This feature
is useful for fast download of data into a J1850 node for diagnostic or
factory programming.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
Reception of a BREAK symbol automatically clears this bit and
sets BSVR (see 14.7.3 Rx and Tx Shadow Registers)
register to $1C.
ES
NBFS — Normalization Bit Format Select
AR
CH
IVE
DB
YF
RE
This bit controls the format of the normalization bit (NB). SAE J1850
strongly encourages the use of an active long, 0, for in-frame
responses containing CRC and active short, 1, for in-frame responses
without CRC.
1 = NB that is received or transmitted is a 0 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 1 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
0 = NB that is received or transmitted is a 1 when the response part
of an in-frame response (IFR) ends with a CRC byte. NB that
is received or transmitted is a 0 when the response part of an
in-frame response (IFR) does not end with a CRC byte.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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A G R E E M E N T
RX4XE — Receive 4X Enable
N O N - D I S C L O S U R E
DU
Freescale Semiconductor, Inc...
CT
OR
, IN
C.2
006
be reflected back into the receive buffer. If no faults exist in the digital
block, the fault is in the physical interface block or elsewhere on the
J1850 bus.
1 = When set, RxPD is connected to TxPD. The BDLC is now in
digital loopback mode of operation and the TxPD signal is not
observable on the TXP pin.
0 = When cleared, RxPD is connected to the RXP input pin and the
BDLC is taken out of digital loopback mode. Now the BDLC
can drive and receive from the J1850 bus normally after the
bus is idle for at least a Ttv4 time for receive and a Ttv6 time for
transmit.
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
Freescale Semiconductor, Inc.
R E Q U I R E D
Byte Data Link Controller-Digital
CT
OR
, IN
C.2
006
TEOD — Transmit End of Data
DU
ON
MIC
SE
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control
DB
YF
RE
ES
CA
LE
These three bits control the type of in-frame response being sent. The
programmer should not set more than one of these control bits to 1 at
any given time. However, if more than one of these three control bits
are set to 1, the priority encoding logic will force the internal register
bits to a known value as shown in Table 14-3. But, when these bits
are read, they will be the same as written earlier. For instance, if 011
is written to TSIFR, TMIFR1, and TMIFR0, then internally they’ll be
encoded as 010. However, when these bits are later read back, the
value will still be 011.
Table 14-3. Transmit In-Frame Response Control
Bit Priority Encoding
WRITE
(then READ
BACK)
TMIFR1
WRITE
(then READ
BACK)
TMIFR0
ACTUAL
TSIFR
ACTUAL
TMIFR1
ACTUAL
TMIFR0
0
0
0
0
0
0
1
X
X
1
0
0
0
1
X
0
1
0
0
0
1
0
0
1
CH
IVE
WRITE
(then READ
BACK)
TSIFR
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
The programmer sets this bit to indicate the end of a message being
sent by the BDLC. It will append an 8-bit CRC after completing
transmission of the current byte. This bit also is used to end an IFR.
If the transmit shadow register (refer to 14.7.3 Rx and Tx Shadow
Registers for a description of the transmit shadow register) is full
when TEOD is set, the CRC byte will be transmitted after the current
byte in the Tx shift register and the byte in the Tx shadow register
have been transmitted. Once TEOD is set, the transmit data register
empty flag (TDRE) in the BDLC state vector register (BSVR) is
cleared to allow lower priority interrupts to occur.
1 = Transmit EOD symbol
0 = The TEOD bit will be cleared automatically at the rising edge of
the first CRC bit that is sent or whenever an error is detected.
If TEOD is used to end an IFR transmission, it is cleared when
the BDLC receives a valid EOD symbol or an error condition
occurs.
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
CRC
EOD
NB
CRC
EOD
SOF
HEADER
NB
HEADER
DATA FIELD
ID N
NB
IFR DATA FIELD
CRC
MIC
CRC
EOF
EOD
DATA FIELD
EOD
SOF
ON
TYPE 2 — SINGLE BYTE FROM MULTIPLE RESPONDERS
HEADER
ID1
DU
SOF
TYPE 3 — MULTIPLE BYTES FROM A SINGLE RESPONDER
SE
NB = Normalized Bit
ID = Identifier (usually the physical address of the responder(s))
LE
Figure 14-5. Types of In-Frame Response
DB
YF
RE
ES
This bit is used to request the BDLC to transmit the byte in the BDLC
data register (BDR) as a single byte IFR with no CRC.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by the byte in the BDR.
0 = The TSIFR bit will be automatically cleared once the BDLC has
successfully transmitted the byte in the BDR onto the bus, or
TEOD is set by the CPU, or an error is detected on the bus.
CH
IVE
If a loss of arbitration occurs when the BDLC attempts to transmit the
byte in the BDLC, once the IFR byte winning arbitration completes
transmission, the BDLC will again attempt to transmit the byte in the
BDR (with no normalization bit). The BDLC will continue transmission
attempts until an error is detected on the bus, or TEOD is set by the
CPU, or the BDLC transmission is successful. If loss of arbitration
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
CA
TSIFR — Transmit Single Byte IFR with No CRC (Type 1)
AR
Freescale Semiconductor, Inc...
TYPE 1 — SINGLE BYTE FROM A SINGLE RESPONDER
ID
A G R E E M E N T
DATA FIELD
TYPE 0 — NO IFR
EOF
EOD
CRC
EOF
EOD
DATA FIELD
EOF
EOD
SOF
HEADER
CT
OR
, IN
C.2
006
The BDLC supports the in-frame response (IFR) feature of J1850.
The three types of J1850 IFR are shown in Figure 14-5.
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
Freescale Semiconductor, Inc.
R E Q U I R E D
Byte Data Link Controller-Digital
CT
OR
, IN
C.2
006
occurs in the last two bits of the IFR byte, two additional 1 bits will not
be sent out because the BDLC will attempt to retransmit the byte in
the Tx shift register after the IFR byte winning arbitration completes
transmission.
If the programmer attempts to set the TSIFR bit immediately after the
EOD symbol has been received from the bus, the TSIFR bit will
remain in the reset state, and no attempt will be made to transmit the
IFR byte.
ON
DU
This bit requests the BDLC to transmit the byte in the BDLC data
register (BDR) as the first byte of a multiple byte IFR with CRC or as
a single byte IFR with CRC.
RE
ES
CA
LE
SE
MIC
If this bit is set prior to a valid EOD being received with no CRC error
and once the EOD symbol has been received, the BDLC will attempt
to transmit the appropriate normalization/format symbol, followed by
the byte in the BDR. After the byte in the BDR has been loaded into
the transmit shift register, a TDRE interrupt will occur, similar to the
main message transmit sequence. The programmer should then load
the next byte of the IFR into the BDR for transmission. When the last
byte of the IFR has been loaded into the BDR, the programmer should
set the TEOD bit in the BCR register. This will instruct the BDLC to
transmit a CRC byte once the byte in the BDR is transmitted, and then
transmit an EOD symbol, indicating the end of the IFR portion of the
message frame.
DB
YF
The TMIFR1 bit will be automatically cleared once the BDLC has
successfully transmitted the CRC byte and EOD symbol, by the
detection of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to the BDR
after the TDRE interrupt.
If a loss of arbitration occurs when the BDLC is transmitting any
multiple byte IFR, BDLC will go to the loss of arbitration state, set the
appropriate flag, and cease transmission. If the BDLC loses
arbitration during the IFR, the TMIFR1 bit will be cleared and no
attempt will be made to retransmit the byte in the BDR. If loss of
arbitration occurs in the last two bits of the IFR byte, two additional 1
bits will be sent out.
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
TMIFR1 — Transmit Multiple Byte IFR with CRC (Type 3)
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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Freescale Semiconductor, Inc.
ES
CA
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 2)
YF
RE
This bit is used to request the BDLC to transmit the byte in the BDLC
data register (BDR) as the first byte of a multiple byte IFR without
CRC.
AR
CH
IVE
DB
If this bit is set prior to a valid EOD being received with no CRC error,
once the EOD symbol has been received, the BDLC will attempt to
transmit the appropriate normalization/format symbol, followed by the
byte in the BDR. After the byte in the BDR has been loaded into the
transmit shift register, a TDRE interrupt will occur, similar to the main
message transmit sequence. The programmer should then load the
next byte of the IFR into the BDR for transmission. When the last byte
of the IFR has been loaded into the BDR, the programmer should set
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
If the programmer attempts to set the TMIFR1 bit immediately after
the EOD symbol has been received from the bus, the TMIFR1 bit will
remain in the reset state, and no attempt will be made to transmit an
IFR byte.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into BDR register. After TEOD has
been set and the last IFR byte has been transmitted, the CRC
byte is transmitted.
0 = The TMIFR1 bit will be cleared automatically, once the BDLC
has successfully transmitted the CRC byte and EOD symbol,
by the detection of an error on the multiplex bus or by a
transmitter underrun caused when the programmer does not
write another byte to the BDR after the TDRE interrupt.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
If the programmer wishes to transmit a single byte followed by a CRC
byte, the programmer should load the byte into the BDR before the
EOD symbol has been received and then set the TMIFR1 bit. Once
the EOD interrupt occurs, the programmer should then set the TEOD
bit in the BCR. This will result in the byte in the BDR being the only
byte transmitted before the IFR CRC byte, and no TDRE interrupt will
be generated.
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
Freescale Semiconductor, Inc.
R E Q U I R E D
Byte Data Link Controller-Digital
CT
OR
, IN
C.2
006
the TEOD bit in the BCR2 register. This will instruct the BDLC to
transmit an EOD symbol, indicating the end of the IFR portion of the
message frame. The BDLC will not append a CRC.
The TMIFR0 bit will be cleared automatically, once the BDLC has
successfully transmitted the EOD symbol, by the detection of an error
on the multiplex bus or by a transmitter underrun caused when the
programmer does not write another byte to the BDR following the
TDRE interrupt.
DU
DB
YF
RE
ES
CA
LE
SE
MIC
ON
If the programmer attempts to set the TMIFR0 bit after the EOD
symbol has been received from the bus, the TMIFR0 bit will remain in
the reset state and no attempt will be made to transmit an IFR byte.
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into BDR register. After TEOD has
been set, the last IFR byte to be transmitted will be the last byte
which was written into the BDR register.
0 = The TMIFR0 bit will be cleared automatically once the BDLC
has successfully transmitted the EOD symbol, by the detection
of an error on the multiplex bus or by a transmitter underrun
caused when the programmer does not write another byte to
the BDR after the TDRE interrupt.
14.6.3 BDLC State Vector Register
IVE
This register is provided to substantially decrease the CPU overhead
associated with servicing interrupts while under operation of a MUX
protocol. It provides an index offset that is directly related to the BDLC’s
current state, which can be used with a user supplied jump table to
rapidly enter an interrupt service routine. This eliminates the need for the
user to maintain a duplicate state machine in software.
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
If a loss of arbitration occurs when the BDLC is transmitting, the
TMIFR0 bit will be cleared, and no attempt will be made to retransmit
the byte in the BDR. If loss of arbitration occurs in the last two bits of
the IFR byte, two additional one bits (active short bits) will be sent out.
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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Freescale Semiconductor, Inc.
Bit 7
6
5
Read:
0
0
I3
0
0
0
Write:
Reset:
4
3
2
1
Bit 0
I2
I1
I0
0
0
0
0
0
0
0
CT
OR
, IN
C.2
006
$003C
= Unimplemented
Figure 14-6. BDLC State Vector Register (BSVR)
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
I3
I2
I1
I0
Interrupt Source
Priority
$00
0
0
0
0
No Interrupts Pending
0 (lowest)
$04
0
0
0
1
Received EOF
1
$08
0
0
1
0
Received IFR byte (RXIFR)
2
$0C
0
0
1
1
Rx data register full (RDRF)
3
$10
0
1
0
Tx data register empty (TDRE)
4
$14
0
1
0
1
Loss of arbitration
5
$18
LE
0
0
1
CA
1
0
CRC error
6
0
1
1
1
Symbol invalid or out of range
7
1
0
0
0
Wakeup
8 (highest)
ES
$1C
SE
BSVR
MIC
ON
Table 14-4. Interrupt Sources
RE
$20
A read of the BSVR in either a symbol invalid or loss of arbitration
condition will result in removal of a pending Tx data register empty
condition.
AR
CH
IVE
DB
YF
Bits I0, I1, I2, and I3 are cleared by a read of the BSVR register except
when the BDLC data register needs servicing (RDRF, RXIFR, or
TDRE conditions). RXIFR and RDRF can be cleared only by a read
of the BSVR register followed by a read of BDR. TDRE can either be
cleared by a read of the BSVR register followed by a write to the
BDLC BDR register or by setting the TEOD bit in BCR2.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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N O N - D I S C L O S U R E
DU
Freescale Semiconductor, Inc...
These bits indicate the source of the interrupt request that is currently
pending. The encoding of these bits is found in Table 14-4.
A G R E E M E N T
I0, I1, I2, I3 — Interrupt Source
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
Upon receiving a BDLC interrupt, the user may read the value within
the BSVR, transferring it to the CPU’s index register. The value may
then be used to index into a jump table with entries four bytes apart to
quickly enter the appropriate service routine. For example:
SERVICE LDX
JMP
*
*
JMPTAB JMP
NOP
JMP
NOP
JMP
NOP
SERVE0Service condition #0
SERVE1Service condition #1
DU
SERVE2Service condition #2
.
.
SERVE8Service condition #8
ON
.
JMP
END
BSVR Fetch State Vector Number
JMPTAB,XEnter service routine,
(must end in an ’RTI’)
MIC
.
NOTE:
LE
SE
The NOPs are just used to align the JMPs onto 4-byte boundaries so
that the value in the BSVR may be used intact. Each of the service
routines must end with an RTI instruction to guarantee correct continued
operation of the device. Note also that the first entry can be omitted since
it corresponds to no interrupt occurring.
RE
ES
CA
The service routines should clear all of the sources that are causing
the pending interrupts. Note that the clearing of a high priority
interrupt may still leave a lower priority interrupt pending, in which
case bits I0, I1, and I2 of the BSVR will then reflect the source of the
remaining interrupt request.
DB
YF
If fewer states are used or if a different software approach is taken,
the jump table may be made smaller or omitted altogether.
14.6.4 BDLC Data Register
IVE
This register is used to pass the data to be transmitted to the J1850 bus
from the CPU to the BDLC. It is also used to pass data received from the
J1850 bus to the CPU. Each data byte (after the first one) should be
written only after a Tx data register empty (TDRE) interrupt has occurred
or the BSVR register has been polled indicating this condition.
CH
AR
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
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Byte Data Link Controller-Digital (BDLC-D)
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MIC
ON
DU
The receive shadow register works similarly. Once a complete byte has
been received, the receive shift register stores the newly received byte
into the receive shadow register. The RDRF flag is set to indicate that a
new byte of data has been received. The programmer has one BDLC
byte reception time to read the shadow register and clear the RDRF flag
before the shadow register is overwritten by the newly received byte.
ES
CA
LE
SE
To abort an in-progress transmission, the programmer should simply
stop loading more data into the BDR. This will cause a transmitter
underrun error and the BDLC automatically will disable the transmitter
on the next non-byte boundary. This means that the earliest a
transmission can be halted is after at least one byte (plus two extra 1
bits) has been transmitted. The receiver will pick this up as an error and
relay it in the state vector register as an invalid symbol error.
Read:
Bit 7
RE
$003D
D7
5
4
3
2
1
Bit 0
D6
D5
D4
D3
D2
D1
D0
YF
Write:
6
Indeterminate after reset
Figure 14-7. BDLC Data Register (BDR)
IVE
DB
Reset:
AR
CH
14.6.5 BDLC Analog and Roundtrip Delay
This register is used to program the BDLC so that it compensates for
various delays of different external transceivers. The default delay value
is 16 µs. The BARD offset bits range from 0 through 15. Table 14-1
illustrates the corresponding expected delays on the external
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
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The BDR register is double buffered via a transmit shadow register and
a receive shadow register. After the byte in the transmit shift register has
been transmitted, the byte currently stored in the transmit shadow
register is loaded into the transmit shift register. Once the transmit shift
register has shifted the first bit out, the TDRE flag is set, and the shadow
register is ready to accept the next byte of data.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
Data read from this register will be the last data byte received from the
J1850 bus. This received data should only be read after a Rx data
register full (RDRF) interrupt has occurred.
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
Freescale Semiconductor, Inc.
R E Q U I R E D
Byte Data Link Controller-Digital
This register can be written to only once after a reset. Subsequent writes
to the register will have no effect.
$003E
Bit 7
6
5
ATE
RXPOL
0
1
1
0
Read:
Write:
Reset:
A G R E E M E N T
4
3
2
1
Bit 0
0
BO3
BO2
BO1
BO0
0
0
1
1
1
ON
Read: Any time
Write: Once after reset
DU
Figure 14-8. BDLC Analog Roundtrip Delay Register (BARD)
MIC
ATE — Analog Transceiver Enable
LE
SE
The analog transceiver enable (ATE) bit is used to select either the
on-board or an off-chip analog transceiver.
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
NOTE:
CA
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
CH
IVE
DB
YF
RE
ES
RXPOL — RXP Polarity Select
1 = Receiver polarity is J1850 protocol without an inversion
0 = Receiver polarity is inverted J1850 protocol
AR
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
transceivers to be connected to the BDLC. This allows flexibility of timing
adjustments from 9 µs to 24 ms in 1 µs steps.
General Release Specification
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Byte Data Link Controller-Digital (BDLC-D)
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Table 14-5 shows the expected transceiver delay with respect to
BARD offset values:
Table 14-5. BARD Offset Delays
BARD Offset Bits
(BO3, BO2, BO1, BO0)
Corresponding Expected
Transceiver’s Delays (µs)
0000
9
0011
ON
0100
DU
0010
12
13
14
0110
15
0111
16
1000
17
1001
18
1010
19
1011
20
1100
21
1101
22
1110
23
1111
24
SE
MIC
0101
LE
CA
ES
11
AR
CH
IVE
DB
YF
RE
10
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
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A G R E E M E N T
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0001
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
BO3−BO0 — BARD Offset bits
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC CPU Interface
Freescale Semiconductor, Inc.
The protocol handler is responsible for framing, collision detection,
arbitration, CRC generation/checking, and error detection. The protocol
handler conforms to “SAE J1850 − Class B Data Communications
Network Interface.”
14.7.1 Protocol Architecture
The protocol handler contains the state machine, Rx shadow register, Tx
shadow register, Rx shift register, Tx shift register, and loopback
multiplexer as shown in Figure 14-9. Each block is described in more
detail.
MIC
ON
DU
Freescale Semiconductor, Inc...
ES
ALBE
CONTROL
STATE MACHINE
Tx SHIFT REGISTER
Rx SHADOW REGISTER
Tx SHADOW REGISTER
8
Tx DATA
8
CONTROL
Rx SHIFT REGISTER
Rx DATA
RE
YF
DB
IVE
CH
TxPD
LOOPBACK
MULTIPLEXER
CA
LE
DLBE FROM BCR2
LOOPBACK CONTROL
TXP
RxPD
SE
RXP
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.7 BDLC Protocol Handler
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 14-9. BDLC Protocol Handler Outline
General Release Specification
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Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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SE
MIC
ON
DU
Immediately after the Rx shift register has completed shifting in a byte of
data, this data is transferred to the Rx shadow register and RDRF or
RXIFR is set and interrupt is generated if the interrupt enable bit (IE) in
BCR1 is set. After the transfer takes place, this new data byte in the Rx
shadow register is available to the CPU interface, and the Rx shift
register is ready to shift in the next byte of data. Data in Rx shadow
register must be retrieved by the CPU before it is overwritten by new
data from the Rx shift register.
ES
CA
LE
Once the Tx shift register has completed its shifting operation for the
current byte, the data byte in the Tx shadow register is loaded into the
Tx shift register. After this transfer takes place, the Tx shadow register
is ready to accept new data from the CPU.
RE
14.7.4 Digital Loopback Multiplexer
All functions associated with performing the protocol are executed or
controlled by the state machine. The state machine is responsible for
framing, collision detection, arbitration, CRC generation/checking, and
error detection. The following sections describe the BDLC’s actions in a
variety of situations.
CH
IVE
14.7.5 State Machine
DB
YF
The digital loopback multiplexer connects RXP to TXP internally, when
the DLBE bit in BCR2 register is set.
AR
Freescale Semiconductor, Inc...
14.7.3 Rx and Tx Shadow Registers
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A G R E E M E N T
The Rx shift register gathers received serial data bits from the J1850 bus
and makes them available in parallel form to the Rx shadow register.
The Tx shift register takes data, in parallel form, from the Tx shadow
register and presents it serially to the state machine so that it can be
transmitted onto the J1850 bus.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.7.2 Rx and Tx Shift Registers
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC Protocol Handler
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
14.7.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a
special 4X (41.6 kbps) mode of J1850 VPW operation. The BDLC
cannot transmit in 4X mode, but can receive messages in 4X mode, if
the RX4X bit is set in the BCR2 register. If the RX4X bit is not set in the
BCR2 register, any 4X message on the J1850 bus is treated as noise by
the BDLC and is ignored.
14.7.5.2 Receiving a Message in Block Mode
MIC
ON
DU
Although not a part of the SAE J1850 protocol, the BDLC does allow for
a special block mode of operation of the receiver. As far as the BDLC is
concerned, a block mode message is simply a long J1850 frame that
contains an indefinite number of data bytes. All of the other features of
the frame remain the same, including the SOF, CRC, and EOD symbols.
LE
SE
Another node wishing to send a block mode transmission must first
inform all other nodes on the network that this is about to happen. This
is usually accomplished by sending a special predefined message.
CA
14.7.5.3 Transmitting a Message in Block Mode
CH
IVE
DB
YF
RE
ES
A block mode message is transmitted inherently by simply loading the
bytes one by one into the BDR register until the message is complete.
The programmer should wait until the TDRE flag is set prior to writing a
new byte of data into the BDR register. The BDLC does not contain any
predefined maximum J1850 message length requirement.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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ON
14.7.6.1 CRC Error
SE
MIC
A CRC error is detected when the data bytes and CRC byte of a received
message are processed, and the CRC calculation result is not equal to
$C4. The CRC code should detect any single-bit and 2- bit errors, as well
as all 8-bit burst errors and almost all other types of errors. CRC error
flag is set when a CRC error is detected.
LE
14.7.6.2 Symbol Error
YF
RE
ES
CA
A symbol error is detected when an abnormal (invalid) symbol is
detected in a message being received from the J1850 bus. However, if
the BDLC is transmitting when this happens, it will be treated as a loss
of arbitration rather than a transmitter error. Symbol invalid or out-ofrange flag is set when a symbol error is detected.
14.7.6.3 Framing Error
CH
14.7.6.4 Bus Fault
IVE
DB
A framing error is detected if an EOD or EOF symbol is detected on a
non-byte boundary from the J1850 bus. Symbol invalid or out-of-range
flag is set when a framing error is detected.
If a bus fault occurs, the response of the BDLC will depend upon the type
of bus fault.
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
DU
If the BDLC is transmitting a message and the message received
contains invalid bits or framing symbols on non-byte boundaries, this
constitutes a transmission error. When a transmission error is detected,
the BDLC will immediately cease transmitting. The error condition is
reflected in the BSVR register. If the interrupt enable bit (IE) is set, an
interrupt request from the BDLC is generated.
AR
Freescale Semiconductor, Inc...
The BDLC detects several types of transmit and receive errors which
can occur during the transmission of a message onto the J1850 bus.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.7.6 J1850 Bus Errors
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC Protocol Handler
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
If the bus is shorted to Vbatt, the BDLC will wait for the bus to fall to a
passive state before it will attempt to transmit a message. As long as the
short remains, the BDLC will never attempt to transmit a message onto
the J1850 bus.
If the bus is shorted to ground, the BDLC will see an idle bus, begin to
transmit the message, and then detect a transmission error, since the
short to ground would not allow the bus to be driven to the active
(dominant) state. The BDLC will abort that transmission and wait for the
next CPU command to transmit.
ON
DU
In any case, if the bus fault is temporary, as soon as the fault is cleared,
the BDLC will resume normal operation. If the bus fault is permanent, it
may result in permanent loss of communication on the J1850 bus.
MIC
14.7.6.5 Break (BREAK)
LE
SE
If a BREAK symbol is received while the BDLC is transmitting or
receiving, an invalid symbol interrupt will be generated. Reading the
BSVR register will clear this interrupt condition. The BDLC will wait for
bus to idle, then wait for SOF.
CH
IVE
DB
YF
RE
ES
CA
The BDLC cannot transmit a BREAK symbol. It can receive only a
BREAK symbol from the J1850 bus.
AR
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
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Bus short to Battery
The BDLC will not transmit until the bus is idle.
Fault condition is reflected in BSVR as invalid
symbol.
Bus short to Gnd
Invalid symbol: BDLC receives
invalid bits (noise).
Invalid symbol interrupt will be generated. The
BDLC will wait for SOF.
Framing error
CRC error interrupt will be generated. The
BDLC will wait for SOF.
DU
CRC error
ON
BDLC receives BREAK symbol
Invalid symbol interrupt will be generated. The
BDLC will wait for SOF.
MIC
Invalid symbol: BDLC sends an
EOD but receives an active
symbol.
The BDLC will wait for the next valid SOF.
Invalid symbol interrupt will be generated.
SE
14.8 BDLC MUX Interface
CA
LE
The MUX interface is responsible for bit encoding/decoding and digital
noise filtering between the protocol handler and the physical interface.
ES
14.8.1 Rx Digital Filter
CH
IVE
DB
YF
RE
The receiver section of the BDLC includes a digital low pass filter to
remove narrow noise pulses from the incoming message. An outline of
the digital filter is shown in Figure 14-10.
AR
Freescale Semiconductor, Inc...
The BDLC will abort transmission immediately.
Invalid symbol interrupt will be generated.
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A G R E E M E N T
BDLC Function
N O N - D I S C L O S U R E
Error Condition
CT
OR
, IN
C.2
006
Table 14-6. BDLC J1850 Bus Error Summary
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Freescale Semiconductor, Inc.
INPUT
SYNC
Rx DATA
FROM
PHYSICAL
INTERFACE
(RxP)
CT
OR
, IN
C.2
006
R E Q U I R E D
Byte Data Link Controller-Digital
4-BIT UP/DOWN COUNTER
4
d
UP/DOWN
q
OUT
EDGE AND
COUNT
COMPARATOR
d
q
DU
Figure 14-10. BDLC Rx Digital Filter Block Diagram
ON
14.8.1.1 Operation
LE
SE
MIC
The clock for the digital filter is provided by the MUX interface clock. At
each positive edge of the clock signal, the current state of the receiver
physical interface (RxP) signal is sampled. The RxP signal state is used
to determine whether the counter should increment or decrement at the
next negative edge of the clock signal.
ES
CA
The counter will increment if the input data sample is high but decrement
if the input sample is low. The counter will thus progress up toward 15 if,
on average, the RxP signal remains high or progress down towards 0 if,
on average, the RxP signal remains low.
DB
YF
RE
When the counter eventually reaches the value 15, the digital filter
decides that the condition of the RxP signal is at a stable logic level one
and the data latch is set, causing the filtered Rx data signal to become a
logic level 1. Furthermore, the counter is prevented from overflowing and
can only be decremented from this state.
CH
IVE
Alternatively, should the counter eventually reach the value 0, the digital
filter decides that the condition of the RxP signal is at a stable logic level
zero and the data latch is reset, causing the filtered Rx data signal to
become a logic level 0. Furthermore, the counter is prevented from
underflowing and can only be incremented from this state.
AR
Freescale Semiconductor, Inc...
A G R E E M E N T
MUX INTERFACE CLOCK
N O N - D I S C L O S U R E
FILTERED
Rx DATA OUT
The data latch will retain its value until the counter next reaches the
opposite end point, signifying a definite transition of the RxP signal.
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If the signal on the RxP signal transitions, then there will be a delay
before that transition appears at the filtered Rx data output signal. This
delay will be between 15 and 16 clock periods, depending on where the
transition occurs with respect to the sampling points. This filter delay
must be taken into account when performing message arbitration.
ON
DU
For example, if the frequency of the MUX interface clock (fBDLC) is 1.0486
MHz, then the period (tBDLC) is 954ns and the maximum filter delay in the
absence of noise will be 15.259 µs.
SE
MIC
The effect of random noise on the RxP signal depends on the
characteristics of the noise itself. Narrow noise pulses on the RxP signal
will be completely ignored if they are shorter than the filter delay. This
provides a degree of low pass filtering.
CA
LE
If noise occurs during a symbol transition, the detection of that transition
may be delayed by an amount equal to the length of the noise burst. This
is just a reflection of the uncertainty of where the transition is truly
occurring within the noise.
RE
ES
Noise pulses that are wider than the filter delay, but narrower than the
shortest allowable symbol length will be detected by the next stage of the
BDLC’s receiver as an invalid symbol.
AR
CH
IVE
DB
YF
Noise pulses that are longer than the shortest allowable symbol length
will normally be detected as an invalid symbol or as invalid data when
the frame’s CRC is checked.
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
The performance of the digital filter is best described in the time domain
rather than the frequency domain.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.8.1.2 Performance
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
14.8.2 J1850 Frame Format
All messages transmitted on the J1850 bus are structured using this
format:
IDLE
SOF
PRIORITY
MESSAGE
(Data0)
ID (Data1)
Datan
CRC
E
O
D
OPTIONAL
IFR
EOF
I
F
S
IDLE
DU
Figure 14-11. J1850 Bus Message Format (VPW)
ON
SAE J1850 states that each message has a maximum length of 101 bit
times or 12 bytes (excluding SOF, EOD, NB, and EOF).
MIC
SOF — Start of Frame Symbol
LE
SE
All messages transmitted onto the J1850 bus must begin with an SOF
symbol. This indicates the start of a new message transmission to any
listeners on the J1850 bus. The SOF symbol is not used in the CRC
calculation.
Data — In Message Data Bytes
YF
RE
ES
CA
The data bytes contained in the message include the message
priority/type, message ID byte, and any actual data being transmitted
to the receiving node. The message format used by the BDLC is
similar to the 3-byte consolidated header message format outlined by
the SAE J1850 document. See “SAE J1850 - Class B Data
Communications Network Interface,” for more information about 1and 3-byte headers.
CH
IVE
DB
Messages transmitted by the BDLC onto the J1850 bus must contain
at least one data byte, and, therefore, can be as short as one data
byte and one CRC byte. Each data byte in the message is eight bits
in length and is transmitted MSB to LSB.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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This byte is used by the receiver(s) of each message to determine if
any errors have occurred during the transmission of the message.
The BDLC calculates the CRC byte and appends it onto any
messages transmitted onto the J1850 bus, and also performs CRC
detection on any messages it receives from the J1850 bus.
DU
Freescale Semiconductor, Inc...
CRC generation uses the divisor polynomial X8 + X4 + X3 + X2 + 1.
The remainder polynomial is initially set to all ones, and then each
byte in the message after the SOF symbol is serially processed
through the CRC generation circuitry. The one’s complement of the
remainder then becomes the 8-bit CRC byte, which is appended to
the message after the data bytes, in MSB to LSB order.
MIC
ON
When receiving a message, the BDLC uses the same divisor
polynomial. All data bytes, excluding the SOF and EOD symbols, but
including the CRC byte, are used to check the CRC. If the message
LE
SE
is error free, the remainder polynomial will equal X7 + X6 + X2 ($C4),
regardless of the data contained in the message. If the calculated
CRC does not equal $C4, the BDLC will recognize this as a CRC error
and set the CRC error flag in the BSVR register.
A G R E E M E N T
CT
OR
, IN
C.2
006
CRC — Cyclical Redundancy Check Byte
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
RE
ES
The EOD symbol is a short passive period on the J1850 bus used to
signify to any recipients of a message that the transmission by the
originator has completed. No flag is set upon reception of EOD
symbol.
YF
IFR — In-Frame Response Bytes
DB
The IFR section of the J1850 message format is optional. Users
desiring further definition of in-frame response should review the SAE
J1850 Class B Data Communications Network Interface Specification
This symbol is a passive period on the J1850 bus, longer than an
EOD symbol, which signifies the end of a message. Since an EOF
symbol is longer than an EOD symbol, if no response is transmitted
AR
CH
IVE
EOF — End of Frame Symbol
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N O N - D I S C L O S U R E
CA
EOD — End of Data Symbol
Freescale Semiconductor, Inc.
R E Q U I R E D
Byte Data Link Controller-Digital
CT
OR
, IN
C.2
006
after an EOD symbol, it becomes an EOF, and the message is
assumed to be completed. EOF flag is set upon receiving the EOF
symbol.
IFS — Inter-Frame Separation Symbol
The IFS symbol is a passive period on the J1850 bus which allows
proper synchronization between nodes during continuous message
transmission. The IFS symbol is transmitted by a node following the
completion of the EOF period.
DU
ON
SE
MIC
However, if the BDLC is waiting for the IFS period to expire before
beginning a transmission and a rising edge is detected before the IFS
time has expired, it will internally synchronize to that edge. If a write
to the BDR register (initiate transmission) occurred on or before 104
X tBDLC from the received rising edge, then the BDLC will transmit and
LE
arbitrate for the bus. If a CPU write to the BDR register occurred after
104 X tBDLC from the detection of the rising edge, then the BDLC will
CA
not transmit, but will wait for the next IFS period to expire before
attempting to transmit the byte.
YF
RE
ES
A rising edge may occur during the IFS period because of varying
clock tolerances and loading of the J1850 bus, causing different
nodes to observe the completion of the IFS period at different times.
Receivers must synchronize to any SOF occurring during an IFS
period to allow for individual clock tolerances.
DB
BREAK — Break
CH
IVE
If the BDLC is transmitting at the time a BREAK is detected, it treats
the BREAK as if a transmission error had occurred, and halts
transmission. The BDLC cannot transmit a BREAK symbol. If while
receiving a message the BDLC detects a BREAK symbol, it treats the
BREAK as a reception error and sets the invalid symbol flag. If while
receiving a message in 4X mode, the BDLC detects a BREAK
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
When the last byte of a message has been transmitted onto the J1850
bus, and the EOF symbol time has expired, all nodes must then wait
for the IFS symbol time to expire before transmitting an SOF, marking
the beginning of another message.
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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DU
14.8.3 J1850 VPW Symbols
MIC
ON
Huntsinger’s variable pulse width modulation (VPW) is an encoding
technique in which each bit is defined by the time between successive
transitions and by the level of the bus between transitions, active or
passive. Active and passive bits are used alternately.
LE
SE
Each logic 1 or logic 0 contains a single transition, and can be at either
the active or passive level and one of two lengths, either 64 µs or 128 µs
(tNOM at 10.4 kbps baud rate), depending upon the encoding of the
previous bit. The SOF, EOD, EOF and IFS symbols will always be
encoded at an assigned level and length. See Figure 14-12.
ES
CA
Each message will begin with an SOF symbol, an active symbol, and
therefore each data byte (including the CRC byte) will begin with a
passive bit, regardless of whether it is a logic 1 or a logic 0.
YF
RE
All VPW bit lengths stated in the following descriptions are typical values
at a 10.4 kbps bit rate.
DB
14.8.3.1 Logic 0
CH
IVE
A logic 0 is defined as either an active-to-passive transition followed by
a passive period 64 µs in length or a passive-to-active transition followed
by an active period 128 µs in length (Figure 14-12(a)).
AR
Freescale Semiconductor, Inc...
An idle condition exists on the bus during any passive period after
expiration of the IFS period. Any node sensing an idle bus condition
can begin transmission immediately.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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A G R E E M E N T
Idle Bus
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
symbol, it treats the BREAK as a reception error, sets BSVR register
to $1C, and exits 4X mode. The RX4XE bit in BCR2 is cleared
automatically upon reception of the BREAK symbol.
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Freescale Semiconductor, Inc.
14.8.3.2 Logic 1
CT
OR
, IN
C.2
006
R E Q U I R E D
Byte Data Link Controller-Digital
A logic 1 is defined as either an active-to-passive transition followed by
a passive period 128 µs in length or a passive-to-active transition
followed by an active period 64 µs in length (Figure 14-12(b)).
ACTIVE
128 µs
(a)
ON
ACTIVE
DU
LOGIC 0
128 µs
MIC
PASSIVE
64 µs
OR
LOGIC 1
SE
(b)
ACTIVE
LE
200 µs
CA
PASSIVE
(c)
ACTIVE
RE
280 µs
ES
START OF FRAME
YF
PASSIVE
200 µs
END OF DATA
(d)
240 µs
BREAK
(e)
(f)
DB
END OF FRAME
CH
IVE
Figure 14-12. J1850 VPW Symbols
AR
A G R E E M E N T
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
64 µs
OR
PASSIVE
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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14.8.3.4 Start of Frame Symbol (SOF)
DU
14.8.4 EOD − End of Data Symbol
MIC
ON
The EOD symbol is defined as an active-to-passive transition followed
by a passive period 200 µs in length (Figure 14-12(d)).
SE
14.8.4.1 End of Frame Symbol (EOF)
CA
LE
The EOF symbol is defined as an active-to-passive transition followed by
a passive period 280 µs in length (Figure 14-12(e)). If there is no IFR
byte transmitted after an EOD symbol is transmitted, after another 80 µs
the EOD becomes an EOF, indicating the completion of the message.
ES
14.8.4.2 Inter-Frame Separation Symbol (IFS)
YF
RE
The IFS symbol is defined as a passive period 300 µs in length. The IFS
symbol contains no transition, since it always follows an EOF symbol
when it is used.
DB
14.8.4.3 Break Signal (BREAK)
CH
IVE
The BREAK signal is defined as a passive-to-active transition followed
by an active period of at least 240 µs (Figure 14-12(f)).
AR
Freescale Semiconductor, Inc...
The SOF symbol is defined as passive-to-active transition followed by an
active period 200 µs in length (Figure 14-12(c)). This allows the data
bytes which follow the SOF symbol to begin with a passive bit,
regardless of whether it is a logic 1 or a logic 0.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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A G R E E M E N T
The NB symbol has the same property as a logic 1 or a logic 0.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.8.3.3 Normalization Bit (NB)
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
14.8.5 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850
bus have been defined to allow for variations in oscillator frequencies. In
many cases, the maximum time allowed to define a data bit or symbol is
equal to the minimum time allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol
is being received is equal to a single period of the MUX interface clock
(tBDLC), an apparent separation in these maximum time/minimum time
concurrences equal to one cycle of tBDLC occurs.
MIC
ON
DU
This one clock resolution allows the BDLC to differentiate properly
between the different bits and symbols, without reducing the valid
window for receiving bits and symbols from transmitters onto the J1850
bus having varying oscillator frequencies.
CH
IVE
DB
YF
RE
ES
CA
LE
SE
In VPW bit encoding, the tolerances for the both passive and active data
bits and symbols are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the
minimum length of a passive logic 1, and the maximum length of an
active logic 0 is equal to the minimum length of a valid SOF symbol.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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Freescale Semiconductor, Inc.
200 µs
128 µs
64 µs
ACTIVE
(1) INVALID PASSIVE BIT
PASSIVE
ttrvp1(Min)
ttrvp1(Max)
DU
ttrvp1(Min)
ACTIVE
ON
PASSIVE
(3) VALID PASSIVE LOGIC 1
ttrvp1(Max)
trvp2(Max)
MIC
ACTIVE
PASSIVE
SE
trvp2(Max)
(4) VALID EOD SYMBOL
ttrvp3(Max)
CA
LE
Figure 14-13. J1850 VPW Passive Symbols
14.8.5.1 Invalid Passive Bit
YF
RE
ES
If the passive-to-active transition beginning the next data bit or symbol
occurs between the active-to-passive transition beginning the current
data bit or symbol and ttrvp1(Min), the current bit would be invalid. See
Figure 14-13(1).
DB
14.8.5.2 Valid Passive Logic 0
CH
IVE
If the passive-to-active transition beginning the next data bit or symbol
occurs between ttrvp1(Min) and ttrvp1(Max), the current bit would be
considered a logic 0. See Figure 14-13(2).
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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N O N - D I S C L O S U R E
PASSIVE
A G R E E M E N T
(2) VALID PASSIVE LOGIC 0
AR
Freescale Semiconductor, Inc...
ACTIVE
R E Q U I R E D
CT
OR
, IN
C.2
006
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
14.8.5.3 Valid Passive Logic 1
If the passive-to-active transition beginning the next data bit or symbol
occurs between ttrvp1(Max) and ttrvp2(Max), the current bit would be
considered a logic 1. See Figure 14-13(3).
14.8.5.4 Valid EOD Symbol
DU
If the passive-to-active transition beginning the next data bit or symbol
occurs between ttrvp2(Max) and ttrvp3(Max), the current symbol would be
considered a valid EOD symbol. See Figure 14-13(4).
MIC
280 µs
ON
300 µs
SE
ACTIVE
LE
PASSIVE
CA
ACTIVE
ES
PASSIVE
ttrv4(Min)
(1) VALID EOF
SYMBOL
ttrv4(Max)
(2) VALID EOF+
IFS SYMBOL
ttv6(Min)
CH
IVE
DB
YF
RE
Figure 14-14. J1850 VPW EOF and IFS Symbols
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
LE
SE
If the passive-to-active transition beginning the SOF symbol of the next
message does not occur before d, the bus is considered to be idle, and
any node wishing to transmit a message may do so immediately.
ES
64 µs
PASSIVE
YF
ttrva2(Min)
ACTIVE
DB
PASSIVE
ttrva2(Min)
CH
PASSIVE
IVE
ACTIVE
ACTIVE
(1) INVALID ACTIVE BIT
RE
ACTIVE
PASSIVE
CA
200 µs
128 µs
(2) VALID ACTIVE LOGIC 1
ttrva2(Max)
(3) VALID ACTIVE LOGIC 0
ttva2(Max)
ttrva1(Max)
(4) VALID SOF SYMBOL
ttrva1(Max)
ttva3(Max)
Figure 14-15. J1850 VPW Active Symbols
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
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A G R E E M E N T
14.8.5.6 Idle Bus
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
MIC
ON
DU
In Figure 14-14(1), if the passive-to-active transition beginning the SOF
symbol of the next message occurs between ttrv4(Min) and ttrv4(Max), the
current symbol will be considered a valid EOF symbol. If the passive-toactive transition beginning the SOF symbol of the next message occurs
after ttv6(Min), the current symbol will be considered a valid EOF symbol
followed by a valid IFS symbol. See Figure 14-14(2). All nodes must
wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others
and immediately begin transmitting. Therefore, any time a node waiting
to transmit detects a passive-to-active transition once a valid EOF has
been detected, it should begin transmission immediately, initiating the
arbitration process.
AR
Freescale Semiconductor, Inc...
14.8.5.5 Valid EOF and IFS Symbol
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
14.8.5.7 Invalid Active Bit
If the active-to-passive transition beginning the next data bit or symbol
occurs between the passive-to-active transition beginning the current
data bit or symbol and ttrva2(Min), the current bit would be invalid. See
Figure 14-15(1).
14.8.5.8 Valid Active Logic 1
DU
If the active-to-passive transition beginning the next data bit or symbol
occurs between ttrva2(Min) and ttrva2(Max), the current bit would be
considered a logic 1. See Figure 14-15(2).
ON
14.8.5.9 Valid Active Logic 0
SE
MIC
If the active-to-passive transition beginning the next data bit or symbol
occurs between ttrva2(Max) and ttva1(Max), the current bit would be
considered a logic 0. See Figure 14-15(3).
LE
14.8.5.10 Valid SOF Symbol
RE
ES
CA
If the active-to-passive transition beginning the next data bit or symbol
occurs between ttrva1(Max) and ttva3(Max), the current symbol would be
considered a valid SOF symbol. See Figure 14-15(4).
YF
240 µs
DB
ACTIVE
CH
IVE
PASSIVE
(2) VALID BREAK
SYMBOL
ttrv6(Min)
Figure 14-16. J1850 VPW BREAK Symbol
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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Freescale Semiconductor, Inc.
14.8.6 Message Arbitration
ON
DU
Freescale Semiconductor, Inc...
Message arbitration on the J1850 bus is accomplished in a nondestructive manner, allowing the message with the highest priority to be
transmitted, while any transmitters which lose arbitration simply stop
transmitting and wait for an idle bus to begin transmitting again.
SE
MIC
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it automatically waits until the bus is
idle. However, if multiple nodes begin to transmit in the same
synchronization window, message arbitration will occur beginning with
the first bit after the SOF symbol and continue with each bit thereafter.
ES
CA
LE
The VPW symbols and J1850 bus electrical characteristics are chosen
carefully so that a logic 0 (active or passive type) will always dominate
over a logic 1 (active or passive type) simultaneously transmitted. Hence
logic 0s are said to be dominant and logic 1s are said to be recessive.
AR
CH
IVE
DB
YF
RE
Whenever a node detects a dominant bit when it transmitted a recessive
bit, it loses arbitration and immediately stops transmitting. This is known
as bitwise arbitration.
MC68HC05V12 — Rev. 1.0
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Byte Data Link Controller-Digital (BDLC-D)
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A G R E E M E N T
If the next active-to-passive transition does not occur until after ttrv6(Min),
the current symbol will be considered a valid BREAK symbol. A BREAK
symbol should be followed by a SOF symbol beginning the next
message to be transmitted onto the J1850 bus. See Figure 14-16.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.8.5.11 Valid BREAK Symbol
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC MUX Interface
Freescale Semiconductor, Inc.
0
1
0
1
ACTIVE
Transmitter A
PASSIVE
ACTIVE
Transmitter B
PASSIVE
0
1
Data
Bit 1
Data
Bit 2
J1850 Bus
0
TRANSMITTER A
DETECTS AN ACTIVE
STATE ON THE BUS
AND STOPS
TRANSMITTING.
0
TRANSMITTER B WINS
ARBITRATION AND
CONTINUES
TRANSMITTING.
1
0
0
Data
Bit 3
Data
Bit 4
Data
Bit 5
ON
SOF
1
DU
PASSIVE
1
MIC
Figure 14-17. J1850 VPW Bitwise Arbitrations
YF
RE
ES
CA
LE
SE
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is immediately stopped unless
it occurs on the eighth bit of a byte. In this case, the BDLC automatically
will append two extra 1 bits and then stop transmitting. These two extra
bits will be arbitrated normally and thus will not interfere with another
message. The second 1 bit will not be sent if the first loses arbitration. If
the BDLC has lost arbitration to another valid message, then the two
extra ones will not corrupt the current message. However, if the BDLC
has lost arbitration due to noise on the bus, then the two extra ones will
ensure that the current message will be detected and ignored as a noisecorrupted message.
DB
Since a 0 dominates a 1, the message with the lowest value will have the
highest priority and will always win arbitration, for instance, a message
with priority 000 will win arbitration over a message with priority 011.
CH
IVE
This method of arbitration will work no matter how many bits of priority
encoding are contained in the message.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
ACTIVE
1
CT
OR
, IN
C.2
006
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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Freescale Semiconductor, Inc.
DU
14.9.2 BDLC Stop Mode
MIC
ON
This power-conserving mode is entered automatically from the run mode
whenever the CPU executes a STOP instruction or if the CPU executes
a WAIT instruction and the WCM bit in the BCR register is previously set.
This is the lowest power mode that the BDLC can enter.
RE
ES
CA
LE
SE
A subsequent passive-to-active transition on the J1850 bus will cause
the BDLC to wake up and generate a non-maskable CPU interrupt
request. When a STOP instruction is used to put the BDLC in stop mode,
the BDLC will not correctly receive the byte that woke it up. This is due
to a required oscillator stabilization delay for the BDLC internal operating
clocks to restart. If a WAIT instruction is used to put the BDLC in stop
mode, the BDLC is guaranteed to receive correctly the byte which woke
it up, if and only if an EOF has been detected prior to issuing the WAIT
instruction by the CPU. Otherwise the BDLC wil not correctly receive the
byte that woke it up.
It is important to ensure that all transmissions are complete or aborted
prior to putting the BDLC into stop mode.
CH
NOTE:
IVE
DB
YF
If this mode is entered while the BDLC is receiving a message, the first
subsequent received edge will cause the BDLC to wake up immediately,
generate a CPU interrupt request, and wait for the BDLC internal
operating clocks to restart and stabilize before normal communications
can resume. Therefore, the BDLC is not guaranteed to receive that
message correctly.
AR
Freescale Semiconductor, Inc...
The MCU will first write to the BDLC control register (BCR1). This byte
should configure the rate select bits to configure the MUX interface clock
to its nominal value, clear the IMSG bit to enable normal BDLC
operations, and set the interrupt enable bit if desired.
MC68HC05V12 — Rev. 1.0
General Release Specification
Byte Data Link Controller-Digital (BDLC-D)
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A G R E E M E N T
14.9.1 Initialization
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
14.9 BDLC Application Notes
R E Q U I R E D
Byte Data Link Controller-Digital (BDLC-D)
BDLC Application Notes
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
14.9.3 BDLC Wait Mode
This power-conserving mode is entered automatically from run mode
whenever the CPU executes a WAIT instruction and the WCM bit in the
BCR register is previously clear.
A subsequent successfully received message, including one that is in
progress at the time that this mode is entered, will cause the BDLC to
wake up and generate a CPU interrupt request if the interrupt enable (IE)
bit in the BCR register is previously set. This results in saving less power,
but the BDLC is guaranteed to correctly receive the message which
woke it up, since the BDLC internal operating clocks are kept running.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Byte Data Link Controller-Digital
General Release Specification
MC68HC05V12 — Rev. 1.0
Byte Data Link Controller-Digital (BDLC-D)
For More Information On This Product,
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15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
15.3 Gauge System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
15.4 Coil Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
15.5 Technical Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
15.6 Gauge Driver Control Registers . . . . . . . . . . . . . . . . . . . . . . .179
15.6.1
Gauge Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . .179
15.6.2
Current Magnitude Registers . . . . . . . . . . . . . . . . . . . . . .181
15.6.3
Current Direction Registers . . . . . . . . . . . . . . . . . . . . . . . .183
15.6.3.1
Current Direction Register for Major A . . . . . . . . . . . . . .183
15.6.3.2
Current Direction Register for Major B . . . . . . . . . . . . . .184
15.6.3.3
Current Direction Register for Minor A . . . . . . . . . . . . . .184
15.6.3.4
Current Direction Register for Minor B . . . . . . . . . . . . . .185
15.6.3.5
Current Direction Register for Minor C. . . . . . . . . . . . . .185
15.6.3.6
Current Direction Register for Minor D. . . . . . . . . . . . . .186
15.7 Coil Sequencer and Control . . . . . . . . . . . . . . . . . . . . . . . . . .186
15.7.1
Scanning Sequence Description . . . . . . . . . . . . . . . . . . . .186
15.7.1.1
Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.7.1.2
Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
15.7.2
Scan Status and Control Register . . . . . . . . . . . . . . . . . . .189
15.8 Mechanism Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.9 Gauge Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.10 Gauge Regulator Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . .194
15.11 Coil Current Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
15.12 External Component Considerations . . . . . . . . . . . . . . . . . . .195
15.12.1 Minimum Voltage Operation . . . . . . . . . . . . . . . . . . . . . . .196
15.12.2 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
15.12.3 Coil Inductance Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15.13 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
15.14 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
AR
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
15.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 15. Gauge Drivers
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
15.2 Introduction
MIC
ON
DU
The MC68HC05V12 contains on-chip circuitry to drive six cross coil air
core gauges. Four of the gauge drivers are 3-pin drivers intended for
180° gauges (minor gauges) and two of the drivers are full 4-pin Hbridge drivers for 360° gauges (major gauges). The output drivers for
both major and minor gauges operate in a current drive mode. That is,
the current in the gauge coils is controlled rather than the voltage across
the coil. The maximum amount of current that can be driven into any coil
is set by the value of the resistance between the Imax and VSSA pins. The
current driven into each coil is set by writing a hex value to the current
magnitude registers and the direction of current is selected by setting or
clearing the appropriate bits in the current direction registers. The ratio
of the current used to set the gauge deflection angle is software
configured. No particular drive technique is implemented in hardware.
SE
15.3 Gauge System Overview
RE
ES
CA
LE
The circuitry contained within the MC68HC05V12 provides a great deal
of flexibility for driving the coils. The user specifies coil currents rather
than degrees of deflection. This allows the software to drive the coil
currents in a variety of ways. The user must specify the magnitude of the
current as well as the direction it should flow for full H-bridge drivers. Half
H-bridge drivers require specification of a magnitude only. Eight full Hbridge drivers and four half H-bridge drivers support two 360° and four
180° gauges.
DB
YF
Figure 15-1 is a block diagram of the gauge driver module within the
MC68HC05V12. Each of the blocks requiring more description is
described in the following subsections.
IVE
There are 20 coil driver pins on the MC68HC05V12. These are grouped
into two types. The pins whose names start with MAJ are full H-bridge
coil drivers. A or B in the pin name indicates major gauge A or B. A 1 or
2 in the name refers to coil 1 or coil 2 within the same gauge. It is
important to keep coils within the same gauge connected to the same A
or B coil driver pins. The + or − in the pin name indicates the direction of
current flow according to this convention: The current direction positive
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
ON
D/A
MIC
8
S&H
COIL 1
COIL 2
S&H
S&H
COIL 1
COIL 2
MAJA2+
MAJA2−
MAJB1+
MAJB1−
MAJB2+
MAJB2−
MINA1
MINA2+
MINA2−
S&H
DB
COIL SEQUENCER
AND CONTROL
REGISTER
COIL 2
MIND1
MIND2+
MIND2−
AR
CH
IVE
S&H
COIL 1
MINOR DRIVE
D
YF
RE
ES
CA
LE
8 * 12
12 CURRENT
MAGNITUE
AND
6 CURRENT
DIRECTION
REGISTERS
S&H
COIL 2
SE
12-TO-1
8-BITMUX
S&H
MAJA1−
12
MUX CONTROL
Figure 15-1. Gauge Driver Block Diagram
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
+
_
8-BIT
MAJA1+
N O N - D I S C L O S U R E
DU
D/A AMP
COIL 1
MAJOR DRIVE
A
S&H
COIL DRIVERS
MAJOR DRIVE
B
1%
Vref
CPU BUS
Freescale Semiconductor, Inc...
SAMPLE AND HOLD MUX
AND CURRENT SENSE MUX
I to V
CONVERTER
MINOR DRIVE
A
IMAX
RMAX
CT
OR
, IN
C.2
006
current means current flow is out of the pin with the + in its name and into
the pin with − in its name. Negative current means current is flowing into
the pin with the + in its name and out of the pin with − in its name.
R E Q U I R E D
Gauge Drivers
Gauge System Overview
Freescale Semiconductor, Inc.
To support both 180° and 360° gauges and to keep the pin count as low
as possible, it is necessary to use two different types of coil drivers.
These are the full H-bridge drivers and the half H-bridge drivers. Major
gauges will require two of the full H-bridge drivers and the minor gauges
will require one full H-bridge driver and one half H-bridge driver. A full Hbridge driver uses two pins and is capable of driving a controlled current
in either direction in a single coil. A half H-bridge driver uses only one pin
and can sink a controlled amount of current in one direction only. The
amount of current flowing through the coils and its direction in the case
of the full H-bridge driver are controlled through the current magnitude
registers (CMR) and the current direction registers (CDR) described
here.
ON
DU
Freescale Semiconductor, Inc...
ES
CA
LE
SE
MIC
All of the components shown in Figure 15-2 and Figure 15-3 are
internal components except for the gauge coils. The resistive and
inductive properties of the external coils are expected to fall within the
ranges of Rcoil and Lcoil shown in Section 17. Electrical Specifications.
The resistance is important for calculating minimum operating voltages
and power dissipation (see 15.12 External Component
Considerations), and the inductance is important in determining
settling time (a part of tgcs) and controlling the rate of change of the
current driven in the coils.
YF
RE
For consistency, note that the dot on the coil is always connected to the
+ pin in the coil driver, or, in the case of the half H-bridge driver, it is
connected to the positive supply pin.
CH
IVE
DB
The internal resistor RI is used to measure how much current is flowing
in the coil. The op-amp shown in this diagram is actually built only once
and is shared among all 12 coil drivers through a multiplexer to reduce
manufacturing variability among drivers. To determine what voltage
must come from the D/A output, the maximum current level set by the
external RMAX resistor is converted to a reference voltage input to the
D/A. This reference voltage sets the maximum output voltage of the D/A
(with an input of $FF).
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
15.4 Coil Drivers
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DIRECTION
BIT
CT
OR
, IN
C.2
006
VGSUP
CONTROL
LOGIC
MAJA1-
MAJA2−
FROM D/A
DU
GAUGE COILS
Rcoil
Lcoil
D/A AMP
ON
S AND H
MIC
+
−
INPUT MUX
ALL COMPONENTS ARE
INTERNAL EXCEPT
THE GAUGE COILS
SE
SHARED AMONG
ALL COIL DRIVERS
RI
CURRENT
SENSE
MUX
LE
= VSSG
VGSUP
MINA1
YF
RE
CONTROL
LOGIC
FROM D/A
INPUT MUX
S AND H
MINA2-
GAUGE COILS
Rcoil
Lcoil
CH
IVE
+
−
MINA2+
DB
D/A AMP
SHARED AMONG
ALL COIL DRIVERS
CURRENT
SENSE
MUX
RI
ALL COMPONENTS ARE
EXTERNAL EXCEPT
THE GAUGE COILS
= VSSG
VSSG
Figure 15-3. Half H-Bridge Coil Driver
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
ES
CA
Figure 15-2. Full H-Bridge Coil Driver
AR
Freescale Semiconductor, Inc...
MAJA2+
MAJA1+
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
Coil Drivers
Freescale Semiconductor, Inc.
An auto-zeroing scheme is implemented in the MC68HC705V12 to
reduce errors internal to the chip. Prior to each coil update, during the
auto-zero phase, the amplifier output is disconnected from all FET gates
(see Figure 15-2) while the input is connected to it’s new input voltage.
On completion of the auto-zero cycle, the amplifier output is connected
to the appropriate FET gate. Since the FET gate and amplifier output are
typically not at the same potential, the FET gate is momentarily pulled
down, until the amplifier control loop re-establishes the correct gate
potential. This abrupt change in gate potential results in voltage spikes,
and thus current spikes in the gauge coil. The magnitude, duration, and
number of spikes are dependent on the coil resistance, gauge supply
voltage (VGSUP), and the coil current prior to the auto-zero cycle
(Figure 15-4). Only the worst case spike durations, under the specified
test conditions, are shown. Typically the spike duration and total spike
duration is smaller.
DU
ON
MIC
NOTE:
CA
LE
SE
Due to the positive and negative spikes, there is negligible D.C. error
introduced.
ES
I1
YF
RE
I0
DB
I1
t1
=
=
=
t1 =
=
t2 =
=
tMAX =
=
Current before spikes
Maximum spike magnitude
(VGSUP + 0.9 V)/Rcoil
Maximum negative spike duration
300 µs
Maximum positive spike duration
200 µs
Maximum duration of all spikes
500 µs
Conditions: VGSUP = 8.00 V
Lcoil = 30 mH
Rcoil = 200 W (typical)
TA = 27 °C
CH
IVE
tMAX
t2
I0
I1
Figure 15-4. Specification for Current Spikes
AR
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
15.5 Technical Note
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
•
The current magnitude registers set the amount of current to flow
in a particular coil.
•
The current direction register determines which direction the
current will flow in a coil.
•
The scan control register controls how the 12 coil drivers will be
sequenced and updated by the analog multiplexers and control
logic.
ON
MIC
Each register is described in more detail in the following sections.
SE
15.6.1 Gauge Enable Register
CA
LE
All bits in this register are used to select which of the six gauges will be
driven when the gauge module is active. If any bit of bits 7-2 is set, the
gauge module will become active.
YF
RE
ES
When all bits are cleared, the gauge module is considered off. As much
circuitry as possible is shut off to conserve power. The D/A, the coil
sequencing logic, and the coil current measurement circuits are turned
off. All high-side drivers in the H-bridge drivers are left on to absorb any
transient current that may be generated when the drivers are initially
turned on or off; all low-side drivers are high-Z.
CH
IVE
DB
The effects of these bits on the scanning sequence of the gauges are
described in 15.7 Coil Sequencer and Control
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
The gauge enable register enables or disables individual gauges.
DU
•
AR
Freescale Semiconductor, Inc...
The gauge driver module requires the use of four types of control
registers:
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
15.6 Gauge Driver Control Registers
R E Q U I R E D
Gauge Drivers
Gauge Driver Control Registers
Freescale Semiconductor, Inc.
$20
Bit 7
6
5
4
3
2
1
Bit 0
MJAON
MJBON
MIAON
MIBON
MICON
MIDON
CMPS
R
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
R
CT
OR
, IN
C.2
006
R E Q U I R E D
Gauge Drivers
= Reserved
Figure 15-5. Gauge Enable Register (GER)
A G R E E M E N T
MJAON — Major Gauge A On Bit
DU
ON
MJBON — Major Gauge B On Bit
SE
MIC
This bit controls whether major gauge B is on or off.
1 = Gauge is on.
0 = Gauge is off.
MIAON — Minor Gauge A On Bit
CA
LE
This bit controls whether minor gauge A is on or off.
1 = Gauge is on.
0 = Gauge is off.
ES
MIBON — Minor Gauge B On Bit
YF
RE
This bit controls whether minor gauge B is on or off.
1 = Gauge is on.
0 = Gauge is off.
MICON — Minor Gauge C On Bit
IVE
DB
This bit controls whether minor gauge C is on or off.
1 = Gauge is on.
0 = Gauge is off.
CH
MIDON — Minor Gauge D On Bit
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
This bit controls whether major gauge A is on or off.
1 = Gauge is on.
0 = Gauge is off.
This bit controls whether minor gauge D is on or off.
1 = Gauge is on.
0 = Gauge is off.
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Read/
Write
Magnitude Register - MAJA2
$24
Magnitude Register - MAJB1
$25
Magnitude Register - MAJB2
$26
Magnitude Register - MINA1
$27
Magnitude Register - MINA2
$28
Magnitude Register - MINB1
$29
Magnitude Register - MINB2
$2A
Magnitude Register - MINC1
$2B
Magnitude Register - MINC2
$2C
Magnitude Register - MIND1
$2D
Magnitude Register - MIND2
CA
ES
RE
YF
DB
IVE
CH
5
4
3
2
1
Bit 0
B6
B5
B4
B3
B2
B1
B0
B6
B5
B4
B3
B2
B1
B0
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
DU
$23
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
6
ON
Magnitude Register - MAJA1
B7
LE
$22
Bit 7
MIC
Register
B7
SE
Addr.
Figure 15-6. Current Magnitude Registers
AR
Freescale Semiconductor, Inc...
15.6.2 Current Magnitude Registers
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
This bit is provided to enable the user to select between one of two
gauge driver feedback paths, depending upon the characteristics of
the load.
1 = Alternate feedback circuit
0 = Default feedback circuit
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
CMPS — Feedback Compensation Select
R E Q U I R E D
Gauge Drivers
Gauge Driver Control Registers
Freescale Semiconductor, Inc.
R E Q U I R E D
Gauge Drivers
CT
OR
, IN
C.2
006
The naming convention used in the CMRs above indicates whether it is
a major or minor gauge driver, which major or minor gauge (A, B, C,
etc.), and which coil within the gauge is affected (coil 1 or coil 2).
DU
ON
reg value
I = ( ICM )X  ------------------------

 255 
LE
SE
MIC
The 8-bit value written to these registers will determine the amount of
current that will flow in each of the 12 coils. For example, MAJA1 controls
the magnitude of the current between the MAJA1+ and MAJA1− pins.
The theoretical current that will flow between the + and − pins is given by
this equation:
CA
ICM is the maximum current that can be driven into any of the coil drivers
and is given by this equation:
ES
ICM = (IMAX x 10) x (1 + ECA + EMAX)
YF
RE
ECA is the total internal error in generating ICM from IMAX and is shown
in 17.11 Gauge Driver Electricals.
DB
The EMAX is the error tolerance of the RMAX resistor and is shown in
17.11 Gauge Driver Electricals.
IVE
The “reg value” is the base 10 representation of the value written to the
magnitude registers.
CH
IMAX is set by the external resistor and is a reference current that is used
to generate the coil currents.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Each of the magnitude registers is double buffered to keep both coil
currents within the same gauge as closely coupled as possible. Transfer
of data from the master to the slave buffers in these registers is under
control of the coil sequencer and control logic and is described in 15.7
Coil Sequencer and Control. A read of any of the CMRs will return only
the contents of the slave buffer. If a read of one of the CMRs takes place
after a write of data but before the master-to-slave transfer takes place,
the data read may be different from the data written. The master register
will always hold the contents of the last write. Reset clears all bits.
IMAX is related to the external RMAX resistor by the equation:
2.5
IMAX =  ------------------  X4
 RMAX 
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Bit 7
6
R
R
0
0
5
ON
$2E
DU
15.6.3.1 Current Direction Register for Major A
Read:
Reset:
0
3
2
1
Bit 0
R
R
0
DMJA1
DMJA2
0
0
0
0
0
= Reserved
SE
R
R
MIC
Write:
4
LE
Figure 15-7. MAJA Current Direction Register (DMAJA)
CH
IVE
DB
YF
RE
ES
CA
DMJA1 and DMJA2 — Current Direction Bits for Major Gauge A
1 = Current flow will be from the – pin to the + pin on the
corresponding coil driver.
0 = Current flow will be from the + pin to the – pin on the
corresponding coil driver.
AR
Freescale Semiconductor, Inc...
The CDR also contains a master and slave latch. A read of any of these
registers will return the value in the slave buffer.
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
The bits in these registers control the direction of current flow in each of
the full eight H-bridge drive outputs. Note that only coil 2 in the minor
gauges requires a direction bit. Since coil 1 in each of the minor gauges
is a half H-bridge driver, it only requires a current magnitude register.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
15.6.3 Current Direction Registers
R E Q U I R E D
Gauge Drivers
Gauge Driver Control Registers
Freescale Semiconductor, Inc.
$2F
Bit 7
6
5
0
0
0
0
0
0
Read:
Write:
Reset:
CT
OR
, IN
C.2
006
15.6.3.2 Current Direction Register for Major B
4
3
2
1
Bit 0
0
0
0
DMJB1
DMJB2
0
0
0
0
0
Figure 15-8. MAJB Current Direction Register (DMAJB)
MIC
ON
DU
DMJB1 and DMJB2 — Current Direction Bits for Major Gauge B
1 = Current flow will be from the – pin to the + pin on the
corresponding coil driver.
0 = Current flow will be from the + pin to the – pin on the
corresponding coil driver.
$30
SE
15.6.3.3 Current Direction Register for Minor A
Bit 7
0
0
CA
Write:
Reset:
5
4
3
2
1
Bit 0
0
0
0
0
0
0
DMIA
0
0
0
0
0
0
0
LE
Read:
6
ES
Figure 15-9. MINA Current Direction Register (DMINA)
RE
DMIA — Current Direction Bit for Minor Gauge A
CH
IVE
DB
YF
1 = Current flow will be from the – pin to the + pin on the
corresponding coil driver.
0 = Current flow will be from the + pin to the – pin on the
corresponding coil driver.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
6
5
0
0
0
0
0
0
Read:
Write:
Reset:
4
3
2
1
Bit 0
0
0
0
0
DMIB
0
0
0
0
0
MIC
ON
DU
DMIB — Current Direction Bit for Minor Gauge B
1 = Current flow will be from the – pin to the + pin on the
corresponding coil driver.
0 = Current flow will be from the + pin to the – pin on the
corresponding coil driver.
$32
SE
15.6.3.5 Current Direction Register for Minor C
Bit 7
0
0
CA
Write:
Reset:
5
4
3
2
1
Bit 0
0
0
0
0
0
0
DMIC
0
0
0
0
0
0
0
LE
Read:
6
ES
Figure 15-11. MINC Current Direction Register (DMINC)
CH
IVE
DB
YF
RE
DMIC — Current Direction Bit for Minor Gauge C
1 = Current flow will be from the – pin to the + pin on the
corresponding coil driver.
0 = Current flow will be from the + pin to the – pin on the
corresponding coil driver.
AR
Freescale Semiconductor, Inc...
Figure 15-10. MINB Current Direction Register (DMINB)
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Bit 7
N O N - D I S C L O S U R E
$31
CT
OR
, IN
C.2
006
15.6.3.4 Current Direction Register for Minor B
R E Q U I R E D
Gauge Drivers
Gauge Driver Control Registers
Freescale Semiconductor, Inc.
$33
Read:
Write:
Reset:
Bit 7
6
5
0
0
0
0
0
0
CT
OR
, IN
C.2
006
15.6.3.6 Current Direction Register for Minor D
4
3
2
1
Bit 0
0
0
0
0
DMID
0
0
0
0
0
Figure 15-12. MIND Current Direction Register (DMIND)
15.7 Coil Sequencer and Control
MIC
ON
DU
DMID — Current Direction Bit for Minor Gauge D
1 = Current flow will be from the – pin to the + pin on the
corresponding coil driver.
0 = Current flow will be from the + pin to the – pin on the
corresponding coil driver.
RE
ES
CA
LE
SE
As shown in Figure 15-1 the digital/analog converter is shared among
all 12 coils. The sequence in which the coils are scanned and the events
that take place during the scanning process are described in this section.
The scan control and status register in 15.7.2 Scan Status and Control
Register controls how the coil sequencer will operate. This register
contains control bits that affect how the gauge sequencer will scan
through the six gauges as well as a status bit to indicate where the
scanning sequencer is in the scanning operation.
YF
15.7.1 Scanning Sequence Description
CH
IVE
DB
The coil sequencer can be operated in two basic modes: automatic or
manual. In either mode, each coil is updated by the D/A, muxes, and
sample and hold circuits in the sequence shown in Figure 15-1. One
time through the coil sequence is referred to as a scan cycle. It takes a
time, tgcs, to update each coil during the scanning sequence. Since there
are 12 coils in the six gauge drivers, it will take a time, 12*tgcs, to
complete one scan cycle.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
The differences between the automatic and manual modes are as
follows.
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MIC
ON
DU
For example, if the MIND1 register is written with any value, then the
MIND2 register must also be written. Otherwise, minor gauge D will not
be updated on subsequent scans and the currents driven into the coils
will maintain their previously programmed values. This sequence must
be followed even if the data written to one magnitude register is not
different from the data already in the register. The hardware works off
the write operation to the registers, not off the data written.
CA
LE
SE
Before the master-to-slave transfer takes place in the CDRs, each coil in
a particular gauge must be updated. Because writes to the CMRs are the
only requirement for transferring master to slave of the CDRs, the CDRs
should be written before the CMRs are written.
15.7.1.2 Manual Mode
CH
IVE
DB
YF
RE
ES
The user must set the SCNS bit in the scan status and control register
(SSCR) to initiate a scan cycle. Once a single scan cycle takes place,
the coil sequencer stops and waits for the SCNS bit to be set again
before starting another scan cycle. The SCNS bit must be set at a fast
enough rate (the scan period) to prevent the sample and hold circuits
from drooping and introducing error and current fluctuations into the
output currents. This minimum time is called the minimum scan period,
tmsn (see 17.11 Gauge Driver Electricals). The transfer of data from the
CMR and CDRs master-to-slave buffers is performed at the beginning of
each gauge update time even if all CMRs and CDRs were not updated.
AR
Freescale Semiconductor, Inc...
When one of the coil registers associated with a gauge is written, the
second register also must be written before either value will be used.
The coil registers may be written in either order.
If any of the gauges are turned off by clearing the appropriate bits in the
gauge enable register (GER), the time the coil sequencer would have
spent updating the coils in the disabled gauge is still expended, but the
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
Once all of the coils have been updated, the sequence repeats
automatically. The transfer of data in the CMR and CDRs master-toslave buffers is performed at the beginning of each gauge update time.
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
15.7.1.1 Automatic Mode
R E Q U I R E D
Gauge Drivers
Coil Sequencer and Control
Freescale Semiconductor, Inc.
R E Q U I R E D
Gauge Drivers
The scanning sequence for the coils is shown in Table 15-1. It takes a
time, tgcs, to update each coil. This includes time to move the data from
the CMR and CDR (automatic mode), perform the digital/analog
conversion, update the sample and hold circuit at the coil driver, and wait
for all transient currents to settle for each coil.
A G R E E M E N T
Table 15-1. Coil Scanning Sequencer
Freescale Semiconductor, Inc...
1
Major A
MAJA2
Major A
MAJB1
Major B
MAJB2
Major B
MINA1
Minor A
6
MINA2
Minor A
7
MINB1
Minor B
8
MINB2
Minor B
9
MINC1
Minor C
10
MINC2
Minor C
11
MIND1
Minor D
12
MIND2
Minor D
4
CA
ON
LE
SE
5
MIC
3
ES
Gauge Name
MAJA1
2
YF
RE
Coil Name
DU
Coil Number
CH
IVE
DB
Because several CPU write operations may be necessary to write to the
CMRs and CDRs, all of the CMRs and the CDRs contain a master and
a slave buffer to help prevent unwanted fluctuations in coil currents
between the writes to the three registers on a given gauge. Only the
slave buffers will affect the coil currents and direction.
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
coil driver remains off. This provides for a consistent scan rate
regardless of the number of gauges that are enabled.
General Release Specification
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Gauge Drivers
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Freescale Semiconductor, Inc.
DU
2. Increment pointer to next CMR slave register. If both CMRs for this
gauge have been written, transfer new master data to slave buffer
for this CMR and corresponding CDR. If both CMRs have not
been written, don’t transfer data from master to slave.
3. Move slave buffer data to the D/A input.
ON
4. Wait for the D/A output to muxes.
MIC
5. Close sample and hold mux and update direction control from
CDR.
SE
6. Wait for sample and hold to settle.
LE
7. Go back to step 1 above.
YF
RE
ES
Although the CDR and CMRs can be written at any time, the user may
want to write the CDR and CMRs at a particular time in the scanning
sequence. Some of the bits in the SSCR give the user the information
need to synchronize the writes to the CDR and CMRs with the coil
sequencer.
CH
IVE
DB
In addition to the sychronization bits, this register also contains a bit that
affects the type of scanning that will take place (automatic or manual)
and a bit to initiate a scan cycle manually when using manual mode.
MC68HC05V12 — Rev. 1.0
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N O N - D I S C L O S U R E
CA
15.7.2 Scan Status and Control Register
AR
Freescale Semiconductor, Inc...
1. Open all sample and hold switches.
A G R E E M E N T
CT
OR
, IN
C.2
006
For coil currents to remain as consistent as possible during the scanning
and updating of the gauge coil currents, the sample and hold update
operation must take place in a particular way. The control logic will
perform this function. When the scanning control logic is ready to
advance to the next coil, this operations sequence must take place:
R E Q U I R E D
Gauge Drivers
Coil Sequencer and Control
Freescale Semiconductor, Inc.
$21
Bit 7
Read:
6
5
SYNF
0
SYNIE
Write:
4
3
2
1
Bit 0
R
GCS1
GCS0
SCNS
AUTOS
0
0
0
0
0
R
= Reserved
CT
OR
, IN
C.2
006
R E Q U I R E D
Gauge Drivers
SYNR
Reset:
0
0
0
= Unimplemented
Figure 15-13. Scan Status and Control Register (SSCR)
A G R E E M E N T
SYNIE — Synchronize Interrupt Enable Bit
DU
ON
MIC
SE
SYNF — Synchronize Flag Bit
YF
RE
ES
CA
LE
This bit is a read-only status bit and indicates that the coil sequencer
has begun to service coil 11 (minor D). At this point in the scanning
cycle, it is safe to write any of the CMRs or CDRs without affecting the
current scan cycle. Any time this bit is set and the SYNIE bit is set, a
CPU interrupt will be generated. The bit will be set even if minor D is
not enabled in the GER, since the scanning sequence time is not
affected by the enabling or disabling of the gauges. This bit will
function in either auto or manual mode and does not affect the
scanning operation in any way. It serves only as a status flag. Note
that once this bit is set, the software will have a time, 2*tgcs, to update
DB
the CDR and CMR register if new data is to be used in the next scan
cycle.
IVE
The bit is cleared by writing a 1 to the SYNR bit and by reset.
CH
SYNR — Synchronize Flag Reset Bit
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
When this bit is set, an interrupt signal will be sent to the CPU when
the SYNF bit is set. The I bit in the CPU condition code register must
be cleared in order for the interrupt to be recognized by the CPU. The
interrupt vector assigned to the gauge module is shown in
Table 15-2.
1 = Interrupt is enabled.
0 = Interrupt is disabled.
This bit is used to clear the SYNF bit. Writing a 1 to this bit will clear
the SYNF bit if the SYNF bit was set during a read of the SSCR. This
bit will always read 0.
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
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Table 15-2. Gauge Module Clock Select Bits
CPU Bus
Clock Frequency
Freescale Semiconductor, Inc...
fop = 0.5 MHz
GCS0
Division
Scan Cycle
Time
0
0
512
tgcs
0
1
1024
tgcs
1
0
2048
tgcs
1
1
4096
tgcs
DU
fop = 1.0 MHz
GCS1
fop = 2.0 MHz
ON
fop = 4.0 MHz (see Note)
MIC
NOTE: Must not be selected
SCNS — Scan Start Bit
LE
SE
When the coil sequencer is being operated in manual mode, this bit is
used to initiate a scan cycle. Setting this bit starts the scan cycle. All
CMRs and CDRs will transfer data from the master to the slave when
this bit is set.
RE
ES
CA
This bit clears automatically once the scan cycle begins to service coil
11 (minor D). The bit will clear at the proper time, even if the minor D
gauge is not enabled in the GER, since the scan cycle time is not
affected by the enabling or disabling of the gauges. The bit is cleared
once coil 11 begins to be serviced because adequate time (2 * tgcs)
AR
CH
IVE
DB
YF
for the software (either interrupt driven or polled) to recognize the flag
and write new data to the CDR and CMR registers for the next scan
cycle should be provided. Note that after the scan cycle has finished,
a new scan cycle will not begin until this bit is set again. If a 1 is written
to this bit before it clears, the write will be ignored. In automatic mode,
this bit has no effect.
MC68HC05V12 — Rev. 1.0
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A G R E E M E N T
These bits determine the clock divide ratio for the clock used by the
scan sequencer. This provides for the use of several different system
clock rates while still providing the gauge driver module with the same
scanning rate.
N O N - D I S C L O S U R E
CT
OR
, IN
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006
GCS1–GCS0 — Gauge Clock Select Bits
R E Q U I R E D
Gauge Drivers
Coil Sequencer and Control
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
AUTOS — Automatic Mode Select Bit
This bit selects whether the coil sequencer will operate in manual or
automatic mode.
1 = Automatic mode
0 = Manual mode
15.8 Mechanism Diagram
MIC
ON
DU
The diagram in Figure 15-15 shows one way the gauge coils could be
connected to the coil driver pins and how some of the other pins should
be connected. The external components that have actual part numbers
are merely examples of suitable components. Other components with
similar operating characteristics also may be used.
SE
15.9 Gauge Power Supply
YF
RE
ES
CA
LE
The MC68HC05V12 contains most of the circuitry to provide the coil
drivers with a regulated supply that is necessary to drive the coil.
Referring to Figure 15-3, the gauge drive voltage, VGSUP, is derived with
the aid of an external P-channel enhancement mode MOSFET device
which serves as the series pass devices between a +12 V supply and
the VGSUP pin. Two external resistors also are used to set the level of
VGSUP. The drive to the gate of the external pass devices will be
whatever is required to produce a VGVREF voltage of 2.5. The value of
resistors Rg1 and Rg2 should be chosen so that
VGSUP * [Rg2/(Rg1+Rg2)] = 2.5
The VGSUP pin requires a 100 µF low ESR capacitor for regulator
stability. In addition, the VDD and VCCA pins should have the usual 0.1
µF bypass capacitors to VSS and VSSA respectively.
CH
IVE
DB
NOTE:
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
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Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
VBATT
1N5822
REVERSE BATTERY
AND TRANSIENT PROTECTION
0.1 mF
68HC05V12
0.1 mF
+5 VOLTS +/-5%
EXTERNAL
REGULATOR
CIRCUITRY
VPGC
VDD
0.1 m
VGSUP
MTP2955
RECOMMENDED
~8 V
Rg1
VDD
Freescale Semiconductor, Inc...
*100K
5%
VGVREF
DU
0.1 m
Rg2
100 mF
LOW ESR
0.1 mF
ON
MINA1
VCCA
VSS
VSS
SE
MIC
0.1 m
IVE
MINOR GAUGE C
MIND1
MINOR GAUGE D
MIND2+
MIND2−
MAJA1+
MAJA1−
MAJOR GAUGE A
MAJA2+
MAJA2−
MAJB1+
MAJB1−
MAJOR GAUGE B
MAJB2+
MAJB2−
AR
CH
NOTE: PASS DEVICE AND
RELATED COMPONENTS
SHOULD BE AS PHYSICALLY
CLOSE TO THE MCU AS POSSIBLE.
MINB2+
MINB2−
MINC2+
MINC2−
CA
RECOMMENDED VALUES
Rg1 − 55 k
Rg2 − 25 k
*R = PMOS VT(NOM)/50 x 10 –6
MINOR GAUGE B
IMAX
ES
DB
YF
RE
1%
MINB1
MINC1
VSSG
RMAX
MINA2+
MINA2−
LE
VSSA
MINOR GAUGE A
A G R E E M E N T
P6KE15A
Figure 15-14. Sample Gauge Connections to the MC68HC05V12
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
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N O N - D I S C L O S U R E
P6KE30A
R E Q U I R E D
Gauge Drivers
Gauge Power Supply
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
To provide effective decoupling and to reduce radiated RF emissions,
the small decoupling capacitors must be located as close to the supply
pins as possible. The self-inductance of these capacitors and the
parasitic inductance and capacitance of the interconnecting traces
determine the self-resonant frequency of the decoupling network. Too
low a frequency will reduce decoupling effectiveness and could increase
radiated RF emissions from the system. A low-value capacitor (470 pF
to 0.01 µF) placed in parallel with the other capacitors will improve the
bandwidth and effectiveness of the network.
DU
15.10 Gauge Regulator Accuracy
SE
MIC
ON
The on-chip portion of the regulator will contribute no more than Egs %
to the variation in the VGSUP voltage. The remaining errors will come
from the tolerances in the RG1 and RG2 resistors off-chip.
15.11 Coil Current Accuracy
CA
LE
The accuracy of the current flowing between the + and – coil pins of a
particular coil driver pin pair is described here.
ES
Matching of currents between coils within the same gauge is specified in
17.11 Gauge Driver Electricals as ECM.
YF
RE
The absolute accuracy of the coil current that can be driven into any coil
is determined by the accuracy of ICM given by the equations in 15.10
Gauge Regulator Accuracy and will be a total of (ECA + EMAX).
CH
IVE
DB
Because the D/A amp is shared among all coil drivers and between both
sets of drivers in the full H-bridge drivers, there will be no difference in
the magnitude of the current when the magnitude register value remains
constant and only the polarity bit is changed in a coil driver.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Gauge Drivers
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
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Freescale Semiconductor, Inc.
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006
15.12 External Component Considerations
To determine the values and tolerances of the external components
required to drive the air core gauge coils, the minimum VBATT voltage, at
the V12 pin, and the power dissipation should be considered.
Figure 15-15 shows the components in the path between the +12 V
coming in through the external devices the internal devices and into
VSSG.
R E Q U I R E D
Gauge Drivers
External Component Considerations
+
V
− diode
+
−
Vpass
COIL DRIVER PAD
GAUGE COILS
RE
ES
Rcoil
Lcoil
RI
PIN
ON PACKAGE
VSSG PAD
Figure 15-15. Coil Driver Current Path
AR
CH
IVE
DB
YF
COIL DRIVER PAD
MC68HC05V12 — Rev. 1.0
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N O N - D I S C L O S U R E
CA
LE
SE
VGSUP
A G R E E M E N T
DU
MIC
ON
1N5822
Freescale Semiconductor, Inc...
+12 V
Freescale Semiconductor, Inc.
15.12.1 Minimum Voltage Operation
CT
OR
, IN
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006
R E Q U I R E D
Gauge Drivers
To maintain accuracy to as low a VBATT voltage as possible, the
following equations should be used to calculate the range of values for
the external components.
VBATT(min) = VGSUP(max) + VDIODE + VPASS
VPASS is the drop across the external P-channel MOSFET at SF * 12
A G R E E M E N T
* ICOIL(max)
DU
VDIODE = Drop across reverse battery protection diode at 12 *
ON
ICOIL(max)
SE
MIC
To solve the above equation, the factors involved in generating the
gauge supply voltage, VGSUP, must first be calculated due to both
internal tolerances and the tolerances of external resistors RG1 and RG2,
LE
VGSUP = VGSUP(nom) x (1 ± TOL)
VGSUP(nom) is the VGSUP voltage generated with all tolerances set to
CA
0%.
TOL = Egs + TOL(RG1) + TOL(RG2) and includes temperature effects.
ES
RG1 and RG2 are the external resistors used to set the VGSUP voltage.
RE
The internal tolerances are Egs.
YF
The minimum VGSUP voltage required for proper operation is given by,
DB
ICOIL(max) x [RCOIL(max) + RSI(max)]
where
•
RSI is the total of the internal resistances from the transistors and
sense resistor and is found in the electrical specifications.
•
ICOIL is the minimum required coil current.
•
RCOIL is the minimum coil resistance including temperature
effects.
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
SF = % of max current driven by all coil drivers in application. Worst
case 0.707 (45o) assumes SIN/COS drive algorithm.
General Release Specification
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Gauge Drivers
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VGSUP(min) = VGSUP(nom) x (1-TOL)
equating the two
DU
ICOIL ( max ) X [ RCOIL ( max ) + RSI ( max ) ]
VGSUP ( nom ) = ----------------------------------------------------------------------------------------------------------------( 1 – TOL )
ON
15.12.2 Power Dissipation
LE
SE
MIC
To keep the junction temperature to a minimum, the power consumed by
the gauge drivers must be factored into the chip power dissipation
equation. The total chip power dissipation combined with the thermal
resistance of the package cannot exceed the maximum junction
temperature, TJ. The total chip power dissipation is given by this
equation:
RE
ES
PCHIP is the power contribution by all chip modules that are connected
to the VDD and VDDA sources including part of the gauge module. To
calculate PCHIP, use this equation:
CH
IVE
DB
YF
PCHIP = (IDD x VDD) + (ICCA x VCCA)
MC68HC05V12 — Rev. 1.0
General Release Specification
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N O N - D I S C L O S U R E
CA
PD = PGAUGE + PCHIP
AR
Freescale Semiconductor, Inc...
VGSUP(nom) x (1-TOL) = ICOIL(max) x [ RCOIL(max) + RSI(max) ]
A G R E E M E N T
CT
OR
, IN
C.2
006
The minimum required VGSUP must agree with the minimum generated
VGSUP of,
R E Q U I R E D
Gauge Drivers
External Component Considerations
Freescale Semiconductor, Inc.
R E Q U I R E D
Gauge Drivers
CT
OR
, IN
C.2
006
The power dissipation contributed by the gauge module is given by this
equation.
PGAUGE = [VGSUP(max) X IGSUP] + PGDRIVERS
where
PGDRIVERS =
[(VGSUP(max) x ICOIL(max)) – (ICOIL(max) 2 x RCOIL(min))] x 12 x SF
IGSUP = the current consumed by the gauge module from the
VGSUP pin for functions other than generating coil currents.
•
12 is the number of coil drivers
•
SF = % of max current driven in any coil; worse case for power
dissipation purposes, 0.707 (45o) assumes SIN/COS drive
algorithm
•
ICOIL(max) = maximum required coil current in each coil
LE
SE
MIC
ON
DU
•
CA
15.12.3 Coil Inductance Limits
DB
YF
RE
ES
Since the MCU pins will drive the gauge coils directly without any
external voltage limiting devices, precautions must be taken to avoid
generating voltages and currents high enough to damage the MCU. The
high voltages generated by the inductive impedance of the coil will be
related directly to the coil drivers. This imposes a limit on the maximum
coil inductance referred to as Lcoil in the electrical specifications.
15.13 Operation in Wait Mode
IVE
During wait mode, the gauge driver module will continue to operate
normally. The gauges will continue to be driven to the currents and
directions that were last written to the CMR and CDR. In manual mode,
if the CPU will be put into wait mode between scan cycles, the SYNIE bit
in the SSCR should be set to enable the gauge module to generate an
interrupt request (which will take the CPU out of wait mode) to properly
service the gauge coils.
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
where
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AR
CH
IVE
DB
YF
RE
ES
N O N - D I S C L O S U R E
CA
LE
SE
MIC
ON
DU
Freescale Semiconductor, Inc...
During stop mode, the system clocks will stop operating. All bits in the
GER register will be cleared automatically when stop mode is entered.
No other bits in any other gauge module registers will be affected. The
gauge controller sequence and control logic will be reset/initialized such
that a new scan sequence will begin once the gauges are turned on
during the user’s stop mode recovery sequence.
MC68HC05V12 — Rev. 1.0
General Release Specification
Gauge Drivers
For More Information On This Product,
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A G R E E M E N T
CT
OR
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006
15.14 Operation in Stop Mode
R E Q U I R E D
Gauge Drivers
Operation in Stop Mode
Freescale Semiconductor, Inc.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
CT
OR
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R E Q U I R E D
Gauge Drivers
General Release Specification
MC68HC05V12 — Rev. 1.0
Gauge Drivers
For More Information On This Product,
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General Release Specification — MC68HC05V12
Section 16. Instruction Set
16.1 Contents
SE
MIC
ON
DU
16.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
16.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
16.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
16.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
AR
CH
IVE
DB
YF
16.5
RE
ES
CA
LE
16.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
16.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .206
16.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .207
16.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .208
16.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .210
16.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
MC68HC05V12 — Rev. 1.0
General Release Specification
Instruction Set
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
16.2
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
CT
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16.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
DU
16.3 Addressing Modes
MIC
ON
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
LE
CA
ES
RE
Relative
CH
IVE
DB
YF
•
SE
•
AR
N O N - D I S C L O S U R E
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MIC
ON
DU
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
16.3.3 Direct
CA
LE
SE
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
ES
16.3.4 Extended
YF
RE
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
CH
IVE
DB
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
AR
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16.3.2 Immediate
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Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
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16.3.1 Inherent
R E Q U I R E D
Instruction Set
Addressing Modes
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16.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
DU
16.3.6 Indexed, 8-Bit Offset
SE
MIC
ON
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
RE
16.3.7 Indexed,16-Bit Offset
ES
CA
LE
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
IVE
DB
YF
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
CH
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
AR
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Instruction Set
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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ON
DU
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
MIC
16.4 Instruction Types
SE
The MCU instructions fall into the following five categories:
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
CH
IVE
DB
YF
RE
ES
N O N - D I S C L O S U R E
CA
LE
•
AR
Freescale Semiconductor, Inc...
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
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16.3.8 Relative
R E Q U I R E D
Instruction Set
Instruction Types
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16.4.1 Register/Memory Instructions
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R E Q U I R E D
Instruction Set
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 16-1. Register/Memory Instructions
Mnemonic
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
ON
DU
Add Memory Byte and Carry Bit to Accumulator
CMP
MIC
Compare Accumulator
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
LE
SE
Compare Index Register with Memory Byte
MUL
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
RE
ES
CA
OR Accumulator with Memory Byte
SUB
CH
IVE
DB
YF
Subtract Memory Byte from Accumulator
AR
N O N - D I S C L O S U R E
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These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
Do not use read-modify-write operations on write-only registers.
Table 16-2. Read-Modify-Write Instructions
Freescale Semiconductor, Inc...
Instruction
DU
Arithmetic Shift Left (Same as LSL)
Bit Clear
MIC
Bit Set
ON
Arithmetic Shift Right
ASR
BCLR(1)
BSET(1)
Complement (One’s Complement)
COM
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
ES
CA
Decrement
LE
SE
CLR
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
RE
YF
ASL
Clear Register
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
AR
CH
IVE
DB
Mnemonic
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A G R E E M E N T
NOTE:
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16.4.2 Read-Modify-Write Instructions
R E Q U I R E D
Instruction Set
Instruction Types
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16.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
DU
ON
MIC
SE
LE
CA
ES
RE
YF
DB
IVE
CH
AR
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Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
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DU
Branch if Higher or Same
BHS
Branch if IRQ Pin Low
BIL
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
CA
LE
MIC
Branch if Lower
SE
ON
BIH
ES
Branch if Bit Clear
Branch Never
RE
BHI
Branch if IRQ Pin High
Branch Always
Branch if Bit Set
BRA
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
AR
CH
IVE
DB
YF
Mnemonic
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Instruction
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Table 16-3. Jump and Branch Instructions
R E Q U I R E D
Instruction Set
Instruction Types
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16.4.4 Bit Manipulation Instructions
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R E Q U I R E D
Instruction Set
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 16-4. Bit Manipulation Instructions
A G R E E M E N T
Instruction
BCLR
BRCLR
Branch if Bit Set
BRSET
ON
DU
Branch if Bit Clear
BSET
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
Bit Set
AR
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Bit Clear
Mnemonic
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These instructions act on CPU registers and control CPU operation
during program execution.
Table 16-5. Control Instructions
Clear Carry Bit
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Clear Interrupt Mask
DU
No Operation
Mnemonic
CLC
CLI
NOP
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
MIC
ON
Reset Stack Pointer
STOP
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
AR
CH
IVE
DB
YF
RE
ES
CA
Software Interrupt
LE
SE
Stop Oscillator and Enable IRQ Pin
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Instruction
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16.4.5 Control Instructions
R E Q U I R E D
Instruction Set
Instruction Types
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16.5 Instruction Set Summary
DU
↕ —
A ← (A) + (M)
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
↕
↕
MIC
ON
Add without Carry
↕
Logical AND
A ← (A) ∧ (M)
— — ↕
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
ES
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
C
0
b7
C
b7
↕
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
YF
DB
— — ↕
b0
Mn ← 0
— — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
ff
ff
Cycles
Opcode
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
SE
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
A ← (A) + (M) + (C)
Add with Carry
LE
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
H I N Z C
CA
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
Description
RE
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Effect on
CCR
Address
Mode
Source
Form
Operand
Table 16-6. Instruction Set Summary
5
3
3
6
5
5
3
3
6
5
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
BHS rel
Branch if Higher or Same
CH
IVE
BCLR n opr
AR
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Instruction Set
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
PC ← (PC) + 2 + rel ? C = 0
General Release Specification
— — — — —
REL
22
rr
3
REL
24
rr
3
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Operand
Cycles
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
Description
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
(A) ∧ (M)
DU
PC ← (PC) + 2 + rel ? C = 1
H I N Z C
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
Branch if Interrupt Mask Set
Branch if Not Equal
BPL rel
Branch if Plus
BRA rel
Branch Always
MIC
BMS rel
BNE rel
ON
BMC rel
BMI rel
— — — — —
REL
2A
rr
3
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
SE
CA
LE
BRCLR n opr rel Branch if Bit n Clear
Branch Never
RE
ES
BRN rel
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
Set Bit n
CH
IVE
BSET n opr
DB
YF
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 0
REL
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
AR
BSR rel
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A G R E E M E N T
Opcode
Branch if IRQ Pin High
Operation
Effect on
CCR
N O N - D I S C L O S U R E
Address
Mode
BIH rel
Source
Form
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Table 16-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
3F
4F
5F
6F
7F
dd
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
— — 0 1 —
↕
DU
— — ↕
ON
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
MIC
LE
SE
Compare Index Register with Memory Byte
CA
Decrement Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Increment Byte
Unconditional Jump
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Operand
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Opcode
INC opr
INCA
INCX
INC opr,X
INC ,X
(A) – (M)
Complement Byte (One’s Complement)
ES
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
Compare Accumulator with Memory Byte
RE
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
Clear Byte
YF
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DB
COM opr
COMA
COMX
COM opr,X
COM ,X
DIR
INH
INH
IX1
IX
Effect on
CCR
H I N Z C
IVE
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
Description
CH
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Address
Mode
Source
Form
CT
OR
, IN
C.2
006
Table 16-6. Instruction Set Summary (Continued)
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
General Release Specification
MC68HC05V12 — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
Negate Byte (Two’s Complement)
NOP
No Operation
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ON
C
b7
0 — — — 0
INH
42
— — ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
— — — — —
INH
9D
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
↕
DIR
INH
INH
IX1
IX
39
49
59
69
79
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
IVE
CH
Rotate Byte Left through Carry Bit
C
— — 0 ↕
— — ↕
b7
↕
↕
b0
X : A ← (X) × (A)
Logical OR Accumulator with Memory
— — ↕
b0
0
DB
YF
RE
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
0
b7
b0
MC68HC05V12 — Rev. 1.0
↕
↕
↕
ff
ff
5
3
3
6
5
5
3
3
6
5
1
1
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
↕ —
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
N O N - D I S C L O S U R E
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
Cycles
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
— — ↕
C
Operand
Opcode
Unsigned Multiply
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — — — —
DIR
EXT
IX2
IX1
IX
DU
MUL
SE
Logical Shift Left (Same as ASL)
Logical Shift Right
X ← (M)
MIC
Load Index Register with Memory Byte
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
A ← (M)
Load Accumulator with Memory Byte
LE
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
Jump to Subroutine
CA
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
ES
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Description
H I N Z C
AR
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect on
CCR
Address
Mode
Source
Form
CT
OR
, IN
C.2
006
Table 16-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
Opcode
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
↕
↕
INH
80
9
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
C←1
— — — — 1
INH
99
2
I←1
— 1 — — —
INH
9B
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
1
0
INH
97
2
Operation
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
C
b7
SP ← $00FF
Return from Interrupt
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SEC
Set Carry Bit
SEI
Set Interrupt Mask
LE
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
M ← (A)
ES
RE
↕
↕
M ← (X)
↕
↕
↕
↕
DB
YF
Store Index Register In Memory
Subtract Memory Byte from Accumulator
CH
IVE
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
CA
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
A ← (A) – (M) – (C)
SE
Subtract Memory Byte and Carry Bit from
Accumulator
MIC
ON
DU
RTI
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
— — ↕
b0
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
A ← (A) – (M)
X ← (A)
General Release Specification
— — ↕
— — — — —
ff
Cycles
Address
Mode
Source
Form
CT
OR
, IN
C.2
006
Table 16-6. Instruction Set Summary (Continued)
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
2
MC68HC05V12 — Rev. 1.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
dd
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
— — — — —
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — —
INH
8F
2
— — ↕
(M) – $00
A ← (X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
ff
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
CH
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
↕ —
4
3
3
5
4
MC68HC05V12 — Rev. 1.0
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
3D
4D
5D
6D
7D
N O N - D I S C L O S U R E
Operand
DIR
INH
INH
IX1
IX
H I N Z C
Cycles
Opcode
Description
TST opr
TSTA
TSTX
TST opr,X
TST ,X
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Address
Mode
Operation
Effect on
CCR
AR
Freescale Semiconductor, Inc...
Source
Form
CT
OR
, IN
C.2
006
Table 16-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
CH
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
9
MSB
0
LSB
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
0
MSB of Opcode in Hexadecimal
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
CT
OR
, IN
C.2
006
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
DU
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
ON
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
1
1
1
1
1
1
2
2
2
2
2
2
2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
MIC
SE
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
LE
CA
ES
RE
YF
DB
IVE
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
3
1
DIR 2
DIR 2
REL
5
11
5
3
BRSET1
MUL
BHI
BSET1
3
1
DIR 2
INH
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
1
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
AR
0
MSB
LSB
DIR
Bit Manipulation
Table 16-7. Opcode Map
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
nc...
N O N - D I S C LFreescale
O S U R E Semiconductor,
A G R E E M E IN
T
R E Q U I R E D
Freescale Semiconductor, Inc.
Instruction Set
MC68HC05V12 — Rev. 1.0
Section 17. Electrical Specifications
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
17.3
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .221
17.4
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
17.5
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
17.6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .223
17.7
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
17.8
A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . .226
17.9
LVR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
SE
MIC
ON
DU
17.2
LE
Freescale Semiconductor, Inc...
17.1 Contents
A G R E E M E N T
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
ES
17.11 Gauge Driver Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230
AR
CH
IVE
DB
YF
RE
17.12 BDLC Electricals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231
17.12.1 Transmitter VPW Symbol Timings . . . . . . . . . . . . . . . . . .231
17.12.2 Receiver VPW Symbol Timings . . . . . . . . . . . . . . . . . . . .231
MC68HC05V12 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
N O N - D I S C L O S U R E
CA
17.10 Serial Peripheral Interface (SPI) Timing . . . . . . . . . . . . . . . . .228
Freescale Semiconductor, Inc.
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
ON
DU
Rating
MIC
Supply Voltage
SE
Input Voltage
Current Drain Per Pin (I/O)
Current Drain Per Pin (Gauge)
LE
Storage Temperature Range
ES
CA
Write/Erase Cycles
(@ 10 ms write time and –40 °C,
+25 °C, and +85°C)
Value
Unit
VPGC, VGSUP,
and VGREF
VDD
VCCA
–0.5 to +42.0
–0.5 to +7.0
VDD
VIN
VSS –0.3 to VDD
+0.3
V
I
25
50
mA
Tstg
–65 to +150
°C
—
10,000
Cycles
—
10
Years
V
RE
Data Retention EEPROM
(–40 °C, to + 85 °C)
Symbol
NOTE:
CH
IVE
DB
YF
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 17.6 DC Electrical Characteristics for guaranteed
operating conditions.
AR
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
17.2 Maximum Ratings
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05V12 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Operating Temperature Range
Standard
Extended
17.4 Thermal Characteristics
DU
Characteristic
Unit
TA
TL to TH
0 to +70
–40 to +85
°C
TJ
150
°C
Symbol
Value
Unit
θJA
50
°C/W
CH
IVE
DB
YF
RE
ES
N O N - D I S C L O S U R E
CA
LE
SE
MIC
ON
Thermal Resistance
PLCC (68 Pin)
Value
AR
Freescale Semiconductor, Inc...
Maximum Junction Temperature
Symbol
MC68HC05V12 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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R E Q U I R E D
Characteristic
A G R E E M E N T
17.3 Operating Temperature Range
CT
OR
, IN
C.2
006
Electrical Specifications
Operating Temperature Range
Freescale Semiconductor, Inc.
The average chip junction temperature, TJ, in °C can be obtained from:
T J = T A + (P D × θ JA )
(1)
where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
DU
Freescale Semiconductor, Inc...
PINT and can be neglected.
ON
For most applications, PI/O
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
P D = -----------------------------T J + 273 °C
Solving equations (1) and (2) for K gives:
SE
MIC
(2)
= PD × ( T A + 273 °C) + θ JA × ( PD )2
(3)
CH
IVE
DB
YF
RE
ES
CA
LE
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
AR
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
17.5 Power Considerations
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05V12 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Output Voltage
ILOAD = 10.0 µA
ILOAD = −10.0 µA
Output High Voltage
(ILOAD −0.8 mA) Port A, Port B, Port C, TXP
DU
Input High Voltage
Port A, Port B, Port C Port D, IRQ, RESET, OSC1, RXP
SE
MIC
Supply Current (see Notes)
Run
Wait SPI, TIMER, A/D, PWM, COP, LVR On
Wait Above Modules Off
Stop
LVR Enabled
LVR Disabled
LE
I/O Ports Hi-Z Leakage Current
Port A, Port B, Port C
CA
Input Current
RESET, IRQ, OSC1, PD0-PD4
ES
Capacitance (see Note 9)
Ports (as Input or Output)
RESET, IRQ
RE
Low-Voltage Reset Inhibit
Low-Voltage Reset Recover
YF
Low-Voltage Reset Inhibit/Recover Hysteresis
DB
VDD Slew Rate Rising (see Note 9)
VDD Slew Rate Falling (see Note 9)
Max
Unit
VOL
VOH
—
VDD − 0.1
0.1
—
V
VOH
VDD − 0.8
—
V
VOL
—
0.4
V
VIH
0.7 x VDD
VDD
V
VIL
VSS
0.3 x VDD
V
IDD
—
__
__
10
6
4
mA
mA
mA
—
—
300
200
µA
µA
IOZ
—
1
µA
IIN
—
1
µA
COUT
CINT
—
—
12
8
pF
VLVRI
3.5
4.2
V
VLVRR
3.6
4.5
V
HLVR
0.1
0.3
V
SVDDR
—
0.1
V/µs
SVDDF
—
0.05
V/µs
ON
Input Low Voltage
Port A, Port B, Port C, Port D, IRQ, RESET, OSC1, RXP
Min
CH
IVE
NOTES:
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. All values shown reflect average measurements.
3. Run (Operating) IDD, wait IDD: Measured using external square wave clock source to OSC1 (fOSC = 4.2 MHz), all inputs 0.2 Vdc
from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc.
5. Stop IDD measured with OSC1 = VSS.
6. Wait IDD is affected linearly by the OSC2 capacitance.
7. Total
8. All coil drivers are set to the maximum current in automatic mode with no loading on the gauge pins.
9. Not Tested
AR
Freescale Semiconductor, Inc...
Output Low Voltage
(ILOAD = 1.6 mA) Port A, Port B, Port C, TXP
Symbol
MC68HC05V12 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
17.6 DC Electrical Characteristics
R E Q U I R E D
Electrical Specifications
DC Electrical Characteristics
Freescale Semiconductor, Inc.
Characteristic
CT
OR
, IN
C.2
006
17.7 Control Timing
Symbol
Min
Max
Unit
fOSC
fOSC
0.1
dc
4.2
4.2
MHz
fOP
fOP
—
dc
2.1
2.1
MHz
tCYC
476
—
ns
tOXON
—
100
ms
tILCH
—
100
ms
tRL
120
—
ns
tILIH
120
—
ns
tILIL
See Note 3
—
tCYC
Port C Interrupt Pulse Width High (Edge-Triggered)
tILHI
120
—
ns
Port C Interrupt Pulse Period
tIHIH
See Note 3
—
tCYC
tOSC1
90
—
ns
tEEPGM
10
—
ms
tEBYT
10
—
ms
tEBLOCK
10
—
ms
tEBULK
10
—
ms
tFPV
—
10.0
µs
tRCON
—
5
tCYC
tRESL
tTH, tTL
tTLTL
4.0
85
See Note 4
__
__
__
tCYC
ns
tCYC
Frequency of Operation
Crystal Oscillator Option
External Clock Source
Internal Operating Frequency
Crystal (fOSC /2)
External Clock (fOSC /2)
Cycle Time (1/fOP)
Stop Recovery Startup Time (Crystal Oscillator Option)
ON
RESET Pulse Width Low (See Figure 5-2)
Interrupt Pulse Width Low (Edge-Triggered)
SE
MIC
Interrupt Pulse Period
LE
OSC1 Pulse Width
EEPROM Programming Time per Byte
CA
EEPROM Erase Time per Byte
ES
EEPROM Erase Time per Block
EEPROM Bulk Erase Time
DB
YF
RC Oscillator Stabilization Time
RE
EEPROM Programming Voltage Discharge Period
16-Bit Timer
Resolution (See Note 2)
Input Capture Pulse Width
Input Capture Period
DU
Crystal Oscillator Startup Time (Crystal Oscillator Option)
CH
IVE
NOTES:
1. VDD = 5.0 Vdc, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service routine
plus 19 tCYC.
4. The minimum period, tTLTL, should not be less than the number of cycles it takes to execute the capture interrupt service routine
plus 24 tCYC.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05V12 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
OSC11
tRL
RESET
tILIH
IRQ2
DU
IRQ3
MIC
ON
INTERNAL
CLOCK
INTERNAL
ADDRESS
BUS
3FFE
3FFE
SE
3FFE
3FFF4
RESET OR INTERRUPT
VECTOR FETCH
CA
LE
NOTES:
1. Represents the internal gating of the OSC1 pin.
2. IRQ pin is edge-sensitive mask option.
3. IRQ pin is level- and edge-sensitive mask option.
4. RESET vector address is shown for timing example.
3FFE
CH
IVE
DB
YF
RE
ES
Figure 17-1. Stop Recovery Timing Diagram
MC68HC05V12 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
4064 tCYC
N O N - D I S C L O S U R E
tILCH
AR
Freescale Semiconductor, Inc...
R E Q U I R E D
Electrical Specifications
Control Timing
Freescale Semiconductor, Inc.
Min
Max
Unit
Resolution
8
8
Bits
Absolute Accuracy
(VREFL = 0.0 V, VREFH = VDD)
—
+1
LSB
VREFL
VREFL
−0.1
VREFH
VDD
VREFH
V
V
V
Power-Up Time
—
100
µs
Input Leakage
PD0–PD4
VREFL, VREFH
—
—
DU
µA
µA
32
TAD
(see Note 2)
Conversion Range
VREFH
VREFL
Conversion Time
(Includes Sampling Time)
MIC
32
+1
+1
ON
Characteristic
CT
OR
, IN
C.2
006
17.8 A/D Converter Characteristics
Monotonicity
Comments
Include quantization
A/D accuracy decreases
proportionately as VREFH is
reduced below VCCA min.
(see Note 3)
Inherent (Within Total Error)
00
01
Hex
VIN = 0 V
Full-Scale Reading
FE
FF
Hex
VIN = VREFH
12
12
TAD
(see Note 2)
8
pF
VREFL
VREFH
V
—
100
µs
—
5
µs
SE
Zero Input Reading
LE
Sample Time
—
Analog Input Voltage
RC Oscillator Stabilization Time (tRCON)
ES
A/D On Current Stabilization Time (tADON)
CA
Input Capacitance
Not Tested
CH
IVE
DB
YF
RE
NOTES:
1 VCCA = 5.0 ±10% Vdc +10%, VSSA = 0.0 Vdc, TA = −40 °C to +85 °C, unless otherwise noted.
2. TAD = tCYC if clock source equals MCU.
3. Not Tested
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05V12 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
tVDDF = V /S
DD VDDF
VDD
VLVRI
DU
VLVRR
ON
RESET PIN
CH
IVE
DB
YF
RE
ES
N O N - D I S C L O S U R E
CA
LE
SE
MIC
Figure 17-2. LVR Timing Diagram
AR
Freescale Semiconductor, Inc...
INTERNAL LVR
tVDDR = V /S
DD VDDR
MC68HC05V12 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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A G R E E M E N T
CT
OR
, IN
C.2
006
17.9 LVR Timing Diagram
R E Q U I R E D
Electrical Specifications
LVR Timing Diagram
Freescale Semiconductor, Inc.
Num
CT
OR
, IN
C.2
006
17.10 Serial Peripheral Interface (SPI) Timing
Characteristic
Operating Frequency
Master
Slave
1
Cycle Time
Master
Slave
2
Enable Lead Time
Master
Slave
Symbol
Min
Max
Unit
fOP(M)
fOP(S)
dc
dc
0.5
4.2
fOP
MHz
tCYC(m)
tCYC(s)
2.0
240
—
—
tCYC
ns
tLEAD(M)
lLEAD(S)
see Note 2
240
—
—
ns
ns
tLAG(m)
tLAG(s)
see Note 2
240
—
—
ns
ns
tw(SCKH)m
tw(SCKH)s
340
190
—
—
ns
ns
tw(SCKL)m
tw(SCKL)s
340
190
—
—
ns
ns
tSU(m)
tSU(s)
100
100
—
—
ns
ns
tH(m)
tH(s)
100
100
—
—
ns
ns
tA
0
120
ns
Enable Lag Time
Master
Slave
4
Clock (SCK) High Time
Master
Slave
5
Clock (SCK) Low Time
Master
Slave
6
Data Setup Time (Inputs)
Master
Slave
7
Data Hold Time (Inputs)
Master
Slave
8
Access Time (Time to Data Active from High-Impedance State)
Slave
9
Disable Time (Hold Time to High-Impedance State)
Slave
tDIS
—
240
ns
10
Data Valid (After Enable Edge) (see Note 3)
tV(s)
—
240
ns
11
Data Hold Time (Output) (After Enable Edge)
tHO
0
—
ns
12
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
—
100
2.0
ns
µs
13
Fall Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
—
100
2.0
ns
µs
IVE
DB
YF
RE
ES
CA
LE
SE
MIC
ON
DU
3
CH
NOTES:
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05V12 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
CT
OR
, IN
C.2
006
5
SCK (CPOL = 0)
(INPUT)
4
2
4
13
12
10
MSB IN
9
SEE
NOTE
SLAVE LSB OUT
11
11
ON
7
6
MOSI
(INPUT)
BIT 6 --- 1
MSB OUT
DU
SLAVE
LSB IN
BIT 6 --- 1
MIC
NOTE: Not defined, but normally LSB of character previously transmitted.
SE
Figure 17-3. SPI Slave Timing (CPHA = 0)
LE
SS
(INPUT)
CA
12
13
1
RE
SCK (CPO L = 1)
(INPUT)
ES
5
SCK (CPOL = 0)
(INPUT)
4
5
4
3
12
13
YF
2
10
9
BIT 6 --- 1
SLAVE MSB OUT
6
7
MSB IN
SLAVE LSB OUT
11
10
BIT 6 --- 1
LSB IN
CH
MOSI
(INPUT)
SEE
NOTE
IVE
MISO
(OUTPUT)
DB
8
NOTE: Not defined but normally LSB of character previously transmitted.
AR
Freescale Semiconductor, Inc...
8
MISO
(OUTPUT)
2
1
5
SCK (CPOL + 1)
(INPUT)
12
A G R E E M E N T
13
Figure 17-4. SPI Slave Timing (CPHA = 1)
MC68HC05V12 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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N O N - D I S C L O S U R E
SS
(INPUT)
R E Q U I R E D
Electrical Specifications
Serial Peripheral Interface (SPI) Timing
Freescale Semiconductor, Inc.
17.11 Gauge Driver Electricals
CT
OR
, IN
C.2
006
R E Q U I R E D
Electrical Specifications
Characteristic
Input Current on VGSUP with No Coil Current
Input Current on VGSUP with Coil Current (see Note 3)
Input Current on VGSUP in Stop Mode
Maximum Reference Current
Internal Total Series Impedance
Coil Inductance (see Note 4)
Max
Unit
IGSUP
—
—
—
5
135
40
mA
mA
µA
IMAX
0.47
0.57
mA
RSI
20
60
Ω
tMSN
12 * tGCS
20
ms
LCOIL
—
31
mH
RCOIL
140
270
Ω
±1
%
DU
Coil Resistance (see Note 4)
Min
Error Tolerance of RMAX
EMAX
ON
Coil Current Matching Error (as % of ICM)
MIC
Coil Current Absolute Error
Coil Current Update Time
SE
Coil Current Maximum
Gauge Supply Regular Error
LE
Monotonicity
0
±1
%
ECA
0
±9
%
tGCS
TBD
1.67
ms
ICM
—
23
mA
EGS
—
±5
%
See Note 5
IStep
(ICM/255) *
0.50
(ICM/255) *
1.50
mA
CA
Coil Current Step Size
ECM
CH
IVE
DB
YF
RE
ES
NOTES:
1. VGSUP = 7.6 Vdc, TA = −40 °C to +85 °C, unless otherwise noted.
2. Minimum/Maximum is dependent upon power calculation.
3. Assumes sin/cos
4. Coil is not on chip; values stated are indicative of the intended application.
5. Inherent within total error.
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Manual Scan Cycle Period
Symbol
General Release Specification
MC68HC05V12 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Symbol
Min
Typ
Max
Unit
Passive Logic 0
10
tTVP1
62
64
66
µs
Passive Logic 1
11
tTVP2
126
128
130
µs
Active Logic 0
12
tTVA1
126
128
130
µs
Active Logic 1
13
tTVA2
62
64
66
µs
tTVA3
198
200
202
µs
15
tTVP3
198
200
202
µs
16
tTV4
278
280
282
µs
17
tTV6
298
300
302
µs
14
ON
Start of Frame (SOF)
End of Data (EOD)
MIC
End of Frame (EOF)
Inter-Frame Separator (IFS)
LE
SE
NOTE: fBDLC = 1.048576 MHz or 1.0 MHz
17.12.2 Receiver VPW Symbol Timings
CA
Table 17-2. BDLC Receiver VPW Symbol Timings (BARD Bits BO[3:0] = 0111)
ES
Characteristic
RE
Passive Logic 0
Passive Logic 1
YF
Active Logic 0
Active Logic 1
DB
Start of Frame (SOF)
End of Frame (EOF)
Symbol
Min
Typ
Max
Unit
10
tTRVP1
34
64
96
µs
11
tTRVP2
96
128
163
µs
12
tTRVA1
96
128
163
µs
13
tTRVA2
34
64
96
µs
14
tTRVA3
163
200
239
µs
15
tTRVP3
163
200
239
µs
16
tTRV4
239
280
320
µs
18
tTRV6
239
—
—
µs
CH
Break
IVE
End of Data (EOD)
Number
NOTE: fBDLC = 1.048576 MHz or 1.0 MHz
AR
NOTE:
The receiver symbol timing boundaries are subject to an uncertainty of
1 tBDLC µs due to sampling considerations.
MC68HC05V12 — Rev. 1.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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R E Q U I R E D
Characteristic
Freescale Semiconductor, Inc...
Number
DU
Table 17-1. BDLC Transmitter VPW Symbol Timings (BARD Bits BO[3:0] = 0111)
A G R E E M E N T
17.12.1 Transmitter VPW Symbol Timings
N O N - D I S C L O S U R E
17.12 BDLC Electricals
CT
OR
, IN
C.2
006
Electrical Specifications
BDLC Electricals
Freescale Semiconductor, Inc.
1
1
12
SOF
0
0
CT
OR
, IN
C.2
006
11
10
15
0
EOD
DU
13
14
ON
16
MIC
EOF
BRK
CA
LE
SE
18
CH
IVE
DB
YF
RE
ES
Figure 17-5. BDLC Variable Pulse Width Modulation (VPW) Symbol Timings
AR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05V12 — Rev. 1.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
18.3
68-Lead Plastic Leaded Chip Carrier (PLCC). . . . . . . . . . . . .234
DU
18.2
ON
18.2 Introduction
LE
SE
MIC
This section describes the dimensions of the dual in-line package (DIP),
plastic shrink dual in-line package (SDIP), plastic leaded chip carrier
(PLCC), and quad flat pack (QFP) MCU packages. Package dimensions
available at the time of this publication are provided in this section. To
make sure that you have the latest case outline specifications, contact
one of the following:
Local Motorola Sales Office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
Worldwide Web (wwweb) at http://design-net.com
YF
•
RE
ES
CA
•
CH
IVE
DB
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
AR
Freescale Semiconductor, Inc...
18.1 Contents
MC68HC05V12 — Rev. 1.0
General Release Specification
Mechanical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 18. Mechanical Specifications
N O N - D I S C L O S U R E
CT
OR
, IN
C.2
006
General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
Y BRK
–N–
T L–M
M
0.007
U
D
M
N
S
T L–M
S
S
N
S
Z
DU
–M–
W
D
1
ON
68
0.007
R
0.007
M
T L–M
S
M
T L–M
S
N
N
LE
Z
A
MIC
V
CA
E
C
0.004
–T– SEATING
J
PLANE
VIEW S
G
T L–M
S
N
S
S
0.007
M
T L–M
S
N
DB
H
YF
RE
0.010
ES
G1
K
VIEW S
0.007
CH
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K1
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0.007
B
–L–
N O N - D I S C L O S U R E
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18.3 68-Lead Plastic Leaded Chip Carrier (PLCC)
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R E Q U I R E D
Mechanical Specifications
M
T L–M
S
N
S
S
S
S
X
G1
0.010
VIEW D–D
S
T L–M
S
N
S
NOTES:
1. DATUMS L, M, AND N DETERMINED WHERE TOP OF LEAD
SHOULDER EXITS PLASTIC BODY AT MOLD PARTING
LINE.
2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT
DATUM T, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM BY UP TO 0.012. DIMENSIONS R AND
U ARE DETERMINED AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE
BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT
INCLUDING ANY MISMATCH BETWEEN THE TOP AND
BOTTOM OF THE PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION
TO BE GREATER THAN 0.037. THE DAMBAR
INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO
BE SMALLER THAN 0.025.
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.985
0.995
0.985
0.995
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.950
0.956
0.950
0.956
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10_
0.910
0.930
0.040
–––
Figure 18-1. 68-Lead PLCC, Case 779-02
General Release Specification
MC68HC05V12 — Rev. 1.0
Mechanical Specifications
For More Information On This Product,
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Section 19. Ordering Information
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
19.3
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
19.4
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .236
19.5
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .237
19.6
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .238
19.7
MC Order Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
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19.2 Introduction
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19.3 MCU Ordering Forms
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To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit the
following items when ordering MCUs:
A current MCU ordering form that is completely filled out
(Contact your Motorola sales office for assistance.)
•
A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU
•
Customer’s application program on one of the media listed in 19.4
Application Program Media
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•
MC68HC05V12 — Rev. 1.0
General Release Specification
Ordering Information
For More Information On This Product,
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This section contains ordering information.
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19.1 Contents
A G R E E M E N T
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General Release Specification — MC68HC05V12
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
19.4 Application Program Media
Please deliver the application program to Motorola in one of the following
media:
Macintosh®1 3-1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
•
MS-DOS®2 or PC-DOSTM3 3-1/2-inch diskette (double-sided 720
K or double-sided high-density 1.44 M)
•
MS-DOS® or PC-DOSTM 5-1/4-inch diskette (double-sided
double-density 360 K or double-sided high-density 1.2 M)
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Use positive logic for data and addresses.
CA
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When submitting the application program on a diskette, clearly label the
diskette with the following information:
Customer name
•
Customer part number
•
Project or product name
RE
ES
•
File name of object code
YF
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
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•
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On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
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The current MCU ordering form is also available through the Motorola
Freeware Bulletin Board Service (BBS). The telephone number is (512)
891-FREE. After making the connection, type bbs in lowercase letters.
Then press the return key to start the BBS software.
A G R E E M E N T
R E Q U I R E D
Ordering Information
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
General Release Specification
MC68HC05V12 — Rev. 1.0
Ordering Information
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
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In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
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19.5 ROM Program Verification
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The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
YF
RE
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Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
IVE
DB
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Motorola. The signed
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
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If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
MC68HC05V12 — Rev. 1.0
General Release Specification
Ordering Information
For More Information On This Product,
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A G R E E M E N T
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Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations or leave all non-user ROM locations blank. Refer to the current
MCU ordering form for additional requirements. Motorola may request
pattern re-submission if non-user areas contain any non-zero code.
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Ordering Information
ROM Program Verification
Freescale Semiconductor, Inc.
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19.6 ROM Verification Units (RVUs)
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After receiving the signed listing verify form, Motorola manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Motorola then produces ten MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The ten RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Motorola Quality Assurance.
19.7 MC Order Number
SE
Table 19-1 shows the MC order number for the available package type.
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Table 19-1. MC Order Number
Temperature
Range
Order Number
68-Lead Plastic Leaded Chip Carrier (PLCC)
–40 °C to 85 °C
MC68HC05V12CFN
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Package Type
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NOTES:
1. FN = Plastic-leaded chip carrier (PLCC)
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A G R E E M E N T
R E Q U I R E D
Ordering Information
General Release Specification
MC68HC05V12 — Rev. 1.0
Ordering Information
For More Information On This Product,
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Freescale Semiconductor, Inc.
For More Information On This Product,
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HC05V12GRS/D