Complete, 12-Bit, 45 MHz CCD Signal Processor ADDI7100 FEATURES GENERAL DESCRIPTION Pin-compatible upgrade for the AD9945 45 MHz correlated double sampler (CDS) with variable gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) Low noise optical black clamp circuit Preblanking function 12-bit, 45 MHz ADC No missing codes guaranteed 3-wire serial digital interface 3 V single-supply operation Space-saving, 32-lead, 5 mm × 5 mm LFCSP The ADDI7100 is a complete analog signal processor for chargecoupled device (CCD) applications. It features a 45 MHz, single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The signal chain for the ADDI7100 consists of a correlated double sampler (CDS), a digitally controlled variable gain amplifier (VGA), a black level clamp, and a 12-bit ADC. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input clock polarity, and power-down modes. The ADDI7100 operates from a single 3 V power supply, typically dissipates 125 mW, and is packaged in a space-saving, 32-lead LFCSP. APPLICATIONS Digital still cameras Digital video camcorders PC cameras Portable CCD imaging devices CCTV cameras FUNCTIONAL BLOCK DIAGRAM REFT ADDI7100 −3dB, 0dB, +3dB, +6dB CCDIN CDS REFB PBLK DRVDD BAND GAP REFERENCE DRVSS 6dB TO 42dB 12 12-BIT ADC VGA DOUT D0 TO D11 CLP 10 AVDD CLPOB AVSS CONTROL REGISTERS VD SL SCK SDATA SHP SHD DATACLK DVDD DVSS 07608-001 INTERNAL TIMING DIGITAL INTERFACE Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved. ADDI7100 TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .................................................................................... 11 Applications ....................................................................................... 1 Circuit Description and Operation .............................................. 12 General Description ......................................................................... 1 DC Restore .................................................................................. 12 Functional Block Diagram .............................................................. 1 Correlated Double Sampler (CDS) .......................................... 12 Revision History ............................................................................... 2 Optical Black Clamp .................................................................. 12 Specifications..................................................................................... 3 Analog-to-Digital Converter (ADC) ....................................... 13 General Specifications ................................................................. 3 Variable Gain Amplifier (VGA) ............................................... 13 Digital Specifications ................................................................... 3 Digital Data Outputs .................................................................. 13 System Specifications ................................................................... 4 Applications Information .............................................................. 14 Timing Specifications .................................................................. 5 Initial Power-On Sequence ....................................................... 15 Absolute Maximum Ratings............................................................ 7 Grounding and Decoupling Recommendations .................... 15 Thermal Resistance ...................................................................... 7 Serial Interface Timing .................................................................. 16 ESD Caution .................................................................................. 7 Complete Register Listing ............................................................. 17 Pin Configuration and Function Descriptions ............................. 8 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 9 Ordering Guide .......................................................................... 19 Equivalent Input Circuits .............................................................. 10 REVISION HISTORY 6/10—Rev. B to Rev. C Changes to 0x0D Description and 0xFF Description in Table 8 .............................................................................................. 18 9/09—Rev. A. to Rev. B Changes to Features Section............................................................ 1 Changed Power-Down Mode to Full Standby Mode, Table 1 .... 3 Moved Timing Diagrams Section .................................................. 5 Changes to Table 4, Figure 3, and Figure 4 ................................... 5 Changes to Figure 9 Caption ......................................................... 10 Changes to Optical Black Clamp Section .................................... 12 Changes to Initial Power-On Sequence Section ......................... 15 Changes to Figure 16 ...................................................................... 16 Changes to Table 8 .......................................................................... 17 2/09—Rev. 0 to Rev. A Changes to Serial Interface Timing Section ................................ 16 Changes to Figure 16 and Figure 17 ............................................. 16 10/08—Revision 0: Initial Version Rev. C | Page 2 of 20 ADDI7100 SPECIFICATIONS GENERAL SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 45 MHz, unless otherwise noted. Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Full Standby Mode MAXIMUM CLOCK RATE Min Typ Max Unit −25 −65 +85 +150 °C °C 2.7 3.6 V 125 1 mW mW MHz 45 DIGITAL SPECIFICATIONS DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted. Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA Symbol Min VIH VIL IIH IIL CIN 2.1 VOH VOL 2.2 Typ Max 0.6 10 10 10 0.5 Rev. C | Page 3 of 20 Unit V V μA μA pF V V ADDI7100 SYSTEM SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 45 MHz, unless otherwise noted. Table 3. Parameter CDS Allowable CCD Reset Transient CDS Gain Accuracy −3 dB CDS Gain 0 dB CDS Gain +3 dB CDS Gain +6 dB CDS Gain Maximum Input Range Before Saturation 0 dB CDS Gain −3 dB CDS Gain +6 dB CDS Gain Maximum CCD Black Pixel Amplitude 0 dB CDS Gain +6 dB CDS Gain VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain (VGA Code 15) Maximum Gain (VGA Code 1023) Test Conditions/Comments Input characteristics definition 1 Typ Max Unit 0.5 1.2 V −2.95 5.90 9.15 11.60 −3.45 6.40 9.65 12.10 dB dB dB dB VGA gain = 6 dB (Code 15, default value) −2.45 5.40 8.65 11.10 Default setting Default setting 1.0 1.4 0.5 Positive offset definition1 Default setting −100 −50 V p-p V p-p V p-p +200 +100 1024 Guaranteed See Figure 13 for VGA curve See Variable Gain Amplifier (VGA) section for VGA gain equation BLACK LEVEL CLAMP MEASURED AT ADC OUTPUT Clamp Level Resolution Clamp Level Minimum Clamp Level (Code 0) Maximum Clamp Level (Code 1023) ADC Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 15) Maximum Gain (VGA Code 1023) Peak Nonlinearity, 1 V Input Signal Total Output Noise Power Supply Rejection (PSR) mV mV Steps 6.0 42.0 dB dB 2048 Steps 0 511 LSB LSB Measured at ADC output 12 −1.0 Bits LSB ±0.5 Guaranteed 2.0 V 2.0 1.0 V V Specifications include entire signal chain 6 dB total gain (default CDS, VGA) 5.4 41.4 6 dB total gain (default CDS, VGA) AC grounded input, 6 dB total gain Measured with step change on supply Input signal characteristics are defined as shown in Figure 2. 500mV TYP RESET TRANSIENT 100mV TYP OPTICAL BLACK PIXEL 1V TYP INPUT SIGNAL RANGE Figure 2. Rev. C | Page 4 of 20 07608-002 1 Min 5.9 41.9 0.1 0.8 45 6.4 42.4 dB dB % LSB rms dB ADDI7100 TIMING SPECIFICATIONS CL = 20 pF, fSAMP = 45 MHz, unless otherwise noted. See Figure 3, Figure 4, and Figure 16. Table 4. Parameter SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period DATACLK High/Low Pulse Width SHP Pulse Width SHD Pulse Width CLPOB Pulse Width 1 SHP Rising Edge to SHD Falling Edge SHP Rising Edge to SHD Rising Edge SHD Rising Edge to SHP Rising Edge SHD Rising Edge to SHP Falling Edge Internal Clock Delay DATA OUTPUTS Output Delay Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency (Must Not Exceed Pixel Rate) SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Rising Edge to SDATA Valid Hold 1 Symbol Min tCONV tADC tSHP tSHD 22 9 2 tS3 tS1 tS2 tS4 tID 9 9 tOD fSCLK tLS tLH tDS tDH Typ Max 11 5.5 5.5 20 5.5 11 11 5.5 4 Unit tCONV − tS2 tCONV − tS1 15 15 ns ns ns ns Pixels ns ns ns ns ns ns Cycles 40 10 10 10 10 MHz ns ns ns ns Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Timing Diagrams CCD SIGNAL (CCDIN) PIXEL N tID PIXEL N+1 PIXEL N+2 PIXEL N + 14 PIXEL N + 15 tID SHP tS4 tS3 tS1 tS2 tCONV SHD DATACLK tOD N – 15 N – 14 N – 13 NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING (ACTIVE) EDGE IS NEAR THE SHP OR SHD RISING (ACTIVE) EDGE. THE BEST LOCATION FOR LOWEST NOISE WILL BE SYSTEM DEPENDENT. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. Figure 3. CCD Sampling Timing (Default Polarity Settings) Rev. C | Page 5 of 20 N–1 N 07608-012 OUTPUT DATA ADDI7100 EFFECTIVE PIXELS OPTICAL BLACK PIXELS HORIZONTAL BLANKING DUMMY PIXELS EFFECTIVE PIXELS CCD SIGNAL (CCDIN) CLPOB ACTIVE PBLK ACTIVE EFFECTIVE PIXEL DATA OB PIXEL DATA NOTES 1. CLPOB AND PBLK SHOULD BE ALIGNED WITH THE CCD SIGNAL INPUT (CCDIN). CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB. 2. PBLK SIGNAL IS OPTIONAL. KEEP THE PBLK PIN IN THE INACTIVE STATE IF NOT USED. 3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS FIFTEEN DATACLK CYCLES. Figure 4. Typical Clamp Timing (Default Polarity Settings) Rev. C | Page 6 of 20 DUMMY BLACK EFFECTIVE DATA 07608-013 OUTPUT DATA ADDI7100 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter AVDD to AVSS DVDD to DVSS DRVDD to DRVSS Digital Outputs to DRVSS SHP, SHD, DATACLK to DVSS CLPOB, PBLK to DVSS SCK, SL, SDATA to DVSS REFT, REFB, CCDIN to AVSS Junction Temperature Lead Temperature (10 sec) θJA is specified for a device with the exposed bottom pad soldered to the circuit board ground. Rating −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to DRVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to AVDD + 0.3 V 150°C 300°C Table 6. Thermal Resistance Package Type 32-Lead LFCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. C | Page 7 of 20 θJA 27.7 Unit °C/W ADDI7100 32 31 30 29 28 27 26 25 D1 D0 NC NC VD SCK SDATA SL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADDI7100 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 REFB REFT CCDIN AVSS AVDD SHD SHP CLPOB NOTES 1. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED TO THE GROUND PLANE OF THE PCB. 2. NC = NO CONNECT. 07608-003 D10 D11 DRVDD DRVSS DVDD DATACLK DVSS PBLK 9 10 11 12 13 14 15 16 D2 D3 D4 D5 D6 D7 D8 D9 Figure 5. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 to 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic D2 to D11 DRVDD DRVSS DVDD DATACLK DVSS PBLK CLPOB SHP SHD AVDD AVSS CCDIN REFT REFB SL SDATA SCK VD Type 1 DO P P P DI P DI DI DI DI P P AI AO AO DI DI DI DI 29, 30 31, 32 NC D0, D1 NC DO 1 Description Digital Data Outputs. Digital Output Driver Supply. Digital Output Driver Ground. Digital Supply. Digital Data Output Latch Clock. Digital Supply Ground. Preblanking Clock Input. Black Level Clamp Clock Input. CDS Sampling Clock for CCD Reference Level. CDS Sampling Clock for CCD Data Level. Analog Supply. Analog Ground. Analog Input for CCD Signal. ADC Top Reference Voltage Decoupling. ADC Bottom Reference Voltage Decoupling. Serial Digital Interface Load Pulse. Serial Digital Interface Data Input. Serial Digital Interface Clock Input. Vertical Sync Input. Controls the update time of VD-updated registers. If this pin is not needed, it should be tied to GND. Not Internally Connected. Digital Data Output. AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect. Rev. C | Page 8 of 20 ADDI7100 TYPICAL PERFORMANCE CHARACTERISTICS 3 200 180 2 160 3.0V 120 0 INL (LSB) POWER (mW) 1 3.6V 140 100 2.7V 80 –1 –2 60 –3 40 10 22 36 45 SAMPLE RATE (MHz) –5 07608-018 0 1 523 262 1045 1567 2089 2611 3133 3655 784 1306 1828 2350 2872 3394 3916 CODE Figure 8. Typical INL Performance Figure 6. Power vs. Sample Rate 0.5 0.4 0.3 0.2 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 1 539 270 808 1077 1615 2153 2691 3229 3767 1346 1884 2422 2960 3498 4036 CODE 07608-016 DNL (LSB) 0.1 Figure 7. Typical DNL Performance Rev. C | Page 9 of 20 07608-017 –4 20 ADDI7100 EQUIVALENT INPUT CIRCUITS DVDD DVSS AVSS Figure 11. CCDIN (Pin 22) Figure 9. Digital Inputs SHP, SHD, DATACLK, CLPOB, PBLK, SCK, SL, SDATA, and VD DVDD DRVDD DATA THREESTATE DRVSS 07608-005 D[0:11] DVSS AVSS 07608-006 60Ω 330Ω 07608-004 INPUT AVDD Figure 10. Data Outputs Rev. C | Page 10 of 20 ADDI7100 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Power Supply Rejection (PSR) PSR is measured with a step change applied to the supply pins. This represents a very high frequency disturbance on the power supply of the ADDI7100. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the ADDI7100 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level that is 1.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always gained appropriately to fill the full-scale range of the ADC. Internal Delay for SHP/SHD The internal delay (also called aperture delay) is the time delay that occurs from the time a sampling edge is applied to the ADDI7100 until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high; therefore, the internal delay is measured from the rising edge of each clock to the instant that the actual internal sample is taken. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSBs and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2N codes) where N is the bit resolution of the ADC. For example, 1 LSB of the ADDI7100 is 0.5 mV. Rev. C | Page 11 of 20 ADDI7100 CIRCUIT DESCRIPTION AND OPERATION DC RESTORE DATACLK 0.1µF PBLK DCBYP –3dB, 0dB, +3dB, +6dB CCDIN INTERNAL VREF 6dB TO 42dB 2V FULL SCALE VGA CDS DATA OUTPUT LATCH 12-BIT ADC SHP 10 DAC 12 CLPOB OPTICAL BLACK CLAMP DOUT D0 TO D11 PBLK CLPOB SHD DIGITAL FILTERING VGA GAIN REGISTER 11 BLANK TO ZERO OR CLAMP LEVEL CLAMP LEVEL REGISTER 07608-010 SHP Figure 12. CCD Mode Block Diagram The ADDI7100 signal processing chain is shown in Figure 12. Each processing step is essential for achieving a high quality image from the raw CCD pixel data. DC RESTORE To reduce the large dc offset of the CCD output signal, a dc restore circuit is used with an external 0.1 μF series coupling capacitor. This circuit restores the dc level of the CCD signal to approximately 1.5 V, which is compatible with the 3 V supply of the ADDI7100. CORRELATED DOUBLE SAMPLER (CDS) The CDS circuit samples each CCD pixel twice to extract video information and to reject low frequency noise. The timing shown in Figure 3 illustrates how the two CDS clocks, SHP and SHD, are used to sample the reference level and the data level, respectively, of the CCD signal. The CCD signal is sampled on the rising edges of SHP and SHD. Placement of these two clock signals is critical for achieving the best performance from the CCD. An internal SHP/SHD delay (tID) of 4 ns is caused by internal propagation delays. OPTICAL BLACK CLAMP The optical black clamp loop removes residual offsets in the signal chain and tracks low frequency variations in the CCD black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with the fixed black level reference selected by the user in the clamp level register (Address 0x04). The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a DAC. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during postprocessing, optical black clamping for the ADDI7100 can be disabled using Address 0x00, Bit 2. When the optical black clamp loop is disabled, the clamp level register can still be used to provide programmable offset adjustment. Note that if the CLPOB is disabled, higher VGA gain settings reduce the dynamic range because the uncorrected offset in the signal path is amplified. Horizontal timing is shown in Figure 4. Align the CLPOB pulse with the optical black pixels of the CCD. It is recommended that the CLPOB pulse be used during valid CCD dark pixels. It is recommended that the CLPOB pulse should be 20 pixels wide to minimize clamp noise. Shorter pulse widths can be used, but the ability of the loop to track low frequency variations in the black level is reduced. Rev. C | Page 12 of 20 ADDI7100 ANALOG-TO-DIGITAL CONVERTER (ADC) DIGITAL DATA OUTPUTS The ADDI7100 uses a high performance ADC architecture optimized for high speed and low power. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB. The ADC uses a 2 V full-scale input range. By default, the digital output data is latched by the rising edge of the DATACLK input. Output data timing is shown in Figure 3. It is also possible to make the output data latch transparent, immediately validating the data outputs from the ADC. Setting the DOUTLATCH register (Address 0x01[5]) to 1 configures the latch as transparent. The data outputs can also be disabled by setting the DOUT_OFF register (Address 0x01[4]) to 1. VARIABLE GAIN AMPLIFIER (VGA) The VGA stage provides a gain range of 6 dB to 42 dB, programmable with 10-bit resolution through the serial digital interface. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. A plot of the VGA gain curve is shown in Figure 13. VGA Gain (dB) = (VGA Code × 0.0358 dB) + 5.4 dB where Code is in the range of 0 to 1023. 42 30 24 18 12 6 0 127 255 383 511 639 767 VGA GAIN REGISTER MODE 895 1023 07608-011 VGA GAIN (dB) 36 Figure 13. VGA Gain Curve Rev. C | Page 13 of 20 ADDI7100 APPLICATIONS INFORMATION processed by the image processing ASIC. The internal registers of the ADDI7100—used to control gain, offset level, and other functions—are programmed by the ASIC or by a microprocessor through a 3-wire serial digital interface. A system timing generator provides the clock signals for both the CCD and the AFE (see Figure 14). The ADDI7100 is a complete analog front-end (AFE) product for digital still camera and camcorder applications. As shown in Figure 14, the CCD image (pixel) data is buffered and sent to the ADDI7100 analog input through a series input capacitor. The ADDI7100 performs the dc restoration, CDS sampling, gain adjustment, black level correction, and analog-to-digital conversion. The digital output data of the ADDI7100 is then ADDI7100 CCD VOUT ADCOUT 0.1µF CCDIN REGISTER DATA BUFFER DIGITAL OUTPUTS DIGITAL IMAGE PROCESSING ASIC SERIAL INTERFACE CDS/CLAMP TIMING V-DRIVER CCD TIMING 07608-014 TIMING GENERATOR Figure 14. System Applications Diagram 3 SERIAL INTERFACE SL SCK VD NC D1 NC D0 SDATA VD OUTPUT FROM ASIC/DSP (SHOULD BE GROUNDED IF NOT USED.) 32 31 30 29 28 27 26 25 D2 1 D3 2 D4 3 D5 4 ADDI7100 D6 5 TOP VIEW (Not to Scale) PIN 1 IDENTIFIER 24 REFB 1.0µF 23 REFT 1.0µF 22 CCDIN 21 AVSS 20 AVDD 19 SHD D7 6 D8 7 18 SHP D9 8 17 CLPOB 0.1µF CCDIN 3V ANALOG SUPPLY 0.1µF PBLK DVSS DATACLK DVDD DRVSS D11 12 5 CLOCK INPUTS 3V ANALOG SUPPLY 3V DRIVER SUPPLY 0.1µF 0.1µF NC = NO CONNECT (NOT INTERNALLY CONNECTED, MAY BE TIED TO GROUND OR LEFT FLOATING). Figure 15. Recommended Circuit Configuration for CCD Mode Rev. C | Page 14 of 20 07608-015 DATA OUTPUTS DRVDD D10 9 10 11 12 13 14 15 16 ADDI7100 INITIAL POWER-ON SEQUENCE After power-on, the ADDI7100 automatically resets all internal registers to default values. Settling of the internal voltage reference takes approximately 1 ms to complete. During this time, normal clock signals and serial write operations can take place, but valid output data do not occur until the reference is fully settled. When loading the desired register settings, the STARTUP register (Address 0x05[1:0]) must be set to 0x3. GROUNDING AND DECOUPLING RECOMMENDATIONS As shown in Figure 15, a single ground plane is recommended for the ADDI7100. This ground plane should be as continuous as possible to ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. Place all decoupling capacitors as close as possible to the package pins. A single clean power supply is recommended for the ADDI7100, but a separate digital driver supply can be used for DRVDD (Pin 11). Always decouple DRVDD to DRVSS (Pin 12), which should be connected to the analog ground plane. The advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing digital power dissipation and potential noise coupling. If the digital outputs must drive a load larger than 20 pF, buffering is the recommended method to reduce digital code transition noise. Alternatively, placing series resistors close to the digital output pins may also help to reduce noise. Note that the exposed pad on the bottom of the package should be soldered to the ground plane of the printed circuit board. Rev. C | Page 15 of 20 ADDI7100 SERIAL INTERFACE TIMING Figure 17 shows a more efficient way to write to the registers, using the ADDI7100 address autoincrement capability. Using this method, the lowest desired address is written first, followed by multiple 16-bit data-words. Each data-word is automatically written to the address of the next highest register. By eliminating the need to write each address, faster register loading is achieved. Continuous write operations can start with any register location. All ADDI7100 internal registers are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 16-bit data-word. Both the address and the data-word are written starting with the LSB. To write to each register, a 24-bit operation is required, as shown in Figure 16. Although many data-words are fewer than 16 bits wide, all 16 bits must be written for each register. For example, if the data-word is only eight bits wide, the upper eight bits are don’t care bits and must be filled with zeros during the serial write operation. If fewer than 16 data bits are written, the register is not updated with new data. 8-BIT ADDRESS A0 SDATA A1 A2 A4 A3 tDS SCK 1 2 16-BIT DATA A5 A6 A7 D0 D1 D2 D3 D13 D14 D15 tDH 3 4 5 6 7 8 9 10 11 12 22 tLS 23 24 tLH NOTES 1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS. 2. ALL 24 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 16 BITS FOR DATA. 3. IF THE REGISTER LENGTH IS LESS THAN 16 BITS, THEN ZEROS MUST BE USED TO COMPLETE THE 16-BIT DATA LENGTH. 4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE PARTICULAR REGISTER WRITTEN TO. 07608-019 SL Figure 16. Serial Write Operation DATA FOR STARTING REGISTER ADDRESS SDATA SCK A0 1 A1 2 A2 3 A3 4 A6 7 A7 8 D0 9 D1 10 D14 23 DATA FOR NEXT REGISTER ADDRESS D15 24 D0 25 D1 D14 26 39 D15 40 D0 41 D1 42 D2 43 NOTES 1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY. 2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS. 3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN). 4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. Figure 17. Continuous Serial Write Operation Rev. C | Page 16 of 20 07608-020 SL ADDI7100 COMPLETE REGISTER LISTING Note that when an address contains fewer than 16 data bits, all remaining bits must be written as zeros. Table 8. AFE Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Data Bits [1:0] Default Value 0 Update Type 1 SCK [2] 0x1 CLAMP_EN [3] 0 FASTCLAMP [4] 0 FASTUPDATE [5] 0 PBLK_LVL [6] 0 DCBYP [8:7] [10:9] [0] 0x2 0x2 0 Test Test SHPD_POL [1] 0 DATACLK_POL [2] 0 CLP_POL [3] 0 PBLK_POL [4] 0 DOUT_OFF [5] 0 DOUTLATCH [6] [2:0] 0 0x1 [9:0] [10:0] [1:0] [3:2] [2:0] [3] [5:4] [0] [11:0] [11:0] [0] [0] [0] 0x0F 0x1EC 0 0 0x6 0 0 0 0xFFF 0xFFF 0 0 0x1 SCK SCK/VD SCK/VD SCK/VD SCK SCK SCK SCK SCK SCK SCK SCK Name STANDBY GRAY_EN CDSGAIN VGAGAIN CLAMPLEVEL STARTUP Test Test Test Test Test Test Test Test SW_RST OUTCONTROL Description 00: normal operation 01: reference standby 10: full standby 11: full standby 1: enable black clamp 0: disable black clamp 0: normal CLPOB settling 1: faster CLPOB settling 1: enable very fast clamping when CDS gain is changed 0: ignore CDS gain updates 0: blank to 0 1: blank to clamp level 0: normal dc restore operation 1: dc restore disabled during PBLK active Test use only; must be set to 2 Test use only; must be set to 2 0: rising edge sample 1: falling edge sample 0: rising edge triggered 1: falling edge triggered 0: active low 1: active high 0: active low 1: active high 0: data outputs are driven 1: data outputs are disabled (high-Z) 0: retime data outputs with output latch (using DATACLK) 1: do not retime data outputs; output latch is transparent 1: gray encode ADC outputs CDS gain setting: 0x0: −3 dB 0x1: 0 dB 0x2: +3 dB 0x3: +6 dB VGA gain, 6 dB to 42 dB (0.0358 dB per step) Optical black clamp level, 0 LSB to 511 LSB (0.25 LSB per step) Must be set to 0x3 after power-up Test use only; must be set to 0 Test use only; must be set to 6 Test use only; must be set to 0 Test use only; must be set to 0 Test use only; must be set to 0 Test use only; must be set to 0xFFF Test use only; must be set to 0xFFF Test use only; must be set to 0 1: software reset; automatically resets to 0 after software reset Data output control: 0: make all outputs dc inactive 1: enable data outputs Rev. C | Page 17 of 20 ADDI7100 Address 0x0D Data Bits [0] Default Value 0 Update Type 1 SCK Name VD_POL 0x0E [6:0] 0 SCK REG_UPDATE 0xFF [0] 0 SCK Test 1 Description 0: falling edge triggered 1: rising edge triggered Set the appropriate bits high to enable VD update of the selected registers: [0]: CDSGAIN (Register 0x02) [1]: VGAGAIN (Register 0x03) [2]: CLAMPLEVEL (Register 0x04) [3]: test use only; must be set to 0 [4]: test use only; must be set to 0 [5]: test use only; must be set to 0 [6]: test use only; must be set to 0 Test use only; do not access SCK = register is immediately updated when the 16th data bit (D15) is written. VD = register is updated at the VD falling edge. Rev. C | Page 18 of 20 ADDI7100 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX 17 16 0.80 MAX 0.65 TYP 0.30 0.23 0.18 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 011708-A TOP VIEW 1.00 0.85 0.80 PIN 1 INDICATOR 32 25 24 Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADDI7100BCPZ ADDI7100BCPZRL 1 Temperature Range −25°C to +85°C −25°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. Rev. C | Page 19 of 20 Package Option CP-32-2 CP-32-2 ADDI7100 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07608-0-6/10(C) Rev. C | Page 20 of 20