Product Selector Guide 2010 CHINA ROHS EU ROHS About PhaseLink Leading Edge in Mixed Signal Technology PhaseLink is the world leader in high performance Frequency Generation and Signal Conditioning Timing Source ICs for the Communications, Consumer, and Storage Network markets. PhaseLink has developed many of the world’s ‘first to market’ products, such as Analog Frequency Multipliers (AFM), Industry’s first CMOS ‘balanced oscillator’ with practically no jitter or phase noise deterioration, and PicoPLL, world’s smallest and lowest power programmable clocks, and the world’s first 3-PLL with variable voltage on each clock output. Applied Expertise Our expertise resides in analog intensive mixed signal integrated circuits for low-jitter and phase noise frequency synthesis, multiplication, and conditioning circuits. Through our proprietary technology, we provide unequalled performance in frequency multiplication for optical, Gigabit Ethernet, and telecommunication networks as well as the world’s smallest foot-print and lowest power programmable clocks. Our constant efforts for improvement, innovation, and simplification have enabled us to deliver the highest quality and reliability products with an affordable price. Flexibility and Methodology Through our advanced design, manufacturing and packaging capabilities, coupled with our responsiveness to shifting market trends and customer demands, we have established a track record of producing high-performance, low-cost products, in an expedited manner. Our worldwide manufacturing information system ensures on-time delivery of products to our customers, while maintaining ISO 9001 and ISO14001 certification. Contents Featured Products 4 5 6-17 Analog Frequency Multiplier (AFM) PhasorVI Frequency Multiplier PicoPLL Programmable Clocks Frequency Generation Voltage Controlled Frequency Source (VCXO ICs) 22-23 24-25 26-27 VCXO with PhasorVI Frequency Multiplier IC VCXOs with & without PLL Multiplier VCXO with Analog Frequency Multiplier IC Reference Frequency Clock (XO ICs) 28-29 30-31 22-23 26-27 Crystal Oscillator (XO) ICs Programmable Clocks with Differential Outputs PhasorVI Frequency Multiplier Clocks Analog Frequency Multiplier Clocks PicoPLL - Programmable Clocks 6-21 Programmable Clocks 30-31 Programmable Clocks with Differential Outputs 32-33 Programmable PCIe/HCSL Compatible Clocks Signal Conditioning 18-21 EMI Reduction ICs Clock Distribution 34-35 32-33 32-33 32-33 34-35 Zero Delay Buffers Reference Input Fanout Buffers Crystal Input Fanout Buffers TCXO Buffers Translator Buffers Featured Product Featured Product < 500fs Phase Jitter (12KHz to 20MHz), @ 622MHz < 30ps PK-PK Period Jitter < 50fs Phase Jitter (12KHz to 20MHz), @ 622MHz < 2.5ps RMS Period Jitter < 30ps PK-PK Period Jitter 0 20 -10.6dBc @ 1Hz -51.3dBc @ 10Hz -83.5dBc @ 100Hz -113.7dBc @ 1KHz -133.4dBc @ 10KHz -144.0dBc @ 100KHz -150.3dBc @ 1MHz -154.9dBc @ 10MHz 20 40 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) 0 60 80 38 fs RMS for 12KHz ~ 20MHz @ 622.08MHz 100 60 80 100 120 140 160 120 1 10 100 1K 10K 100K 1M 10M L(f) [dBc/Hz] vs f [Hz] Practically, No Accumulated Jitter 140 160 40 10 100 1K 10K 100K 1M 10M PhasorVI Long Term Jitter 100M (Crystal=38.88MHZ, Output=155.52MHz) Industry’s first CMOS Non-PLL multiplier utilizing analog multiplication of a high frequency fundamental or 3rd overtone crystal input. Our patented AFM technology can generate up to 800MHz in PECL, LVDS or CMOS without using a Phase-Locked Loop. This is achieved with practically no jitter or phase noise deterioration. See page 28 for detailed product selector guide. RMS Jitter (ps) L(f) [dBc/Hz] vs f [Hz] Interval (us) See page 22 for detailed product selector guide. 100M Featured Product Tiny Package, Big Benefits ! World’s Smallest Programmable Clock Applications Unlimited ! Lowest Power Consumption 1.8V, 2.5V, 3.3V Supply 30~70ps Peak-Peak Jitter Fast Turnaround with Factory Programming Unit: mm TSSOP 16 6.4X5 12.3X SOP8 6X5 11.5X MSOP 10 4.9X3 5.7X QFN 3X3 3X3 3.5X 3X3 3.5X 1.3X2 Device Family # of PLLs Input (MHz) # of Outputs Voltage Package PL611s 1 Crystal: 10-50 Ref Clock: 0.01-200 Up to 2 1.62V~ 3.63V DFN, SOT-6 PL613 3 Crystal: 10-50 Ref Clock: 5-200 Up to 8 1.62V~ 3.63V QFN 3x3, (T)SSOP PL613-21 3 Crystal: 10-40 Ref Clock: 5-200 Up to 4 with varying voltage on each output 1.62V~ 3.63V QFN 3x3, (T)SSOP PL671 1 Crystal: 10-40 Ref Clock: 1-200 Up to 3 2.25V~ 3.63V SOT-23, (M)SOP PL585/685 1 PECL, LVDS, CMOS 3.3V (T)SSOP 1X PhaseLink’s PicoPLL programmable clock family is a general purpose frequency synthesizer with the key features of low jitter, low power and tiny package. This low cost frequency source solution is designed to fit almost any application where high performance, space saving and time to market is crucial. EMI √ Crystal: 19-40 Programming Box Available Contact PhaseLink for Programming box support Programmable Clocks PicoPLL is PhaseLink’s line of programmable, high performance clock ICs. Accepting a single reduce system cost and fit almost any application where high performance, low-power, space FEATURES (PL613-21) crystal or reference clock input and producing up to 8 outputs, the PicoPLL family is designed to saving, cost sensitivity, and time-to-market are crucial. APPLICATION EXAMPLES • 3-programmable PLLs, with individual Power Down (PDB) pins o One 32.768K Clock and 3 pins with ‘MHz’ range Clock outputs • 4 outputs with individual voltage on each output o Covers from 1.62V to 3.63V • Small form-factor for PCB Space Savings • Ultra Low-Power Consumption o Ultra-Low Power-Down Mode, <5µA • Input Frequency: o Fundamental Crystal: 10MHz to 40MHz o Reference Input: 10MHz to 200MHz • Active Low or Hi-Z Disabled Output State • Operating Temperature Ranges: o Commercial: 0°C to 70°C o Industrial: -40°C to 85°C • Power supply voltages: 1.62V to 3.63V • Available in GREEN/RoHS Compliant 3x3 QFN-16 Package Smartphone PL613 takes advantage of the available TCXO reference clock to four required system clocks for a typical Smartphone application. CLK1 32 .768kHz FM Tuner CLK2 27MHz Video Decoder CLK3 54MHz MPEG CLK4 48MHz USB 19.20MHz TCXO PD_1 PD_23 PL613-21 Package : 3x3 QFN-16 PD_4 PD pins disable CLK outputs and corresponding PLL for maximum power savings BLOCK DIAGRAM FREF XIN/FIN XOUT Xtal Osc FREF PLL1 VCO1 5-bit ÷ Odd/Even ÷ 1,2,4,8 CLK2 VDD2_3* CLK3 FREF PLL2 PDB2_3 PDB1 PDB4 VCO2 15-bit ÷ Odd/Even CLK1 VDD1* Portable Navigation Device (PND) PL613-21 takes advantage of the available TCXO reference clock to create three required system clocks for a typical PND application. 16.369 MHz TCXO PD_1 PD_23 PLL3 Programmable Function VCO3 5-bit ÷ Odd/Even * Separate buffer VDD’s allow output level control (1.8V ~ 3.3V, ±10%) CLK4 VDD4* PD_4 PL613-21 Package: 3x3 QFN-16 CLK1 32.768 kHz FM Tuner CLK2 12MHz USB CLK4 26MHz Apps. Processor PD pins disable CLK outputs and corresponding PLL for maximum power savings Programmable Clocks PhaseLink’s extensive arrays of programmable clock families allow selection from a wide Part Number Input (MHz) # of PLLs Xtal Range Reference Output (MHz) # of Outputs Voltage(V) 1.8 2.5 3.3 UltraLow Power variety of features and form-factors to suit most demanding design requirements. Programmable Pin PDB OE FSEL CLK Other Features Package MHz to MHz Clocks PL611s-02 PL611s-04 1 10 - 40 1 - 200 200 2 • World's smallest programmable clock Die, Wafer, DFN-6L, SOT23-6L PL611s-27 1 - 1 - 200 125 2 • 2 CLKs & PDB/OE DFN-6L, SOT23-6L PL611s-6X PL611-01 PL611-30 PL611-31 1 1 1 1 10 - 40 10 - 30 10 - 30 10 - 30 1 - 200 1 - 200 1 - 200 200 200 400 200 1 3 3 3 • By 4/8 multiplier • 3 output multiplier PLL Die, Wafer Die, Wafer, SOT23-6L • Complementary LVCMOS Outputs MSOP-8L, SOP-8L PL613-01 3 10 - 40 5 - 200 200 8 • Master OE/PDB • 4 Clocks with 4 OE QFN-16L, (T)SSOP-16L PL613-05 3 10 - 40 5 - 200 200 3 • Master OE/PDB SOP-8L QFN-16L(3x3mm) PL613-21 3 10 - 40 5 - 200 125 4 • Variable Voltage on Each Output • Individual CLK/PLL Power-Down pins • KHz outputs on CLK1 EMI Reduction Clocks PL671-01 1 10 - 40 1-200 200 3 • SS Rate: ±0.125%~±2.0% (Center), or -0.25% ~-4.0% (Down) SOT23-6L , MSOP-8L, SOP-8L PL671-02 1 - 1-200 200 3 • Contact PhaseLink for Cross Ref. List SOT23-6L - .01 - 200 65 2 • 32.768KHz input to MHz output. (Ideal for USB Clock) Die, Wafer .0325768 • 0.3mA from MHZ to 32K clock out Die, Wafer • Low-power MHz to RTC clock DFN-6L, SOT-6 kHz to MHz Clocks PL611s-17 1 MHz to kHz Clocks PL610-32 0 16.67772 - PL611s-18 1 10 - 40 1 - 200 PL611s-19 1 - DC - 200 PL613-21 3 10 - 40 5 - 200 125 Yes 725 0.5kHz125 0.5kHz125 1 2 • Ideal for Two Outputs, One a LowPower 32K Clock, With Ref. Input • Variable Voltage on Each Output • Individual CLK/PLL Power-Down pins • KHz output on CLK1 2 4 High Performance Clocks PL585/685XX 10 1 19 - 40 LVPECL LVDS LVCMOS N/A • 0.5 ps phase jitter at 622.08MHz • 90 mA (PECL) Power Consumption DFN-6L, SOT-23-6L QFN-16L(3x3mm) TSSOP-16L 11 Backplane SERDES PHY 25MHz 25MHz 25MHz PL613 -01 33MHz PCI 33MHz (optional) 4X3.125 Gbps XAUI Serial Links HDTV Controller 10-12 Gbps Links Links MAC SERDES NPU/ ASIC PL685 PL613 OPTICs 12 Switch MAC Marvell 5180 CPU 25MHz PL685 Memory Crossbar Switch Cards Backplane 3.125-12 Gbps Backplane Serial Links Application Examples Audio Serializer 54.1MHz Sleep Mode uc 24MHz USB PHY 25MHz Ethernet PHY 4MHz 7.3428MHz PL613 -01 25MHz 13 Application Examples The PL613-01’s multiple PLLs and frequency generator circuitry provides all the clocking requirements for the complex Optical Networking systems, in a small form-factor package. PL685-28 SGMII Link PL685-28 TSSOP-16 2.5~3.3V MPC8313 Spartan 6 FPGA PL685-XX 33MHz 133.33MHz 19.44MHz PL613 -01 155.52MHz CLK PMC Sierra PAS6201/11 CLKB 125MHz 12.8MHz PL610-D71 25MHz 25MHz 25MHz PL611S-02 19.44MHz 25MHz Cortina 8212 Cortina 8212 GPN Interface PL611s-17 DFN-6 RTC/ASIC REF 32.768KHz PDB 1.8V 48MHz USB PHY CLK PL611S-02-F10 25MHz 14 125MHz Broadlight BL2348R 32.768KHz 15 Application Examples PL611s-02 PL611s-18 SOT-23 CKIH 611s-18 1.8~3.3V 32.768KHz 02 PL611s-02 DNF-6 26MHz CKIL Freescale Multimedia Processor i.MX21/31 Bluetooth Module REF GPIO (2 x 1.3 x 0.6mm) 24.576MHz PDB 16.667MHz USB PHY 16 PL671-02 16.667MHz uController CLK 2.5-3.3V PL611s-02 DFN-6 CLK 19 PL611s-02 DNF-6 PLL500-17 (VCXO) SOT-23 66.66MHz ±1% SST 66.66MHz ±1% SST 66.66MHz ±1% SST VCON 2.5-3.3V PL500-17 48MHz 49.152MHz Audio DSP 24.576MHz 26MHz 2.5-3.3V 1.8~3.3V Memory 27MHz MPEG 27MHz FSEL 74.125MHz/ 74.1758MHz DVI Link 17 Pico-EMI Clock Summary PhaseLink’s proprietary Spread Spectrum Timing (SST) technology can efficiently suppress ICs with very low cycle to cycle jitter (100ps Peak-Peak) are suitable for clock generation FEATURES (PL671-01) • • • • • • • • • • APPLICATION EXAMPLES Advanced programmable PLL with Spread Spectrum with up to 3 outputs Crystal or Reference Clock input o Fundamental crystal: 10MHz to 40MHz o Reference input: 1MHz to 200MHz Four programmed configurations to select from (CSEL) Output frequency range: ≤166MHz @ 2.5V operation ≤200MHz @ 3.3V operation Programmable Spread Spectrum Modulation Magnitude: o Center Spread: ±0.125% to ±2.0% in ±0.125% steps o Down Spread: -0.25% to -4.0% in 0.25% steps Spread Spectrum On/Off selection Low Cycle to Cycle jitter. Programmable output drive (4mA, 8mA, 16mA) Single 2.5V to 3.3V, ± 10% power supply Operating temperature range from -40°C to 85°C Available in 8-pin SOP, MSOP and 6-pin SOT GREEN/RoHS compliant packaging BLOCK DIAGRAM PhaseLink’s PL671 PicoEMI Programmable Spread Spectrum Clock Generator (PSSCG) can generate multiple clocks to reduce EMI emission. 16.667MHz 2.5-3.3V 48MHz USB PHY 2.5-3.3V PL611s-02 DNF-6 16.667MHz uController CLK 66.66MHz ±1% SST 66.66MHz ±1% SST 66.66MHz ±1% SST Memory Note: ^ Denotes 60KΩ Pull-up resistor Application Example: Using Reference CLK to Generate SST Processor CLK SST Modulation XIN/FIN Xtal Osc XOUT PDB CLK[0:2] CSEL[0:1] SST On/Off FREF R-Counter 9-bits Programming Logic Modulation Magnitude* * Optional Pre-defined Modulation Magnitude Control Programmable Function 18 Printer PL671-02 • • EMI without requiring expensive enclosures or system redesign. These EMI reduction from a single crystal or a signal reference. M-Counter 11-bits ÷8 ÷8 PDB Phase Detector Charge Pump Loop Filter VCO GND Processor Clock PL671 1MHz to 200 MHz Ref Input FVCO = FREF * (M/R) CSEL VDD SOT23-6L P-Counter FOUT = FVCO / P 6-bits Odd/Even CLK1/PDB CLK0 /1, /2 /1, /2, /4 CLK2/CSEL0 CSEL1 1 0 CLK0 33MHz, ±1.0% 66MHz, ±2.0% 19 EMI Reduction ICs PhaseLink’s PicoEMI PL671 Programmable Spread Spectrum Clocks provide the flexibility Features -01A Input (MHz) Crystal: 10-40 Ref: 10-40 Output (MHz) Selectable Spread Spectrum Magnitude -01B -01C Ref: -01D 30-150 -1.0% -2.0% -3.0% OFF ± 0.25% ± 0.50% ± 1.00% OFF Part Number -0.5% -1.0% -2.0% OFF Xtal: 10-40 PL671-00 PL671-02 Ref.:1-200 Programmable PLL PL671-01 PL671-02 Input (MHz) Crys tal: 10-40 Ref: 1-200 Output (MHz) Programmable up to 200MHz # of outputs Up to 21 Reference: 1-200 Fixed Selectable Power Down Yes 1 1: Pin 1 can be configured as PDB input or CLK output. 2: Factory Program: Center: ± 0.125~± 2.0% (+0.125% step) Down: -0.25~ -4.0% (-0.25 step), or OFF PL671-01 Input (MHz) Crys tal: 10-40 or Ref : 1-200 Output (MHz) Programmable up to 200MHz # of outputs Up to 3 1 Spread Spectrum Up to 4 Fixed Selectable Magnitude 2 Yes1 1: Pin 2,6 can be configured as CLK output. 2: Factory Program: Center: ± 0.125~± 2.0% (+0.125% step) Down: -0.25~ -4.0% (-0.25% step), or OFF 20 Ref.:1-200 ≤ 200 ≤ 200 ≤ 200 Other Features Voltage SS Rate: ±0.125%~ ±2.0% (C ) or -0.25%~ -4.0% (D) 2.25V~ 3.63V SS Rate: ±0.125%~ ±2.0% (C) or -0.25%~ -4.0% (D) 2.25V~ 3.63V Package SOT23-6L MSOP-8L SOP-8L Die, Wafer SOT23-6L SOT23-6L MSOP-8L SOP-8L Die, Wafer Note: C: Center Spread. D: Down Spread. General SS spread is at .25% increments. Please refer to the datasheet for more detail Application Example: Selectable Frequency Video System Clock, using the CSEL Feature, or Adding Spread to DVI Video 27MHz XIN/FIN PDB^ CSEL1^ XOUT PL671 GND MSOP-8L VDD SST _Pixel _CLK SI 1160 CSEL0^ Pixel_CLK 27MHz/54MHz/ 108MHz Video Clock CSEL0 CSEL1 Drive Strength CLK0 8mA 27MHz, SST Off 1 1 0 8mA 1 27MHz, ±1.0% 16mA 54MHz, ±1.0% 0 1 16mA 0 108MHz, ±1.0% 0 CLK0 GND CLK1 PL671-02 Features Power Down 200 Output (MHz) Up to 21 Spread Spectrum Fixed Magnitude2 Yes1 Ref: Xtal: 10-40 PL671-29 Features Input (MHz) Function PL671-01 CLK0 = FIN X 1 ± 0.5% ± 1.0% ± 1.5% OFF and performance required for the most demanding EMI reduction requirements ^ CSEL0 VDD SOT23-6L 15MHz to 200MHz Switching Ref Input CSEL0 1 0 CLK 0 Input Frequency, ±1.0% Input Frequency, ±2.0% CLK 1 Ref Out Ref Out 21 PhasorVI Frequency Multiplier The PhasorVI is a low jitter and low phase noise frequency multiplier, capable of achieving 0.5ps Using a low-cost crystal of 19 to 40MHz, the PhasorVI enables output frequencies of up to 800MHz, LVDS, and LVPECL outputs. RMS phase jitter and less than 30ps peak to peak period jitter, with practically no Accumulated Jitter. in a single IC, with specific frequencies above 800MHz in discrete ICs. The family supports CMOS, VCXO FEATURES • <500fs RMS phase jitter (12kHz to 20MHz) at 622.08MHz (LVPECL/LVDS) • 30ps max peak to peak period jitter • < 90mA @622MHz PECL output Jitter(PS) - Typical Output Range (MHz)) Output Type PL585-88 19 to 40 PL585-89 725 LVPECL (-88) LVDS (-89) PL585-48 19 to 40 PL585-49 360 PL585-27 19 to 40 PL585-08 75-100 Part Number • Ultra Low-Power Consumption Input Range (MHz) Voltage Peak to Peak Period Jitter Phase Jitter (12kHz to 20MHz) 3.3V 5 <30 <0.5 DIE/Wafer TSSOP-16 LVPECL (-48) LVDS (-49) 3.3V 5 <30 <0.5 DIE/Wafer TSSOP-16 180 LVCMOS (-27) 3.3V 5 <30 <0.5 DIE/Wafer TSSOP-16 75-175 LVPECL 3.3V 2 <22 <0.15 DIE/Wafer TSSOP-16 • <15µA at Power Down (PDB) Mode • Input Frequency: • Fundamental Crystal: 19MHz to 40MHz • Output Frequency: • 19MHz to 800MHz output. • Output types: LVPECL, LVDS, or LVCMOS,. • High Linearity VCXO: <10% linearity • Pullability: ±150 ppm • Programmable OE input polarity, о Programmable Hi-Z or Active Low disabled state Package RMS Period • Power Supply: 3.3V, ±10% • Operating Temperature Ranges: XO • Commercial: 0°C to 70°C • Industrial: -40°C to 85°C Jitter(PS) - Typical • Available in Die or Wafer Output Range (MHz) ) Output Type Voltage PL685-88 19 to 40 PL685-89 725 LVPECL (-88) LVDS (-89) PL685-48 19 to 40 PL685-49 360 PL685-27 19 to 40 180 Part Number Input Range (MHz) Peak to Peak Period Jitter Phase Jitter (12kHz to 20MHz) 3.3V 5 <30 <0.5 DIE/Wafer TSSOP-16 LVPECL (-48) LVDS (-49) 3.3V 5 <30 <0.5 DIE/Wafer TSSOP-16 LVCMOS (-27) 3.3V 6 <30 <0.5 DIE/Wafer TSSOP-16 PhasorVI BLOCK DIAGRAM OE/PDB (Default pre-programmed output path ) XIN/REF XOUT Xtal Osc VCON Varicap PD/CP LF – HF LCVCOs Q Pre-scalar 4/6 /2 N Div (5 bit) 22 Package RMS Period QB P Div (4 bit) /2 23 VCXO (Voltage Controlled Crystal Oscillator) ICs PhaseLink’s integrated low phase noise VCXO products provide cost efficient solutions with high packaged ICs, or die form. Our products meet performance requirements of SONET, ADSL, VDSL, MULTIPLIER AND NON MULTIPLIER VCXO ICS FEATURES (PLL502-3X) • • • • • • • • • 750kHz to 800MHz output range. Low phase noise output • -127dBc/Hz for 155.52MHz @ 10kHz offset • -115dBc/Hz for 622.08MHz @ 10kHz offset Selectable LVCMOS, LVPECL or LVDS output. Selectable High Drive or Standard Drive LVCMOS. 12MHz to 25MHz crystal input. No external load capacitor or varicap required. Output Enable selector. Wide pull range (±200ppm) Single 3.3V, ±10% power supply Part Number PLL502-30 BLOCK DIAGRAM VCON XIN XOUT SEL[3:0] Varicap Xtal Osc Reference Divider VCO Divider Phase Detector linearity, wide pull-range, and very high temperature stability. They are available in small form factor video, and many more applications. Charge Pump + Loop Filter QB VCO Q Function Input (MHz) Multiplier Output Output Type Pull Range (MHz) (ppm) Voltage Package PL500-15 PL500-16 PL500-17 VCXO 17 - 36 N/A 1 - 36 LVCMOS ±200 Die, Wafer 2.5V, 3.3V SOT23-6 SOP-8 PL500-37 VCXO 36 - 130 N/A 36 - 130 LVCMOS ±150 2.5V, 3.3V Die, Wafer SOP-8 PL520-20 VCXO 120 - 200 N/A 120 - 200 LVCMOS LVPECL LVDS ±110 3.3V Die, Wafer PL520-30 VCXO 65 - 130 N/A 32.5 - 30 LVPECL LVDS ±120 2.5V, 3.3V Die, Wafer PL520-80 VCXO 19 - 65 N/A 9.5 - 65 LVPECL LVDS ±200 2.5V, 3.3V Die, Wafer PL502-00 VCXO+PL 12 - 25 1,2,4,8 12 - 200 LVCMOS ±200 3.3V Die, Wafer PL502-02 VCXO+PL 12 - 25 2 24 - 50 LVCMOS ±200 3.3V SOP-8 PL502-03 VCXO+PL 12 - 25 4 48 - 100 LVCMOS ±200 3.3V SOP-8 PL502-04 VCXO+PL 12 - 25 8 96 - 200 LVCMOS ±200 3.3V SOP-8 PL502-11 VCXO+PL 12 - 25 8 96 - 200 LVPECL ±200 3.3V TSSOP-16 ±200 3.3V Die, Wafer PL502-30 VCXO+PL 12 - 25 16 to x32 0.75 - 800 LVCMOS LVPECL LVDS PL502-37 PL502-35/38 PL502-39 VCXO+PL 12 - 25 16 to x32 0.75 - 800 LVCMOS LVPECL LVDS ±200 3.3V QFN-16, 3x3 TSSOP-16 PL520-00 VCXO+PL 100 - 200 1,2,4,8 LVCMOS LVPECL LVDS ±110 3.3V Die, Wafer 100 - 800 OE 24 25 Analog Frequency (non-PLL) Multiplier (AFM) PhaseLink’s Analog Frequency Multiplier products offer the world’s lowest phase noise and jitter of most cost efficient clocking solutions for high performance applications. The AFM ICs are designed and high speed networking LAN applications. VCXO ICs (AFM) FEATURES • • • • • • • • • • • • any multiplier clock IC, without the use of a PLL. Analog Frequency Multiplier products provide the to surpass the most stringent performance requirements of telecommunications, storage networking, Non-PLL frequency multiplication Input frequency from 30-200 MHz Output frequency from 60-800 MHz World’s best phase noise and jitter performance (equivalent to fundamental crystal at the output frequency) Ultra-low jitter o RMS phase jitter < 0.25 ps (12kHz-20MHz) o RMS period jitter < 2.5 ps Low phase noise o -142 dBc/Hz @100kHz offset from 155.52 MHz o -150 dBc/Hz @10MHz offset from 155.52 MHz High linearity pull range (typ. 5%) +/- 120 PPM pullability VCXO Differential output levels (PECL, LVDS), or single-ended CMOS Single 3.3V, ±10% power supply Temperature range (-40˚C to +85˚C) Available in 16-pin Green/RoHS compliant TSSOP, and 3x3 QFN packages Jitter (PS) - Typical Part Number Input Range (MHz) Output Range (MHz) Output Type Voltage PL565-08 75 - 200 300 - 800 (4X) LVPECL (-08) PL560-08 PL560-09 75 - 200 300 - 800 (4X) PL560-37 PL560-38 PL560-39 30 - 80 PL560-47 PL560-48 PL560-49 PL560-68 PL560-69 RMS Period Peak to Peak Period Phase Jitter (12kHz to 20MHz) 3.3V 4 25 0.05 @ 622MHz LVPECL (-08) LVDS (-09) 3.3V 4 25 0.1 120 - 320 (2X) LVCMOS (-37) LVPECL (-38) LVDS (-39) 3.3V 2.5 25 0.25 30 - 80 60 - 160 (2X) LVCMOS (-47) LVPECL (-48) LVDS (-49) 3.3V 2.5 18 0.25 30 - 80 60 - 160 (2X) LVPECL (-48) LVDS (-49) 3.3V 2.5 18 0.18 XO ICs (AFM) Jitter (PS) - Typical Part Number Input Range (MHz) Output Range (MHz) Output Type Voltage PL663-18 75 - 140 150 to 280 (2X) PECL (-18) LVDS (-19) PL663-28 PL663-29 140 - 160 280 to 320 (2X) PECL (-28) LVDS (-29) RMS Period Peak to Peak Period Phase Jitter (12kHz to) 20MHz) 3.3V 2.5 18 0.14 @212M 3.3V 2.5 18 0.13 @311M 2x AFM Phase Noise at 311.04MHz 26 27 Crystal Oscillator (XO) ICs PhaseLink’s crystal oscillator ICs provide the best level of negative impedance, lowest jitter, and them suitable for all types of applications, including low-current, low-jitter, low-phase noise system CRYSTAL OSCILLATOR (XO) ICS FEATURES (PL610-01/03) • • • • • • • • Part Number Single die, wide frequency coverage, programmable advanced oscillator design. Single IC to cover up to 130MHz output frequency. Direct oscillation operation with optional programmable features: o ±50ppm Frequency Tuning o Output Drive Setting (4, 8, or 16mA) o 6-bit Odd/Even Output Divider (≤ ÷63) Input Frequency: Fundamental crystal: o 10MHz to 60MHz (Default) o 60MHz to 130MHz (programming option) Output Frequency: LVCMOS o 160kHz to 130MHz. Very low-Jitter and Phase Noise Low current consumption Operating temperature range from -40˚C to 85˚C XOUT XTAL OSC P-Counter FREF (PDB) Programmable CLoad Programmable Function OE XIN/FIN XOUT 28 Phase Comparator XTAL OSC VCO Divider Charge Pump Loop Filter Output Type Voltage 10 - 130 0.16 - 130 LVCMOS 1.8V to 3.3V Die, Wafer DFN-6 SOT23-6 10 - 60 2.5 - 60 LVCMOS 1.8V to 3.3V Wafer Package PL610-32 MHz to KHz Clock IC 16.777 .032768 LVCMOS 1.8V to 3.3V Die, Wafer DFN-6 SOT23-6 PL611s-64 PL611s-68 Fixed Multiplier IC (x4 , x8 ) 10 - 25 40-200 LVCMOS 1.8V to 3.3V Die, Wafer PL600-27T XO 10 - 52 10 - 52 3-LVCMOS PL620-20 XO 100 - 200 100 - 200 LVPECL, LVDS Die, Wafer PL620-30 XO 65 - 130 32.5 - 130 PL620-80 XO 19 - 65 9.5 - 65 LVPECL, LVDS (selectable %2) LVCMOS, LVPECL, LVDS (selectable %2) 1.8V to 3.3V 3.3V 2.5V to 3.3V 3.3V Die, Wafer Part Number BLOCK DIAGRAM OF PL 602-XX MULTIPLIER , FOR PCIe/HCSL OUTPUT Reference Divider Output (MHz) SOP-8 Die, Wafer GENERAL PURPOSE PLL MULTIPLIER CLOCKS OE, PDB, CLK1 /1, 2 Input (MHz) PL610-61 PL610-62 PL610-63 PL610-03 CLK0 (6-bit) Function XO With Programmable CLoad, Output Dividers Smallest non Programmable XO(÷1, ÷2, ÷4) PL610-01 BLOCK DIAGRAM OF ALL PROGRAMMABLE PL610 DEVICES XIN/FIN lowest phase noise up to 200MHz. Our best in class buffer outputs (LVCMOS, LVDS, LVPECL) make clock reference, and for replacing ceramic based SMD modules. Q VCO QB Function Input (MHz) Output (MHz) Output Type Voltage Package PL602-00 XO+PL 12 - 25 12 - 200 LVCMOS 3.3V Die, Wafer PL602-03 XO+PL 12 - 25 48 - 100 LVCMOS 3.3V SOP-8 PL602-04 XO+PL 96 - 200 12 - 200 LVCMOS 3.3V SOP-8 Diff. CMOS/HCSL LVCMOS, LVPECL, LVDS 3.3V SOT-6 SOP-8 3.3V Die, Wafer 3.3V QFN-16, 3x TSSOP-16 3.3V Die, Wafer PL602-2X XO+PL 25 25, 100, 125, 200, 250 PL602-30 XO+PL 12 - 25 0.75 - 800 PL602-37 PL602-38 PL602-39 XO+PL 12 - 25 0.75 - 800 PL620-00 XO+PL 100 - 200 100 - 800 PL620-20 XO 100 - 200 100 - 200 PL620-30 XO 65 - 130 32.5 - 130 PL620-80 XO 19 - 65 9.5 - 65 LVCMOS (-37) LVPECL (-38) LVDS (-39) LVCMOS LVPECL, LVDS LVPECL, LVDS LVPECL, LVDS (selectable %2) 3.3V Die, Wafer 3.3V Die, Wafer 3.3V Die, Wafer 29 Programmable Clock with Differential Output PhaseLink’s PL611-30 is world’s first programmable clock that is capable of offering differential PL611-30 offers the best performance for applications requiring performance, space savings, PECL, LVDS, and CMOS outputs. Housed in a small 6-pin SOT package or in an 8-pin SOP, differential outputs, at an affordable price. FEATURES (PL611-30) • • • • • • • • • Advanced programmable PLL design Very low Jitter and Phase Noise (< 40ps Pk-Pk typ.) Supports complementary LVCMOS outputs to drive LVPECL and LVDS inputs. Output Frequencies: o ≤ 400MHz at 3.3V o ≤ 350MHz at 2.5V Input Frequencies: o Fundamental Crystal: 10MHz - 30MHz o 3RD overtone Crystal: Up to 75MHz o Reference Input: 1MHz to 200MHz Accepts <1.0V reference signal input voltage One programmable I/O pin can be configured as Output Enable (OE) input, Frequency Selection (FSEL) input or Reference Clock (CLK2) output. Single 2.5V or 3.3V ± 10% power supply Operating temperature range from -40˚C to 85˚C Features -31A -31B -31C -31D Crystal Input (MHz) Ref Input (MHz) - 27 - 27 27 27 27 27 PK-PK Jitter <50ps Selectable Output Frequency (MHz) via FSEL input Package Type 148.50000 148.35164 SOT6 74.25000 74.17582 SOP8 SOT6 SOP8 PL611-30/31 BLOCK DIAGRAM XIN/FIN XTAL Osc XOUT FREF R-Counter (8-bit) M-Counter (11-bit) OE CLoad Programming Logic FSEL Programmable Function 30 Phase Detector Charge Pump Loop Filter VCO P-Counter (5-bit) Input Logic Control CLK [0:1] OE, FSEL, CLK2 For PECL input For LVDS Input R1 = 130 ohm R2 = 82 ohm R3 = 130 ohm R1 = 360 ohm R2 = 82 ohm R3 = 130 ohm Notes: 1. Place R1 as close to the CMOS outputs as possible 2. Place R2 and R3 as close to the PECL/LVDS Inputs as possible 31 HCSL Compatible Clock Generator for PCI Express PhaseLink’s PL602-2X is the smallest, high performance, lowest power differential output clock at 100MHz, with a very low jitter (2 ps TIE RMS), making it ideal for HCSL applications requiring any given input, or you can select for standard HCSL frequencies. FEATURES • • • • • • • • Input Frequency: o Fundamental Crystal: 10-30MHz o Reference Input: ≤200MHz Output Frequency: ≤200MHz Very low Jitter: 28ps Pk-Pk typ. Very low Phase Noise: o -130 dBc at 10kHz offset at 100MHz Very low Jitter: 28ps Pk-Pk typ. Very low Phase Noise: o -130 dBc at 10kHz offset at 100MHz No external loop filter is required Power supply range: 2.25V to 3.63V Operating temperature range from -40°C to 85°C Available in 6-pin SOT or 8-pin SOP Green/RoHS compliant package. Power supply range: 2.25V to 3.63V Operating temperature range from -40°C to 85°C Available in 6-pin SOT or 8-pin SOP Green/RoHS compliant package. CLK1 GND FIN Part Number M-Counter - PD - CP - LF VCO GND OE CLK0 CLK1 DNC VDD Input (MHz) PL602-23 Output (MHz) Crystal Reference 10-30 ≤200 ≤200 25 100 25 125 25 200 PL602-22 P-Counter OE SOP-8L PL602-21 OE R-Counter VDD XOUT FREQUENCY OPTIONS BLOCK DIAGRAM of Programmable PL602-20, for PCIe/HCSL OUTPUT Xtal OSC XIN SOT23-6L PL602-20 (Programmable) XIN, FIN XOUT CLK0 PL602-2x • • PIN CONFIGURATION PL602-2x • • • IC available for HCSL timing applications. PhaseLink’s PL602-2X offers -130dBc at 10kHz offset small size and low power. PL602-2X family offers fully programmable output frequencies for 25 PL602-26 25 25 PL602-27 25 250 Q QB Programmable Function 32 33 Clock Distribution PhaseLink’s clock distribution products consist of zero delay buffers, TCXO fanout buffers, crystal or reference input fan out buffers, and translator buffers. These general purpose buffer products will reproduce a master clock frequency up to 1GHz with low skew between the outputs. Our zero delay buffers use a phase locked loop to ensure zero-delay between the outputs and the master signal. Zero Delay Buffers Part Number PL123-05(H) PL123S-05(H) PL123E-05(H) PL123-09(H) PL123S-09(H) PL123E-09(H) # of Outputs 5 9 FEATURES PL102-10 • • Non PLL Buffers • • PLL REF Mux PL135-27 2.25V, 3.63V SOP-8 (H): High Drive Buffer (S): Spread Spectrum Ready CMOS (E): High Speed Enhanced (H): High Drive Buffer (S): Spread Spectrum Ready CMOS (E): High Speed Enhanced High Performance, LowCMOS skew 2.25V, 3.63V TSSOP-16 2.25V, 3.63V SOT-23-6 SOP-8 Output Type Voltage Package Description 10 - 40 Crystal input fan out buffer CMOS 1.62V ~ 3.63V DFN PL135-37 3 10 - 40 Crystal input with 1-OE pin CMOS 1.62V ~ 3.63V SOT23-6 PL135-47 4 10 - 40 Crystal input with 4-OE pins CMOS PL135-57 5 10 - 40 Crystal input with PDB CMOS PL135-67 6 10 - 40 Crystal input with 2-OE pins CMOS 1.62V ~ 3.63V QFN3x3-16 Tssop-16 CLKOUT PL133-27 2 DC - 150 Clock input fan out buffer CMOS 1.62V ~ 3.63V DFN CLKA1 PL133-37 3 DC - 150 Crystal input with 1-OE pin CMOS 1.62V ~ 3.63V SOT23-6 PL133-47 4 1 - 150 Crystal input with 4-OE pins CMOS PL135-57 5 10 - 40 Crystal input with PDB CMOS PL133-67 6 1 - 150 Crystal input with 2-OE pins CMOS Translator Buffers Input Output (MHz) 2.5V, 3.3V QFN3x3-16 - AC coupled input (min. 100mV swing) - 200MHz CMOS Output 2.5V, 3.3V SOP-8 QFN3x3-16 - AC coupled input (min. 100mV swing) - PECL (-08), LVDS (-09) 2.5V, 3.3V SOP-8 QFN3x3-16 Function CLKB2 PL130-05 Translator 1MHz - 1.0 GHz to PECL - AC coupled input (min. 100mV swing) - 1GHz PECL Output PL130-07 Translator to CMOS PL130-08 PL130-09 Translator to PECL 1MHz - 1.0 GHz 1MHz - 200 1.62V ~ 3.63V QFN3x3-16 Tssop-16 QFN3x3-16 1.62V ~ 3.63V Tssop-16 QFN3x3-16 1.62V ~ 3.63V Tssop-16 Package Part Number CLKB3 QFN3x3-16 1.62V ~ 3.63V Tssop-16 1.62V ~ 3.63V QFN3x3-16 Tssop-16 Operating Voltage CLKB1 CLKB4 34 1 Package 2 Bank B (PL 123-09 Only ) PL138-17 Voltage DFN-6L >0.1VPP 1.62V ~ 3.63V SOT-6L CLKA4 S2 Input/Output Output Type 1 - 100 CLKA3 Selector Inputs 15-170 Description - Sine/clipped sine wave input, Square wave output, with 1-OE pin CLKA2 S1 3 # of Outputs Part Number Bank A • • Frequency Range 10MHz to 134 MHz Output Options: o 5 outputs PL123-05 o 9 outputs PL123-09 Zero input - output delay Optional Drive Strength: Standard (8mA) PL123-05/-09 High (12mA) PL123-05H/-09H Single 3.3V ±10% power supply Available in Commercial and Industrial temperature ranges Input/Output (MHz) 10-134 10-134 10-220 10-134 10-134 10-220 Description/Output Type 35 2880 Zanker Road San Jose, CA 95134 + 1.408-571-1668 + 1.408-571-1688 2010