PL671-33 PicoEMI T M Programmable Spread Spectrum Clock FEATURES DESCRIPTION • Advanced programmable PLL with Spread Spectrum • Crystal or Reference Clock input o Fundamental Crystal input: 10MHz-40MHz o Reference Clock input: 1MHz-200MHz • Accepts ≥0.1V reference signal input voltage • Output Frequency Range: up to 166MHz @ 2.5V or up to 200MHz @ 3.3V operation • Up to 2 Programmable outputs • Programmable Spread Spectrum Modulation Magnitude: o Center Spread: ±0.125% to ±2.0% in ±0.125% steps o Down Spread: -0.25% to -4.0% in 0.25% steps • Programmable Output Drive (4mA, 8mA, 16mA) • Low Cycle to Cycle jitter. • Single 2.5V ~ 3.3V, ± 10% power supply • Operating temperature range from -40°C to 85°C • Available in 8-pin (M)SOP GREEN/RoHS compliant packaging. The PL671-33 is an advanced programmable Spread Spectrum clock generator (PSSCG), and a member of PhaseLink’s PicoPLL™ Programmable Clock family. The PL671-33 offers up to two 200MHz outputs, and allows for programming the modulation type (Center or Down Spread) as well as 16 modulation magnitudes (±0.125% to ±2.0% or -0.25% to -4.0%). The PL671-33’s frequency modulation greatly reduces the fundamental and harmonic frequencies’ peak magnitude, therefore reducing the system level Electro Magnetic Interference (EMI), by as much as 20dB. In addition, the Power Down (PDB) feature allows the IC to draw <10µA of when enabled. PIN CONFIGURATION Note: ^ Denotes 60KΩ Pull-up resistor BLOCK DIAGRAM Programming Logic 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 1 PL671-33 PicoEMI T M Programmable Spread Spectrum Clock PACKAGE PIN ASSIGNMENT Name (M)SOP-8L Pin # Type XIN, FIN 1 I Crystal or Reference input pin VDD 2 P VDD connection (2.25~3.63V) GND 3 P GND connection CLK0 4 O Programmable Clock Output with spread spectrum. NC 5, 7 - No Connect. Not connected internally This pin can be programmed to function as PDB (input) or CLK1 (output). Power Down (PDB) input. This pin has an internal 60KJ pull up resistor and turns off the oscillator and the output when pulled to logic “0”. PDB, CLK1 (Programmable) 6 I/O XOUT 8 O Description PDB Logic Osc PLL Output 0 Off Off Hi Z (Default) 1 Normal Operation (Default) Clock1 (CLK1) output. This optional clock can be set to F REF , F REF /2 or F OUT (Programmable PLL output). Crystal output pin. Do Not Connect when using FIN. KEY PROGRAMMING PARAMETERS CLK[ 0:1 ] Output Frequency FOUT = FREF * M / (R * P) where M =11 bit R = 9 bit P = 6 bit • CLK0= FREF, FREF/2 or FVCO/P • CLK1= FREF, FREF/2 or FVCO/P SST Modulation Magnitude (Spread Percentage) 16 programmable modulation magnitudes to choose from: Programmable Input/Output Output Drive Strength Programmable I/O’s include: Three optional drive strengths to choose from: • PDB – input • Center Spread: ±0.125% to • CLK[0:1] - output ±2.0% in ±0.125% steps • Down Spread: -0.25% to -4.0% in 0.25% steps • Low: 4mA • Std: 8mA (default) • High: 16mA ‘P’ is a 6-bit Odd/Even divider. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 2 PL671-33 PicoEMI T M Programmable Spread Spectrum Clock FUNCTIONAL DESCRIPTION The PL671-33 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower Spread Spectrum modulation applications. The PL671-33 accepts a fundamental input crystal of 10MHz to 40MHz or a reference clock input of 1MHz to 200MHz and is capable of producing two SST modulated outputs up to 200MHz This flexible design allows the PL671-33 to deliver any PLL generated frequency, F REF (Crystal or Ref Clk) frequency or F REF /2 to CLK0 and/or CLK1. Some of the design features of the PL671-33 are mentioned below. PLL Programming Clock Outputs (CLK[0:]) The PLL in the PL671-33 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 6-bit post VCO Odd/Even divider (PCounter). The output frequency is determined by the following formula [F OUT = (F REF * 2M)/(R*P). CLK0 is the main clock output. The PL671-33 can also be programmed with an additional clock output, CLK1. The outputs of CLK[0:1] can be configured as described below: Modulation Magnitude and Type The PL671-33 provides the following programmable capabilities for Modulation Type and Modulation Magnitude (Spread Percentage): Modulation Type Modulation Magnitude Programming Steps Center Spread ±0.125% thru ±2.00% ±0.125% Down Spread -0.25% thru -4.00% 0.25% Modulation Rate The PL671-33 modulation rate is defined as F REF (Crystal or Ref Clk Frequency) divided by 8 times the R-counter, i.e. Modulation Rate = (F REF / 8*R). The rate can be changed by choosing alternate R-Counter settings. • CLK0= FREF, FREF/2 or FVCO/P* • CLK1= FREF, FREF/2 or FVCO/P* Where F REF - Reference (Crystal or Ref Clk) Frequency FOUT = FREF * M / (R * P) The output drive level of each output can be independently programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The output frequency can be programmed up to 200MHz at 3.3V (166MHz at 2.5V). Power-Down Control (PDB) When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <10µA of power. The PDB input incorporates a 60kJ pull up resistor giving a default condition of logic “1”. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 3 PL671-33 PicoEMI T M Programmable Spread Spectrum Clock LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces (>1 inch) as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Multiple VDD pins should be decoupled separately for best performance. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1µF for designs using frequencies < 50MHz and 0.01µF for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20 50 line Series Resistor Use value to match output buffer impedance to 50 trace. Typical value 30 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 4 PL671-33 PicoEMI T M Programmable Spread Spectrum Clock ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 4.6 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V 260 °C Supply Voltage Range Soldering Temperature 10 Data Retention @ 85°C Storage Temperature TS Ambient Operating Temperature* Year -65 150 °C -40 85 °C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. AC SPECIFICATIONS PARAMETERS CONDITIONS Crystal Input Frequency(XIN) Fundamental Crystal Input (FIN) Frequency Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude Output Frequency @ V DD =3.3V @ V DD =2.5V Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz @ V DD =3.3V MIN. TYP. 10 MAX. UNITS 40 MHz 200 1 166 MHz 0.9 V DD Vpp 0.1 V DD Vpp 200 MHz 166 MHz @ V DD =2.5V Settling Time At power-up (after V DD increases over 2.25V) 2 ms Output Enable Time PDB Function; Ta=25º C, 15pF Load 2 ms Output Rise Time Output Fall Time Duty Cycle Cycle to Cycle Jitter* 15pF Load, 10/90% V DD , Standard Drive 2.0 3.0 ns 15pF Load, 10/90% V DD , High Drive 1.2 1.7 ns 15pF Load, 90/10% V DD , Standard Drive 2.0 3.0 ns 15pF Load, 90/10% V DD , High Drive 1.2 1.7 ns 50 55 % 100 ps At V DD /2 T CYC - CYC Over output frequency range @ 3.3V 45 * Note: Jitter performance depends on the programming parameters. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 5 PL671-33 PicoEMI T M Programmable Spread Spectrum Clock DC SPECIFICATIONS PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs I DD Operating Voltage V DD CONDITIONS MIN. TYP. MAX. UNITS At 25MHz, 3.3V, load=15pF, (PDB=1) 15 mA PDB=0 10 µA 3.63 V 100 ms 0.4 V 2.25 Power Supply Ramp t PU Time for V DD to reach 90% V DD . Power ramp must be monotonic. Output Low Voltage V OL I OL = +4mA (Std. Drive) Output High Voltage V OH I OH = -4mA (Std. Drive) V DD – 0.4 V Output Current, Low Drive I OSD V OL = 0.4V, V OH = 2.4V 4 mA Output Current, Standard Drive I OSD V OL = 0.4V, V OH = 2.4V 8 mA Output Current, High Drive I OHD V OL = 0.4V, V OH = 2.4V 16 mA CRYSTAL SPECIFICATIONS PARAMETERS Fundamental Crystal Resonator Frequency Crystal Loading Rating SYMBOL MIN. F XIN 10 C L (xtal) TYP. 40 MHz pF 100 Operating Drive Level Small SMD Crystal UNITS 15 Maximum Sustainable Drive Level Metal Can Crystal MAX. 30 Shunt Capacitance ESR Max Shunt Capacitance ESR Max µW µW C0 5.5 pF ESR 50 J C0 2.5 pF ESR 80 J 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 6 PL671-33 PicoEMI T M Programmable Spread Spectrum Clock PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) MSOP 8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. --1.10 0.05 0.15 0.81 0.91 0.25 0.40 0.13 0.23 2.90 3.10 2.90 3.10 4.90 BSC 0.445 0.648 0.65 BSC E H D A2 A A1 C e L b SOP 8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C e b L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 7 PL671-33 PicoEMI T M Programmable Spread Spectrum Clock ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part Number, Package Type and Operating Temperature Range PL671-33-XXX X X-R NONE= TUBE R=TAPE and REEL PART NUMBER 3 DIGIT ID Code * TEMPERATURE C=COMMERCIAL I = INDUSTRIAL PACKAGE TYPE M=MSOP-8L S=SOP-8L * PhaseLink will assign a unique 3-digit ID code for each approved programmed part number. Part/Order Number Package Option PL671-33-XXXMC FDXXX 8-Pin MSOP Tube PL671-33-XXXMC-R FDXXX P671-33 XXX P671-33 XXX 8-Pin MSOP (Tape and Reel) PL671-33-XXXSC PL671-33-XXXSC-R † Marking† 8-Pin SOP Tube 8-Pin SOP (Tape and Reel) Note: ‘XXX’ designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales representative for marking information. PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/2/08 Page 8