19MHz to 800MHz Low Phase-Noise XO

ie
(Preliminary)
19MHz to 800MHz Low Phase-Noise XO
FEATURES










< 0.5ps RMS phase jitter (12kHz to 20MHz) at
622.08MHz
30ps max peak to peak period jitter
Ultra Low-Power Consumption
о < 90 mA @622MHz PECL output
о <10A at Power Down (PDB) Mode
Input Frequency:
о Fundamental Crystal: 19MHz to 44MHz
Output Frequency:
о 19MHz to 800MHz output.
Output types: PECL.
Programmable OE input polarity selection.
Power Supply: 3.3V, ±10%
Operating Temperature Ranges:
о Commercial: 0C to 70C
о Industrial: -40C to 85C
Available in Die or Wafer
PIN CONFIGURATION
XIN
1
16
XOUT
DNC
2
15
VDDANA
DNC
3
14
VDDDIG
OE/PDB
4
13
VDDBUF
DNC
5
12
QB
GNDANA
6
11
VDDBUF
GNDDIG
7
10
Q
GNDBUF
8
9
DNC
TSSOP-16L
DESCRIPTION
The PL685 is a Dual LC core monolithic IC clock,
capable of maintaining sub-1ps RMS phase jitter,
while covering a wide frequency output range up to
800MHz, without the use of external components.
The high performance and high frequency output is
achieved using a low cost fundamental crystal of
between 19MHz and 44 MHz. The PL685 family is
designed to address the demanding requirements of
high performance applications such Fiber Channel,
serial ATA, Ethernet, SAN, SONET/SDH, etc.
OUTPUT ENABLE CONTROL
OE Select
(Programmable)
0
1 (Default)
OE
State
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
BLOCK DIAGRAM
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 09/16/11
Page 1
ie
(Preliminary)
19MHz to 800MHz Low Phase-Noise XO
PIN ASSIGNMENT
Name
Pin #
Type
Description
XIN
1
I
Crystal input connection.
DNC
2, 3, 5, 9
-
OE/PDB
4
I
GND_ANA
6
P
Do Not Connect.
This pin may be programmed as output enable (OE), or power-down
(PDB) pin. This pin incorporates an Internal pull-up resistor of 60KΩ
for OE, and PDB, operations.
GND connection for analog circuitry.
GND_DIG
7
P
GND connection for digital circuitry.
GND_BUF
8
P
GND connection for buffer circuitry.
Q
10
O
True Output buffer.
QB
12
O
Complementary Output buffer.
VDD_BUF
11, 13
P
VDD connection for buffer circuitry.
VDD_DIG
14
P
VDD connection for digital circuitry.
VDD_ANA
15
P
VDD connection for analog circuitry.
XOUT
16
P
Output connection to crystal.
OPTION SELECTION TABLE
PL685 is a fully programmable clock IC. However, for ordering convenience, the following part numbers have
been created for when simple multiplication is used, for your convenience. When other features of the IC are
exercised (i.e. reverse polarity on OE, power down, etc.), another 3-digit code is used to identify the functionality.
Input Crystal
Frequency Range (MHz)
33.750000 ~ 40.000000
33.333333 ~ 42.187500
32.142857 ~ 38.095238
33.333333 ~ 37.500000
33.750000 ~ 40.000000
33.333333 ~ 42.187500
32.142857 ~ 38.095238
33.333333 ~ 37.500000
33.750000 ~ 40.000000
33.333333 ~ 42.187500
32.142857 ~ 38.095238
33.333333 ~ 37.500000
33.750000 ~ 40.000000
32.812500 ~ 42.187500
Multiplication
Factor
X20
X16
X14
X12
X10
X8
X7
X6
X5
X4
X3.5
X3
X2.5
X2
Output Frequency Range (MHz)
Low Limit
High Limit
675.00
800.00
533.33
675.00
450.00
533.33
400.00
450.00
337.50
400.00
266.67
337.50
225.00
266.67
200.00
225.00
168.75
200.00
133.33
168.75
112.50
133.33
100.00
112.50
84.375
100.00
65.625
84.375
Part #
PL685-P8-020
PL685-P8-168
PL685-P8-148
PL685-P8-128
PL685-P8-108
PL685-P8-088
PL685-P8-078
PL685-P8-068
PL685-P8-058
PL685-P8-048
PL685-P8-358
PL685-P8-038
PL685-P8-258
PL685-P8-028
Common functionality for packaged parts in the above table:
 OE function active high polarity.

Crystal Cload is 12pF.
Please inform your Sales representative for active low OE functionality.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 09/16/11
Page 2
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(Preliminary)
19MHz to 800MHz Low Phase-Noise XO
FUNCTIONAL DESCRIPTION
PL685 family of products is an advanced,
programmable LCVCO clock IC that is designed to
meet the most stringent performance specifications
for phase noise, jitter, and power consumption.
There are two main types of VCOs, a) Ring
Oscillator, b) LC Tank oscillator. An LCVCO is made
up of LC tank oscillator. Although a Ring Oscillator
has very good performance, and has a good tuning
range, its phase noise and jitter performance, in
particular at higher frequencies, degrades.
On the other hand, an LCVCO has an outstanding
phase noise and jitter performance, even at higher
frequencies. PhaseLink’s PL685 family of products
takes advantage of this state of the art technology,
and incorporates the LC tank on-chip, for optimal
performance.
PL685 family exhibit very low phase noise/phase
jitter and peak to peak jitter, wide tuning range, and
very low-power. All members of the PL685 family
accept a low-cost fundamental crystal input of
19MHz to 44MHz or a reference clock input of up to
800MHz and its flexible core is capable of producing
any output frequency between 19MHz to 800MHz.
PLL Programming
The PLL in the PL685 family is fully programmable.
The PLL is equipped with a Prescaler to divide down
the VCO frequency, and a 5-bit VCO frequency
feedback loop divider (M-Counter). The output of the
PLL is transferred to a 4-bit post VCO divider (PCounter), to achieve the desired output frequency.
OE (Output Enable)
The OE pin in PL685 family, through programming,
can be configured to support OE pin activation with a
logic ‘1’ or logic ’0’, to provide you with the desired
enable polarity.
OE Select
(Programmable)
0
1 (Default)
OE
State
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
The OE pin incorporates a 60K Ω resistor to either
pull-up or pull-down to the default state when the OE
pin is left open.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 09/16/11
Page 3
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(Preliminary)
19MHz to 800MHz Low Phase-Noise XO
ELECTRICAL SPECIFICATIONS
1. ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
Supply Voltage
MIN
V DD
MAX
UNITS
4.6
V
Input Voltage, dc
VI
-0.5
V DD +0.5
V
Output Voltage, dc
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
C
Ambient Operating Temperature (industrial temperature)*
T AI
-40
85
C
Ambient Operating Temperature (commercial temperature)
T AC
0
70
C
Junction Temperature
TJ
125
C
ESD Protection, Machine Model
200
V
2
kV
ESD Protection, Human Body Model
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to
commercial grade only.
2. GENERAL ELECTRICAL SPECIFICATIONS
PARAMETERS
MAX
UNITS
LVPECL, 622.08MHz, 3.3V
90
mA
Supply Current, Dynamic
PDB Enabled
PDB = 0, 3.3V
10
uA
Output Enable Time
t OE
OE logic 0 to logic 1, Ta=25º C.
Add one clock period to this
measurement for a usable clock
output.
50
ns
Power Up Time
T PU
PDB logic 0 to logic 1, Ta=25º C
10
ms
Operating Voltage
V DD
LVPECL
2.97
3.63
V
Power Up Ramp Rate
t PU
0.1
100
ms
Auto-Calibration Time
t AC
10
ms
55
%
Supply Current, Dynamic
Output Clock Duty Cycle
SYMBOL
I DDQ
CONDITIONS
MIN
Time for V DD to reach 90% V DD .
Power ramp must be monotonic.
At power up
@ 50% of output waveform
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
45
www.phaselink.com
TYP
50
Rev 09/16/11
Page 4
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(Preliminary)
19MHz to 800MHz Low Phase-Noise XO
4. CRYSTAL SPECIFICATIONS
PARAMETERS
SYMBOL
CONDITIONS
MIN
Crystal Resonator Frequency
F XIN
Parallel Fundamental Mode
Crystal Cload
C L_Crystal
V DD = 3.3V, programmable
Shunt Capacitance
C 0_Crystal
Recommended ESR
RE
TYP
MAX
UNITS
19
44
MHz
8
12
pF
3.5
pF
AT cut , up to 40MHz
50
Ω
AT cut , up to 44MHz
45
Ω
MAX
UNITS
5. JITTER SPECIFICATIONS
PARAMETERS
FREQUENCY
CONDITIONS
MIN
TYP
RMS Phase Jitter
622.08MHz
12kHz to 20MHz, XIN=38.88MHz
0.5
ps
Period Jitter, Pk-to-Pk
622.08MHz
10K cycles, XIN=38.88MHz
30
ps
6. PHASE NOISE SPECIFICATIONS
PARAMETERS
Phase Noise, relative
to carrier (typical)
FREQUENCY
@10Hz
@100Hz
@1kHz
@10kHz
@100kHz
155.52MHz
-61
-90
-114
-123
-126
622.08MHz
-46
-77
-101
-111
-114
7. LVPECL OUTPUTS (Q, QB)
PARAMETERS
SYMBOL
Output High Voltage
V OH
Output Low Voltage
V OL
Output Frequency
Output Rise, Fall Times
Output Voltage Swing
F out
tr, tf
V pp
CONDITIONS
Q, QB
Standard LVPECL Termination,
V DD = 3.3V
3.3V
20% - 80% of output waveform
Q, QB
LVPECL Levels Test Circuit
UNITS
dBc/Hz
MIN
TYP
MAX
UNITS
2.275
2.350
2.420
V
1.490
1.600
1.680
V
300
800
800
500
930
MHz
ps
mV
Rev 09/16/11
Page 5
19
550
LVPECL Transistion Time Waveform
DUTY CYCLE
OUT
VDD
50?
2.0V
45 - 55%
55 - 45%
OUT
80%
50%
50?
20%
OUT
OUT
tR
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
tF
www.phaselink.com
ie
(Preliminary)
19MHz to 800MHz Low Phase-Noise XO
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
Decoupling and Power Supply Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the V DD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this
equals ringing!
- Multiple V DD pins should be decoupled separately
for best performance.
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing).
- Addition of a ferrite bead in series with V DD can
help prevent noise from other board sources
- Design long traces (<1 inch) as “striplines” or
“microstrips” with defined impedance.
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
- Match trace at one side to avoid reflections
bouncing back and forth.
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
TSSOP-16L
Symbol
A
A1
b
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.20
6.60
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
e
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
B
www.phaselink.com
L
Rev 09/16/11
Page 6
ie
(Preliminary)
19MHz to 800MHz Low Phase-Noise XO
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
2880 Zanker Road, San Jose, CA, USA
Tel: (408) 571-1668 Fax: (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type, Thickness and Operating temperature range
Part Number/Order Number
PL685-XX-XXXOC
PL685-XX-XXXOC-R
Marking †
P685-XX
XXX(I)
LLLLL
Package Option
16-Pin TSSOP (Tube)
16-Pin TSSOP (Tape and Reel)
†
Marking Notes:
1) The “I” after the 3 digit programming code will be marked for Industrial Temperature grade products only. Commercial
grade products will not have a character in this position.
2) LLLLL represents the production lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com
Rev 09/16/11
Page 7