PicoEMI Spread Spectrum Clock Generator

PicoEMI T M Spread Spectrum Clock Generator
FEATURES
PIN CONFIGURATION
 Advanced programmable PLL with Spread Spectrum
 Reference Clock input
o 1MHz to 200MHz
 Output Frequency
o <200MHz
 Two programmable I/O pins
o PDB for Power Down function
o CSEL for Configuration Select
o CLK1/CLK2 additional clock outputs
 Programmable Output Drive
 Low Cycle to Cycle jitter
 Single 2.5V or 3.3V ± 10% power supply
 Available in 6-pin SOT23 or Thin SOT (TSOT)
GREEN/RoHS compliant packaging .
Note: ^ Denotes 60kΩ Pull-up resistor
DESCRIPTION
The PL671-02 is an advanced Spread Spectrum clock generator (SSCG), and a member of PhaseLink’s
PicoPLL™ Programmable Clock family.
The PL671-02 offers up to three 200MHz outputs, and allows for programming the modulation type (Center or
Down Spread) as well as 16 modulation magnitudes (±0.125% to ±2.0% or -0.25% to -4.0%). In addition, the
CSEL pin can be used to toggle the device between 2 pre-programmed configurations. The option of being able
to turn ‘ON/OFF’ the Spread Spectrum modulation allows for completing a design with PL671-02 and having the
assurance of turning ‘ON’ the EMI modulation, if EMI becomes an issue. The PL671-02’s frequency modulation
greatly reduces the fundamental and harmonic frequencies’ peak magnitude, therefore reducing the system level
Electro Magnetic Interference (EMI), by as much as 20dB
BLOCK DIAGRAM
SST
Modulation
R-Counter
9-bits
Modulation Magnitude*
PDB
M-Counter
11-bits
÷8
÷8
Phase
Detector
Charge
Pump
Loop
Filter
VCO
FVCO = FREF * (M/R)
CLK[0:2]
CSEL
* Optional Pre-defined
Modulation Magnitude Control
Programmable Function
P-Counter
6-bits
Odd/Even
FOUT = FVCO / P
/1, /2
/1, /2, /4
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/24/09 Page 1
PicoEMI T M Spread Spectrum Clock Generator
KEY PROGRAMMING PARAMETERS
CLK[ 0:2 ]
Output Frequency
SST Modulation Magnitude
(Spread Percentage)
FOUT = FREF * M / (R * P)
where M =11 bit
R = 9 bit
P = 6 bit
 CLK0= FREF, FREF/2 or FVCO/P*
 CLK1= FREF, FREF/2 or FVCO/P*
 CLK2= FREF, CLK0, CLK0/2 or CLK0/4
16 programmable modulation
magnitudes to choose from:
Programmable
Input/Output
Output Drive
Strength
Programmable I/O’s
include:
 Center Spread: ±0.125%  PDB – input
to ±2.0% in ±0.125%
 CSEL Configuration
steps
Selection - input
 Down Spread: -0.25% to -  CLK[0:2] - output
4.0% in 0.25% steps
 SST On/Off Control.
* ‘P’ is a 6-bit Odd/Even divider.
Three optional
drive strengths
to choose from:
Low: 4mA
Std: 8mA
(default)
High: 16mA
PACKAGE PIN ASSIGNMENT
Name
(T)SOT23-6L
Pin #
Type
Description
This pin can be programmed as PDB (input) or CLK1 (output).
Power Down (PDB) input. This pin has an internal 60KΩ pull up
resistor and turns off the oscillator and the output when pulled to
logic “0”.
PDB, CLK1
1
B
PDB Logic
Osc
PLL
Output
0
Off
Off
Hi Z (Default)
1
Normal Operation (Default)
Clock1 (CLK1) output. This optional clock can be set to F REF ,
F REF /2 or F OUT (Programmable PLL output).
GND
2
P
GND connection
FIN
3
I
Reference input pin
VDD
4
P
VDD connection
I
This pin can be programmed as CSEL (input) or CLK2 (output).
CSEL input. Selector pin used to toggle between two preprogrammed configurations.
CSEL, CLK2
5
CLK2 output. This optional clock can be set to F REF , CLK0, CLK0/2
or CLK0/4.
CLK0
6
O
Programmable Clock Output
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PicoEMI T M Spread Spectrum Clock Generator
FUNCTIONAL DESCRIPTION
PL671-02 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-power
Spread Spectrum modulation applications. The PL671-02 accepts a reference clock input of 1MHz to 200MHz and
is capable of producing three SST modulated outputs up to 200MHz. This flexible design allows the PL671-02 to
deliver any PLL generated frequency, F REF (Ref Clk) frequency or F REF /2 to CLK0, CLK1 and/or CLK2. Alternate
programming using CSEL allows the device to choose from 2 different pre-programmed settings providing a range
of spread settings and outputs to choose from. Some of the design features of the PL671-02 are mentioned below.
PLL Programming
The PLL in the PL671-02 is fully programmable. The
PLL is equipped with a 9-bit input frequency divider
(R-Counter), and an 11-bit VCO frequency feedback
loop divider (M-Counter). The output of the PLL is
transferred to a 6-bit post VCO Odd/Even divider (PCounter). The output frequency is determined by the
following formula [F OUT = (F REF * M)/(R*P).
Modulation Magnitude and Type
The PL671-02 provides the following programmable
capabilities for Modulation Type and Modulation
Magnitude (Spread Percentage):
Modulation
Type
Modulation
Magnitude
Programming
Steps
Center Spread ±0.125% thru ±2.00%
Down Spread
-0.25% thru -4.00%
±0.125%
0.25%
Modulation Rate
The PL671-02 modulation rate is defined as F REF (Ref
Clk Frequency) divided by 8 times the R-counter, i.e.
Modulation Rate = (F REF / 8R). The rate can be
changed by choosing alternate R-Counter settings.
The output drive level of each output can be
independently programmed to Low Drive (4mA),
Standard Drive (8mA) or High Drive (16mA). The
output frequency can be programmed up to 200MHz
at 3.3V (166MHz at 2.5V).
Power-Down Control (PDB)
When activated (logic ‘0’), PDB ‘Disables the PLL,
the oscillator circuitry, counters, and all other active
circuitry. In Power Down mode the IC consumes
<10µA of power. The PDB input incorporates a
60kΩ pull up resistor giving a default condition of
logic “1”.
Configuration Select (CSEL)
The PL671-02 has the capability to be programmed
with 2 distinct configurations and to toggle “On the
Fly” between these configurations using the selector
pin CSEL. CSEL incorporates a 60kΩ pull up
resistor giving a default condition of logic “1”.
Clock Outputs (CLK[0:2])
CLK0 is the main clock output. The PL671-02 can
also be programmed with additional clock outputs
CLK1 and CLK2. The outputs of CLK[0:2] can be
configured as described below:



CLK0= FREF, FREF/2 or FVCO/P*
CLK1= FREF, FREF/2 or FVCO/P*
CLK2= FREF, CLK0, CLK0/2 or CLK0/4
Where
F REF - Reference (Ref Clk) Frequency
FOUT = FREF * M / (R * P)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/24/09 Page 3
PicoEMI T M Spread Spectrum Clock Generator
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like
ringing ).
- Design long traces (> 1 inch) as “striplines” or
“microstrips” with defined impedance.
- Match trace at one side to avoid reflections
bouncing back and forth.
- Multiple VDD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical values to use are 0.1F for
designs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/24/09 Page 4
PicoEMI T M Spread Spectrum Clock Generator
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN
MAX
UNITS
V DD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
260
C
Supply Voltage Range
Soldering Temperature (Green package)
10
Data Retention @ 85C
Storage Temperature
TS
Ambient Operating Temperature*
Year
-65
150
C
-40
85
C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Input (FIN) Frequency
CONDITIONS
@ V DD =3.3V
@ V DD =2.5V
Input (FIN) Signal Amplitude Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
Input (FIN) Signal Amplitude
3.3V <50MHz, 2.5V <40MHz
@ V DD =3.3V
Output Frequency
@ V DD =2.5V
MIN
TYP
MAX
200
1
166
UNITS
MHz
0.9
V DD
Vpp
0.1
V DD
Vpp
200
166
MHz
Settling Time
At power-up (after V DD increases over 2.25V)
2
ms
Output Enable Time
PDB Function; Ta=25º C, 15pF Load
2
ms
Output Rise Time
Output Fall Time
15pF Load, 10/90% V DD , Standard Drive
2.0
3.0
15pF Load, 10/90% V DD , High Drive
1.2
1.7
15pF Load, 90/10% V DD , Standard Drive
1.7
2.5
15pF Load, 90/10% V DD , High Drive
1.2
1.7
50
55
%
100
ps
Duty Cycle
At V DD /2
Cycle to Cycle Jitter*
T CYC - CYC Over output frequency range @ 3.3V
45
ns
ns
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/24/09 Page 5
PicoEMI T M Spread Spectrum Clock Generator
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded Outputs
SYMBOL
I DD
CONDITIONS
MIN.
TYP.
At 27MHz, 3.3V,
load=15pF, (PDB=1)
PDB=0 [with reference
input pin (FIN) pulled down]
2.25
MAX.
UNITS
15
mA
10
A
3.63
V
100
ms
0.4
V
Operating Voltage
V DD
Power Supply Ramp
t PU
Output Low Voltage
V OL
Time for V DD to reach
90% V DD . Power ramp
must be monotonic.
I OL = +4mA (Std. Drive)
Output High Voltage
V OH
I OH = -4mA (Std. Drive)
V DD – 0.4
V
Output Current, Low Drive
I OSD
V OL = 0.4V, V OH = 2.4V
4
mA
Output Current, Standard Drive
I OSD
V OL = 0.4V, V OH = 2.4V
8
mA
Output Current, High Drive
I OHD
V OL = 0.4V, V OH = 2.4V
16
mA
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
1.05
1.35
0.05
0.15
1.00
1.20
0.30
0.50
0.08
0.20
2.80
3.00
1.50
1.70
2.60
3.00
0.35
0.55
0.95 BSC
Pin1 Dot
E
H
D
A2 A
A1
C
e
b
L
TSOT-6L
Symbol
A
A1
A2
b
c
D
E
H
L
e
Dimension in MM
Min.
Max.
1.00
0.00
0.10
0.84
0.90
0.30
0.50
0.127 w/o plating
2.90 BSC
1.60 BSC
2.80 BSC
0.30
0.50
0.95 TYP
Pin1 Dot
E
H
D
A2 A
A1
C
e
b
L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/24/09 Page 6
PicoEMI T M Spread Spectrum Clock Generator
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: +1 510 492-0990 • Fax: +1 510 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part Number, Package Type and Operating Temperature Range
Shipping Option
R = Tape & Reel
None = Tube
Part Number
3 Digit ID Code*
Temperature Range
C = Commercial (0°C to 70°C)
Package Type
R = TSOT-6L
T = SOT23-6L
* PhaseLink will assign a unique 3-digit ID code for each approved programmed part number.
Part/Order Number
Marking
Package Option
PL671-02-xxxRC-R
F2xxx
6-Pin TSOT (Tape and Reel)
PL671-02-xxxTC-R
F2xxx
6-Pin SOT23 (Tape and Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 07/24/09 Page 7