1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock FEATURES DESCRIPTION The PL611s-17 is a low-cost general purpose frequency synthesizer and a member of PhaseLink’s PicoPLL TM Factory Programmable ‘Quick Turn Clock (QTC)’ family. Designed to fit in a small SOT23, SC70, or DFN package for high performance, low power applications, the PL611s-17 accepts a low frequency (>10kHz) reference input and generates up to 125MHz outputs with the jitter performance, and power consumption needed in handheld devices and notebook applications. In addition, one programmable I/O pin can be configured as Output Enable (OE), Frequency switching (FSEL), Power Down (PDB) input, or CLK1 (F OUT , F REF , F REF /2) output. Cascading the PL611s-17 with other PicoPLL ICs can result in producing all required system clocks with specific savings in board space, power consumption, and cost. Advanced Programmable PLL design for lowfrequency (kHz) input applications Input Frequency: 10kHz to 200MHz DC Input Coupling Very low Jitter and Phase Noise Output Frequency: o <65MHz @ 1.8V operation o <90MHz @ 2.5V operation o <125MHz @ 3.3V operation Disabled outputs programmable as HiZ or Active Low. Single 1.8V ~ 3.3V, ± 10% power supply Operating temperature range from -40C to 85C Available in 6-pin DFN and SOT23 GREEN/RoHS compliant packages. PACKAGE PIN CONFIGURATION BLOCK DIAGRAM FIN FREF R-Counter (7-bit) M-Counter (16-bit) Phase Detector Charge Pump Loop Filter FVCO = FREF * (2 * M/R) Programmable Function /2 VCO P-Counter (4-bit) CLK0 FOUT = FVCO / (2 * P) /1, /2 Programming Logic OE, PDB, FSEL, CLK1 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 1 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock KEY PROGRAMMING PARAMETERS CLK Output Frequency Programmable Input/Output Output Drive Strength F OUT = F REF * (M / R) /(2*P) Where M=16 bit R= 7 bit P= 4 bit CLK0 = F OUT , F REF or F REF / (2*P) CLK1 = F REF , F REF /2, CLK0 or CLK0/2 Three optional drive strengths to choose from: One output pin can be configured as: Low: 4mA Std: 8mA (default) OE - input FSEL - input PDB - input CLK1 – output PACKAGE PIN ASSIGNMENT Name VDD Pin # SOT23 DFN 4 3 Type P Description VDD connection. This programmable I/O pin can be configured as Output Enable (OE) input, Power Down (PDB) input, Frequency Selector (FSEL) or CLK1 clock output. OE, PDB, FSEL, CLK1 5 2 I/O The OE and PDB features can be programmed to allow the output to float (Hi Z), or to operate in the ‘Active low’ mode. State OE PDB FSEL 0 Disable CLK Power Down Mode Frequency ‘2’ 1 (default) Normal mode Normal mode Frequency ‘1’ FIN 6 1 I Reference input pin. LF 1 6 I Loop Filter input pin. GND 2 5 P GND connection CLK0 3 4 O Programmable Clock Output 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 2 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock FUNCTIONAL DESCRIPTION PL611s-17 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-17 accepts a reference clock input of 10kHz to 200MHz and is capable of producing two outputs up to 125MHz. This flexible design allows the PL611s-17 to deliver any PLL generated frequency, F REF (Ref Clk) frequency or F REF /(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-17 are mentioned below: PLL Programming Output Enable (OE) The PLL in the PL611s-17 is fully programmable. The PLL is equipped with an 7-bit input frequency divider (R-Counter), and an 16-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 4-bit post VCO divider (PCounter). The output frequency is determined by the following formula [FOUT = FREF * (M / R) / (2 * P) ]. The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60KΩ pull up resistor giving a default condition of logic “1”. Clock Output (CLK0) CLK0 is the main clock output. The PL611s-17 can also be programmed to provide a second clock output, CLK1, on the programmable I/O pin (see OE/PDB/FSEL/CLK1 pin description below). The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), F REF (Ref Clk Frequency) output, or F REF /(2*P) output. The output drive level can be programmed to Low Drive (4mA) or Standard Drive (8mA). The maximum output frequency is 125MHz. Clock Output (CLK1) The CLK1 feature allows the PL611s-17 to have an additional clock output. This output can be programmed to one of the following: Power-Down Control (PDB) The Power Down (PDB) feature allows the user to put the PL611s-17 into “Sleep Mode”. When activated (logic ‘0’), PDB ‘Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <10µA of power. The PDB pin incorporates a 10MΩ pull up resistor giving a default condition of logic “1”. Frequency Select (FSEL) The Frequency Select (FSEL) feature allows the PL611s-17 to switch between two pre-programmed outputs allowing the device “On the Fly” frequency switching. The FSEL pin incorporates a 60KΩ pull up resistor giving a default condition of logic “1”. FREF - Reference ( Ref Clk ) Frequency FREF / 2 CLK0 CLK0 / 2 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 3 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock GUIDELINES FOR EXTERNAL COMPONENT SELECTION For the optimum performance, an accurate external loop filter capacitor must be selected. A general guideline for selecting this component based on the input frequency is shown in the table below. Input Frequency Capacitor Value 3MHz ~ 200MHz 1.0nF 300KHz ~ 10MHz 1.0nF 30KHz ~ 1.0MHz 4.7nF 10KHz ~ 100KHz 47nF The optimal way to choose the value is using the following formula: C(nF) = 0.8 + M/280 Where C = Loop Filter Capacitor value (in nF) M = M counter value. Provided by PhaseLink with device samples. Notes: * Find the closest commercially available value. Values in the E12 range with 5% tolerance are acceptable. * With possible M-counter values between 1 and 65536, the capacitor value is expected in the range 820pF thru 220nF. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 4 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL MIN. MAX. UNITS V DD -0.5 7 V Input Voltage Range VI -0.5 V DD +0.5 V Output Voltage Range VO -0.5 V DD +0.5 V 260 C Supply Voltage Range Soldering Temperature (Green package) 10 Data Retention @ 85C Storage Temperature TS Ambient Operating Temperature* Year -65 150 C -40 85 C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. DC SPECIFICATIONS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current, Dynamic, with Loaded LVCMOS Outputs I DD VDD =3.3V, FIN=32.768kHz, CLK0=16MHz, load=15pF 3.5 mA Supply Current, Dynamic, with Loaded LVCMOS Outputs I DD VDD =2.5V, FIN=32.768kHz, CLK0=16MHz, load=15pF 2.3 mA Supply Current, Dynamic with Loaded LVCMOS Outputs I DD VDD =1.8V, FIN=32.768kHz, CLK0=16MHz, load=15pF 1.6 mA Operating Voltage V DD Power Supply Ramp t PU Output Low Voltage V OL Time for V DD to reach 90% V DD . Power ramp must be monotonic. I OL = +4mA Standard Drive Output High Voltage V OH I OH = -4mA Standard Drive Output Current, Low Drive I OSD Output Current, Standard Drive I OSD 1.62 3.63 V .001 100 ms 0.4 V V DD – 0.4 V V OL = 0.4V, V OH = 2.4V 4 mA V OL = 0.4V, V OH = 2.4V 8 mA 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 5 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock AC SPECIFICATIONS PARAMETERS CONDITIONS MIN. TYP. @ V DD =3.3V Input (FIN) Frequency @ V DD =2.5V 10kHz 166 Internally DC Coupled, LVCMOS input, High 0.7*V DD Internally DC Coupled, LVCMOS input, Low 0.3*V DD 125 @ VDD =2.5V 90 65 Output Rise Time @ VDD =1.8V At power-up, FIN=32.768kHz, CLK0=48MHz, F VCO = 96MHz, C LF = 47nF Dependant on loop filter configuration OE Function; Ta=25º C, 15pF Load Add one clock period for a useable output PDB Function; Ta=25º C, 15pF Load FIN=32.768kHz, CLK0=48MHz, F VCO = 96MHz, C LF = 47nF Dependant on loop filter configuration 15pF Load, 10/90% VDD, Std Drive, 3.3V Output Fall Time 15pF Load, 90/10% VDD, Std Drive, 3.3V Duty Cycle VDD /2 Period Jitter, Pk-to-Pk* (10,000 samples measured) With capacitive decoupling between VDD and GND Settling Time Output Enable Time MHz 133 @ VDD =3.3V Output Frequency UNITS 200 @ V DD =1.8V Input (FIN) Signal Amplitude MAX. 15 45 Vpp MHz 25 ms 10 ns 15 25 ms 2.0 3.0 ns 2.0 3.0 ns 50 55 % 100 ps * Note: Jitter performance depends on the programming parameters. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 6 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock PCB LAYOUT CONSIDERATIONS FOR PERFORMANCE OPTIMIZATION The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to PL611s-17 as short as possible, as well as keeping all other traces as far away from it as possible. - Please contact PhaseLink for the application note on how to design outputs driving long traces or the Gerber files for the PL611s-17 layout. - When a reference input clock is generated from a crystal (see diagram above), place the PL611s-17 ‘FIN’ as close as possible to the ‘Xout’ crystal pin. This will reduce the cross-talk between the reference input and the other signals. - Place the Loop Filter (LF) components as close to the package pin of PL611s-17 as possible. - Place a 0.01µF~0.1µF decoupling capacitor between V DD and GND, on the component side of the PCB, close to the V DD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the V DD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or ‘stripline’, to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually ‘striplines’ are designed for 50Ω impedance and CMOS outputs usually have lower than 50Ω impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the ‘stripline’ trace. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 7 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) SOT23-6 L Symbol A A1 A2 b c D E H L e Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.00 0.35 0.55 0.95 BSC Pin1 Dot E H D A2 A A1 C b e L DFN-6L D1 Symbol A A1 A3 b e D E D1 E1 L Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30 b e D Pin 6 ID Chamfer E E1 Pin1 Dot L Bottom View A A1 Top View A3 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 8 1.8V to 3.3V PicoPLL TM kHz to MHz Programmable Clock ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL611s-17-XXX X X X PART NUMBER 3 DIGIT ID Code * (assigned by Factory) NONE= TUBE R=TAPE and REEL PACKAGE TYPE G=DFN-6L T=SOT23-6L TEMPERATURE C=COMMERCIAL (0°C to 70°C) I = INDUSTRIAL (-40°C to 85°C) * PhaseLink will assign a unique 3-digit ID code for each approved programmed part number. Part/Order Number Marking PL611s-17-XXXGC-R XXX PL611s-17-XXXTC-R 17XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SOT23 (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/20/09 Page 9