2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout

(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
FEATURES
DESCRIPTION
 Two differential 2.5V/3.3V LVPECL output pairs.
 Output Frequency: ≤ 1 GHz.
 Translates any standard single-ended or differential
input format to LVPECL output. It can accept the
following standard input formats and more:
o LVPECL, LVCMOS, LVDS, HCSL, SSTL,
LVHSTL, CML.
 Output Skew: 25ps (typ.).
 Part-to-part skew: 140ps (typ.).
 Propagation delay: 1.5ns (typ.).
 Additive Jitter: <100 fs (typ.).
 Operating Supply Voltage: 2.375V ~ 3.63V.
 Operating temperature range from -40C to 85C.
 Package availability: SOP-8L and TSSOP-8L.
The PL138-28 is a high performance low-cost
1: 2 outputs Differential PECL fanout buffer.
PhaseLink’s family of Differential LVPECL buffers are
designed to operate from a single power supply of 2.5V±5% or
3.3V±10%. The differential input pair is designed to accept
most standard input signal levels, using an appropriate resistor
bias network, and produce a high quality set of outputs with
the lowest possible skew on the outputs, which is guaranteed
for part-to-part or lot-to lot skew.
Designed to fit in a small form-factor package, PL138
family very low-power consumption, and the lowest
additive jitter of any comparable device.
BLOCK DIAGRAM
CC
Q0
CLK-IN0
CLK-IN0B
QB0
EE
Q1
QB1
8-Lead SOIC or TSSOP Package
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
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Rev 10/11/11 Page 1
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
PIN DESCRIPTIONS
Package Pin #
SOIC-8L / TSSOP-8L
Type
Q0 ~ Q1
1, 3
O
LVPECL True output
QB0 ~ QB1
2, 4
O
LVPECL Complementary output
VEE
5
P
Power Supply pin connection
CLK-IN0B
6
I
Complementary part of differential clock input signal
CLK-IN0
7
I
True part of differential clock input signal
Vcc
8
P
Power Supply pin connection
Name
Description
INPUT LOGIC BLOCK DIAGRAM
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Rev 10/11/11 Page 2
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
MIN.
V DD
MAX.
UNITS
4.6
V
Input Voltage, dc
VI
-0.5
V DD +0.5
V
Output Voltage, dc
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
C
Ambient Operating Temperature*
TA
-40
85
C
Junction Temperature
TJ
110
C
260
C
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
2
kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Parameter
Output High Voltage*
Output Low Voltage*
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input High Voltage Common Mode
Range † ††
Input High
CLK-IN0,
Current
CLK-IN1
Input Low
Current
Symbol
-40°C
Typ
Min
VOH
VOL
VIH
VIL
VPP
2.215
1.470
2.075
1.470
150
VCMR
1.2
2.320
1.610
800
IIH
IIL
Max
Min
2.420
1.745
2.420
1.890
1200
2.275
1.490
2.135
1.490
150
3.3
1.2
75
-75
25°C
Typ
2.350
1.585
800
Max
2.420
1.680
2.420
1.825
1200
3.3
Min
80°C
Typ
Units
2.275 2.35 2.420
1.490 1.585 1.680
2.135
2.420
1.490
1.825
150
800 1200
1.2
75
-75
Max
3.3
V
75
µA
-75
µA
.
Input and output parameters vary 1:1 with VCC VEE can vary +0.925V to -0.5V.
* Outputs terminated with 50Ω to VCCO – 2V.
** Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
.
† Common mode voltage is defined as VIH
†† For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC + 0.3V
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
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V
V
V
V
V
Rev 10/11/11 Page 3
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Parameter
Symbol
Output High Voltage*
Output Low Voltage*
Input High Voltage
Input Low Voltage
Peak-to-Peak Input Voltage
Input High Voltage Common Mode
Range†
Input High
CLK-IN0,
Current
CLK-IN1
Input Low
VOH
VOL
VIH
VIL
VPP
1.415
0.670
1.275
0.670
150
VCMR
1.2
Current
-40°C
Typ
Min
1.520
0.810
800
Max
Min
1.620
0.945
1.620
1.090
1200
1.475
0.690
1.335
0.690
150
2.5
1.2
IIH
IIL
25°C
Typ
1.550
0.785
800
Max
1.620
0.880
1.620
1.025
1200
2.5
60
Min
80°C
Typ
-60
V
V
V
V
V
1.475 1.55 1.620
0.690 0.785 0.880
1.335
1.620
0.690
1.025
150
800 1200
1.2
60
-60
Units
Max
2.5
V
60
µA
-60
µA
.
Input and output parameters vary 1:1 with VCC VEE can vary +0.925V to -0.5V.
* Outputs terminated with 50Ω to VCCO – 2V.
V .
** Common mode voltage is defined as IH
† For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC + 0.3V
AC Electrical Characteristics
VCC = -3.8V to -2.375V or, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Parameter
Symbol
Output Frequency
fMAX
Propagation Delay*
tPD
Min
-40°C
Typ
Max
Min
25°C
Typ
700
600
680
750
Max
Min
80°C
Typ
700
650
725
790
690
Max
Units
700
MHz
790
890
ps
Output Skew ** †
tsk(o)
25
37
25
37
25
37
ps
Part-to-Part Skew *** †
tsk(pp)
85
225
85
225
85
225
ps
tAPJ
0.10
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
Output Rise/Fall Time
20%to80%
tR / tF
200
0.10
700
200
0.10
700
200
ps
700
ps
All parameters are measured at f ≤ 1000MHz, unless otherwise noted.
* Measured from the differential input crossing point to the differential output crossing point.
** Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
*** Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of
inputs on each device, the outputs are measured at the differential cross points.
†This parameter is defined in accordance with JEDEC Standard 65.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
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Rev 10/11/11 Page 4
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices)
Parameter
tAPJ
Description
Test Conditions
Min.
V DD=3.3V, Frequency=622.08MHz
Offset=12KHz ~ 20MHz
Additive Phase Jitter
REF Input
Typ.
21
Max.
Unit
fs
PL138-28 Output
-60
-70
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140
-150
-160
100
1000
10000
100000
1000000
10000000
100000000
Offset Frequency (Hz)
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
2
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)
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Rev 10/11/11 Page 5
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
PARAMETER MEASUREMENT INFORMATION
Output Waveform Test Circuit:
Differential Input Level:
+2.0V
VCC
OSCILLOSCOPE
VCC
50 
Channel
50  Line
LVPECL
CLK-INxB
Cross Points
V PP
CLK-INx
50 
Channel
50  Line
VEE
V CMR
VEE
-1.80V to -0.375V
Part-to-Part Skew:
Output Skew:
QBx
QBx
Part 1
Qx
Qx
QBy
QBy
Part 2
Qy
Qy
tsk(o)
tsk(pp)
Output Rise/Fall Time:
Qx
80%
Propagation Delay:
CLK-INxB
80%
CLK-INx
QBx
20%
20%
tR
QBy
tF
Qy
t PD
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Rev 10/11/11 Page 6
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
APPLICATION INFORMATION
The following circuits show different configurations for different input logic type signals. For
good signal integrity at the PL138 input, the signals need to be properly terminated according
to the logic type requirements. The signals need to be presented at the PL138 input according
to V CMR , V PP and other input requirements.
CLK-IN Input Driven by a 3.3V LVPECL Driver:
+3.3V
+3.3V
130
+3.3V
3.3V LVPECL Driver, Alternative Termination:
+3.3V
+3.3V
PL138
130
PL138
50  Line
50  Line
LVPECL
CLK-INx
LVPECL
50  Line
CLK-INx
50  Line
82
82
50
50
50
CLK-IN Input Driven by a CML Driver:
+3.3V
CLK-IN Input Driven by an SSTL Driver:
+3.3V
50
+3.3V
+2.5V
+2.5V
PL138
50
120
50  Line
PL138
120
50  Line
CML
CLK-INx
SSTL
CLK-INx
50  Line
50  Line
120
CLK-IN Input Driven by an LVDS Driver:
+2.5V or +3.3V
120
LVDS Driver, Alternative AC Coupling:
+2.5V or +3.3V
+2.5V or +3.3V
+2.5V or +3.3V
1K
PL138
PL138
1K
50  Line
50  Line
LVDS
+3.3V
100
CLK-INx
LVDS
CLK-INx
100
50  Line
50  Line
1K
1K
This circuit is for compatibility only. AC coupling is not really
required for LVDS. The V CMR range of the PL138 reaches
low enough that LVDS signals can be connected directly to
the PL138 input like in the circuit to the left.
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Rev 10/11/11 Page 7
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
CLK-IN Input Driven by a CMOS Driver:
CLK-IN Input Driven by Single Ended LVPECL:
+3.3V
+2.5V or +3.3V
+3.3V
PL138
1K
CMOS
LVPECL
CLK-INx
1K
PL138
130
50  Line
0.1µF
CLK-INx
1K
82
0.1µF
CLK-IN Input Driven by an HCSL Driver:
+2.5V or +3.3V
+2.5V or +3.3V
1K
PL138
1K
50  Line
HCSL
CLK-INx
50  Line
50
50
1K
HCSL presents its signals very close to the ground
rail, below the V CMR range, so the HCSL signals can
not be connected to the PL138 input directly. AC
coupling is required for HCSL signals on the PL138
input.
1K
TERMINATION FOR LVPECL OUTPUTS
The required termination for LVPECL is 50 to a V CC -2V DC voltage level. Below are two schematics to
implement this termination.
LVPECL Termination Schematic #1:
VCC
LVPECL Termination Schematic #2:
VCC
R1
VCC
R1
50  Line
Target
LVPECL
Input
PL138
Qx Buffer
50  Line
R2
50  Line
Target
LVPECL
Input
PL138
Qx Buffer
50  Line
R2
50
50
RT
VCC=3.3V, Ideal values: R1=127  , R2=82.5 
Commercial values (E24): R1=130  , R2=82 
VCC=2.5V, Ideal values: R1=250  , R2=62.5 
Commercial values (E24): R1=240  , R2=62 
Schematic #2 is an alternative simplified termination.
VCC=3.3V, Ideal value: RT=48.7 
Commercial value: RT=50  (E24: 51 )
VCC=2.5V, Ideal value: RT=18.7 
Commercial value: RT=18 
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Rev 10/11/11 Page 8
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
POWER CONSIDERATIONS
Driving LVPECL outputs requires an amount of power that can warm up the chip significantly.
The general requirement for the chip is that the junction temperature should not exceed +110°C.
The power consumption can be divided into two parts:
1) Core power dissipation
2) Output buffers power dissipation
CORE POWER DISSIPATION
The chip core power is equal to VCC×IEE. With a worst case VCC and IEE the power dissipation in the core is
3.63V×45mA=163mW.
OUTPUT BUFFER POWER DISSIPATION
The output buffers are not exposed to the full VCC-VEE voltage. On the differential output, one line is at logic 1
with a small voltage across the buffer and a large output current. The other line is at logic 0 with a larger voltage
across the buffer and a smaller output current. The power dissipation per output buffer is 32mW. Only buffers that
are loaded will have power dissipation. With both buffers loaded the worst case output buffer power dissipation
will be 64mW.
Total Chip Power Dissipation, worst case, is 163mW + 64mW = 227mW.
JUNCTION TEMPERATURE
How much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to
the environment, also known as “junction to ambient”. The thermal resistance depends upon the type of package,
how the package is assembled to the PCB and if there is additional air flow for improved cooling. For the LQFP
package with use of the Thermal Relief pad, the thermal resistance is as follows:
JEDEC Standard Multi Layer PCB
Air Flow Velocity in Linear Feet per Minute
0
200
500
SOIC 8-pin Package
θ JA = 97°C/W
θ JA = 85°C/W
θ JA = 77°C/W
TSSOP 8-pin Package
θ JA = 120°C/W
θ JA = 105°C/W
θ JA = 95°C/W
SOIC 8-pin:
The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to θ JA ×
Power. For an ambient temperature of +85°C, all outputs loaded and no air flow, the junction temperature T J =
85°C+97×0.227 = 107°C.
TSSOP 8-pin:
For an ambient temperature of +85°C, all outputs loaded and 200LFM air flow, the junction temperature T J =
85°C+105×0.227 = 109°C. It is recommended to use at least 200LFM air flow to prevent the junction temperature
from increasing above +110°C.
For use up to +80°C or lower no air flow is needed: T J = 80°C+120×0.227 = 107°C.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688
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Rev 10/11/11 Page 9
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
8 Pin (dimensions in mm)
Symbol
A
A1
A2
B
C
D
E
H
L
e
SOIC
Min. Max.
1.35 1.75
0.10 0.25
1.25 1.50
0.33 0.53
0.19 0.27
4.80 5.00
3.80 4.00
5.80 6.20
0.40 0.89
1.27 BSC
TSSOP
Min. Max.
1.20
0.05 0.15
1.05
0.19 0.30
0.09 0.20
2.90 3.10
4.30 4.50
6.20 6.60
0.45 0.75
0.65 BSC
E
H
D
A2 A
A1
C
e
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L
b
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Rev 10/11/11 Page 10
(Preliminary)
2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
2880 Zanker Road, San Jose, CA 95134 USA
Tel (408) 571-1668 Fax (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Part/Order Number
PL138-28SC-R
PL138-28OC-R
Marking
P138-28
SC
LLLLL
P138-28
OC
LLLLL
Package Option
8-Pin SOP (Tape and Reel)
8-Pin TSSOP (Tape and Reel)
*Note: LLLLL designates lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
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Rev 10/11/11 Page 11