XRK69774 PRELIMINARY 1:14 LVCMOS PLL CLOCK GENERATOR APRIL 2006 REV. P1.0.1 GENERAL DESCRIPTION to125MHz and an input frequency range of 4.16MHz to 62.5MHz. The XRK69774 is a PLL based LVCMOS Clock Generator targeted for high performance and low skew clock distribution applications. The XRK69774 can select between one of two reference inputs and provides 15 LVCMOS outputs 14 outputs (2 banks of 5 and 1 bank of 4) for clock distribution and 1 for feedback. The XRK69774 has two LVCMOS inputs to support clock redundancy. Switching the internal reference clock is controlled by the control input, CLK_SEL. The XRK69774 uses PLL technology to frequency lock its outputs to the input reference clock. The divider in the feedback path will determine the frequency of the VCO. Each of the separate output banks can individually divide down the VCO output frequency. This allows the XRK69774 to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. The outputs of the XRK69774 can be immobilized, in the low state, by use of the stop clock feature. Global output disabling and reset can be achieved with the control input MR/OE. The XRK69774 has an output frequency range of 8.33MHz FEATURES • Fully Integrated PLL • 15 LVCMOS outputs ■ ■ ■ • • • • • 2 banks with 5 outputs and 1 with 4 outputs each 1 dedicated feedback for frequency control Output Frequency of each Bank can be individually controlled VCO Range 200MHz to 500MHz Output freq. range: 8.33MHz to 125MHz Max Output Skew of 175ps Max Cycle-to-cycle jitter: 90ps LVCMOS inputs for reference clock source APPLICATIONS • System Clock generator • Zero Delay Buffer FIGURE 1. BLOCK DIAGRAM OF THE XRK69774 VDD QA0 0 CLK0 0 ÷2, ÷4 Ref VCO 1 CLK1 1 QA1 Divider Select ÷2 0 STOP CLK QA2 1 ÷4 ÷2, ÷4 QA3 PLL ÷4, ÷6 QA4 200-500MHz ÷4, ÷6, ÷8, ÷12 CLK_SEL VDD QB0 FB FB_IN QB1 PLL_EN STOP CLK VCO_SEL FSEL_A QB2 QB3 FSEL_B QB4 FSEL_C 2 FSEL_FB[1:0] QC0 STOP CLK VDD QC1 QC2 __________ STOP_CLK QC3 VDD POR QFB ___ MR/OE Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 PRODUCT ORDERING INFORMATION PRODUCT NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRK69774CR 52-LEAD LQFP 0°C to +70°C XRK69774IR 52-LEAD LQFP -40°C to +85°C VCO_SEL GND QC0 VDD QC1 GND QC2 VDD QC3 GND NC VDD QB0 FIGURE 2. PIN OUT OF THE XRK69774 52 51 50 49 48 47 46 45 44 43 42 41 40 39 GND ___ MR/OE _________ STOP_CLK 1 GND 2 38 QB1 3 37 VDD FSEL_B 4 36 QB2 FSEL_C 5 35 GND PLL_EN 6 34 QB3 FSEL_A 7 33 VDD CLK_SEL 8 32 QB4 CLK0 9 31 FB_IN CLK1 10 30 GND NC 11 29 QFB VDD 12 28 VDD 23 24 25 VDD GND 22 QA0 QA3 21 GND QA4 20 QA1 19 VDD 18 QA2 17 27 26 FSEL_FB1 16 VDD 15 GND 13 14 FSEL_FB0 VDD_PLL XRK69774 2 NC PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 PIN DESCRIPTIONS PIN # NAME TYPE 1,15, 19, 24, 30, 35, 39, 43, 47, 51 GND POWER 2 MR/OE INPUT DESCRIPTION Power supply ground Master reset and output enable. High = output enabled, Low = device reset & outputs tri-stated NOTE: 25kΩ Pull-Up resistor. 3 STOP_CLK INPUT Clock input for serial control NOTE: 25kΩ Pull-Up resistor. 7 4 5 FSEL_A, FSEL_B, FSEL_C INPUT Select inputs for control of feedback divide value. NOTE: Each input has a 25kΩ Pull-Down resistor. 6 PLL_EN INPUT PLL bypass High = PLL Enabled. Low = PLL bypass NOTE: 25kΩ Pull-Up resistor. 8 CLK_SEL INPUT CLK0 or CLK1 Select. High = CLK1 selected, Low = CLK0 selected NOTE: 25kΩ Pull-Down resistor. 9 10 CLK0 CLK1 INPUT INPUT PLL Reference Clock Inputs 11, 27, 42 NC - 12, 17, 22, 26, 28, 33, 37, 41, 45, 49 VDD POWER Power supply 13 VDD_PLL POWER Analog supply for PLL 14 20 FSEL_FB0 FSEL_FB1 INPUT INPUT 16, 18,21, 23, 25 QA[4:0] OUTPUT Clock outputs (Bank A) 29 QFB OUTPUT Feedback clock output 31 FB_IN INPUT NOTE: CLK1 has 25kΩ Pull-Up resistor. CLK0 has 25kΩ Pull-Down resistor. NO CONNECT Frequency Divider Select for QFB output NOTE: Each input has a 25kΩ Pull-Down resistor. Feedback input NOTE: 25kΩ Pull-Up resistor. 32, 34, 36, 38, 40 QB[4:0] OUTPUT Clock outputs (Bank B) 44, 46, 48, 50 QC[3:0] OUTPUT Clock outputs (Bank C) 52 VCO_SEL INPUT VCO select. high = VCO/1, low = VCO/2. NOTE: 25kΩ Pull-Down resistor. 3 PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 1.0 ELECTRICAL SPECIFICATIONS TABLE 1: GENERAL SPECIFICATIONS SYMBOL VTT CHARACTERISTICS CONDITION MIN Output Termination Voltage TYP MAX VDD÷2 UNIT V ESDMM ESD Protection (Machine model) 200 V ESDHBM ESD Protection (Human body model) 2000 V LU Latch-up Immunity 200 mA CIN Input capacitance Per input 4 pf TABLE 2: ABSOLUTE MAXIMUM RATINGS SYMBOL CHARACTERISTICS VDD Supply Voltage VIN CONDITION MIN TYP MAX UNIT -0.3 3.9 V DC Input Voltage -0.3 VDD + 0.3 V VOUT DC Output Voltage -0.3 VDD + 0.3 V IIN DC Input Current +/-20 mA IOUT DC Output Current +/-50 mA TS Storage Temperature 125 °C MAX UNIT -65 TABLE 3: DC CHARACTERISTICS (VDD = 3.3V +/- 5%) SYMBOL CHARACTERISTICS CONDITION MIN VDD_PLL PLL Supply Voltage LVCMOS 3.0 VDD V VIH Input High Voltage LVCMOS 2.0 VDD + 0.3 V VIL Input Low Voltage LVCMOS 0.8 V VOH Output High Voltage IOH=-24mA VOL Output Low Voltage IOL = 24mA IOL = 12mA ZOUT Output Impedance IPU Input Pull-Up/Down Current VIN = GND or VDD IDD_PLL PLL Supply Current @ V DD_PLL Pin IDDQ Quiescent Supply Current All VDD pins TYP 2.4 V 0.55 0.30 Ω 14 -17 4 5.0 V +200 μA 7.5 mA 8 mA PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 TABLE 4: AC CHARACTERISTICS (VDD = 3.3V +/- 5%) SYMBOL fREF CHARACTERISTICS Input reference frequency CONDITION MIN ÷8 feedback ÷12 feedback ÷16 feedback ÷24 feedback ÷32 feedback ÷48 feedback 25.0 16.6 12.5 8.33 6.25 4.16 TYP MAX UNIT 62.5 41.6 31.25 20.83 15.625 10.41 MHz MHz MHz MHz MHz MHz 250 MHz 200 500 MHz 50.0 25.0 16.6 12.5 8.33 125 62.5 41.6 31.25 20.83 MHz MHz MHz MHz MHz PLL bypass mode fVCO VCO frequency range fMAX Output frequency tPW CLKx pulse width ItR, ItF Input CLKx Rise/Fall time t(∅) Propagation Delay (static phase offset)a tSK(O) DC Output to output skew ÷4 output ÷8 output ÷12 output ÷16 output ÷24 output 2.0 ns 0.8V to 2.0V CLK to FB_IN fREF = 50MHz & FB = ÷8 -250 Bank A (QAx to QAy) Bank B (QBx to QBy) Bank C (QCx to QCy) all outputs (QXy to QWz) Output duty cycle 47 0.55 to 2.4V 0.1 50 1 ns +100 ps 100 125 100 175 ps ps ps ps 53 % 1.0 ns OtR, OtF Output Rise/Fall time tPLZ, tPHZ Output Disable Time 10 ns tPZL, tPZH Output Enable Time 10 ns tJIT(CC) Cycle-to-Cycle Jitter Time All outputs @ same frequency 90 ps tJIT(PER) Period Jitter All outputs @ same frequency 90 ps ÷8 feedback ÷12 feedback ÷16 feedback ÷24 feedback ÷32 feedback ÷48 feedback 15 49 18 22 26 34 ps ps ps ps ps ps tJIT(∅) I/O Phase Jitter (rms) VCO= 400MHz NOTE: a. t(∅) = +50ps ± (1÷ (120 x fREF)) for any reference frequency. 5 PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 TABLE 5: AC CHARACTERISTICS (VDD = 3.3V +/- 5%) SYMBOL CHARACTERISTICS CONDITION BW PLL closed loop bandwidth ÷8 feedback ÷12 feedback ÷16 feedback ÷24 feedback ÷32 feedback ÷48 feedback tLOCK MIN TYP MAX 0.50-1.80 0.30-1.00 0.25-0.70 0.17-0.40 0.12-0.30 0.07-0.20 Maximum PLL Lock Time MHz MHz MHz MHz MHz MHz 10 FIGURE 3. TEST LOAD Transmission Line Z = 50Ω 50Ω VTT 6 UNIT ms PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 2.0 CONFIGURATION TABLES TABLE 6: FUNCTION C ONTROLS CONTROL PIN DEFAULT LOGIC 0 LOGIC 1 MR/OE 1 Resets the output divide circuitry and serial interface, tri-states all outputs PLL_EN 1 PLL bypass mode enabled. This is a test PLL enabled - normal operation mode in which the reference clock is provided to the output dividers in place of the VCO output. STOP_CLK 1 QA[4:0], QB[4:0] and QC[3:0] outputs disabled Outputs enabled, normal operation in Low state. CLK_SEL 0 CLK0 selected as PLL reference CLK1 selected VCO_SEL 0 VCO ÷ 2 VCO ÷ 4 Enables all outputs - normal operation TABLE 7: BANK OUTPUT D IVIDER CONTROLS INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT VC0_SEL FSEL_A QA[4:0] VCO_SEL FSEL_B QB[4:0] VC0_SEL FSEL_C QC[3:0] 0 0 ÷4 0 0 ÷4 0 0 ÷8 0 1 ÷8 0 1 ÷8 0 1 ÷12 1 0 ÷8 1 0 ÷8 1 0 ÷16 1 1 ÷16 1 1 ÷16 1 1 ÷24 TABLE 8: FEEDBACK D IVIDER CONTROL VCO_SEL FSEL_FB1 FSEL_FB0 QFB 0 0 0 ÷8 0 0 1 ÷16 0 1 0 ÷12 0 1 1 ÷24 1 0 0 ÷16 1 0 1 ÷32 1 1 0 ÷24 1 1 1 ÷48 7 PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 FIGURE 4. OUTPUT-TO-OUTPUT SKEW tSK(O) VCC VCC÷2 GND VCC VCC÷2 GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. FIGURE 5. PROPOGATION DELAY (t(Ø), STATIC PHASE OFFSET) TEST REFERENCE VCC CCLKx VCC÷2 GND VCC VCC÷2 FB_IN GND t(Ø) FIGURE 6. OUTPUT DUTY C YCLE (DC) VCC VCC÷2 GND tp T0 DC=tP/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage FIGURE 7. I/O JITTER CCLKx FB_IN TJIT(I/O) = |T0-T1mean | The deviation in t0 for a controlled edge with respect to a t 0 mean in a random sample of cycles 8 PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 FIGURE 8. CYCLE-TO-CYCLE JITTER TN TN+1 TJIT(CC)= |TN-TN+1 | The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs FIGURE 9. PERIOD JITTER T0 TJIT(Per)= |TN-1/f0 | The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles FIGURE 10. OUTPUT TRANSITION TIME TEST R EFERENCE VCC=3.3V 2.4 0.55 OtF OtR 9 E PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR PACKAGE DIMENSIONS REV. P1.0.1 52 LEAD LOW-PROFILE QUAD FLAT PACK (10 mm x 10 mm X 1.4 mm LQFP, 1.0 mm Form) Rev. 1.00 Note: The control dimension is in millimeters. SYMBOL A A1 A2 B C D D1 e L α INCHES MIN MAX 0.055 0.063 0.002 0.006 0.053 0.057 0.010 0.014 0.004 0.009 0.465 0.480 0.390 0.398 0.0256 BSC 0.029 0.041 0° 7° MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.25 0.35 0.11 0.23 11.80 12.20 9.90 10.10 0.65 BSC 0.73 1.03 0° 7° α 10 PRELIMINARY XRK69774 1:14 LVCMOS PLL CLOCK GENERATOR REV. P1.0.1 REVISION HISTORY REVISION # DATE DESCRIPTION P1.0.0 April 7, 2006 Initial release P1.0.1 April 10, 2006 General Description edit last line to: ...input frequency range of 4.16MHz to 62.5MHz. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2006 EXAR Corporation Datasheet April 2006. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 11