Low Skew Zero Delay Buffer

(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
FEATURES
DESCRIPTION
Frequency Range 10MHz to 134 MHz
Output Options:
o 5 outputs PL123-05
o 9 outputs PL123-09
Zero input - output delay
Optional Drive Strength:
Standard (8mA) PL123-05/-09
High (12mA) PL123-05H/-09H
3.3V, ±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP or TSSOP (PL123-09),
and 8-Pin SOP (PL123-05) packages
The PL123-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123-05) or two (PL123-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123-09 allows control of the banks of
outputs by using the S1 and S2 inputs as shown in the
Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant applications.
BLOCK DIAGRAM
Mux
CLKOUT
CLKA2
CLKA3
Bank A
CLKA1
CLKA4
(PL123-09 Only)
CLKB2
CLKB3
CLKB4
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
Bank B
S2
Selector
Inputs
1
2
CLKA1
3
GND
4
8
CLKOUT
7
CLKA4
6
VDD
5
CLKA3
REF
1
16
CLKOUT
CLKA1
2
15
CLKA4
CLKA2
3
14
CLKA3
13
VDD
12
GND
PL123-09
S1
CLKB1
REF
CLKA2
PL123-05
PLL
REF
VDD
4
GND
5
CLKB1
6
11
CLKB4
CLKB2
7
10
CLKB3
S2
8
9
www.phaselink.com
S1
Rev 12/13/11
Page 1
(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
PIN DESCRIPTIONS
PL123-09
Name
PL123-05
Type
Description
TSSOP-16L
SOP-16L
SOP-8L
REF [1]
1
1
1
I
Input reference frequency.
CLKA1 [2]
2
2
3
O
Buffered clock output, Bank A
CLKA2 [2]
3
3
2
O
Buffered clock output, Bank A
VDD
4,13
4,13
6
P
VDD connection
GND
5,12
5,12
4
P
GND connection
CLKB1 [2]
6
6
-
O
Buffered clock output, Bank B
CLKB2 [2]
7
7
-
O
Buffered clock output, Bank B
S2 [3]
8
8
-
I
Selector input
S1 [3]
9
9
-
I
Selector input
CLKB3 [2]
10
10
-
O
Buffered clock output, Bank B
CLKB4 [2]
11
11
-
O
Buffered clock output, Bank B
CLKA3 [2]
14
14
5
O
Buffered clock output, Bank A
CLKA4 [2]
15
15
7
O
CLKOUT [2]
16
16
8
O
Buffered clock output, Bank A
Buffered clock output. Internal feedback
on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION FOR PL123-09
S2
S1
CLOCK A1–A4
(Bank A)
CLOCK B1–B4
(Bank B)
CLKOUT
Output Source
PLL Shutdown
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
INPUT / OUTPUT SKEW CONTROL
The PL123-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjustments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact PhaseLink for more information.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
www.phaselink.com
Rev 12/13/11
Page 2
(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
Decoupling and Power Supply
Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible
to the VDD pin(s) to limit noise from the power
supply
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1 F for designs
using frequencies < 50MHz and 0.01 F for designs using frequencies > 50MHz.
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
To CMOS Input
( Typical buffer impedance 20
50
line
Connect a 33 series
resistor at each of the output
clocks to enhance the
stability of the output signal
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
www.phaselink.com
Rev 12/13/11
Page 3
(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage ........................... V SS – 0.5V to 4.6V
Storage Temperature ........................ –65°C to 150°C
Junction Temperature………………………….. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)…………..> 2000V
OPERATING CONDITIONS
Parameter
Description
Min.
Max.
Unit
V DD
Supply Voltage
3.0
3.6
V
0
70
C
Industrial Operating Temperature (ambient temperature)
-40
85
C
Load Capacitance, below 100 MHz
Load Capacitance, above 100 MHz
Input Capacitance
Power-up time for all V DD s to reach minimum specified voltage
(power ramps must be monotonic)
―
―
―
30
10
7
pF
pF
pF
0.05
250
ms
TA
CL
C IN
t PU
Commercial Operating Temperature (ambient temperature)
ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
Description
Min.
Max.
Unit
VIL
Input LOW Voltage
–
0.8
V
VIH
Input HIGH Voltage
2.5
–
V
IIL
Input LOW Current
VIN = 0V
–
50
µA
IIH
Input HIGH Current
–
100
µA
VOL
Output LOW Voltage[4]
–
0.4
V
VOH
Output HIGH Voltage[4]
2.4
–
V
Supply Current
(Unloaded Outputs)
–
32
mA
IDD
VIN = VDD
IOL = 8 mA
IOL = 12 mA
IOH = –8 mA
IOL = –12 mA
66.67MHz with unloaded outputs
Commercial Temp.
66.67MHz with unloaded outputs
Industrial Temp.
–
45
mA
Rev 12/13/11
Page 4
Notes: 4. Parameter is guaranteed by design and c haracterization. Not 100% tested in production.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
www.phaselink.com
(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
SWITCHING CHARACTERISTICS
Parameter Name
t1
t3
t4
t5
t6A
t6B
[5]
Test Conditions
Min.
Typ.
Max.
Unit
30-pF load
10
–
100
MHz
10-pF load
10
–
134
MHz
Duty Cycle [4] = t2 ÷ t1
Measured at 1.4V, FOUT = 66.67MHz
40
50
60
%
Duty Cycle
Measured at 1.4V, FOUT <50MHz
45
50
55
%
Measured between 0.8V and 2.0V
–
2.5
–
ns
Measured between 0.8V and 2.0V
–
1.5
–
ns
Measured between 0.8V and 2.0V
–
2.5
–
ns
Measured between 0.8V and 2.0V
–
1.5
–
ns
All outputs equally loaded
–
–
250
ps
Measured at VDD/2
–
0
±350
ps
Measured at VDD/2. Measured in PLL bypass
mode, PL123-09 only.
1
5
8.5
ns
Output Frequency
[4]
= t2 ÷ t1
Rise Time [4]
Rise Time
[4]
(High Drive)
Fall Time [4]
Fall Time
[4]
(High Drive)
Output to Output Skew
Delay, REF Rising Edge to
CLKOUT Rising Edge [4]
Delay, REF Rising Edge to
CLKOUT Rising Edge [4]
t7
Device to Device Skew [4]
Measured at VDD/2 on the CLKOUT pin
–
0
700
ps
t8
Output Slew Rate [4]
Measured between 0.8V and 2.0V using Test
Circuit #2
1
–
–
V/ns
tJ
Cycle to Cycle Jitter [4]
Measured at 66.67 MHz, loaded outputs
–
75
200
ps
tLOCK
PLL Lock Time [4]
Stable power supply, valid clock presented on
REF pin
–
–
1
ms
Notes:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
5. All parameters are specified with loaded ou tputs.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
www.phaselink.com
Rev 12/13/11
Page 5
(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
1.4V
All Outputs Rise/Fall Time
1.4V
2.0V
2.0V
OUTPUT
0.8V
3.3V
V
0.8V
t3
0V
t4
Output-Output Skew
OUTPUT
1.4V
OUTPUT
1.4V
t5
Input-Output Propagation Delay
INPUT
VDD/2
OUTPUT
VDD/2
t6
Device-Device Skew
CLKOUT, Device 1
CLKOUT, Device 2
VDD/2
VDD/2
t7
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
www.phaselink.com
Rev 12/13/11
Page 6
(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
TEST CIRCUITS
Test Circuit #1
Test Circuit #2
VDD
VDD
0.1 F
OUTPUTS
GND
0.1 F
OUTPUTS
C LOAD
VDD
0.1 F
CLK
GND
1KΩ
1KΩ
VDD
0.1 F
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
GND
10 pF
GND
www.phaselink.com
Rev 12/13/11
Page 7
PL123-05/-09
(Preliminary)
Low Skew Zero Delay Buffer
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOP-16L and TSSOP-16L ( mm )
SOP
Symbol
A
A1
B
C
D
E
H
L
e
Min.
Max.
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
9.80
10.00
3.80
4.00
5.80
6.20
0.40
1.27
1.27 BSC
TSSOP
Min.
Max.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.40 BSC
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
L
B
e
SOP 8L
Symbol
A
A1
A2
B
C
D
E
H
L
e
Dimension in MM
Min.
Max.
1.35
1.75
0.10
0.25
1.25
1.50
0.33
0.53
0.19
0.27
4.80
5.00
3.80
4.00
5.80
6.20
0.40
0.89
1.27 BSC
E
H
D
A2 A
A1
C
e
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
b
www.phaselink.com
L
Rev 12/13/11
Page 8
(Preliminary)
PL123-05/-09
Low Skew Zero Delay Buffer
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
2880 Zanker Road, Suite 103 San Jose, CA 95134
Tel (408) 571-1668 Fax (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL123-0x(H) X X - X
Part Number
H=High Drive
None = Standard Drive
None=Tubes
R=Tape & Reel
Temperature Range
C=Commercial (0°C to 70°C)
I=Industrial (-40°C to 85°C)
Package Type
O=TSSOP
S=SOP
Part/Order Number
(Commercial)
PL123-05SC
PL123-05SC-R
PL123-05HSC
PL123-05HSC-R
PL123-09OC
PL123-09OC-R
PL123-09HOC
PL123-09HOC-R
PL123-09SC
PL123-09SC-R
PL123-09HSC
PL123-09HSC-R
Marking*
(Commercial)
Part/Order Number
(Industrial)
P12305
SC
LLLLL
PL123-05SI
P12305H
SC
LLLLL
PL123-05HSI
P12309
OC
LLLLL
P12309H
OC
LLLLL
PL123-05SI-R
PL123-05HSI-R
PL123-09OI
PL123-09OI-R
PL123-09HOI
PL123-09HOI-R
P12309
SC
LLLLL
PL123-09SI
P12309H
SC
LLLLL
PL123-09HSI
PL123-09SI-R
PL123-09HSI-R
Marking*
(Industrial)
Package Option
P12305
SI
LLLLL
8-Pin SOP Tube
P12305H
SI
LLLLL
8-Pin SOP Tube
P12309
OI
LLLLL
P12309H
OI
LLLLL
8-Pin SOP (Tape
and Reel)
8-Pin SOP (Tape
and Reel)
16-Pin TSSOP
Tube
16-Pin TSSOP
(Tape and Reel)
16-Pin TSSOP
Tube
16-Pin TSSOP
(Tape and Reel)
P12309
SI
LLLLL
16-Pin SOP Tube
P12309H
SI
LLLLL
16-Pin SOP Tube
16-Pin SOP (Tape
and Reel)
16-Pin SOP (Tape
and Reel)
*Note: LLLLL designates lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fu rnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning th e accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or rel iance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life sup port devices or systems without the e xpress written approval of the President of PhaseLink Corporation.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571 -1668 Fax (408) 571-1688
www.phaselink.com
Rev 12/13/11
Page 9