2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output Zero

(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
FEATURES
DESCRIPTION
•
The PL123E-08 is a PLL-based zero-delay buffer family, used to distribute up to eight outputs. Select inputs
S2 and S1 control the state of the two output banks.
•
•
•
•
•
•
•
•
•
Zero input-output propagation delay, adjustable by
capacitive load on FBK input
10 MHz to 220 MHz maximum operating range
Multiple low-skew outputs
─ Low output-output skew
─ One input drives eight outputs, grouped as 4+4
Two banks of four outputs, three-stateable by two
select inputs
Low cycle-to-cycle jitter
Low period jitter
Standard and high drive strength options
16 pin SOP or TSSOP packages
2.5V or 3.3V operation
Commercial and industrial temperature available
An external feedback pin enables removing delay from
external components. It also provides adjustable inputto-output delay by varying its loading relative to the
output pin loading.
Various options are available to multiply the input frequency by 0.5, 1, 2, or 4x (see the Available Configuration table for details). Standard (8 mA) and High (12
mA) drive strengths may also be ordered. In the special case when S2:S1 is 1:0, the PLL is bypassed and
REF is output from DC to the maximum frequency, thus
behaving like a (non-zero delay) fan-out buffer.
These parts are not intended for 5V input-tolerant applications.
BLOCK DIAGRAM
/2
Extra Divider (-083)
Mux
`
CLKA1
CLKA2
CLKA3
CLKA4
Extra
Divider
(-082, -083)
S2
CLKB1
Selector
Decoding
CLKB2
CLKB3
1
16
FBK
2
15
CLKA4
CLKA2
3
14
CLKA3
VDD
4
GND
5
CLKB1
6
CLKB2
7
S2
8
9
13
VDD
12
GND
11
CLKB4
10
CLKB3
S1
Bank B
S1
/2
REF
CLKA1
PL123E-08
Bank A
PLL
REF
FBK
CLKB4
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 1
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
PIN DESCRIPTION
Pin
Name
Type
Description
1
REF[1]
I
Input reference frequency
2
CLKA1[2]
O
Clock output, Bank A
3
CLKA2[2]
O
Clock output, Bank A
4
VDD
P
3.3V (or 2.5V) supply
5
GND
P
Ground
6
CLKB1[2]
O
Clock output, Bank B
7
CLKB2[2]
O
Clock output, Bank B
8
S2[3]
I
Select input, bit 2
9
S1[3]
I
Select input, bit 1
10
CLKB3[2]
O
Clock output, Bank B
11
CLKB4[2]
O
Clock output, Bank B
12
GND
P
Ground
13
VDD
P
3.3V (or 2.5V) supply
14
CLKA3[2]
O
Clock output, Bank A
15
CLKA4[2]
O
Clock output, Bank A
16
FBK
I
PLL feedback input
SELECT INPUT DECODING
S2
0
0
1
1
S1
0
1
0
1
CLK A1–A4
Three-State
Driven
Driven[4]
Driven
CLK B1–B4
Three-State
Three-State
Driven[4]
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
Y
N
Y
N
AVAILABLE CONFIGURATIONS
Device
PL123E-08
PL123E-08H
PL123E-082
PL123E-082
PL123E-083
PL123E-083
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
Bank B Frequency
Reference
Reference
Reference / 2
Reference
Reference or Inverted Reference [5]
2 X Reference
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak pull-up on these inputs.
4: Outputs inverted on PL123E-082 and -083 in bypass mode (S2=1, S1=0).
5: Output is phase indeterminant (0° or 180° from input clock). If phase integrity is required, use PL123E-082.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 2
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
ZERO-DELAY AND SKEW CONTROL
The PLL’s feedback path must be closed by connecting FBK to one of the available eight outputs. The output driving the FBK pin will drive an (internal) output pin load of 5pF plus any additional loading placed on this output pin.
For zero-delay applications, all outputs, including the FBK pin connected to an output pin, must be loaded
equally. Varying the loading between the FBK pin and output pins can adjust the input-to-output delay.
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
Decoupling and Power Supply Considerations
- Keep traces short
- Place decoupling capacitors as close as possible to
the VDD pin(s) to bypass noise from the power
supply
- Trace = Inductor. With a capacitive load, equals
ringing
- Long trace = Transmission Line. Without proper
termination this will cause reflections (causing
ringing).
- Design long traces as “striplines” or “microstrips”
with defined impedance.
- Terminate traces with characteristic impedance of
the trace to avoid reflections (see figure below).
- Multiple VDD pins should be decoupled separately
for best performance.
- Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1μF for designs supporting frequencies below 50MHz
(0.01μF for designs supporting frequencies above
50MHz).
Typical CMOS termination
Place Series Resistor as close as possible to CMOS output
CMOS Output Buffer
(Typical buffer impedance 20Ω)
To CMOS Input
50 Ω line
Series Resistor
Adjust value to match output buffer
impedance to 50 Ω trace. Typical
value 30 Ω.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 3
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
ABSOLUTE MAXIMUM CONDITIONS
Supply Voltage to Ground Potential ...... –0.5V to 4.6V
DC Input Voltage ......................... GND – 0.5V to 4.6V
Storage Temperature ........................ –65°C to 150°C
Junction Temperature ................................... 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015)……………..> 2000V
OPERATING CONDITIONS
Description
Parameter
Min
Max
Unit
Supply Voltage, 3.3V Supplies
V DD
3.0
3.6
V
Supply Voltage, 2.5V Supplies
V DD
2.3
2.7
V
0
70
°C
-40
85
°C
Load Capacitance, <100 MHz, 3.3V Supplies
–
30
pF
Load Capacitance, <100 MHz, 2.5V Supplies with High Drive
–
30
pF
–
22
pF
–
22
pF
Load Capacitance, <133.3 MHz, 2.5V Supplies, Std Drive
–
15
pF
Load Capacitance, >133.3 MHz, 3.3V Supplies
–
15
pF
Load Capacitance, >133.3 MHz, 2.5V Supplies, High Drive
–
15
pF
–
5
pF
Operating Temperature (ambient)—Commercial
Operating Temperature (ambient)—Industrial
TA
Load Capacitance, <133.3 MHz, 3.3V Supplies
Load Capacitance, <133.3 MHz, 2.5V Supplies, High Drive
Input
Capacitance [7]
Closed-loop bandwidth (typical), 3.3V Supplies
Closed-loop bandwidth (typical), 2.5V Supplies
CL
[6]
C IN
BW
Output Impedance (typical), 3.3V Supplies with High Drive
Output Impedance (typical), 3.3V Supplies, Standard Drive
Output Impedance (typical), 2.5V Supplies, High Drive
R OUT
Output Impedance (typical), 2.5V Supplies, Standard Drive
Power-up time for all V DD ’s to reach minimum specified
voltage (power ramps must be monotonic)
t PU
TBD
MHz
TBD
MHz
TBD
Ω
TBD
Ω
TBD
Ω
TBD
Ω
0.01
50
ms
Dissipation, Junction to Ambient, 16-pin SOP
Theta Ja [8]
TBD
°C/W
Dissipation, Junction to Ambient, 16-pin TSSOP
Theta Ja [8]
TBD
°C/W
Dissipation, Junction to Case, 16-pin SOP
Theta Jc [8]
TBD
°C/W
Dissipation, Junction to Case, 16-pin TSSOP
Theta Jc [8]
TBD
°C/W
Notes:
6. Applies to Test Circuit #1.
7. Applies to both REF Clock and FBK input.
8. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 4
PL123E-08
(Preliminary)
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
3.3V DC ELECTRICAL SPECIFICATIONS
Description
Parameter
Test Conditions
Min
Max
Unit
Supply Voltage
V DD
3
3.6
V
Input LOW Voltage
V IL
–
0.8
V
Input HIGH Voltage
V IH
2.0
V DD + 0.3
V
Input Leakage Current
I IL
0 < V IN < V IL
–
±10
µA
Input HIGH Current
I IH
V IN = V DD
–
100
µA
Output LOW Voltage
V OL
Output HIGH Voltage
V OH
–
–
2.4
2.4
0.4
0.4
–
–
V
V
V
V
Power Down Supply
Current
I DD (PD mode)
REF = 0 MHz (Commercial)
–
12
µA
REF = 0 MHz (Industrial)
–
25
µA
Unloaded outputs, 66-MHz REF
–
30
mA
Min
Max
Unit
Supply Current
I DD
I OL = 8 mA (Standard Drive)
I OL = 12 mA (High Drive)
I OH = –8 mA (Standard Drive)
I OH = –12 mA (High Drive)
2.5V DC ELECTRICAL SPECIFICATIONS
Description
Parameter
Test Conditions
Supply Voltage
V DD
2.3
2.7
V
Input LOW Voltage
V IL
–
0.7
V
Input HIGH Voltage
V IH
1.7
V DD + 0.3
V
Input Leakage Current
I IL
0<V IN < V DD
–
10
µA
Input HIGH Current
I IH
V IN = V DD
–
100
µA
Output LOW Voltage
V OL
Output HIGH Voltage
V OH
–
–
V DD – 0.6
V DD – 0.6
0.5
0.5
–
–
Power Down Supply
Current
I DD (PD mode)
REF = 0 MHz (Commercial)
–
12
µA
REF = 0 MHz (Industrial)
–
25
µA
Unloaded outputs, 66-MHz REF
–
45
mA
Supply Current
I DD
I OL = 8 mA (Standard Drive)
I OL = 12 mA (High Drive)
I OH = –8 mA (Standard Drive)
I OH = –12 mA (High Drive)
V
V
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PL123E-08
(Preliminary)
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS
Description
Parameter Test Conditions
Maximum Frequency [9]
(Input/Output)
1/t 1
Input Duty Cycle
T IDC
Output Duty Cycle [10]
t2 ÷ t1
Rise, Fall Time
(3.3V Supplies) [10]
t3, t4
Rise, Fall Time
(2.5V Supplies) [10]
Output to Output Skew
t3, t4
[10]
Delay, REF Rising Edge
to FBK Rising Edge [10]
Part to Part Skew [10]
PLL Lock Time [10]
t5
Min
Typ
Max
Unit
3.3V Supplies, High Drive
10
–
220
MHz
3.3V Supplies, Standard Drive
10
–
167
MHz
2.5V Supplies, High Drive
10
–
200
MHz
2.5V Supplies, Standard Drive
10
–
134
MHz
<133.3 MHz
25
–
75
%
>133.3 MHz
40
–
60
%
<133.3 MHz
47
–
53
%
>133.3 MHz
45
–
55
%
Standard Drive, CL = 30 pF, <100 MHz
–
–
1.6
ns
Standard Drive, CL = 22 pF, <133.3 MHz
–
–
1.6
ns
Standard Drive, CL = 15 pF, <167 MHz
–
–
0.6
ns
High Drive, CL = 30 pF, <100 MHz
–
–
1.2
ns
High Drive, CL = 22 pF, <133.3 MHz
–
–
1.2
ns
High Drive, CL = 15 pF, >133.3 MHz
–
–
0.5
ns
Standard Drive, CL = 15 pF, <133.33 MHz
–
–
1.5
ns
High Drive, CL = 30 pF, <100 MHz
–
–
2.1
ns
High Drive, CL = 22 pF, <133.3 MHz
–
–
1.3
ns
High Drive, CL = 15 pF, >133.3 MHz
All outputs equally loaded, 3.3V supplies,
2.5V supplies with standard drive
All outputs equally loaded, 2.5V supplies
with high drive
–
–
1.2
ns
–
TBD
100
ps
–
–
110
ps
4.4
ns
PLL Bypass mode (S2:S1=1:0)
t6
t7
t LOCK
1.5
PLL enabled @ 3.3V
–100
–
100
ps
PLL enabled @ 2.5V
–200
–
200
ps
Measured at V DD /2 on FBK pins of devices.
3.3V supplies.
–
–
±150
ps
Measured at V D D /2 on FBK pins of devices.
2.5V supplies.
–
–
±300
ps
Stable power supply, valid clocks presented on REF and FBK pins
–
–
1.0
ms
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 6
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS (continued)
Description
Parameter Test Conditions
Min
Typ
Max
Unit
3.3V Supplies, >66 MHz, <15 pF
–
TBD
55
ps
3.3V Supplies, >66 MHz, <30 pF, Std Drive
–
TBD
125
ps
3.3V Supplies, >66 MHz, <30 pF, High Drive
–
TBD
100
ps
2.5V Supplies, >66 MHz, <15 pF, Std Drive
–
TBD
95
ps
–
TBD
65
ps
–
TBD
145
ps
–
TBD
–
ps
S2:S1 = 1:0, 3.3V, <15pF, High Drive
–
TBD
–
ps
S2:S1 = 1:0, 2.5V, <15pF, Standard Drive
–
TBD
–
ps
S2:S1 = 1:0, 2.5V, <15pF, High Drive
–
TBD
–
ps
3.3V Supplies, >66 MHz, < 15 pF
–
–
100
ps
–
–
180
ps
–
TBD
–
ps
–
TBD
–
ps
3.3V Supplies, 66–100 MHz, <15 pF
–
TBD
75
ps
3.3V Supplies, >100 MHz, <15 pF
–
TBD
45
ps
3.3V Supplies, >66 MHz, <30 pF, Std Drive
–
TBD
100
ps
3.3V Supplies, >66 MHz, <30 pF, High Drive
–
TBD
70
ps
–
TBD
60
ps
–
TBD
60
ps
2.5V Supplies, >100 MHz, <15 pF, High Drive
–
TBD
45
ps
S2:S1 = 1:0, 3.3V, <15pF, Standard Drive
–
TBD
–
ps
S2:S1 = 1:0, 3.3V, <15pF, High Drive
–
TBD
–
ps
S2:S1 = 1:0, 2.5V, <15pF, Standard Drive
–
TBD
–
ps
S2:S1 = 1:0, 2.5V, <15pF, High Drive
–
TBD
–
ps
3.3V Supplies, >66 MHz, < 15 pF
–
–
130
ps
2.5V Supplies, >66 MHz, < 15 pF
Period Jitter, Peak
T PER [10,11]
(-082, -083)
S2:S1 = 1:0, 3.3V, <15 pF, Standard Drive
–
–
110
ps
–
TBD
–
ps
S2:S1 = 1:0, 2.5V, <15 pF, Standard Drive
–
TBD
–
ps
Cycle-to-Cycle Jit2.5V Supplies, >66 MHz, <15 pF, High Drive
ter, Peak
T JCC [10,11]
2.5V Supplies, >66 MHz, <30 pF, High Drive
(-08, -08H)
S2:S1 = 1:0, 3.3V, <15pF, Standard Drive
Cycle-to-Cycle Jit2.5V Supplies, >66 MHz, < 15 pF
ter, Peak
T JCC [10,11]
S2:S1 = 1:0, 3.3V, <15 pF, Standard Drive
(-082, -083)
S2:S1 = 1:0, 2.5V, <15 pF, Standard Drive
2.5V Supplies, >66 MHz, <15 pF, Std Drive
Period Jitter, Peak
(-08, -08H)
T PER [10,11] 2.5V Supplies, 66–100 MHz, <15 pF, High Drive
Notes:
9. For the given maximum loading conditions. See C L in Operating Conditions Table.
10. Parameter is guaranteed by design and characterization. Not 100% tested in production.
11. Typical jitter is measured at 3.3V or 2.5V, 29°C, with all outputs driven into the maximum specified load.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 7
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
SWITCHING WAVEFORMS
Duty Cycle Timing
t1
t2
VDD/2
VDD/2
All Outputs Rise/Fall Time
OUTPUT
2.0V(1.8V)
2.0V(1.8V)
0.8V(0.6V)
0.8V(0.6V)
t3
3.3V (2.5V)
0V
t4
Output-Output Skew
OUTPUT
VDD/2
OUTPUT
VDD/2
t5
Input-Output Propagation Delay
INPUT
VDD/2
FBK
VDD/2
t6
Device-Device Skew
FBK, Device 1
FBK, Device 2
VDD/2
VDD/2
t7
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 8
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
TEST CIRCUITS
Test Circuit #1
VDD
0.1 μF
CLK OUT
OUTPUTS
C LOAD
VDD
0.1 μF
GND
GND
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
16 PIN Narrow SOP, TSSOP ( mm )
SOP
TSSOP
Symbol
Min.
Max.
A
A
1
B
1.35
1.75
-
1.20
0.10
0.25
0.05
0.15
0.33
0.51
0.19
0.30
C
0.19
0.25
0.09
0.20
D
9.80
10.00
4.90
5.10
E
3.80
4.00
4.30
H
5.80
6.20
L
0.40
e
1.27
1.27 BSC
Min.
E
H
Max.
D
4.50
6.40 BSC
0.45
0.75
0.65 BSC
A
1
A
C
e
B
L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 9
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Part/Order Number
PL123E-08HOC
PL123E-08HOC-R
PL123E-08SC
PL123E-08SC-R
PL123E-08HSC
PL123E-08HSC-R
PL123E-082SC
PL123E-082SC-R
PL123E-083SC
PL123E-083SC-R
Marking
P123E-08H
P123E-08H
P123E-08
P123E-08
P123E-08H
P123E-08H
P123E-082
P123E-082
P123E-083
P123E-083
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
Package Option
Operating Range
TSSOP Tube
TSSOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Continued on next page
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 10
(Preliminary)
PL123E-08
2.5V or 3.3V, 10-220 MHz, Low Jitter, 8-Output
Zero Delay Buffer
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT) (continued)
(continued)
PART NUMBER
Part/Order Number
PL123E-08HOI
PL123E-08HOI-R
PL123E-08SI
PL123E-08SI-R
PL123E-08HSI
PL123E-08HSI-R
PL123E-082SI
PL123E-082SI-R
PL123E-083SI
PL123E-083SI-R
Marking
P123E-08H
P123E-08H
P123E-08
P123E-08
P123E-08H
P123E-08H
P123E-082
P123E-082
P123E-083
P123E-083
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
16-Pin
Package Option
Operating Range
TSSOP Tube
TSSOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
SOP Tube
SOP (Tape and Reel)
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
PhaseLink Corporation reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 11