PL610-01-02-03 Die

(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
FEATURES
DESCRIPTION
 Single die, wide frequency coverage, programmable
advanced oscillator design.
 Single IC to cover up to 130MHz output frequency.
 Direct oscillation operation with optional
programmable features:
o ±50ppm Frequency Tuning
o Output Drive Setting (4, 8, or 16mA)
o 6-bit Odd/Even Output Divider (< 63)
 Input Frequency: Fundamental crystal:
o 5MHz to 60MHz (Default)
o 60MHz to 130MHz (programming option)
 Output Frequency: LVCMOS
o 80kHz to 130MHz
 Wire Bond and Flip Chip options to choose from.
 Very low Jitter and Phase Noise
 Low current consumption
 Single 1.8V, 2.5V, or 3.3V ± 10% power supply
 Operating temperature range from -40C to 85C
The PL610 is a high performance general purpose
clock that uses a single die to cover outputs up to
130MHz, eliminating the need for multiple ICs to
cover a wide frequency range. Designed to fit in a
small 2.0 x 1.6mm, or larger substrates, the PL610
offers the best phase noise and jitter performance,
smallest die size, and lowest power consumption of
any comparable IC.
The optional ‘frequency fine tuning’ feature of PL610
allows for frequency adjustment after encapsulation
of the module, up to ±50ppm. In addition, there is a
‘6’ bit optional programmable Odd/Even divider
(default= ٪1), and ‘3’ programmable output drive
strengths (4mA, 8mA (default), 16mA) to choose
from. The full feature set of PL610 makes it the
most versatile XO for any application.
BLOCK DIAGRAM
KEY PROGRAMMING PARAMETERS
CLK[0:1]
Output Frequency
CLK0 = F REF , F REF /2 or F REF / P
Where P = 6-bit
Optional
CLK1 = F REF , F REF /2 or CLK0
Crystal Load
Output Drive Strength
Output Dividers
Optional ‘Frequency Tuning’ Three optional drive
Optional 6-bit
after encapsulation, up to:
strengths to choose from: Odd/Even
output divider:
±50ppm Tuning Range
 Low: 4mA
Single bit CL adjustment
 ٪1 (default) to ٪63
 Std: 8mA (default)
for Hi/Low frequency input
 High: 16mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 1
(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
DIE SPECIFICATION
Chip Size
Chip Thickness
Pad Size
Chip Base
0.65x 0.60mm
Optional
90µm
GND level
PAD ASSIGNMENT AND SPECIFICATION
PL610-01
0.60
(650µmx600µm
)
0.65
XIN
1
OE^, PDB^,
CLK1
2
GND
3
X
XOUT
6
PL610-01
(Wire Bond)
5
VDD
4
CLK0
Note: ^ denotes internal pull up
Y
PL610-02
0.60
(650µmx600µm
)
XOUT
1
2
CLK0
3
0.65
VDD
X
XIN
6
PL610-02
(Flip Chip)
5
OE^, PDB^,
CLK1
4
GND
Note: ^ denotes internal pull up
Y
PL610-03
0.60
(650µmx600µm
)
0.65
XIN
1
GND
2
CLK0
3
X
XOUT
6
PL610-03
5
OE^, PDB^,
CLK1
4
VDD
Note: ^ denotes internal pull up
Y
Pad
#
Pad Name
1
Pad Center
X
Y
XIN
-177
231
2
OE, PDB, CLK1
-215
41
3
GND
-215
-186
4
CLK0
215
-186
5
VDD
215
41
6
XOUT
177
231
Pad
#
Pad Name
1
Pad Center
X
Y
XOUT
-177
231
2
VDD
-215
41
3
CLK0
-215
-186
4
GND
215
-186
5
OE, PDB, CLK1
215
41
6
XIN
177
231
Pad
#
Pad Name
1
Pad Center
X
Y
XIN
-177
231
2
GND
-215
41
3
CLK0
-215
-186
4
VDD
215
-186
5
OE, PDB, CLK1
215
41
6
XOUT
177
231
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 2
(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
PAD FUNCTION DESCRIPTION
Pad Name
Description
CLK0
Programmable Clock Output.
GND
GND connection
Programmable as:
Output Enable (OE) – Enables/Disables CLK0 output buffer
Power Down (PDB) – Enables/Disables CLK0 output buffer and crystal oscillator circuitry
CLK1 – Second Clock Output
OE^, PDB^, CLK1
VDD
VDD connection
XIN
Crystal input pad
XOUT
Crystal Output pad
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
7
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
C
-40
85
C
Supply Voltage Range
Ambient Operating Temperature*
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied. * Operating Temperature is guaranteed by design for all parts but tested for COMMERCIAL grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Fundamental Crystal, Low Frequency
5
60
Fundamental Crystal, High Frequency
60
130
.080
130
MHz
-2
2
ppm
Output Frequency
@ V DD = 1.8V to 3.3V, ±10%
VDD Sensitivity
Frequency vs. V DD +/-10%
MHz
Output Rise Time (See MTC-1) 15pF Load, 10/90%V DD , High Drive, 3.3V
1
1.2
ns
Output Fall Time (See MTC-1) 15pF Load, 90/10%V DD , High Drive, 3.3V
1
1.2
ns
50
55
%
Duty Cycle* (See MTC-1)
45
* For 1.8V operation, the 50% ±5% duty cycle is guaranteed for frequencies ≤40MHz.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 3
(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
DC SPECIFICATIONS
PARAMETERS
SYMBOL
Supply Current, Dynamic,
Loaded LVCMOS Output
I DD
Supply Current, Dynamic,
Unloaded LVCMOS Output
CONDITIONS
MIN.
TYP.
@ V DD =3.3V, 40MHz, load=15pF
3.7
@ V DD =2.5V, 40MHz, load=15pF
2.75
@ V DD =1.8V, 40MHz, load=15pF
2.0
@ V DD =3.3V, 26MHz, load=15pF
2.5
@ V DD =2.5V, 26MHz, load=15pF
1.8
@ V DD =1.8V, 26MHz, load=15pF
1.3
@ V DD =3.3V, 40MHz, no load
1.65
@ V DD =2.5V, 40MHz, no load
1.2
@ V DD =1.8V, 40MHz, no load
0.9
@ V DD =3.3V, 26MHz, no load
1.2
@ V DD =2.5V, 26MHz, no load
0.8
@ V DD =1.8V, 26MHz, no load
0.58
Operating Voltage
V DD
Power Supply Ramp
t PU
Time for V DD to reach 90% V DD .
Power ramp must be monotonic.
Output Low Voltage
V OL
I OL = +4mA Standard Drive
Output High Voltage
V OH
I OH = -4mA Standard Drive
Output Current, Low Drive *
I OLD
V OL = 0.4V, V OH = 2.4V
±4
Output Current, Std Drive*
I OSD
V OL = 0.4V, V OH = 2.4V
±8
Output Current, High Drive*
I OHD
V OL = 0.4V, V OH = 2.4V
±16
MAX.
UNITS
mA
mA
1.62
3.63
V
.001
100
ms
0.4
V
V DD – 0.4
V
mA
*Note: See MCT-2 below
CRYSTAL SPECIFICATIONS (5MHz to 60MHz)
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
SYMBOL
MIN.
F XIN
C L (xtal)
TYP.
MAX.
UNITS
5
60
MHz
8
12
pF
100
W
Maximum Sustainable Drive Level
Operating Drive Level
Crystal Shunt Capacitance
Effective Series Resistance, 5MHz to 60MHz, (See MTC-1)
W
25
C0
3
pF
ESR
50
Ω
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 4
(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
CRYSTAL SPECIFICATIONS (60MHz to 130MHz)
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
SYMBOL
MIN.
F XIN
C L (xtal)
TYP.
MAX.
UNITS
60
130
MHz
5
8
pF
100
W
Maximum Sustainable Drive Level
Operating Drive Level
W
25
Crystal Shunt Capacitance
Effective Series Resistance, 60MHz to 130MHz, (See MTC-1)
C0
2.5
pF
ESR
30
Ω
@1M
UNITS
PHASE NOISE SPECIFICATIONS (See MCT-3)
PARAMETERS
FREQ.
@1Hz
@10Hz @100Hz @1kHz @10kHz @100kHz
Phase Noise relative
to carrier (typical)
40.0MHz
-67
-98
-127
-142
-151
-155
-155
26.0MHz
-65
-96
-124
-145
-150
-155
-155
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 5
(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
MEASUREMENT TEST CIRCUITS (MTC)
MTC-1: Rise Time, Fall Time, Duty Cycle, VOL, VOH, Idd,
Power Down Current, Output Enable/Disable
A
0.1µF
0.1µF
VDD
VDD
XIN
XIN
FET
Probe
CLK
XOUT
OE^
GND
MTC-3: Jitter and Phase Noise
CLK
XOUT
OE^
GND
CL
MTC-2: Output Drive Current and Output Impedance
MTC-4: Negative Resistance
0.1µF
VDD
Network
Analyzer
VDD
XIN
XIN
0.1µF
CLK
XOUT
CLK
XOUT
OE^
0.1µF
R
FET
Probe
OE^
GND
GND
0.1µF
V
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 6
(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
WAVEFORM SWITCHING CHARACTERISTICS
Rise and Fall times:
90%VDD
10% VDD
tr
tf
Duty Cycle:
50% VDD
Duty Cycle = 100% ×
Tw
T
Tw
T
VOH, VOL:
VDD
VOH
VOL
GND
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 7
(Preliminary)
1.8V-3.3V Single IC XO with Frequency Tuning (5MHz to 130MHz)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Part / Order Number
Marking
Package Option
Temperature
PL610-01DxC
Die (Waffle Pack)
0°C to +70°C
PL610-01ExC
Die (Waffle Pack)
0°C to +70°C
PL610-01VxC
Wafer
0°C to +70°C
PL610-01WxC
Wafer
0°C to +70°C
PL610-02DxC
Die (Waffle Pack)
0°C to +70°C
PL610-02ExC
Die (Waffle Pack)
0°C to +70°C
PL610-02VxC
Wafer
0°C to +70°C
PL610-02WxC
Wafer
0°C to +70°C
PL610-03DxC
Die (Waffle Pack)
0°C to +70°C
PL610-03ExC
Die (Waffle Pack)
0°C to +70°C
PL610-03VxC
Wafer
0°C to +70°C
PL610-03WxC
Wafer
0°C to +70°C
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 08/10/09 Page 8