PL610 Series (Preliminary)

PL610 Series
(Preliminary)
1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby
FEATURES
DESCRIPTION
• Single IC to cover up to 60MHz output frequency.
• Direct oscillation operation
• Input Frequency: Fundamental crystal:
o 10MHz to 60MHz
• Output Frequency: LVCMOS
o 312.5KHz to 60MHz (2.5V & 3.3V)
o 312.5KHz to 40MHz (1.8V)
• 3 pad layout options
o PL610Ax series: for Flip Chip bonding
o PL610Bx series: for wire bonding Type1
o PL610Cx series: for wire bonding Type2
• Integrated Automatic Level Control (ALC) to maintain
constant drive level.
• Very low Jitter and Phase Noise
• High impedance standby function, <5uA
• Low current consumption
• Single 1.8V to 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
The PL610 Series is a family of high performance
general purpose oscillators to cover outputs from
312.5KHz up to 60MHz. Designed to fit in a small
2.0x1.6mm, or larger substrates, the PL610 Series
offers the best phase noise and jitter performance,
smallest die size, and lowest power consumption of
any comparable IC. With its Standby function, the
PL610 family of products draw <5µA.
BLOCK DIAGRAM
/1, /2, /4, /8, /16,
/32, /64
XTAL
OSC
XT
XTN
Q
INHN
1
VDD
2
Q
3
XT
6
PL610Ax
5
INHN^
4
VSS
XT
650um
650um
XTN
600um
INHN^
VSS
Note: ^ denotes internal pull up
600um
1
2
3
XTN
6
PL610Bx
5
VDD
4
Q
XTN
650um
600um
1
VSS
2
Q
3
Note: ^ denotes internal pull up
XT
6
PL610Cx
5
INHN^
4
VDD
Note: ^ denotes internal pull up
PAD ASSIGNMENT (Pad locations are measured from the center of the die)
Pad #
1
2
3
4
5
6
PL610Ax
XTN
VDD
Q
VSS
INHN^
XT
Pad Name
PL610Bx
XT
INHN^
VSS
Q
VDD
XTN
Pad Center*
PL610Cx
X
Y
XTN
VSS
Q
VDD
INHN^
XT
-177
-215
-215
215
215
177
231
41
-186
-186
41
231
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com
03/01/2011
Page 1
PL610 Series
(Preliminary)
1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby
DIE SPECIFICATION
PAD DESCRIPTION
Pad
Name
XT
Crystal input pad
VSS
GND connection
Q
VDD
INHN
XTN
Parameter
Description
Clock output
VDD connection
Output control input. When activated
(Logic “0”) INHN will Tristate (HiZ),
disabling the oscillator and the output.
10ML internal pull up resistor.
Crystal output pad
Value
Chip size
0.65x 0.60mm
Chip thickness
130um, ±15um
Pad size
90µm
Chip base
GND level
Optional
(see ordering information)
Die back coating
PL610 Series Configurations
Output Cload
Operating
Pad
Drive (pF)
Voltage
Layout
(mA)
Flip Chip
Bonding
1.8V to
3.3V
(±10%)
8
8
Wire
Bonding
Type 1
Wire
Bonding
Type 2
F XT
F XT /2
F XT /4
F XT /8
F XT /16
F XT /32
F XT /64
PL610A1
PL610A2
PL610A3
PL610A4
PL610A5
PL610A6
PL610A7
PL610B1
PL610B2
PL610B3
PL610B4
PL610B5
PL610B6
PL610B7
PL610C1
PL610C2
PL610C3
PL610C4
PL610C5
PL610C6
PL610C7
03/01/2011
Page 2
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com
PL610 Series
(Preliminary)
1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
°C
-40
85
°C
Supply Voltage Range
Ambient Operating Temperature*
ESD Protection, Human Body Model
2
KV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XT)
Output Frequency
CONDITIONS
Fundamental Crystal (2.5V & 3.3V)
Fundamental Crystal (1.8V)
3.3V & 2.5V operation
1.8V operation
MIN.
TYP.
MAX.
60
10
40
60
0.3125
40
UNITS
MHz
MHz
Settling Time
At power-up (VDD > 90%V DD )
2
ms
Output Disable Delay Time
Temp=25
50
µs
Output Rise/Fall Time
(See MTC-1)
3.3V, 15pF Load, 10/90%V DD
1.7
2.2
ns
Output Rise/Fall Time
(See MTC-1)
2.5V, 15pF Load, 10/90%V DD
2
2.5
ns
Output Rise/Fall Time
(See MTC-1)
1.8V, 15pF Load, 10/90%V DD
3
3.5
ns
50
55
%
℃, 15pF Load
Duty Cycle* (See MTC-1)
45
* For 1.8V operation, the 50% ±5% duty cycle is guaranteed for frequencies ≤40MHz.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com
03/01/2011
Page 3
PL610 Series
(Preliminary)
1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby
DC SPECIFICATIONS
PARAMETERS
SYMBOL
Supply Current, Dynamic
Standby Supply Current
I DD
I DD_SB
CONDITIONS
MIN.
TYP.
@V DD =3.3V, 27MHz, No Load
1.2
@V DD =3.3V, 40MHz, No Load
1.7
@V DD =1.8V, 27MHz, No Load
0.6
@V DD =1.8V, 40MHz, No Load
0.9
INHN=”0”, 3.3V
MAX.
mA
1
Operating Voltage
V DD
Power Supply Ramp
t PU
Output Low Voltage
V OL
Time for V DD to reach 90% V DD .
Power ramp must be monotonic.
I OL = +4mA
Output High Voltage
V OH
I OH = -4mA
Output Current(See MCT-2)
I OHD
V OL = 0.4V, V OH = 2.4V
UNITS
uA
1.62
3.63
V
.001
100
ms
0.4
V
V DD – 0.4
V
8
mA
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency (2.5V & 3.3V)
Fundamental Crystal Resonator Frequency (1.8V)
Crystal Loading Rating
SYMBOL
MIN.
F XT
10
C L (xtal)
TYP.
60
40
8
Maximum Sustainable Drive Level
Effective Series Resistance, Fundamental, (See MTC-3)
UNITS
MHz
pF
100
Operating Drive Level @ Frequency <40MHz
Crystal Shunt Capacitance
MAX.
25
µW
µW
C0
3
pF
ESR
50
Ω
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com
03/01/2011
Page 4
PL610 Series
(Preliminary)
1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby
MEASUREMENT TEST CIRCUITS (MTC)
MTC-1: Rise Time, Fall Time, Duty Cycle, VOL, VOH, Idd,
Power Down Current, Output Enable/Disable
A
VDD
0.1µF
Network
Analyzer
VDD
XIN
FET
Probe
CLK
XOUT
OE^
GND
MTC-3: Negative Resistance
XIN
0.1µF
CLK
XOUT
OE^ GND
CL
MTC-2: Output Drive Current and Output Impedance
0.1µF
VDD
XIN
CLK
XOUT
OE^
FET
Probe
GND
0.1µF
V
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com
03/01/2011
Page 5
PL610 Series
(Preliminary)
1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby
WAVEFORM SWITCHING CHARACTERISTICS
Rise and Fall time:
90%VDD
10% VDD
tr
tf
Duty Cycle:
50% VDD
Duty Cycle = 100% ×
Tw
T
Tw
T
VOH, VOL:
VDD
VOH
VOL
GND
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com
03/01/2011
Page 6
PL610 Series
(Preliminary)
1.8V to 3.3V XO IC’s for 312.5kHz to 60MHz, with Standby
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
2880 Zanker Road, San Jose, CA 95134, USA
Tel: (408) 571-1668 Fax: (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
PL610XX-XX
Pad Layout
A: flip chip
B: wire bonding type 1
C: wire bonding type 2
D5: Die form with 5mil thickness
W5: Sawed wafer with 5mil thickness
W8: Un-sawed wafer with 8mil thickness
Q8: ¼ wafer with 8mil thickness
Divider Selection
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com
03/01/2011
Page 7