PL135-27 - Phaselink.com

PL135-27
Low Power, 1.62V to 3.63V, 10MHz TO 40MHz, 1:2 Oscillator Fanout Buffer
FEATURES
DESCRIPTION
 Advanced Oscillator Design for Wide Frequency
Coverage
 2 LVCMOS Outputs
 8 mA Output Drive Strength
 Input/Output Frequency:
o Fundamental Crystal: 10MHz to 40MHz
 Very Low Jitter and Phase Noise
 Low Current Consumption
 Single 1.62V to 3.63V Power Supply
 Available in DFN-6L GREEN/RoHS Compliant
Package
The PL135-27 is an advanced oscillator fanout
buffer design for high performance, low-power,
small form-factor applications. The PL135-27
accepts a fundamental crystal input of 10MHz to
40MHz and produces two LVCMOS outputs of the
same frequency. The PL135-27 is designed to fit in
a small 2 x 1.3mm DFN package, and offers the
best phase noise and jitter performance and lowest
power consumption of any comparable IC.
PACKAGE PIN CONFIGURATION
BLOCK DIAGRAM
2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com Rev 02/14/11 Page 1
PL135-27
Low Power, 1.62V to 3.63V, 10MHz TO 40MHz, 1:2 Oscillator Fanout Buffer
PACKAGE PIN ASSIGNMENT
Name
Package Pin #
DFN-6L
Type
Description
XIN
1
I
Crystal input
CLK1
2
O
Clock output
GND
3
P
GND connection
CLK0
4
O
Clock output
VDD
5
P
V DD connection
XOUT
6
O
Crystal output
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design:
Signal Integrity and Termination Considerations
Decoupling and Power Supply Considerations
- Keep traces short!
- Place decoupling capacitors as close as possible to
the V DD pin(s) to limit noise from the power supply
- Trace = Inductor. With a capacitive load this equals
ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections (looks like ringing).
- Design long traces as “striplines” or “microstrips” with
defined impedance.
- Match trace at one side to avoid reflections bouncing
back and forth.
- Multiple V DD pins should be decoupled separately
for best performance.
- Addition of a ferrite bead in series with V DD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency
dependant. Typical value to use is 0.1F.
Crystal Tuning Circuit
Series and parallel capacitors used to fine tune the crystal load to the circuit load.
Crystal
Cst
XIN
XOUT
1
Cpt
8
Cpt
CST – Series Capacitor, used to lower circuit load to match crystal load. Raises frequency offset.
This can be eliminated by using a crystal with a Cload of equal or greater value than the oscillator.
CPT – Parallel Capacitors, Used to raise the circuit load to match the crystal load. Lowers
frequency offset.
2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com Rev 02/14/11 Page 2
PL135-27
Low Power, 1.62V to 3.63V, 10MHz TO 40MHz, 1:2 Oscillator Fanout Buffer
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
V DD
-0.5
4.6
V
Input Voltage Range
VI
-0.5
V DD +0.5
V
Output Voltage Range
VO
-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
C
-40
85
C
Supply Voltage Range
Ambient Operating Temperature*
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
CONDITIONS
MIN.
TYP.
10
MAX.
UNITS
40
MHz
2
ms
0.5
ppm
Crystal Input Frequency
Fundamental crystal
Settling Time
At Power-Up (V DD > 1.62V)
V DD Sensitivity
Frequency vs. V DD , ±10%
Output Rise Time
15pF Load, 10/90% V DD , 3.3V
2
3
ns
Output Fall Time
15pF Load, 90/10% V DD , 3.3V
2
3
ns
Output to Output Skew
Under all conditions
500
ps
Duty Cycle
Under all conditions
-0.5
45
50
55
%
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic
SYMBOL
I DD
CONDITIONS
V DD = 3.3V, 25MHz, No Load
1.6
mA
V DD = 2.5V, 25MHz, No Load
1.2
mA
V DD = 1.8V, 25MHz, No Load
0.9
mA
Operating Voltage
V DD
1.62
Output Low Voltage
V OL
I OL = +4mA, 3.3V
Output High Voltage
V OH
I OH = -4mA, 3.3V
Output Current
I OSD
V OL = 0.4V, V OH = 2.4V
2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688
3.63
V
0.4
V
2.4
V
8
mA
www.phaselink.com Rev 02/14/11 Page 3
PL135-27
Low Power, 1.62V to 3.63V, 10MHz TO 40MHz, 1:2 Oscillator Fanout Buffer
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
SYMBOL
MIN.
F XIN
10
C L (xtal)
Small SMD Crystal
MAX.
UNITS
40
MHz
12
Operating Drive Level
Metal Can Crystal
TYP.
pF
0.1
Shunt Capacitance
ESR Max
Shunt Capacitance
ESR Max
2
mW
C0
5.5
pF
ESR
40
Ω
C0
2.5
pF
ESR
60
Ω
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
DFN-6L
D1
Symbol
A
A1
A3
b
e
D
E
D1
E1
L
Dimension in MM
Min.
Max.
0.45
0.60
0.00
0.05
0.152
0.152
0.15
0.25
0.40BSC
1.25
1.35
1.95
2.05
0.75
0.85
0.95
1.05
0.20
0.30
b
e
D
Pin 6 ID
Chamfer
E
E1
L
Pin1 Dot
A A1
2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688
A3
www.phaselink.com Rev 02/14/11 Page 4
PL135-27
Low Power, 1.62V to 3.63V, 10MHz TO 40MHz, 1:2 Oscillator Fanout Buffer
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
2880 Zanker Rd., San Jose, CA 95134, USA
Tel: (408) 571-1668 Fax: (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Part/Order Number
PL135-27GC-R
Marking
J27
LLL
Package Option
6-Pin DFN (Tape and Reel)
*Note:LLL designates lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688
www.phaselink.com Rev 02/14/11 Page 5