(Preliminary) PL123-04 3.3V Zero Delay Buffer FEATURES DESCRIPTION • The PL123-04 is a PLL-based zero-delay buffer, used to distribute up to four outputs. An external feedback pin enables removing delay from external components. It also provides adjustable input-to-output delay by varying its loading relative to the output pin loading. • • • • • • • Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations, see “Available Configurations” table Multiple low-skew outputs 10 MHz to 134 MHz operating range Low cycle-to-cycle jitter 8 pin SOP package 3.3V operation Commercial and industrial temperature available The PL123-042 option allows the user to obtain x1, x2, or x0.5 frequencies on the output bank. The exact multiplier depends on which output is connected to the FBK pin. Refer to the Available Configurations table below for more details. These parts are not intended for 5V input-tolerant applications. BLOCK DIAGRAM FBK REF CLKA1 PLL /2 REF 1 CLKA1 2 CLKA2 3 VDD 4 PL123-04 CLKA2 Extra Divider (-042) 8 Pin SOP Top View 8 FBK 7 VDD 6 CLKB2 5 CLKB1 CLKB1 CLKB2 AVAILABLE CONFIGURATIONS Device PL123-04 PL123-042 PL123-042 Feedback From Bank A or Bank B Bank A Bank B Bank A Frequency Reference Reference 2 x Reference Bank B Frequency Reference Reference / 2 Reference 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 1 (Preliminary) PL123-04 3.3V Zero Delay Buffer PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 Name REF[1] CLKA1[2] CLKA2[2] GND CLKB1[2] CLKB2[2] VDD FBK Type I O O P O O P I Description Input reference frequency Clock output, Bank A Clock output, Bank A Ground Clock output, Bank B Clock output, Bank B 3.3V Supply PLL feedback input Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. The PLL’s feedback path must be closed by connecting FBK to one of the available four outputs. The output driving the FBK pin will drive an (internal) pin load of 7pF plus any additional loading placed on this output pin. For zero-delay applications, all outputs, including the FBK pin connected to an output pin, must be loaded equally. Varying the loading between the FBK pin and output pins can adjust the input-to-output delay. MAXIMUM RATINGS Supply Voltage to Ground Potential……………-0.5V to 4.6V DC Input Voltage (Except REF)…..…..…-0.5V to VDD+0.5V DC Input Voltage REF…………………………….-0.5V to 4.6V Storage Temperature………………………...…..-65 to 150 °C Junction Temperature…………………………………….150 °C Static Discharge Voltage (MIL-STD-883, Method 3015). .> 2KV 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 2 (Preliminary) PL123-04 3.3V Zero Delay Buffer LAYOUT RECOMMENDATIONS The following guidelines assist in optimizing a PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short - Place decoupling capacitors as close as possible to the VDD pin(s) to bypass noise from the power supply - Trace = Inductor. Adding a capacitive load may cause ringing. - Long trace = Transmission Line. Without proper termination this will cause reflections (causing ringing). - Design long traces as “striplines” or “microstrips” with defined impedance. - Terminate traces with characteristic impedance of the trace to avoid reflections (see figure below). - Multiple VDD pins should be decoupled separately for best performance. - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1μF for designs supporting frequencies below 50MHz (0.01μF for designs supporting frequencies above 50MHz). Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer (Typical buffer impedance 20Ω) To CMOS Input 50 Ω line Series Resistor Adjust value to match output buffer impedance to 50 Ω trace. Typical value 30 Ω. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 3 (Preliminary) PL123-04 3.3V Zero Delay Buffer OPERATING CONDITIONS Parameter V DD TA CL C IN t PU Description Supply Voltage Min. 3.0 Max. 3.6 Unit V 0 70 °C Industrial Operating Temperature (ambient temperature) -40 85 °C Load Capacitance, below 100 MHz Load Capacitance, above 100 MHz Input Capacitance [3] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) ― ― ― 30 15 7 pF pF pF 0.05 50 ms Commercial Operating Temperature (ambient temperature) Notes: 3: Applies to both REF clock and FBK inputs. ELECTRICAL CHARACTERISTICS Parameter Description Test Conditions Min. Max. Unit VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 – V IIL Input LOW Current VIN = 0V – 50.0 µA IIH Input HIGH Current VIN = VDD – 100.0 µA IOL = 8 mA – 0.4 V IOH = –8 mA 2.4 – V 12.0 µA – 25.0 µA – 45.0 mA – – – – 32.0 18.0 35.0 20.0 mA mA mA mA Voltage[4] VOL Output LOW VOH Output HIGH Voltage[4] IDD (PD mode) Power Down Supply Current IDD Supply Current (Unloaded Outputs) REF = 0 MHz, Commercial Temp. REF = 0 MHz, Industrial Temp. 100-MHz REF Select inputs at VDD or GND 66-MHz REF, Commercial Temp. 33-MHz REF, Commercial Temp. 66-MHz REF, Industrial Temp. 33-MHz REF, Industrial Temp. Notes: 4. Parameter is guaranteed by design and characterization. Not 100% tested in production. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 4 (Preliminary) PL123-04 3.3V Zero Delay Buffer SWITCHING CHARACTERISTICS PaName rameter t1 Output Frequency t1 t3 t4 t5 t6 t7 tJ [5] Min. Typ. Max. Unit 30-pF load 10 – 100 MHz Output Frequency 15-pF load 10 – 134 MHz Duty Cycle [4] = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40.0 50.0 60.0 % Duty Cycle [4] = t2 ÷ t1 Measured at 1.4V, FOUT <50.0 MHz 15-pF load Measured between 0.8V and 2.0V, 30-pF load Commercial Temperature Measured between 0.8V and 2.0V, 30-pF load Industrial Temperature Measured between 0.8V and 2.0V, 15-pF load Measured between 0.8V and 2.0V, 30-pF load Commercial Temperature Measured between 0.8V and 2.0V, 30-pF load Industrial Temperature Measured between 0.8V and 2.0V, 15-pF load 45.0 50.0 55.0 % – – 2.20 ns – – 2.50 ns – – 1.50 ns – – 2.20 ns – – 2.50 ns – – 1.50 ns All outputs equally loaded – – 200 ps All outputs equally loaded – – 200 ps All outputs equally loaded – – 400 ps Measured at VDD/2 – 0 ±250 ps Measured at VDD/2 on the FBK pins of devices – 0 500 ps Measured at 66.67 MHz, loaded outputs, 15-pF load – 90 175 ps Measured at 66.67 MHz, loaded outputs, 30-pF load – – 200 ps Measured at 133.3 MHz, loaded outputs, 15-pF load – – 100 ps Measured at 66.67 MHz, loaded outputs 30-pF load – – 400 ps Measured at 66.67 MHz, loaded outputs 15-pF load Stable power supply, valid clocks presented on REF and FBK pins – – 375 ps – – 1.0 ms Rise Time [4] Fall Time [4] Output to Output Skew on same Bank [4] Output Bank A to Output Bank B Skew (–04) Output Bank A to Output Bank B Skew (–042) Skew, REF Rising Edge to FBK Rising Edge [4] Device to Device Skew [4] Cycle to Cycle Jitter [4] (–04) tJ Cycle to Cycle Jitter [4] (–042) tLOCK PLL Lock Time [4] Test Conditions Notes: 5. All parameters are specified with loaded outputs. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 5 (Preliminary) PL123-04 3.3V Zero Delay Buffer SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 1.4V All Outputs Rise/Fall Time 1.4V 2.0V 2.0V OUTPUT 0.8V 3.3V 0.8V t3 0V t4 Output-Output Skew OUTPUT 1.4V OUTPUT 1.4V t5 Input-Output Propagation Delay OUTPUT VDD/2 FBK VDD/2 t6 Device-Device Skew FBK, Device 1 FBK, Device 2 VDD/2 VDD/2 t7 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 6 (Preliminary) PL123-04 3.3V Zero Delay Buffer TEST CIRCUIT Test Circuit #1 VDD 0.1 μF CLK OUT OUTPUTS C LOAD VDD 0.1 μF GND GND PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) 8-Pin SOP Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 C e b L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 7 (Preliminary) PL123-04 3.3V Zero Delay Buffer ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part/Order Number PL123-04SC PL123-04SC-R PL123-042SC PL123-042SC-R PL123-04SI PL123-04SI-R PL123-042SIC PL123-042SIC-R PL123-04SCA PL123-04SCA-R PL123-042SCA PL123-042SCA-R PL123-04SIA PL123-04SIA-R PL123-042SICA PL123-042SICA-R Marking Package Option Green (Lead-Free) Packages P123-04 8-Pin SOP Tube P123-04 8-Pin SOP (Tape and P123-042 8-Pin SOP Tube P123-042 8-Pin SOP (Tape and P123-04 8-Pin SOP Tube P123-04 8-Pin SOP (Tape and P123-042 8-Pin SOP Tube P123-042 8-Pin SOP (Tape and Not Green Packages P123-04 8-Pin SOP Tube P123-04 8-Pin SOP (Tape and P123-042 8-Pin SOP Tube P123-042 8-Pin SOP (Tape and P123-04 8-Pin SOP Tube P123-04 8-Pin SOP (Tape and P123-042 8-Pin SOP Tube P123-042 8-Pin SOP (Tape and Reel) Reel) Reel) Reel) Reel) Reel) Reel) Reel) Range Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 8