PL123-08 (Preliminary) 3.3V Zero Delay Buffer FEATURES DESCRIPTION • The PL123-08 is a PLL-based zero-delay buffer family, used to distribute up to eight outputs. Select inputs S2 and S1 control the state of the two output banks. • • • • • • • • Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations, see “Available Configurations” table Multiple low-skew outputs Two banks of four outputs, three-stateable by two select inputs 10 MHz to 134 MHz operating range Low cycle-to-cycle jitter 16 pin SOP or TSSOP packages 3.3V operation Commercial and industrial temperature available An external feedback pin enables removing delay from external components. It also provides adjustable inputto-output delay by varying its loading relative to the output pin loading. Various options are available to multiply the input frequency by 0.5, 1, 2, or 4x (see the Available Configuration table for details). Standard (8 mA) and High (12 mA) drive strengths may also be ordered. In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum frequency, thus behaving like a (non-zero delay) fan-out buffer. These parts are not intended for 5V input-tolerant applications. BLOCK DIAGRAM /2 Extra Divider (-083) Mux ` CLKA1 CLKA2 CLKA3 Bank A PLL REF FBK Extra Divider (-082, -083) S2 CLKB1 Selector Decoding CLKB2 CLKB3 16 FBK 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 GND 5 CLKB1 6 CLKB2 7 S2 8 9 13 VDD 12 GND 11 CLKB4 10 CLKB3 S1 Bank B S1 /2 1 2 PL123-08 CLKA4 REF CLKA1 CLKB4 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 1 (Preliminary) PL123-08 3.3V Zero Delay Buffer PIN DESCRIPTION Pin Name Type Description 1 REF[1] I Input reference frequency 2 CLKA1[2] O Clock output, Bank A 3 CLKA2[2] O Clock output, Bank A 4 VDD P 3.3V supply 5 GND P Ground 6 CLKB1[2] O Clock output, Bank B 7 CLKB2[2] O Clock output, Bank B 8 S2[3] I Select input, bit 2 9 S1[3] I Select input, bit 1 10 CLKB3[2] O Clock output, Bank B 11 CLKB4[2] O Clock output, Bank B 12 GND P Ground 13 VDD P 3.3V supply 14 CLKA3[2] O Clock output, Bank A 15 CLKA4[2] O Clock output, Bank A 16 FBK I PLL feedback input SELECT INPUT DECODING S2 0 0 1 1 S1 0 1 0 1 CLK A1–A4 Three-State Driven Driven[4] Driven CLK B1–B4 Three-State Three-State Driven[4] Driven Output Source PLL PLL Reference PLL PLL Shutdown Y N Y N AVAILABLE CONFIGURATIONS Device PL123-08 PL123-08H PL123-082 PL123-082 PL123-083 PL123-083 Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A Frequency Reference Reference Reference 2 X Reference 2 X Reference 4 X Reference Bank B Frequency Reference Reference Reference / 2 Reference Reference or Inverted Reference [5] 2 X Reference Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak pull-up on these inputs. 4: Outputs inverted on PL123-082 and -083 in bypass mode (S2=1, S1=0). 5: Output is phase indeterminant (0° or 180° from input clock). If phase integrity is required, use PL123-082. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 2 (Preliminary) PL123-08 3.3V Zero Delay Buffer ZERO-DELAY AND SKEW CONTROL The PLL’s feedback path must be closed by connecting FBK to one of the available eight outputs. The output driving the FBK pin will drive an (internal) output pin load of 7pF plus any additional loading placed on this output pin. For zero-delay applications, all outputs, including the FBK pin connected to an output pin, must be loaded equally. Varying the loading between the FBK pin and output pins can adjust the input-to-output delay. MAXIMUM RATINGS Supply Voltage to Ground Potential…..……………-0.5V to 4.6V DC Input Voltage (Except REF)…….……..…-0.5V to VDD+0.5V DC Input Voltage REF………………..……………….-0.5V to 4.6V Storage Temperature…………………..………...…..-65 to 150 °C Junction Temperature……………………..………………….150 °C Static Discharge Voltage (MIL-STD-883, Method 3015)..> 2KV OPERATING CONDITIONS Parameter V DD TA CL C IN t PU Description Supply Voltage Min. 3.0 Max. 3.6 Unit V 0 70 °C Industrial Operating Temperature (ambient temperature) -40 85 °C Load Capacitance, below 100 MHz Load Capacitance, above 100 MHz Input Capacitance [6] Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) ― ― ― 30 15 7 pF pF pF 0.05 50 ms Commercial Operating Temperature (ambient temperature) Notes: 6: Applies to both REF clock and FBK inputs. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 3 (Preliminary) PL123-08 3.3V Zero Delay Buffer LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a performance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short - Place decoupling capacitors as close as possible to the VDD pin(s) to bypass noise from the power supply - Trace = Inductor. With a capacitive load, equals ringing - Long trace = Transmission Line. Without proper termination this will cause reflections (causing ringing). - Design long traces as “striplines” or “microstrips” with defined impedance. - Terminate traces with characteristic impedance of the trace to avoid reflections (see figure below). - Multiple VDD pins should be decoupled separately for best performance. - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1μF for designs supporting frequencies below 50MHz (0.01μF for designs supporting frequencies above 50MHz). Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer ( Typical buffer impedance 20Ω) To CMOS Input 50 Ω line Series Resistor Adjust value to match output buffer impedance to 50 Ω trace. Typical value 30 Ω. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 4 (Preliminary) PL123-08 3.3V Zero Delay Buffer ELECTRICAL C HARACTERISTICS Parameter Test Conditions Description Min. Max. Unit VIL Input LOW Voltage – 0.8 V VIH Input HIGH Voltage 2.0 – V IIL Input LOW Current VIN = 0V – 50.0 µA IIH Input HIGH Current – 100.0 µA VOL Output LOW Voltage[7] – 0.4 V VOH Output HIGH Voltage[7] 2.4 – V IDD (PD mode) Power Down Supply Current VIN = VDD IOL = 8 mA (-08, -082, -083) IOL = 12 mA (-08H) IOH = –8 mA (-08, -082, -083) IOL = –12 mA (-08H) REF = 0 MHz, Commercial Temp. 12.0 µA – – – 25.0 45.0 70.0 (-08H) µA mA mA – 32.0 mA – 18.0 mA – 35.0 mA – 20.0 mA REF = 0 MHz, Industrial Temp. 100-MHz REF Select inputs at VDD or GND IDD Supply Current (Unloaded Outputs) 66-MHz REF (-08, -082, -083), Commercial 33-MHz REF (-08, -082, -083), Commercial 66-MHz REF (-08, -082, -083), Industrial Temp. 33-MHz REF (-08, -082, -083), Industrial Temp. Notes: 7. Parameter is guaranteed by design and characterization. Not 100% tested in production. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 5 (Preliminary) PL123-08 3.3V Zero Delay Buffer SWITCHING CHARACTERISTICS PaName ramet1 Output Frequency t1 Output Frequency [8] Test Conditions Min. Typ. Max. Unit 30-pF load, All devices 20-pF load, –08H devices 10 10 – – 100 134 MHz MHz Output Frequency 15-pF load, –08, –082, –083 devices 10 – 134 MHz Duty Cycle [7] = t2 ÷ t1 Measured at 1.4V, FOUT = 66.66 MHz 30-pF load 40 50 60 % Duty Cycle Measured at 1.4V, FOUT <50.0 MHz 15-pF load Measured between 0.8V and 2.0V, 30-pF load Commercial Temperature Measured between 0.8V and 2.0V, 30-pF load Industrial Temperature Measured between 0.8V and 2.0V, 15-pF load 45 50 55 % – – 2.20 ns – – 2.50 ns – – 1.50 ns Rise Time [7] (–08H) Measured between 0.8V and 2.0V, 30-pF load – – 1.50 ns – – 2.20 ns t4 Fall Time [7] (–08,–082,–083) Measured between 0.8V and 2.0V, 30-pF load Commercial Temperature Measured between 0.8V and 2.0V, 30-pF load Industrial Temperature Measured between 0.8V and 2.0V, 15-pF load – – 2.50 ns – – 1.50 ns t4 Measured between 0.8V and 2.0V, 30-pF load – – 1.25 ns All outputs equally loaded – – 200 ps All outputs equally loaded – – 200 ps All outputs equally loaded – – 200 ps All outputs equally loaded – – 400 ps Measured at VDD/2 – 0 ±250 ps t7 Fall Time (–08H) Output to Output Skew on same Bank (–08,–082,–083) Output to Output Skew (–08H) Output Bank A to Output Bank B Skew (–08) Output Bank A to Output Bank B Skew (–082, –083) Delay, REF Rising Edge to FBK Rising Edge [7] Device to Device Skew [7] – 0 700 ps t8 Output Slew Rate [7] 1 – – V/ns – 75 200 ps tJ Cycle to Cycle Jitter [7] (–08, –08H) Measured at VDD/2 on the FBK pins of devices Measured between 0.8V and 2.0V on –08H device using Test Circuit #2 Measured at 66.67 MHz, loaded outputs, 15-pF load Measured at 66.67 MHz, loaded outputs, 30-pF load – – 200 ps Measured at 133.3 MHz, loaded outputs, 15-pF load – – 100 ps Measured at 66.67 MHz, loaded outputs 30-pF load – – 400 ps Measured at 66.67 MHz, loaded outputs 15-pF load Stable power supply, valid clocks presented on REF and FBK pins – – 400 Ps – – 1.0 ms t1 t3 t3 t5 t6 [7] = t2 ÷ t1 Rise Time (–08, –082, –083) [7] [7] tJ Cycle to Cycle Jitter [7] (–082, –083) tLOCK PLL Lock Time [7] Notes: 8. All parameters are specified with loaded outputs. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 6 (Preliminary) PL123-08 3.3V Zero Delay Buffer SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 1.4V All Outputs Rise/Fall Time 1.4V 2.0V 2.0V OUTPUT 0.8V 3.3V 0.8V t3 0V t4 Output-Output Skew OUTPUT 1.4V OUTPUT 1.4V t5 Input-Output Propagation Delay OUTPUT VDD/2 FBK VDD/2 t6 Device-Device Skew FBK, Device 1 FBK, Device 2 VDD/2 VDD/2 t7 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 7 (Preliminary) PL123-08 3.3V Zero Delay Buffer TEST CIRCUITS Test Circuit #1 Test Circuit #2 VDD VDD 0.1 μF CLK OUT OUTPUTS 0.1 μF GND 0.1 μF CLK OUT OUTPUTS C LOAD VDD 1KΩ VDD 0.1 μF GND 1KΩ GND 10 pF GND PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT) 16 PIN Narrow SOP, TSSOP ( mm ) SOIC Symbo l A A 1 B C D E H L e Max . 1.7 Min. 1.3 5 0.1 0 0.3 3 0.1 9 9.8 0 3.8 0 5.8 0 0.4 0 1.27 BSC Min. 5 0.2 5 0.5 0.0 5 0.1 1 0.2 5 10.0 9 0.0 9 4.9 0 4.0 0 6.2 0 4.3 0 0 1.2 7 0.4 5 TSSO P Max . 1.2 E 0 0.1 5 0.3 0 0.2 H D 0 5.1 0 4.5 6.40 0 BSC 0.7 0.65 5 BSC A 1 A C e B L 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 8 (Preliminary) PL123-08 3.3V Zero Delay Buffer ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range Part/Order Number PL123-08HOC PL123-08HOC-R PL123-08SC PL123-08SC-R PL123-08HSC PL123-08HSC-R PL123-082SC PL123-082SC-R PL123-083SC PL123-083SC-R PL123-08HOI PL123-08HOI-R PL123-08SI PL123-08SI-R PL123-08HSI PL123-08HSI-R PL123-082SI PL123-082SI-R PL123-083SI PL123-083SI-R Marking Package Option Green (Lead-Free) Package P123-08H 16-Pin TSSOP Tube P123-08H 16-Pin TSSOP (Tape and Reel) P123-08 16-Pin SOP Tube P123-08 16-Pin SOP (Tape and Reel) P123-08H 16-Pin SOP Tube P123-08H 16-Pin SOP (Tape and Reel) P123-082 16-Pin SOP Tube P123-082 16-Pin SOP (Tape and Reel) P123-083 16-Pin SOP Tube P123-083 16-Pin SOP (Tape and Reel) P123-08H 16-Pin TSSOP Tube P123-08H 16-Pin TSSOP (Tape and Reel) P123-08 16-Pin SOP Tube P123-08 16-Pin SOP (Tape and Reel) P123-08H 16-Pin SOP Tube P123-08H 16-Pin SOP (Tape and Reel) P123-082 16-Pin SOP Tube P123-082 16-Pin SOP (Tape and Reel) P123-083 16-Pin SOP Tube P123-083 16-Pin SOP (Tape and Reel) Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 9 (Preliminary) PL123-08 3.3V Zero Delay Buffer (continuted) PART NUMBER Part/Order Number PL123-08HOCA PL123-08HOCA-R PL123-08SCA PL123-08SCA-R PL123-08HSCA PL123-08HSCA-R PL123-082SCA PL123-082SCA-R PL123-083SCA PL123-083SCA-R PL123-08HOIA PL123-08HOIA-R PL123-08SIA PL123-08SIA-R PL123-08HSIA PL123-08HSIA-R PL123-082SIA PL123-082SIA-R PL123-083SIA PL123-083SIA-R Marking Package Option P123-08H P123-08H P123-08 P123-08 P123-08H P123-08H P123-082 P123-082 P123-083 P123-083 P123-08H P123-08H P123-08 P123-08 P123-08H P123-08H P123-082 P123-082 P123-083 P123-083 Not Green Package 16-Pin TSSOP Tube 16-Pin TSSOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) 16-Pin TSSOP Tube 16-Pin TSSOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) 16-Pin SOP Tube 16-Pin SOP (Tape and Reel) Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 7/19/07 Page 10