RENESAS M30810MC

M32C/81 Group
SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER
REJ03B0031-0100Z
Rev.1.00
Jun. 01, 2004
1. Overview
The M32C/81 group microcomputer is a single-chip control unit that utilizes high-performance silicon gate
CMOS technology with the M32C/80 series CPU core. The M32C/81 group is available in 144-pin and 100pin plastic molded LQFP/QFP packages.
With a 16-Mbyte address space, this microcomputer combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed.
It incorporates a multiplier and DMAC adequate for office automation, communication devices and industrial
equipments and other high-speed processing applications.
1.1 Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
Rev.1.00 Jun. 01, 2004
page 1 of 83
1. Overview
M32C/81 Group
1.2 Difference between the M32C/81 Group and the M32C/83 Group
The M32/C81 group microcomputer has less peripheral functions than the M32C/83 group
miccrocomputer. The intelligent I/O group 3 and the A/D1 converter are not provided in the M32C/81
group. Interrupt requests, and as a result interrupts, DMAC, and DMACII, caused by intelligent I/O group 3
are not available in the M32C/81 group. However, the A/D1 conversion interrupt is generated in place of the
A/D0 conversion interrupt when input voltage applied to AN00 to AN07, AN20 to AN27, AN150 to AN157 pins
are converted.
Rev.1.00 Jun. 01, 2004
page 2 of 83
1. Overview
M32C/81 Group
1.3 Performance Outline
Tables 1.1 and 1.2 list performance outlines of the M32C/81 group.
Table 1.1 M32C/81 Group Performance (144-Pin Package)
CPU
Item
Basic instructions
Shortest instruction execution time
Operation mode
Address space
Memory capacity
Peripheral Port
function Multifunction timer
Intelligent I/O
Serial I/O
CAN module
A/D converter
D/A converter
DMAC
DMAC II
DRAMC
CRC calculation circuit
XY converter
Watchdog timer
Interrupt
Clock generating circuit
Oscillation stop detect function
Electric Supply voltage
characteristics
Power consumption
Performance
108 instructions
31.3 ns (f(BCLK)=32 MHz, VCC=4.2 V to 5.5 V)
50ns (f(BCLK)=20MHz, VCC=3.0 V to 5.5 V)
Single-chip mode, Memory expansion mode and Microprocessor mode
16 Mbytes
See Table 1.3
123 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 12 channels
Waveform generating function: 16 bits x 20 channels
Communication function (Clock synchronous serial I/O, Clock
asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1))
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus(1), I2C bus(2)
1 channel
Supporting CAN 2.0B specification
10-bit A/D converter: 1 circuit, 34 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt factors
Immediate transfer, Calculation transfer and Chain transfer functions
_______
_______
CAS-before-RAS refresh, self-refresh, EDO, FP
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), Sub clock oscillation circuit(*),
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator
or crystal oscillator must be connected externally
Main clock oscillation stop detect function
4.2 V to 5.5 V (f(BCLK)=32 MHz)
3.0 V to 5.5 V (f(BCLK)=20 MHz, through VDC)
3.0 V to 3.6 V (f(BCLK)=20 MHz, not through VDC)
28 mA (VCC=5 V, f(BCLK)=32 MHz)
17 mA (VCC=3.3 V, f(BCLK)=20 MHz)
470 µA (VCC=5 V, f(XCIN)=32 kHz, in wait mode)
340 µA (VCC=3.3 V, f(XCIN)=32 kHz, through VDC in wait mode)
5.0 µA (VCC=3.3 V, f(XCIN)=32 kHz, not through VDC in wait mode)
0.4 µA (VCC=5 V, f(XCIN)=32 kHz, in stop mode)
0.4 µA (VCC=3.3 V, f(XCIN)=32 kHz, in stop mode)
–20 to 85oC, –40 to 85oC (optional)
144-pin plastic molded LQFP
Operating ambient temperature
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
Rev.1.00 Jun. 01, 2004
page 3 of 83
1. Overview
M32C/81 Group
Table 1.2 M32C/81 Group Performance (100-Pin Package)
CPU
Item
Basic instructions
Shortest instruction execution time
Operation mode
Address space
Memory capacity
Peripheral Port
function Multifunction timer
Intelligent I/O
Serial I/O
CAN module
A/D converter
D/A converter
DMAC
DMAC II
DRAMC
CRC calculation circuit
XY converter
Watchdog timer
Interrupt
Clock generating circuit
Oscillation stop detect function
Electric Supply voltage
characteristics
Power consumption
Performance
108 instructions
31.3 ns (f(BCLK)=32 MHz, VCC=4.2 V to 5.5 V)
50ns (f(BCLK)=20MHz, VCC=3.0 V to 5.5 V)
Single-chip mode, Memory expansion mode and Microprocessor mode
16 Mbytes
See Table 1.3
87 I/O pins and 1 input pin
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 6 channels
Three-phase motor control circuit
Time measurement function: 16 bits x 5 channels
Waveform generating function: 16 bits x 8 channels
Communication function (Clock synchronous serial I/O, Clock
asynchronous serial I/O, HDLC data processing, Clock synchronous variable length serial I/O, IEBus(1))
5 channels
Clock synchronous serial I/O, Clock asynchronous serial I/O,
IEBus(1), I2C bus(2)
1 channel
Supporting CAN 2.0B specification
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
4 channels
Can be activated by all peripheral function interrupt factors
Immediate transfer, Calculation transfer and Chain transfer functions
_______
_______
CAS-before-RAS refresh, self-refresh, EDO, FP
CRC-CCITT
16 bits x 16 bits
15 bits x 1 channel (with prescaler)
42 internal and 8 external sources, 5 software sources
Interrupt priority level: 7
4 circuits
Main clock oscillation circuit(*), sub clock oscillation circuit(*), Onchip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resistor. Ceramic resonator
or crystal oscillator must be connected externally
Main clock oscillation stop detect function
4.2 V to 5.5 V (f(XIN)=32 MHz)
3.0 V to 5.5 V (f(XIN)=20 MHz, through VDC)
3.0 V to 3.6 V (f(XIN)=20 MHz, not through VDC)
28 mA (VCC=5 V, f(BCLK)=32 MHz)
17 mA (VCC=3.3 V, f(BCLK)=20 MHz)
470 µA (VCC=5 V, f(XCIN)=32 kHz, in wait mode)
340 µA (VCC=3.3 V, f(XCIN)=32 kHz, through VDC in wait mode)
5.0 µA (VCC=3.3 V, f(XCIN)=32 kHz, not through VDC in wait mode)
0.4 µA (VCC=5 V, f(XCIN)=32 kHz, in stop mode)
0.4 µA (VCC=3.3 V, f(XCIN)=32 kHz, in stop mode)
–20 to 85oC, –40 to 85oC (option)
100-pin plastic molded LQFP/QFP
Operating ambient temperature
Package
NOTES:
1. IEBus is a trademark of NEC Electronics Corporation.
2. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
All options are on a request basis.
Rev.1.00 Jun. 01, 2004
page 4 of 83
1. Overview
M32C/81 Group
1.4 Block Diagram
Figure 1.1 shows a block diagram of the M32C/81 group microcomputer.
The M32C/81 group microcomputer contains ROM and RAM as memory to store instructions and data,
CPU to execute calculations and peripheral functions such as interrupt, timer, serial I/O, DMAC, CRC
calculation circuit, A/D converter, D/A converter, DRAMC, intelligent I/O and ports.
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Peripheral functions
A/D converter
1 circuit
Standard 10 inputs
Maximum 34 inputs(2)
Timer (16 bits)
Timer A 5 channels
Timer B 6 channels
Clock generating circuit
XIN - XOUT
XCIN - XCOUT
On-chip oscillator
PLL frequency synthesizer
Three-phase motor control circuit
UART/Clock synchronous serial I/O
5 channels
DMAC
Watchdog timer (15 bits)
XY converter
16 bits X 16 bits
DMACII
D/A converter
(8 bits X 2 circuits)
CRC calculation circuit (CCITT)
X16+X12+X5+1
Intelligent I/O
( 3 groups )
Time measurement 12 channels(2)
Wave generating 20 channels(2)
Communication function
Clock synchronous serial I/O, UART,
IEBus, HDLC data processing
M32C/80 series CPU core
R0H
R0L
R1H
R1L
8
Port P14
Port P13
7
Port P12
8
ISP
R3
USP
SVF
FB
SVP
SB
VCT
Port P11
8
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. Included in the 144-pin package only.
Rev.1.00 Jun. 01, 2004
page 5 of 83
RAM
PC
(Note1)
Figure 1.1 M32C/81 Group Block Diagram
ROM
INTB
A1
CAN module
Memory
FLG
R2
A0
Port P15
DRAMC
5
Port P10
8
Multiplier
Port P9
8
P85
Port P8
7
1. Overview
M32C/81 Group
1.5 Product Information
Renesas plans to release the following products in the M32C/81 group:
(1) Support for the masked ROM version
(2) ROM/RAM capacity
(3) Package
100P6S-A : Plastic molded QFP
100P6Q-A : Plastic molded LQFP
144P6Q-A : Plastic molded LQFP
RAM size
(Byte)
M3081NMC-XXXGP
12K
M3081LMC-XXXGP
M3081LMC-XXXFP
M30812MC-XXXGP
10K
M30810MC-XXXGP
M30810MC-XXXFP
ROM size
(Byte)
128K
Figure 1.2 ROM/RAM Capacity
Table 1.3 M32C/81 Group
Type number
M30810MC-XXXFP (D)
M30810MC-XXXGP (D)
M30812MC-XXXGP (D)
M3081LMC-XXXFP (D)
M3081LMC-XXXGP (D)
M3081NMC-XXXGP (D)
(D): Under development
As of September, 2003
ROM capacity
RAM capacity
10K
128K
12K
Package type
100P6S-A
100P6Q-A
144P6Q-A
100P6S-A
100P6Q-A
144P6Q-A
Remarks
Masked ROM
M30 81 2 M C - (XXX) GP
Package type options:
FP = Package 100P6S-A
GP = Package 100P6Q-A, 144P6Q-A
ROM capacity:
C = 128 Kbytes
Memory type:
M = Masked ROM version
Shows RAM capacity, pin count, etc
(Value itself has no specific meaning)
M32C/81 Group
M16C Family
Figure 1.3 Product Numbering System
Rev.1.00 Jun. 01, 2004
page 6 of 83
1. Overview
M32C/81 Group
1.6 Pin Assignments
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
109
72
110
71
111
70
112
69
113
68
114
67
115
66
116
65
117
64
118
63
119
62
120
61
121
60
122
59
123
58
124
57
125
56
M32C/81GROUP
126
127
55
54
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
P44 / CS3 / A20 (MA12)
P45 / CS2 / A21
P46 / CS1 / A22
P47 / CS0 / A23
P125
P126
P127
P50 / WRL / WR / CASL
P51 / WRH / BHE / CASH
P52 / RD / DW
P53 / CLKOUT / BCLK / ALE
P130 / OUTC24
P131 / OUTC25
Vcc
P132 / OUTC26
Vss
P133 / OUTC23
P54 / HLDA / ALE
P55 / HOLD
P56 / ALE / RAS
P57 / RDY
P134 / OUTC20 / ISTxD2 / IEOUT
P135 / OUTC22 / ISRxD2 / IEIN
P136 / OUTC21 / ISCLK2
P137 / OUTC27
P60 / CTS0 / RTS0 / SS0
P61 / CLK0
P62 / RxD0 / SCL0 / STxD0
P63 / TxD0 / SDA0 / SRxD0
P64 (1)
P65 / CLK1
Vss
P66 / RxD1 / SCL1 / STxD1
Vcc
P67 / TxD1 / SDA1 / SRxD1
P70 (2, 3)
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
CLK4 / ANEX0 / P95
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
ISTxD2 / IEOUT / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
ISRxD2 / IEIN / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
P146
P145
P144
OUTC17 / INPC17 / P143
OUTC16 / INPC16 / P142
OUTC15 / P141
OUTC14 / P140
BYTE
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
CANOUT / INT0 / P82
U / TA4IN / P81
BE0IN / ISRxD0 / INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
CLK2 / V / TA1OUT / P72
(3) IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
19
37
18
38
144
17
39
143
16
40
142
15
41
141
14
42
140
13
43
139
12
44
138
11
45
137
9
46
136
10
47
135
8
48
134
7
49
133
6
50
132
5
51
131
4
52
130
3
53
129
2
128
1
D8 / P10
AN07 / D7 / P07
AN06 / D6 / P06
AN05 / D5 / P05
AN04 / D4 / P04
P114
OUTC13 / P113
BE1IN / ISRxD1 / OUTC12 / INPC12 / P112
ISCLK1 / OUTC11 / INPC11 / P111
BE1OUT / ISTxD1 / OUTC10 / P110
AN03 / D3 / P03
AN02 / D2 / P02
AN01 / D1 / P01
AN00 / D0 / P00
INPC07 / AN157 / P157
INPC06 / AN156 / P156
OUTC05 / INPC05 / AN155 / P155
OUTC04 / INPC04 / AN154 / P154
INPC03 / AN153 / P153
BE0IN / ISRxD0 / INPC02 / AN152 / P152
ISCLK0 / OUTC01 / INPC01 / AN151 / P151
Vss
BE0OUT / ISTxD0 / OUTC00 / INPC00 / AN150 / P150
Vcc
KI3 / AN7 / P107
KI2 / AN6 / P106
KI1 / AN5 / P105
KI0 / AN4 / P104
AN3 / P103
AN2 / P102
AN1 / P101
AVss
AN0 / P100
VREF
AVcc
STxD4 / SCL4 / RxD4 / ADTRG / P97
107
108
P11 / D9
P12 / D10
P13 / D11
P14 / D12
P15 / D13 / INT3
P16 / D14 / INT4
P17 / D15 / INT5
P20 / A0 ( / D0 ) / AN20
P21 / A1 ( / D1 ) / AN21
P22 / A2 ( / D2 ) / AN22
P23 / A3 ( / D3 ) / AN23
P24 / A4 ( / D4 ) / AN24
P25 / A5 ( / D5 ) / AN25
P26 / A6 ( / D6 ) / AN26
P27 / A7 ( / D7 ) / AN27
Vss
P30 / A8 ( MA0 ) ( / D8 )
Vcc
P120
P121
P122
P123
P124
P31 / A9 ( MA1 ) ( / D9 )
P32 / A10 ( MA2 ) ( / D10 )
P33 / A11 ( MA3 ) ( / D11 )
P34 / A12 ( MA4 ) ( / D12 )
P35 / A13 ( MA5 ) ( / D13 )
P36 / A14 ( MA6 ) ( / D14 )
P37 / A15 ( MA7 ) ( / D15 )
P40 / A16 ( MA8 )
P41 / A17 ( MA9 )
Vss
P42 / A18 ( MA10 )
Vcc
P43 / A19 ( MA11 )
Figures 1.4 to 1.6 show pin assignments (top view).
NOTES:
1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT
3. P70 and P71 are ports for the N-channel open drain output.
Figure 1.4 Pin Assignment for 144-Pin Package
Rev.1.00 Jun. 01, 2004
page 7 of 83
144P6Q-A
1. Overview
M32C/81 Group
Table 1.4 Pin Characteristics for 144-Pin Package
Pin
No
Control
pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 BYTE
16 CNVSS
17 XCIN/VCONT
18 XCOUT
19 RESET
20 XOUT
21 VSS
22 XIN
23 VCC
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 VCC
40
41 VSS
42
43
44
45
46
47
48
Port
Interrupt
pin
P96
P95
P94
P93
P92
Timer pin
TB4IN
TB3IN
TB2IN
P91
P90
P146
P145
P144
TB1IN
TB0IN
UART/CAN pin
Intelligent I/O pin
TxD4/SDA4/SRxD4
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
P143
P142
P141
P140
ANEX1
ANEX0
DA1
DA0
OUTC20/IEOUT/ISTxD2
IEIN/ISRxD2
INPC17/OUTC17
INPC16/OUTC16
OUTC15
OUTC14
P87
P86
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
P70
P67
NMI
INT2
INT1
INT0
CANIN
CANOUT
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
TB5IN/TA0IN
TA0OUT
INPC02/ISRxD0/BE0IN
CANIN
CANOUT
CTS2/RTS2/SS2
CLK2
RxD2/SCL2/STxD2
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
P66
RxD1/SCL1/STxD1
P65
P64
P63
P62
P61
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
RxD0/SCL0/STxD0
Rev.1.00 Jun. 01, 2004
INPC01/OUTC01/ISCLK0
INPC00/OUTC00/ISTxD0/BE0OUT
INPC12/OUTC12/ISRxD1/BE1IN
INPC11/OUTC11/ISCLK1
OUTC10/ISTxD1/BE1OUT
OUTC22/ISRxD2/IEIN
OUTC20/ISTxD2/IEOUT
OUTC21/ISCLK2
CLK0
CTS0/RTS0/SS0
P60
P137
OUTC27
page 8 of 83
Analog pin
Bus control pin
1. Overview
M32C/81 Group
Table 1.4 Pin Characteristics for 144-Pin Package (Continued)
Pin
No
Control
pin
49
50
51
52
53
54
55
56
57 VSS
58
59 VCC
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74 VCC
75
76 VSS
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91 VCC
92
93 VSS
94
95
96
Port
Interrupt
pin
Timer pin
P136
UART/CAN pin
Intelligent I/O pin
Analog pin
Bus control pin
OUTC21/ISCLK2
OUTC22/ISRxD2/IEIN
P135
P134
P57
P56
P55
OUTC20/ISTxD2/IEOUT
RDY
ALE/RAS
HOLD
P54
HLDA/ALE
P133
OUTC23
P132
OUTC26
P131
P130
OUTC25
OUTC24
P53
P52
P51
CLKOUT/BCLK/ALE
RD/DW
WRH/BHE/CASH
P50
P127
P126
WRL/WR/CASL
P125
P47
P46
P45
CS0/A23
CS1/A22
CS2/A21
P44
P43
CS3/A20(MA12)
A19(MA11)
P42
A18(MA10)
P41
P40
A17(MA9)
A16(MA8)
A15(MA7)(/D15)
P37
P36
A14(MA6)(/D14)
A13(MA5)(/D13)
P35
P34
P33
A12(MA4)(/D12)
A11(MA3)(/D11)
A10(MA2)(/D10)
A9(MA1)(/D9)
P32
P31
P124
P123
P122
P121
P120
P30
A8(MA0)(/D8)
P27
P26
P25
Rev.1.00 Jun. 01, 2004
AN27
AN26
AN25
page 9 of 83
A7(/D7)
A6(/D6)
A5(/D5)
1. Overview
M32C/81 Group
Table 1.4 Pin Characteristics for 144-Pin Package (Continued)
Pin
No
Control
pin
Port
Interrupt
pin
Timer pin
UART/CAN pin
Intelligent I/O pin
Analog pin
Bus control pin
97
P24
AN24
A4(/D4)
98
P23
P22
P21
P20
AN23
AN22
AN21
AN20
A3(/D3)
A2(/D2)
A1(/D1)
A0(/D0)
99
100
101
P17
P16
INT5
D15
103
INT4
D14
104
P15
INT3
D13
105
P14
P13
D12
D11
P12
P11
D10
D9
102
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130 VSS
131
132 VCC
133
134
135
136
137
138
139
140 AVSS
141
142 VREF
143 AVCC
144
P10
P07
P06
P05
AN07
AN06
AN05
D8
D7
D6
D5
AN04
D4
D3
D2
D1
D0
INPC07
INPC06
INPC05/OUTC05
INPC04/OUTC04
INPC03
AN03
AN02
AN01
AN00
AN157
AN156
AN155
AN154
AN153
P152
P151
INPC02/ISRxD0/BE0IN
INPC01/OUTC01/ISCLK0
AN152
AN151
P150
INPC00/OUTC00/ISTxD0/BE0OUT
AN150
P04
P114
OUTC13
P113
P112
INPC12/OUTC12/ISRxD1/BE1IN
P111
INPC11/OUTC11/ISCLK1
OUTC10/ISTxD1/BE1OUT
P110
P03
P02
P01
P00
P157
P156
P155
P154
P153
P107
P106
KI3
P105
P104
P103
KI1
KI0
AN7
AN6
KI2
AN5
AN4
AN3
P102
AN2
P101
AN1
P100
AN0
RxD4/SCL4/STxD4
P97
Rev.1.00 Jun. 01, 2004
page 10 of 83
ADTRG
Rev.1.00 Jun. 01, 2004
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91
CLK3 / TB0IN / P90
BYTE
CNVss
VCONT / XCIN / P87
XCOUT / P86
RESET
XOUT
Vss
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
CANOUT / INT0 / P82
U / TA4IN / P81
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
CLK2 / V / TA1OUT / P72
(3) IEIN / ISRxD2 / OUTC22 / STxD2 / SCL2 / RxD2 / TA0IN / TB5IN / P71
(3) IEOUT / ISTxD2 / OUTC20 / SRxD2 / SDA2 / TxD2 / TA0OUT / P70
NOTES:
1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
2. P97 / ADTRG / RxD4 / STxD4 / SCL4
3. P70 and P71 are ports for the N-channel open drain output.
1
AVcc
CLK4 / ANEX0 / P95
(2) P97
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
Figure 1.5 Pin assignment for 100-Pin Package
page 11 of 83
P42 / A18 ( MA10 )
P43 / A19 ( MA11 )
52
51
P37 / A15 ( MA7 ) ( / D15 )
P40 / A16 ( MA8 )
P36 / A14 ( MA6 ) ( / D14 )
55
P41 / A17 ( MA9 )
P35 / A13 ( MA5 ) ( / D13 )
56
53
P34 / A12 ( MA4 ) ( / D12 )
57
54
P33 / A11 ( MA3 ) ( / D11 )
58
Vss
64
P32 / A10 ( MA2 ) ( / D10 )
P27 / A7 ( / D7 ) / AN27
65
59
P26 / A6 ( / D6 ) / AN26
66
P31 / A9 ( MA1 ) ( / D9 )
P25 / A5 ( / D5 ) / AN25
67
60
P24 / A4 ( / D4 ) / AN24
68
61
P23 / A3 ( / D3 ) / AN23
69
P30 / A8 ( MA0 ) ( / D8 )
P22 / A2 ( / D2 ) / AN22
70
Vcc
P21 / A1 ( / D1 ) / AN21
71
62
P20 / A0 ( / D0 ) / AN20
72
63
P17 / D15 / INT5
73
P14 / D12
76
P15 / D13 / INT3
P13 / D11
77
P16 / D14 / INT4
P12 / D10
78
74
P11 / D9
79
75
P10 / D8
80
M32C/81 Group
1. Overview
D7 / AN07 / P07
81
50
D6 / AN06 / P06
82
49
P45 / CS2 / A21
D5 / AN05 / P05
83
48
P46 / CS1 / A22
D4 / AN04 / P04
84
47
P47 / CS0 / A23
D3 / AN03 / P03
85
46
P50 / WRL / WR / CASL
D2 / AN02 / P02
86
45
P51 / WRH / BHE / CASH
D1 / AN01 / P01
87
44
P52 / RD / DW
D0 / AN00 / P00
88
43
P53 / CLKOUT / BCLK / ALE
KI3 / AN7 / P107
89
42
P54 / HLDA / ALE
KI2 / AN6 / P106
90
41
P55 / HOLD
KI1 / AN5 / P105
91
40
P56 / ALE / RAS
KI0 / AN4 / P104
92
39
P57 / RDY
AN3 / P103
93
38
P60 / CTS0 / RTS0 / SS0
AN2 / P102
94
37
P61 / CLK0
AN1 / P101
95
36
P62 / RxD0 / SCL0 / STxD0
AVss
96
35
P63 / TxD0 / SDA0 / SRxD0
AN0 / P100
97
34
P64 (1)
VREF
98
33
P65 / CLK1
99
32
P66 / RxD1 / SCL1 / STxD1
100
31
P67 / TxD1 / SDA1 / SRxD1
M32C/81GROUP
P44 / CS3 / A20 (MA12)
100P6S-A
1. Overview
P21 / A1 ( / D1 ) / AN21
P22 / A2 ( / D2 ) / AN22
P23 / A3 ( / D3 ) / AN23
P24 / A4 ( / D4 ) / AN24
P25 / A5 ( / D5 ) / AN25
P26 / A6 ( / D6 ) / AN26
P27 / A7 ( / D7 ) / AN27
Vss
P30 / A8 ( MA0 ) ( / D8 )
Vcc
P31 / A9 ( MA1 ) ( / D9 )
P32 / A10 ( MA2 ) ( / D10 )
P33 / A11 ( MA3 ) ( / D11 )
P34 / A12 ( MA4 ) ( / D12 )
P35 / A13 ( MA5 ) ( / D13 )
P36 / A14 ( MA6 ) ( / D14 )
P37 / A15 ( MA7 ) ( / D15 )
P40 / A16 ( MA8 )
P41 / A17 ( MA9 )
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P20 / A0 ( / D0 ) / AN20
70
68
P17 / D15 / INT5
71
69
P15 / D13 / INT3
P16 / D14 / INT4
72
P14 / D12
74
73
P13 / D11
75
M32C/81 Group
D10 / P12
76
50
P42 / A18 ( MA10 )
D9 / P11
77
49
P43 / A19 ( MA11 )
P44 / CS3 / A20 (MA12)
D8 / P10
78
48
AN07 / D7 / P07
79
47
P45 / CS2 / A21
AN06 / D6 / P06
80
46
P46 / CS1 / A22
AN05 / D5 / P05
81
45
P47 / CS0 / A23
AN04 / D4 / P04
82
44
P50 / WRL / WR / CASL
AN03 / D3 / P03
83
43
P51 / WRH / BHE / CASH
AN02 / D2 / P02
84
42
P52 / RD / DW
AN01 / D1 / P01
85
41
P53 / CLKOUT / BCLK / ALE
AN00 / D0 / P00
86
40
P54 / HLDA / ALE
KI3 / AN7 / P107
87
39
P55 / HOLD
KI2 / AN6 / P106
88
38
P56 / ALE / RAS
KI1 / AN5 / P105
89
37
P57 / RDY
KI0 / AN4 / P104
90
36
P60 / CTS0 / RTS0 / SS0
AN3 / P103
91
35
P61 / CLK0
AN2 / P102
92
34
P62 / RxD0 / SCL0 / STxD0
AN1 / P101
93
33
P63 / TxD0 / SDA0 / SRxD0
AVss
94
32
P64 (1)
AN0 / P100
95
31
P65 / CLK1
VREF
96
30
P66 / RxD1 / SCL1 / STxD1
AVcc
97
29
P67 / TxD1 / SDA1 / SRxD1
STxD4 / SCL4 / RxD4 / ADTRG / P97
98
28
P70 (2, 4)
SRxD4 / SDA4 / TxD4 / ANEX1 / P96
99
27
P71 (3, 4)
CLK4 / ANEX0 / P95
100
26
P72 / TA1OUT / V / CLK2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
XIN
Vcc
NMI / P85
INT2 / P84
CANIN / INT1 / P83
CANOUT / INT0 / P82
U / TA4IN / P81
BE0IN / ISRxD0 /INPC02 / U / TA4OUT / P80
CANIN / ISCLK0 / OUTC01 / INPC01 / TA3IN / P77
CANOUT / BE0OUT / ISTxD0 / OUTC00 / INPC00 / TA3OUT / P76
BE1IN / ISRxD1 / OUTC12 / INPC12 / W / TA2IN / P75
ISCLK1 / OUTC11 / INPC11 / W / TA2OUT / P74
BE1OUT / ISTxD1 / OUTC10 / SS2 / RTS2 / CTS2 / V / TA1IN / P73
8
VCONT / XCIN / P87
Vss
7
CNVss
11
6
BYTE
XOUT
5
CLK3 / TB0IN / P90
9
4
IEIN / ISRxD2 / STxD3 / SCL3 / RxD3 / TB1IN / P91
10
3
IEOUT / ISTxD2 / OUTC20 / SRxD3 / SDA3 / TxD3 / TB2IN / P92
RESET
2
SS3 / RTS3 / CTS3 / TB3IN / DA0 / P93
XCOUT / P86
1
SS4 / RTS4 / CTS4 / TB4IN / DA1 / P94
M32C/81GROUP
NOTES:
1. P64 / CTS1 / RTS1 / SS1 / OUTC21 / ISCLK2
2. P70 / TA0OUT / TxD2 / SDA2 / SRxD2 / OUTC20 / ISTxD2 / IEOUT
3. P71 / TA0IN / TB5IN / RxD2 / SCL2 / STxD2 / OUTC22 / ISRxD2 / IEIN
4. P70 and P71 are ports for the N-channel open drain output.
Figure 1.6 Pin Assignment for 100-Pin Package
Rev.1.00 Jun. 01, 2004
page 12 of 83
100P6Q-A
1. Overview
M32C/81 Group
Table 1.5 Pin Characteristics for 100-Pin Package
Package
Pin No
FP GP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Control
pin
Port
P94
P93
P92
21
22
P77
P76
25
26
27
28
23
24
25
26
P75
P74
P73
29
30
31
27
28
29
32
33
34
35
36
37
30
31
32
42
43
44
45
46
47
48
49
50
TB4IN
TB3IN
TB2IN
43
44
45
46
47
48
TB1IN
TB0IN
Bus control pin
ANEX1
ANEX0
DA1
DA0
CLK4
CTS4/RTS4/SS4
CTS3/RTS3/SS3
TxD3/SDA3/SRxD3
RxD3/SCL3/STxD3
CLK3
Analog
pin
OUTC20/IEOUT/ISTxD2
IEIN/ISRxD2
VSS
XIN
VCC
23
24
38
39
40
41
Intelligent I/O pin
RESET
XOUT
P85
P84
P83
P82
P81
P80
33
34
35
36
37
38
39
40
41
42
UART/CAN pin
TxD4/SDA4/SRxD4
3
P91
4
P90
5
6 BYTE
7 CNVSS
8 XCIN/VCONT P87
P86
9 XCOUT
10
11
12
13
14
15
Timer pin
P96
P95
99
100
1
2
16
17
18
19
20
17
18
19
20
21
22
Interrupt
pin
P72
P71
P70
P67
P66
NMI
INT2
CANIN
CANOUT
INT1
INT0
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
TA2IN/W
TA2OUT/W
TA1IN/V
TA1OUT/V
CTS2/RTS2/SS2
CLK2
TB5IN/TA0IN RxD2/SCL2/STxD2
TA0OUT
TxD2/SDA2/SRxD2
TxD1/SDA1/SRxD1
RxD1/SCL1/STxD1
CLK1
CTS1/RTS1/SS1
TxD0/SDA0/SRxD0
P65
P64
P63
P62
P61
P60
P57
INPC02/ISRxD0/BE0IN
INPC01/OUTC01/ISCLK0
INPC00/OUTC00/ISTxD0/BE0OUT
INPC12/OUTC12/ISRxD1/BE1IN
INPC11/OUTC11/ISCLK1
OUTC10/ISTxD1/BE1OUT
OUTC22/ISRxD2/IEIN
OUTC20/ISTxD2/IEOUT
OUTC21/ISCLK2
RxD0/SCL0/STxD0
CLK0
CTS0/RTS0/SS0
RDY
ALE/RAS
HOLD
HLDA/ALE
P56
P55
P54
P53
P52
P51
CLKOUT/BCLK/ALE
RD/DW
WRH/BHE/CASH
WRL/WR/CASL
CS0/A23
CS1/A22
P50
P47
P46
P45
P44
Rev.1.00 Jun. 01, 2004
CANIN
CANOUT
CS2/A21
CS3/A20(MA12)
page 13 of 83
1. Overview
M32C/81 Group
Table 1.5 Pin Characteristics for 100-Pin Package (Continued)
Package
pin No
Control
pin
Port
Interrupt
pin
Timer pin
UART/CAN pin
Intelligent I/O pin
Analog
pin
Bus control pin
FP GP
51
52
53
49
50
51
P43
P42
P41
54
55
56
57
58
59
60
61
52
53
54
55
56
57
58
59
P40
62
63
64
65
66
60
61
62
63
64
67
68
69
70
71
72
65
66
67
68
69
70
73
74
71
72
75
76
77
78
73
74
75
76
79
80
81
77
78
79
82
83
84
85
86
87
80
81
82
83
84
85
88
89
90
91
86
87
88
89
92
93
94
95
96
97
98
90
91
92
93
94
95
96
99
100
97
98
A19(MA11)
A18(MA10)
A17(MA9)
A16(MA8)
A15(MA7)(/D15)
A14(MA6)(/D14)
A13(MA5)(/D13)
A12(MA4)(/D12)
A11(MA3)(/D11)
P37
P36
P35
P34
P33
P32
P31
A10(MA2)(/D10)
A9(MA1)(/D9)
P30
A8(MA0)(/D8)
VCC
VSS
P27
P26
AN27
AN26
P25
P24
P23
P22
AN25
AN24
AN23
AN22
P21
P20
P17
P16
AN21
AN20
P15
P14
P13
INT5
INT4
INT3
A7(/D7)
A6(/D6)
A5(/D5)
A4(/D4)
A3(/D3)
A2(/D2)
A1(/D1)
A0(/D0)
D15
D14
D13
D12
D11
P12
P11
P10
D10
D9
D8
P07
P06
AN07
AN06
D7
D6
P05
P04
P03
AN05
AN04
AN03
D5
D4
D3
P02
P01
P00
AN02
AN01
AN00
D2
D1
D0
P107
P106
P105
P104
P103
P102
P101
KI3
AN7
AN6
AN5
KI2
KI1
KI0
AN4
AN3
AN2
AN1
AVSS
P100
AN0
VREF
AVCC
P97
Rev.1.00 Jun. 01, 2004
RxD4/SCL4/STxD4
page 14 of 83
ADTRG
1. Overview
M32C/81 Group
1.7 Pin Description
Table 1.6 Pin Description (100-Pin and 144-Pin Packages)
Symbol
Function
I/O type
VCC
VSS
Power supply input
I
I
Apply 3.0 to 5.5 V to the VCC pins.
Apply 0 V to the VSS pin.
CNVSS
CNVSS
I
Switches processor mode. Connect this pin to VSS to start up in single-chip
mode (memory expansion mode). Connect this pin to VCC to start up in
RESET
Reset input
I
microprocessor mode.
___________
The microcomputer is in a reset state when applying "L" to the RESET pin.
XIN
XOUT
Clock input
Clock output
I
O
I/O pins for the main clock oscillation circuit. Connect a ceramic resonator or
crystal oscillator between XIN and XOUT. To use an external clock, input the
I
clock to XIN and leave XOUT open.
Switches the data bus in external memory space 3. The data bus is 16 bits wide
____________
BYTE
Input to switch
external data bus
width
Description
when the BYTE pin is held "L" and 8 bits wide when the BYTE pin is held "H".
Set to either. Connect this pin to V SS when an external bus is not used.
AVCC
Analog power
supply input
I
Applies power supply for the A/D converter and D/A converter. Connect this
pin to VCC.
AVSS
Analog power
supply input
I
Applies power supply for the A/D converter and D/A converter. Connect this
pin to VSS.
VREF
Reference voltage
input
I
Applies reference voltage for the A/D converter.
P00 to P07
I/O port P0
I/O
8-bit I/O ports in CMOS having a direction register to select input or output.
Each pin is set as an input port or output port. An input port in single-chip
mode can be set for a pull-up or for no pull-up in 4-bit unit by program. When
these pins are used as bus control pins in memory expansion mode and
microprocessor mode, internal pull-up resistor cannot be selected. Ports used
D0 to D7
Data bus
I/O
as input ports can be set for a pull-up or for no pull-up in the modes above.
Inputs and outputs data (D0 to D7) when these pins are set as the separate bus.
AN00 to AN07
P10 to P17
Analog input pin
I/O port P1
I
I/O
Analog input pins for the A/D converter
8-bit I/O ports having equivalent functions to P0
________
______
________
______
INT3 to INT5
INT interrupt input
pin
D8 to D15
P20 to P27
Data bus
I/O port P2
I/O
I/O
Inputs and outputs data (D 8 to D15) when these pins are set as the separate bus.
8-bit I/O ports having equivalent functions to P0
A0 to A7
A0/D0 to
Address bus
Address bus/data
O
I/O
Outputs 8 low-order address bits (A0 to A7).
Inputs and outputs data (D0 to D7) and outputs 8 low-order address bits (A0 to
A7/D7
AN20 to AN27
bus
Analog input pin
I
P30 to P37
A8 to A15
I/O port P3
Address bus
I/O
O
8-bit I/O ports having equivalent functions to P0
Outputs 8 middle-order address bits (A8 to A15).
A8/D8 to
A15/D15
Address bus/data
bus
I/O
Inputs and outputs data (D8 to D15) and outputs 8 middle-order address bits
(A8 to A15) by time-sharing when external 16-bit data bus is set as the multi-
MA0 to MA7
Address bus
O
I : Input
O : Output
Rev.1.00 Jun. 01, 2004
I
Input pins for the INT interrupt
A7) by time-sharing when these pins are set as the multiplexed bus.
Analog input pins for A/D converter
plexed bus.
Outputs row addresses and column addresses by time-sharing when accessing
the DRAM area.
I/O : Input and output
page 15 of 83
1. Overview
M32C/81 Group
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Symbol
Function
I/O type
Description
P40 to P47
I/O port P4
I/O
8-bit I/O ports having equivalent functions to P0
A16 to A22,
_____
A23
Address bus
O
Outputs 8 high-order address bits (A16 to A22, A23).
______
The highest-order bit (A23) inversed is also output.
CS0 to CS3
Chip-select
O
Outputs CS0 to CS3 signals. CS0 to CS3 are chip-select signals specifying an
external space.
MA8 to MA12
Address bus
O
Outputs row addresses and column addresses by time-sharing when accessing
the DRAM area.
P50 to P57
CLKOUT
I/O port P5
Clock output
I/O
O
8-bit I/O ports having equivalent functions to P0
Outputs the main clock divided by 8 or divided by 32 or the clock having the
Bus control pin
O
______
______
_______
______
_______
_______
_______
same frequency as the sub clock from P53.
________
WRL
______
WR
_________
WRH
________ _________
______ ________
_____
_________
________
O
O
Outputs WRL, WRH, (WR, BHE), RD, BCLK, HLDA and ALE signals. WRL
_________
_______
______
and WRH or BHE and WR can be switched by program.
________ _________
_____
WRL, WRH and RD are selected
BHE
_____
RD
O
O
The WRL signal becomes "L" by writing data to an even address in an external
memory space.
BCLK
__________
HLDA
O
O
The WRH signal becomes "L" by writing data to an odd address in an external
memory space.
I
O
The RD pin signal becomes "L" by reading data in an external memory space.
______ ________
_____
WR, BHE and RD are selected
I
The WR signal becomes "L" by writing data to an external memory space.
_____
The RD signal becomes "L" by reading data in an external memory space.
________
________
_________
__________
_____
HOLD
ALE
________
______
RDY
________
The BHE signal becomes "L" by accessing an odd address.
______ ________
_____
Select WR, BHE and RD for an external 8-bit data bus.
__________
While the HOLD pin is held "L", the microcomputer is placed in a hold state.
_________
In a hold state, HLDA outputs a "L" signal.
ALE is a signal latching the address.
________
While the RDY pin is held "L", the microcomputer is placed in a wait state.
______
______
DW
_________
CASL
DRAM bus control
pin
O
O
The DW signal becomes "L" by writing data to the DRAM area.
_________
_________
CASL and CASH are signals indicating a timing to latch column addresses.
O
O
The CASL signal becomes "L" by accessing an even address.
__________
The CASH signal becomes "L" by accessing an odd address.
I/O port P6
I/O
RAS is a signal latching row addresses.
8-bit I/O ports having equivalent functions to P0
UART pin
I
O
_________
_________
CASH
_______
RAS
_______
P60 to P67
_________
_________
CTS0, CTS1
_________ _________
RTS0, RTS1
______
I/O pins for UART0 (P60 to P63) and UART1 (P64 to P67)
______
SS0, SS1
CLK0, CLK1
I
I/O
RxD0, RxD1
SCL0, SCL1
I
I/O
STxD0, STxD1
TxD0, TxD1
O
O
SDA0, SDA1
SRxD0, SRxD1
I/O
I
ISCLK2
OUTC21
Intelligent I/O pin
I/O
O
ISCKL2 inputs and outputs the clock for the intelligent I/O communication
function.
OUTC21 outputs the clock for the waveform generating function.
I : Input
O : Output
Rev.1.00 Jun. 01, 2004
I/O : Input and output
page 16 of 83
1. Overview
M32C/81 Group
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Symbol
P70 to P77
Function
I/O type
Description
I/O port P7
I/O
8-bit I/O ports having equivalent functions to P0
(P70 and P71 are ports for the N-channel open drain output.)
TA0OUT to TA3OUT Timer A pin
TA0IN to TA3IN
I/O
I
I/O pins for timers A0 to A3
TB5IN
Timer B pin
Three-phase motor
I
O
Input pin for timer B5
V-phase output pin
control output pin
UART pin
O
I
W-phase output pin
I/O pins for UART2
___
V, V
___
W, W
_________
CTS2
_________
RTS2
______
SS2
O
I
CLK2
RxD2
I/O
I
SCL2
STxD2
I/O
O
TxD2
SDA2
O
I/O
SRxD2
INPC00, INPC01 Intelligent I/O pin
INPC11, INPC12
OUTC00, OUTC01
I
I
INPC00, INPC01, INPC11 and INPC12 are input pins for the time measure-
O
ment function.
OUTC00, OUTC01, OUTC10 to OUTC12, OUTC20 and OUTC22 are output
OUTC10 to OUTC12
OUTC20, OUTC22
pins for the waveform generating function.
ISCLK0 and ISCLK1 input and output the clock for the intelligent I/O communi-
ISCLK0, ISCLK1
ISTxD0 to ISTxD2
I/O
O
cation function.
ISRxD1, ISRxD2, IEIN and BE1IN input received data for the intelligent I/O
ISRxD1, ISRxD2
IEOUT
I
O
communication function.
ISTxD0 to ISTxD2, IEOUT, BE0OUT, and BE1OUT output transmit data for the
IEIN
BE0OUT
I
O
intelligent I/O communication function.
BE1OUT
BE1IN
O
I
CAN0OUT
CAN0IN
I : Input
CAN pin
O : Output
Rev.1.00 Jun. 01, 2004
O
I
I/O pins for the CAN communication function
I/O : Input and output
page 17 of 83
1. Overview
M32C/81 Group
Table 1.6 Pin Description (100-Pin and 144-Pin Packages) (Continued)
Symbol
Function
I/O type
Description
P80 to P84,
I/O port P8
I/O
I/O ports having equivalent functions to P0
P86, P87
XCIN
Sub clock
I
O
I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator
XCOUT
VCONT
Low-pass filter connect
pin for PLL frequency
between XCIN and XCOUT.
Connects the low-pass filter to the VCONT pin when using the PLL frequency
synthesizer. Connect P86 to VSS to stabilize the PLL frequency.
synthesizer pin
Timer A pin
I/O
I/O pins for timer A4
U, U
Three-phase motor
I
O
U-phase output pins
________
control output pin
______
INT interrupt input
I
Input pins for the INT interrupt
pin
Intelligent I/O pin
I
INPC02 is an input pin for the time measurement function.
ISRxD0 and BE0IN input received data for the intelligent I/O communication
TA4OUT
TA4IN
___
________
INT0 to INT2
INPC02
ISRxD0
______
I
I
BE0IN
CANOUT
CAN pin
O
I
CANIN
_______
_______
_______
NMI interrupt input
pin
P85/NMI
P90 to P97
I
I/O port P9
I/O
TB0IN to TB4IN Timer B pin
_________ __________
UART pin
CTS3, CTS4
_________ _________
RTS3, RTS4
I
I
O
_______
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
8-bit I/O ports having equivalent functions P0.
The PRCR register prevents PD9 and PS3 registers from rewriting.
Input pins for timers B0 to B4
I/O pins for UART3 (P90 to P93) and UART4 (P94 to P97)
_______
SS3, SS4
CLK3, CLK4
I
I/O
RxD3, RxD4
SCL3, SCL4
I
I/O
STxD3, STxD4
TxD3, TxD4
O
O
SDA3, SDA4
SRxD3, SRxD4
I/O
I
DA0, DA1
ANEX0,
D/A output pin
A/D related pin
ANEX1,
___________
ADTRG
OUTC20
ISTxD2
Intelligent I/O pin
IEOUT
IEIN
ISRxD2
P100 to P107
_____
function.
I/O pins for the CAN communication function
_____
I/O port P10
O
I/O
Output pins for the D/A converter
ANEX0 is an extended analog I/O pin for the A/D converter.
I
I
ANEX1 is an extended analog input pin for the A/D converter.
__________
ADTRG is an A/D trigger input pin.
O
O
OUTC20 is an output pin for the waveform generating function.
ISTxD2 and IEOUT output transmit data for the intelligent I/O communication
O
I
function.
ISRxD2 and IEIN input received data for the intelligent I/O communication
I
I/O
function.
8-bit I/O ports having equivalent functions to P0
KI0 to KI3
Key input interrupt
pin
I
Input pins for the key input interrupt
AN0 to AN7
Analog input pin
I
Analog input pins for the A/D converter
I : Input
O : Output
Rev.1.00 Jun. 01, 2004
I/O : Input and output
page 18 of 83
1. Overview
M32C/81 Group
Table 1.6 Pin Description (144-Pin Package only) (Continued)
Symbol
Function
P110 to P114
I/O port P11
INPC11, INPC12 Intelligent I/O pin
OUTC10 to OUTC13
I/O type
Description
I/O
I
5-bit I/O ports having equivalent functions to P0.
INPC11 and INPC12 are input pins for the time measurement function.
O
I/O
OUTC10 to OUTC13 are output pins for the waveform generating function.
ISCLK1 inputs and outputs the clock for the intelligent I/O communication
I
I
function.
ISRxD1 and BE1IN input received data for the intelligent I/O communication
O
O
function.
ISTxD1 and BE1OUT output transmit data for the intelligent I/O communication
I/O
function.
8-bit I/O ports having equivalent functions to P0
I/O
O
8-bit I/O ports having equivalent functions to P0
OUTC20 to OUTC27 are output pins for the waveform generating function.
I/O
I
ISCLK2 inputs and outputs the clock for the intelligent I/O communication
function.
I
O
ISRxD2 and IEIN input received data for the intelligent I/O communication
function.
O
ISTxD2 and IEOUT output transmit data for the intelligent I/O communication
function.
I/O port P14
INPC16,INPC17 Intelligent I/O pin
OUTC14 to OUTC17
I/O port P15
P150 to P157
I/O
I
7-bit I/O ports having equivalent functions to P0
INPC16 and INPC17 are input pins for the time measurement function.
O
I/O
OUTC14 to OUTC17 are output pins for the waveform generating function.
8-bit I/O ports having equivalent functions to P0
INPC00 to INPC07 Intelligent I/O pin
I
O
INPC00 to INPC07 are input pins for the time measurement function.
OUTC00, OUTC01, OUTC04 and OUTC05 are output pins for the waveform
generating function.
ISCLK0
ISRxD0
I/O
I
ISCLK0 inputs and outputs the clock for the intelligent I/O communication
function.
BE0IN
ISTxD0
I
O
ISRxD0 and BE0IN input received data for the intelligent I/O communication
function.
BE0OUT
O
ISTxD0 and BE0OUT output transmit data for the intelligent I/O communication
function.
AN150 toAN157 Analog input port
I
Analog input pins for the A/D converter
ISCLK1
ISRxD1
BE1IN
ISTxD1
BE1OUT
P120 to P127
P130 to P137
I/O port P12
I/O port P13
OUTC20 to OUTC27 Intelligent I/O pin
ISCLK2
ISRxD2
IEIN
ISTxD2
IEOUT
P140 to P146
OUTC00, OUTC01
OUTC04, OUTC05
I : Input
O : Output
Rev.1.00 Jun. 01, 2004
I/O : Input and output
page 19 of 83
2. Central Processing Unit (CPU)
M32C/81 Group
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers.
A register bank comprises 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two
sets of register banks are provided.
b31
b15
General register
b0
R2
R0H
R3
R1H
R0L
R1L
Data register(1)
R2
R3
b23
A0
Address register(1)
A1
SB
Static base register(1)
FB
Frame base register(1)
USP
User stack pointer
ISP
Interrupt stack pointer
INTB
Interrupt table register
Program counter
PC
FLG
b15
Flag register
b8 b7
IPL
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved space
Processor interrupt priority level
Reserved space
b15
High-speed interrupt register
b0
SVF
b23
Flag save register
SVP
PC save register
VCT
Vector register
b7
DMAC related register
b0
DMD0
DMD1
b15
DCT0
DCT1
DMA mode register
DMA transfer count register
DRC0
DRC1
b23
DMA transfer count reload register
DMA0
DMA1
DMA memory address register
DRA0
DRA1
DMA memory address reload register
DSA0
DSA1
DMA SFR adress register
NOTES:
1. A register bank comprise these registers. Two sets of register banks are provided.
Figure 2.1 CPU Register
Rev.1.00 Jun. 01, 2004
page 20
of 83
2. Central Processing Unit (CPU)
M32C/81 Group
2.1 General Registers
2.1.1 Data Registers (R0, R1, R2 and R3)
R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be
split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers.
R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2 Address Registers (A0 and A1)
A0 and A1 are 24-bit registers for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3 Static Base Register (SB)
SB is a 24-bit register for SB-relative addressing.
2.1.4 Frame Base Register (FB)
FB is a 24-bit register for FB-relative addressing.
2.1.5 Program Counter (PC)
PC is 24 bits wide. It indicates an address of an instruction to be executed.
2.1.6 Interrupt Table Register (INTB)
INTB is a 24-bit register indicating a starting address of an interrupt vector table.
2.1.7 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
USP and ISP as the stack pointer are 24 bits wide. The U flag can switch USP to ISP and vice versa.
Refer to "2.1.8 Flag Register (FLG)" about the U flag. Set USP and ISP to even addresses to execute an
interrupt sequence efficiently.
2.1.8 Flag Register (FLG)
FLG is a 16-bit register indicating a CPU state.
2.1.8.1 Carry Flag (C)
The C flag indicates whether carry or borrow occurs after an instruction is executed.
2.1.8.2 Debug Flag (D)
The D flag is for debug only. Set to "0".
2.1.8.3 Zero Flag (Z)
The Z flag is set to "1" when the value of zero is obtained from an arithmetic calculation; otherwise "0".
2.1.8.4 Sign Flag (S)
The S flag is set to "1" when a negative value is obtained from an arithmetic calculation; otherwise "0".
Rev.1.00 Jun. 01, 2004
page 21
of 83
2. Central Processing Unit (CPU)
M32C/81 Group
2.1.8.5 Register Bank Select Flag (B)
The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this
flag is set to "1".
2.1.8.6 Overflow Flag (O)
The O flag is set to "1" when a result of an arithmetic operation overflows; otherwise "0".
2.1.8.7 Interrupt Enable Flag (I)
The I flag enables a maskable interrupt.
An interrupt is disabled when the I flag is set to "0" and is enabled when the I flag is set to "1". The I
flag is set to "0" when an interrupt is acknowledged.
2.1.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to "0". USP is selected when this flag is set to "1".
The U flag is set to "0" when a hardware interrupt is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.1.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide. It assigns an interrupt priority levels from level 0 to level 7.
If a requested interrupt has a greater priority than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
When writing to the reserved space, set to "0". When read, its content is indeterminate.
2.2 High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows.
- Flag save register (SVF)
- PC save register (SVP)
- Vector register (VCT)
2.3 DMAC-associated Registers
Registers associated with DMAC are as follows.
- DMA mode register (DMD0, DMD1)
- DMA transfer count register (DCT0, DCT1)
- DMA transfer count reload register (DRC0, DRC1)
- DMA memory address register (DMA0, DMA1)
- DMA SFR address register (DSA0, DSA1)
- DMA memory address reload register (DRA0, DRA1)
Rev.1.00 Jun. 01, 2004
page 22
of 83
3. Memory
M32C/81 Group
3. Memory
Figure 3.1 shows a memory map of the M32C/81 group.
M32C/81 provides 16-Mbyte address space from addresses 00000016 to FFFFFF16.
The internal ROM is allocated in lower addresses beginning with address FFFFFF16. For example, a 64Kbyte internal ROM is allocated in addresses FF000016 to FFFFFF16.
The fixed interrupt vectors are allocated in addresses FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine.
The internal RAM is allocated in higher addresses beginning with address 00040016. For example, a 10Kbyte internal RAM is allocated in addresses 00040016 to 002BFF16. Besides storing data, it becomes
stacks when the subroutine is called or an interrupt is acknowleged.
The SFR is allocated in addresses 00000016 to 0003FF16. The control registers for peripheral functions
such as I/O port, A/D conversion, serial I/O, timer are allocated here. All addresses, which have nothing
allocated within the SFR, are reserved space and cannot be accessed by users.
The special page vectors are allocated in addresses FFFE0016 to FFFFDB16. It is used for the JMPS
instruction and JSRS instruction. Refer to the Renesas publication Software Manual for details.
In memory expansion mode and microprocessor mode, some space are reserved and cannot be accessed
by users.
00000016
SFR
00040016
XXXXXX16
Internal RAM
Reserved space(1)
FFFE00 16
00800016
Special page
vector table
External space
Type number
Address
XXXXXX 16
M30810MC-XXXFP/GP
M30812MC-XXXGP
002BFF16
M3081LMC-XXXFP/GP
M3081NMC-XXXGP
0033FF16
Address
YYYYYY 16
FFFFDC 16
Undefined instruction
Overflow
BRK instruction
Address match
F0000016
Reserved space(2)
Watchdog timer
YYYYYY16
FE000016
Internal RAM
FFFFFF16
FFFFFF 16
NOTES:
1. In memory expansion and microprocessor modes
2. In memory expansion mode
Figure 3.1 Memory Map
Rev.1.00 Jun. 01, 2004
page 23 of 83
NMI
Reset
4. Special Function Registers (SFR)
M32C/81 Group
4. Special Function Registers (SFR)
Address
000016
000116
000216
000316
Register
Symbol
Value after RESET
1000 00002(CNVss pin ="L")
000416
Processor mode register 0
PM0
000516
000616
000716
000816
000916
000A16
Processor mode register 1
System clock control register 0
System clock control register 1
Wait control register
Address match interrupt enable register
Protect register
PM1
CM0
CM1
WCR
AIER
PRCR
000B16
External data bus width control register
DS
000C16
000D16
000E16
000F16
001016
001116
Main clock division register
Oscillation stop detect register
Watchdog timer start register
Watchdog timer control register
MCD
CM2
WDTS
WDC
Address match interrupt register 0
RMAD0
00000016
Address match interrupt register 1
RMAD1
00000016
VDC control register for PLL
PLV
XXXX XX012
Address match interrupt register 2
RMAD2
00000016
VDC control register 0
VDC0
0016
Address match interrupt register 3
RMAD3
00000016
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 24 of 83
0000 00112(CNVss pin ="H")
0X00 00002
0000 X0002
0010 00002
1111 11112
XXXX 00002
XXXX 00002
XXXX 10002(BYTE pin ="L")
XXXX 00002(BYTE pin ="H")
XXX0 10002
0016
XX16
000X XXXX2
4. Special Function Registers (SFR)
M32C/81 Group
Address
Register
003016
003116
003216
003316
003416
003516
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004016 DRAM control register
004116 DRAM refresh interval set register
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 25
of 83
Symbol
DRAMCONT
REFCNT
Value after RESET
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
Address
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Register
Symbol
Value after RESET
DMA0 interrupt control register
Timer B5 interrupt control register
DMA2 interrupt control register
UART2 receive /ACK interrupt control register
Timer A0 interrupt control register
UART3 receive /ACK interrupt control register
Timer A2 interrupt control register
UART4 receive /ACK interrupt control register
Timer A4 interrupt control register
UART0/UART3 bus conflict detect interrupt control register
UART0 receive/ACK interrupt control register
A/D0 conversion interrupt control register
UART1 receive/ACK interrupt control register
Intelligent I/O interrupt control register 0
Timer B1 interrupt control register
Intelligent I/O interrupt control register 2
Timer B3 interrupt control register
Intelligent I/O interrupt control register 4
INT5 interrupt control register
Intelligent I/O interrupt control register 6
INT3 interrupt control register
Intelligent I/O interrupt control register 8
INT1 interrupt control register
Intelligent I/O interrupt control register 10/
DM0IC
TB5IC
DM2IC
S2RIC
TA0IC
S3RIC
TA2IC
S4RIC
TA4IC
BCN0IC/BCN3IC
S0RIC
AD0IC
S1RIC
IIO0IC
TB1IC
IIO2IC
TB3IC
IIO4IC
INT5IC
IIO6IC
INT3IC
IIO8IC
INT1IC
IIO10IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XX00 X0002
XXXX X0002
XX00 X0002
XXXX X0002
XX00 X0002
CAN interrupt 1 control register
CAN1IC
Intelligent I/O interrupt control register 11/
IIO11IC
CAN interrupt 2 control register
CAN2IC
A/D1 conversion interrupt control register
AD1IC
XXXX X0002
DMA1 interrupt control register
UART2 transmit /NACK interrupt control register
DMA3 interrupt control register
UART3 transmit /NACK interrupt control register
Timer A1 interrupt control register
UART4 transmit /NACK interrupt control register
Timer A3 interrupt control register
UART2 bus conflict detect interrupt control register
DM1IC
S2TIC
DM3IC
S3TIC
TA1IC
S4TIC
TA3IC
BCN2IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
008016
008116
008216
008316
008416
008516
008616
008716
008816
008916
008A16
008B16
008C16
008D16
008E16
008F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 26 of 83
XXXX X0002
4. Special Function Registers (SFR)
M32C/81 Group
Address
009016
009116
009216
009316
009416
Register
UART0 transmit /NACK interrupt control register
UART1/UART4 bus conflict detect interrupt control register
UART1 transmit/NACK interrupt control register
Key input interrupt control register
Timer B0 interrupt control register
Symbol
S0TIC
BCN1IC/BCN4IC
S1TIC
KUPIC
TB0IC
Value after RESET
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
009516
009616
009716
009816
009916
009A16
009B16
009C16
Intelligent I/O interrupt control register 1
Timer B2 interrupt control register
Intelligent I/O interrupt control register 3
Timer B4 interrupt control register
Intelligent I/O interrupt control register 5
INT4 interrupt control register
Intelligent I/O interrupt control register 7
INT2 interrupt control register
Intelligent I/O interrupt control register 9/
IIO1IC
TB2IC
IIO3IC
TB4IC
IIO5IC
INT4IC
IIO7IC
INT2IC
IIO9IC
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XXXX X0002
XX00 X0002
XXXX X0002
XX00 X0002
CAN interrupt 0 control register
INT0 interrupt control register
Exit priority control register
Interrupt request register 0
Interrupt request register 1
Interrupt request register 2
Interrupt request register 3
Interrupt request register 4
Interrupt request register 5
Interrupt request register 6
Interrupt request register 7
Interrupt request register 8
Interrupt request register 9
Interrupt request register 10
Interrupt request register 11
CAN0IC
INT0IC
RLVL
IIO0IR
IIO1IR
IIO2IR
IIO3IR
IIO4IR
IIO5IR
IIO6IR
IIO7IR
IIO8IR
IIO9IR
IIO10IR
IIO11IR
XX00 X0002
XXXX 00002
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
0000 000X2
Interrupt enable register 0
Interrupt enable register 1
Interrupt enable register 2
Interrupt enable register 3
Interrupt enable register 4
Interrupt enable register 5
Interrupt enable register 6
Interrupt enable register 7
Interrupt enable register 8
Interrupt enable register 9
Interrupt enable register 10
Interrupt enable register 11
IIO0IE
IIO1IE
IIO2IE
IIO3IE
IIO4IE
IIO5IE
IIO6IE
IIO7IE
IIO8IE
IIO9IE
IIO10IE
IIO11IE
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
009D16
009E16
009F16
00A016
00A116
00A216
00A316
00A416
00A516
00A616
00A716
00A816
00A916
00AA16
00AB16
00AC16
00AD16
00AE16
00AF16
00B016
00B116
00B216
00B316
00B416
00B516
00B616
00B716
00B816
00B916
00BA16
00BB16
00BC16
00BD16
00BE16
00BF16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 27
of 83
XXXX X0002
4. Special Function Registers (SFR)
M32C/81 Group
Address
00C016
00C116
00C216
00C316
00C416
00C516
00C616
00C716
00C816
00C916
00CA16
00CB16
00CC16
00CD16
00CE16
00CF16
00D016
00D116
00D216
00D316
00D416
00D516
00D616
00D716
00D816
00D916
00DA16
00DB16
00DC16
00DD16
00DE16
00DF16
00E016
00E116
00E216
00E316
00E416
00E516
00E616
00E716
00E816
00E916
00EA16
00EB16
00EC16
00ED16
00EE16
00EF16
Register
Symbol
Value after RESET
XX16
Group 0 time measurement/waveform generating register 0
G0TM0/G0PO0
Group 0 time measurement/waveform generating register 1
G0TM1/G0PO1
Group 0 time measurement/waveform generating register 2
G0TM2/G0PO2
Group 0 time measurement/waveform generating register 3
G0TM3/G0PO3
Group 0 time measurement/waveform generating register 4
G0TM4/G0PO4
Group 0 time measurement/waveform generating register 5
G0TM5/G0PO5
Group 0 time measurement/waveform generating register 6
G0TM6/G0PO6
Group 0 time measurement/waveform generating register 7
G0TM7/G0PO7
Group 0 waveform generating control register 0
Group 0 waveform generating control register 1
Group 0 waveform generating control register 2
Group 0 waveform generating control register 3
Group 0 waveform generating control register 4
Group 0 waveform generating control register 5
Group 0 waveform generating control register 6
Group 0 waveform generating control register 7
Group 0 time measurement control register 0
Group 0 time measurement control register 1
Group 0 time measurement control register 2
Group 0 time measurement control register 3
Group 0 time measurement control register 4
Group 0 time measurement control register 5
Group 0 time measurement control register 6
Group 0 time measurement control register 7
G0POCR0
G0POCR1
G0POCR2
G0POCR3
G0POCR4
G0POCR5
G0POCR6
G0POCR7
G0TMCR0
G0TMCR1
G0TMCR2
G0TMCR3
G0TMCR4
G0TMCR5
G0TMCR6
G0TMCR7
Group 0 base timer register
G0BT
Group 0 base timer control register 0
Group 0 base timer control register 1
Group 0 time measurement prescaler register 6
Group 0 time measurement prescaler register 7
Group 0 function enable register
Group 0 function select register
G0BCR0
G0BCR1
G0TPR6
G0TPR7
G0FE
G0FS
Group 0 SI/O receive buffer register
G0RB
Group 0 transmit buffer/receive data register
G0TB/G0DR
XX00 XXXX2
XX16
Group 0 receive input register
Group 0 SI/O communication mode register
Group 0 transmit output register
Group 0 SI/O communication control register
G0RI
G0MR
G0TO
G0CR
XX16
0016
XX16
0000 X0002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 28 of 83
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0016
0016
0016
0016
0016
0016
0016
0016
XX16
XX16
0016
0016
0016
0016
0016
0016
XXXX XXXX2
4. Special Function Registers (SFR)
M32C/81 Group
Address
00F016
00F116
00F216
00F316
00F416
00F516
00F616
00F716
00F816
00F916
00FA16
00FB16
00FC16
00FD16
00FE16
00FF16
010016
010116
010216
010316
010416
010516
010616
010716
010816
010916
010A16
010B16
010C16
010D16
010E16
010F16
011016
011116
011216
011316
011416
011516
011616
011716
011816
011916
011A16
011B16
011C16
011D16
011E16
011F16
Register
Group 0 data compare register 0
Group 0 data compare register 1
Group 0 data compare register 2
Group 0 data compare register 3
Group 0 data mask register 0
Group 0 data mask register 1
Symbol
G0CMP0
G0CMP1
G0CMP2
G0CMP3
G0MSK0
G0MSK1
Group 0 receive CRC code register
G0RCRC
Group 0 transmit CRC code register
G0TCRC
Group 0 SI/O extended mode register
Group 0 SI/O extended receive control register
Group 0 SI/O special communication interrupt detect register
Group 0 SI/O extended transmit control register
G0EMR
G0ERC
G0IRF
G0ETC
Group 1 time measurement/waveform generating register 0
G1TM0/G1PO0
Group 1 time measurement/waveform generating register 1
G1TM1/G1PO1
Group 1 time measurement/waveform generating register 2
G1TM2/G1PO2
Group 1 time measurement/waveform generating register 3
G1TM3/G1PO3
Group 1 time measurement/waveform generating register 4
G1TM4/G1PO4
Group 1 time measurement/waveform generating register 5
G1TM5/G1PO5
Group 1 time measurement/waveform generating register 6
G1TM6/G1PO6
Group 1 time measurement/waveform generating register 7
G1TM7/G1PO7
Group 1 waveform generating control register 0
Group 1 waveform generating control register 1
Group 1 waveform generating control register 2
Group 1 waveform generating control register 3
Group 1 waveform generating control register 4
Group 1 waveform generating control register 5
Group 1 waveform generating control register 6
Group 1 waveform generating control register 7
Group 1 time measurement control register 0
Group 1 time measurement control register 1
Group 1 time measurement control register 2
Group 1 time measurement control register 3
Group 1 time measurement control register 4
Group 1 time measurement control register 5
Group 1 time measurement control register 6
Group 1 time measurement control register 7
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 29
of 83
XX16
0016
0016
0016
0016
0000 00XX2
0000 0XXX2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0X00 X0002
0016
0016
0016
0016
0016
0016
0016
0016
4. Special Function Registers (SFR)
M32C/81 Group
Address
012016
012116
012216
012316
012416
012516
012616
012716
012816
012916
012A16
012B16
012C16
012D16
012E16
012F16
013016
013116
013216
013316
013416
013516
013616
013716
013816
013916
013A16
013B16
013C16
013D16
013E16
013F16
014016
014116
014216
014316
014416
014516
014616
014716
014816
014916
014A16
014B16
014C16
014D16
014E16
014F16
Register
Symbol
Value after RESET
XX16
Group 1 base timer register
G1BT
Group 1 base timer control register 0
Group 1 base timer control register 1
Group 1 time measurement prescaler register 6
Group 1 time measurement prescaler register 7
Group 1 function enable register
Group 1 function select register
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
G1FS
Group 1 SI/O receive buffer register
G1RB
Group 1 transmit buffer/receive data register
G1TB/G1DR
XX00 XXXX2
XX16
Group 1 receive input register
Group 1 SI/O communication mode register
Group 1 transmit output register
Group 1 SI/O communication control register
Group 1 data compare register 0
Group 1 data compare register 1
Group 1 data compare register 2
Group 1 data compare register 3
Group 1 data mask register 0
Group 1 data mask register 1
G1RI
G1MR
G1TO
G1CR
G1CMP0
G1CMP1
G1CMP2
G1CMP3
G1MSK0
G1MSK1
XX16
0016
XX16
0000 X0002
XX16
XX16
XX16
XX16
XX16
XX16
Group 1 receive CRC code register
G1RCRC
Group 1 transmit CRC code register
G1TCRC
Group 1 SI/O extended mode register
Group 1 SI/O extended receive control register
Group 1 SI/O special communication interrupt detect register
Group 1 SI/O extended transmit control register
G1EMR
G1ERC
G1IRF
G1ETC
Group 2 waveform generating register 0
G2PO0
Group 2 waveform generating register 1
G2PO1
Group 2 waveform generating register 2
G2PO2
Group 2 waveform generating register 3
G2PO3
Group 2 waveform generating register 4
G2PO4
Group 2 waveform generating register 5
G2PO5
Group 2 waveform generating register 6
G2PO6
Group 2 waveform generating register 7
G2PO7
XX16
0016
0016
0016
0016
0016
0016
XXXX XXXX2
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 30 of 83
XX16
0016
0016
0016
0016
0000 00XX2
0000 0XXX2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
Address
015016
015116
015216
015316
015416
015516
015616
015716
015816
015916
015A16
015B16
015C16
015D16
015E16
015F16
016016
016116
016216
016316
016416
016516
016616
016716
016816
016916
016A16
016B16
016C16
016D16
016E16
016F16
017016
017116
017216
017316
017416
017516
017616
017716
017816
017916
017A16
017B16
017C16
017D16
017E16
017F16
to
01AF16
Register
Group 2 waveform generating control register 0
Group 2 waveform generating control register 1
Group 2 waveform generating control register 2
Group 2 waveform generating control register 3
Group 2 waveform generating control register 4
Group 2 waveform generating control register 5
Group 2 waveform generating control register 6
Group 2 waveform generating control register 7
Symbol
G2POCR0
G2POCR1
G2POCR2
G2POCR3
G2POCR4
G2POCR5
G2POCR6
G2POCR7
Value after RESET
0016
0016
0016
0016
0016
0016
0016
0016
Group 2 base timer register
G2BT
Group 2 base timer control register 0
Group 2 base timer control register 1
Base timer start register
G2BCR0
G2BCR1
BTSR
XX16
0016
0016
XXXX 00002
Group 2 function enable register
Group 2 RTP output buffer register
G2FE
G2RTP
0016
0016
Group 2 SI/O communication mode register
Group 2 SI/O communication control register
G2MR
G2CR
00XX X0002
0000 X0002
XX16
Group 2 SI/O transmit buffer register
G2TB
Group 2 SI/O receive buffer register
G2RB
Group 2 IEBus address register
IEAR
Group 2 IEBus control register
Group 2 IEBus transmit interrupt cause detect register
Group 2 IEBus receive interrupt cause detect register
IECR
IETIF
IERIF
00XX X0002
XXX0 00002
XXX0 00002
Input function select register
IPS
0016
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 31
of 83
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
Address
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
Register
Symbol
Value after RESET
01BD16
01BE16
01BF16
01C016
01C116
01C216
01C316
01C416
01C516
01C616
01C716
01C816
01C916
01CA16
01CB16
01CC16
01CD16
01CE16
XX16
A/D1 register 0
AD10
A/D1 register 1
AD11
A/D1 register 2
AD12
A/D1 register 3
AD13
A/D1 register 4
AD14
A/D1 register 5
AD15
A/D1 register 6
AD16
A/D1 register 7
01CF16
01D016
01D116
01D216
01D316
01D416 A/D1 control register 2
01D516
01D616 A/D1 control register 0
01D716 A/D1 control register 1
01D816
01D916
01DA16
01DB16
01DC16
01DD16
01DE16
01DF16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 32 of 83
AD17
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
AD1CON2
X00X X0002
AD1CON0
AD1CON1
0016
XX00 00002
4. Special Function Registers (SFR)
M32C/81 Group
Address
01E016
01E116
01E216
01E316
01E416
01E516
01E616
01E716
01E816
01E916
01EA16
01EB16
01EC16
01ED16
01EE16
01EF16
01F016
01F116
01F216
01F316
01F416
01F516
01F616
01F716
01F816
01F916
01FA16
01FB16
01FC16
01FD16
01FE16
01FF16
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
Register
CAN0 message slot buffer 0 standard ID0
CAN0 message slot buffer 0 standard ID1
CAN0 message slot buffer 0 extended ID0
CAN0 message slot buffer 0 extended ID1
CAN0 message slot buffer 0 extended ID2
CAN0 message slot buffer 0 data length code
CAN0 message slot buffer 0 data 0
CAN0 message slot buffer 0 data 1
CAN0 message slot buffer 0 data 2
CAN0 message slot buffer 0 data 3
CAN0 message slot buffer 0 data 4
CAN0 message slot buffer 0 data 5
CAN0 message slot buffer 0 data 6
CAN0 message slot buffer 0 data 7
CAN0 message slot buffer 0 time stamp high-order
CAN0 message slot buffer 0 time stamp low-order
CAN0 message slot buffer 1 standard ID0
CAN0 message slot buffer 1 standard ID1
CAN0 message slot buffer 1 extended ID0
CAN0 message slot buffer 1 extended ID1
CAN0 message slot buffer 1 extended ID2
CAN0 message slot buffer 1 data length code
CAN0 message slot buffer 1 data 0
CAN0 message slot buffer 1 data 1
CAN0 message slot buffer 1 data 2
CAN0 message slot buffer 1 data 3
CAN0 message slot buffer 1 data 4
CAN0 message slot buffer 1 data 5
CAN0 message slot buffer 1 data 6
CAN0 message slot buffer 1 data 7
CAN0 message slot buffer 1 time stamp high-order
CAN0 message slot buffer 1 time stamp low-order
Symbol
C0SLOT0_0
C0SLOT0_1
C0SLOT0_2
C0SLOT0_3
C0SLOT0_4
C0SLOT0_5
C0SLOT0_6
C0SLOT0_7
C0SLOT0_8
C0SLOT0_9
C0SLOT0_10
C0SLOT0_11
C0SLOT0_12
C0SLOT0_13
C0SLOT0_14
C0SLOT0_15
C0SLOT1_0
C0SLOT1_1
C0SLOT1_2
C0SLOT1_3
C0SLOT1_4
C0SLOT1_5
C0SLOT1_6
C0SLOT1_7
C0SLOT1_8
C0SLOT1_9
C0SLOT1_10
C0SLOT1_11
C0SLOT1_12
C0SLOT1_13
C0SLOT1_14
C0SLOT1_15
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX01 0X012(1)
CAN0 control register 0
C0CTLR0
XXXX 00002(1)
0000 00002(1)
CAN0 status register
C0STR
X000 0X012(1)
0016(1)
CAN0 extended ID register
C0IDR
0016(1)
0000 XXXX2(1)
CAN0 configuration register
C0CONR
0000 00002(1)
0016(1)
CAN0 time stamp register
C0TSR
CAN0 transmit error count register
CAN0 receive error count register
C0TEC
C0REC
0016(1)
0016(1)
0016(1)
0016(1)
CAN0 slot interrupt status register
C0SISTR
0016(1)
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a
clock to the CAN module after reset.
Rev.1.00 Jun. 01, 2004
page 33
of 83
4. Special Function Registers (SFR)
M32C/81 Group
Address
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
Register
Symbol
Value after RESET
0016(2)
CAN0 slot interrupt mask register
C0SIMKR
0016(2)
CAN0 error interrupt mask register
CAN0 error interrupt status register
C0EIMKR
C0EISTR
XXXX X0002(2)
XXXX X0002(2)
CAN0 baud rate prescaler
C0BRP
0000 00012(2)
CAN0 global mask register standard ID0
CAN0 global mask register standard ID1
CAN0 global mask register extended ID0
CAN0 global mask register extended ID1
CAN0 global mask register extended ID2
C0GMR0
C0GMR1
C0GMR2
C0GMR3
C0GMR4
XXX0 00002(2)
XX00 00002(2)
XXXX 00002(2)
0016(2)
XX00 00002(2)
(Note 1)
00002(2)
CAN0 message slot 0 control register /
C0MCTL0/
0000
CAN0 local mask register A standard ID0
CAN0 message slot 1 control register /
C0LMAR0
C0MCTL1/
XXX0 00002(2)
0000 00002(2)
CAN0 local mask register A standard ID1
CAN0 message slot 2 control register /
C0LMAR1
C0MCTL2/
XX00 00002(2)
0000 00002(2)
CAN0 local mask register A extended ID0
CAN0 message slot 3 control register /
C0LMAR2
C0MCTL3/
XXXX 00002(2)
0016(2)
CAN0 local mask register A extended ID1
CAN0 message slot 4 control register /
C0LMAR3
C0MCTL4/
0016(2)
0000 00002(2)
CAN0 local mask register A extended ID2
CAN0 message slot 5 control register
CAN0 message slot 6 control register
CAN0 message slot 7 control register
CAN0 message slot 8 control register /
CAN0 local mask register B standard ID0
C0LMAR4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8/
C0LMBR0
XX00 00002(2)
0016(2)
0016(2)
0016(2)
0000 00002(2)
XXX0 00002(2)
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16.
2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a
clock to the CAN module after reset.
Rev.1.00 Jun. 01, 2004
page 34 of 83
4. Special Function Registers (SFR)
M32C/81 Group
Address
023916
023A16
023B16
023C16
023D16
023E16
023F16
024016
024116
024216
024316
024416
024516
024616
024716
024816
024916
024A16
024B16
024C16
024D16
024E16
024F16
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
026016
026116
to
02BF16
Register
CAN0 message slot 9 control register /
Symbol
C0MCTL9/
Value after RESET
0000 00002(2)
CAN0 local mask register B standard ID1
CAN0 message slot 10 control register /
C0LMBR1
C0MCTL10/
XX00 00002(2)
0000 00002(2)
CAN0 local mask register B extended ID0
CAN0 message slot 11 control register /
C0LMBR2
C0MCTL11/
XXXX 00002(2)
0016(2)
CAN0 local mask register B extended ID1
CAN0 message slot 12 control register /
C0LMBR3
C0MCTL12/
0016(2)
0000 00002(2)
CAN0 local mask register B extended ID2
CAN0 message slot 13 control register
CAN0 message slot 14 control register
CAN0 message slot 15 control register
CAN0 slot buffer select register
CAN0 control register 1
CAN0 sleep control register
C0LMBR4
C0MCTL13
C0MCTL14
C0MCTL15
C0SBS
C0CTLR1
C0SLPR
XX00 00002(2)
0016(2)
0016(2)
0016(2)
0016(2)
XX00 00XX2(2)
XXXX XXX02
CAN0 acceptance filter support register
C0AFS
0016(2)
0116(2)
(Note 1)
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1. The BANKSEL bit in the C0CTLR1 register switches functions for addresses 022016 to 023F16.
2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) and supplying a
clock to the CAN module after reset.
Rev.1.00 Jun. 01, 2004
page 35
of 83
4. Special Function Registers (SFR)
M32C/81 Group
Address
02C016
02C116
02C216
02C316
02C416
02C516
02C616
02C716
02C816
02C916
02CA16
02CB16
02CC16
02CD16
02CE16
02CF16
02D016
02D116
02D216
02D316
02D416
02D516
02D616
02D716
02D816
02D916
02DA16
02DB16
02DC16
02DD16
02DE16
02DF16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
Register
Symbol
X0 register Y0 register
X0R,Y0R
X1 register Y1 register
X1R,Y1R
X2 register Y2 register
X2R,Y2R
X3 register Y3 register
X3R,Y3R
X4 register Y4 register
X4R,Y4R
X5 register Y5 register
X5R,Y5R
X6 register Y6 register
X6R,Y6R
X7 register Y7 register
X7R,Y7R
X8 register Y8 register
X8R,Y8R
X9 register Y9 register
X9R,Y9R
X10 register Y10 register
X10R,Y10R
X11 register Y11 register
X11R,Y11R
X12 register Y12 register
X12R,Y12R
X13 register Y13 register
X13R,Y13R
X14 register Y14 register
X14R,Y14R
X15 register Y15 register
X15R,Y15R
XY control register
XYC
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART1 transmit/receive mode register
UART1 baud rate register
U1SMR4
U1SMR3
U1SMR2
U1SMR
U1MR
U1BRG
UART1 transmit buffer register
02EB16
02EC16 UART1 transmit/receive control register 0
02ED16 UART1 transmit/receive control register 1
02EE16
UART1 receive buffer register
02EF16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 36 of 83
U1TB
U1C0
U1C1
U1RB
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XXXX XX002
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
Address
02F016
02F116
02F216
02F316
02F416
02F516
02F616
02F716
02F816
02F916
02FA16
02FB16
02FC16
02FD16
02FE16
02FF16
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
Register
Symbol
Value after RESET
UART4 special mode register 4
UART4 special mode register 3
UART4 special mode register 2
UART4 special mode register
UART4 transmit/receive mode register
UART4 baud rate register
U4SMR4
U4SMR3
U4SMR2
U4SMR
U4MR
U4BRG
0016
0016
0016
0016
0016
XX16
XX16
UART4 transmit buffer register
U4TB
UART4 transmit/receive control register 0
UART4 transmit/receive control register 1
U4C0
U4C1
UART4 receive buffer register
U4RB
Timer B3,B4,B5 count start flag
TBSR
Timer A1-1 register
TA11
Timer A2-1 register
TA21
Timer A4-1 register
TA41
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
Timer B2 interrupt generating frequency set counter
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
Timer B3 register
TB3
Timer B4 register
TB4
Timer B5 register
TB5
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
TB3MR
TB4MR
TB5MR
00XX 00002
00XX 00002
00XX 00002
External interrupt cause select register
IFSR
0016
XX16
0000 10002
0000 00102
XX16
XX16
000X XXXX2
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
XX11 11112
XX11 11112
XX16
XX16
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 37
of 83
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
Address
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
Register
Symbol
UART3 special mode register 4
UART3 special mode register 3
UART3 special mode register 2
UART3 special mode register
UART3 transmit/receive mode register
UART3 baud rate register
U3SMR4
U3SMR3
U3SMR2
U3SMR
U3MR
U3BRG
UART3 transmit buffer register
U3TB
UART3 transmit/receive control register 0
UART3 transmit/receive control register 1
U3C0
U3C1
UART3 receive buffer register
U3RB
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 baud rate register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
UART2 transmit buffer register
U2TB
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
U2C0
U2C1
UART2 receive buffer register
U2RB
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
TABSR
CPSRF
ONSF
TRGSR
UDF
Timer A0 register
TA0
Timer A1 register
TA1
Timer A2 register
TA2
Timer A3 register
TA3
Timer A4 register
TA4
Value after RESET
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
0016
0XXX XXXX2
0016
0016
0016
XX16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 38 of 83
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
Address
Register
035016
Timer B0 register
035116
035216
Timer B1 register
035316
035416
Timer B2 register
035516
035616 Timer A0 mode register
035716 Timer A1 mode register
035816 Timer A2 mode register
035916 Timer A3 mode register
035A16 Timer A4 mode register
035B16 Timer B0 mode register
035C16 Timer B1 mode register
035D16 Timer B2 mode register
035E16 Timer B2 special mode register
035F16 Count source prescaler register
036016
036116
036216
036316
036416 UART0 special mode register 4
036516 UART0 special mode register 3
036616 UART0 special mode register 2
036716 UART0 special mode register
036816 UART0 transmit/receive mode register
036916 UART0 baud rate register
036A16
UART0 transmit buffer register
036B16
036C16 UART0 transmit/receive control register 0
036D16 UART0 transmit/receive control register 1
036E16
UART0 receive buffer register
036F16
037016
037116
037216
037316
037416
037516
037616 PLL control register 0
037716 PLL control register 1
037816 DMA0 cause select register
037916 DMA1 cause select register
037A16 DMA2 cause select register
037B16 DMA3 cause select register
037C16
CRC data register
037D16
037E16 CRC input register
037F16
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 39
of 83
Symbol
TB0
TB1
TB2
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
TCSPR
U0SMR4
U0SMR3
U0SMR2
U0SMR
U0MR
U0BRG
U0TB
U0C0
U0C1
U0RB
PLC0
PLC1
DM0SL
DM1SL
DM2SL
DM3SL
CRCD
CRCIN
Value after RESET
XX16
XX16
XX16
XX16
XX16
XX16
0000 0X002
0000 0X002
0000 0X002
0000 0X002
0000 0X002
00XX 00002
00XX 00002
00XX 00002
XXXX XXX02
0XXX 00002
0016
0016
0016
0016
0016
XX16
XX16
XX16
0000 10002
0000 00102
XX16
XX16
0011 X1002
XXXX 00002
0X00 00002
0X00 00002
0X00 00002
0X00 00002
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
Register
Symbol
Value after RESET
XX16
A/D0 register 0
AD00
A/D0 register 1
AD01
A/D0 register 2
AD02
A/D0 register 3
AD03
A/D0 register 4
AD04
A/D0 register 5
AD05
A/D0 register 6
AD06
A/D0 register 7
AD07
A/D0 control register 2
AD0CON2
X000 00002
A/D0 control register 0
A/D0 control register 1
D/A register 0
AD0CON0
AD0CON1
DA0
0016
0016
XX16
D/A register 1
DA1
XX16
D/A control register
DACON
XXXX XX002
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 40 of 83
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
4. Special Function Registers (SFR)
M32C/81 Group
<144-pin package>
Address
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
Register
Function select register A8
Function select register A9
Symbol
PS8
PS9
Value after RESET
X000 00002
0016
Function select register C
Function select register A0
Function select register A1
Function select register B0
Function select register B1
Function select register A2
Function select register A3
Function select register B2
Function select register B3
PSC
PS0
PS1
PSL0
PSL1
PS2
PS3
PSL2
PSL3
00X0 00002
0016
0016
0016
0016
00X0 00002
0016
00X0 00002
0016
Function select register A5
PS5
XXX0 00002
Function select register A7
PS7
0016
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
Port P11 register
Port P10 direction register
Port P11 direction register
Port P12 register
Port P13 register
Port P12 direction register
Port P13 direction register
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
XX16
XX16
0016
0016
XX16
XX16
00X0 00002
0016
XX16
XX16
0016
XXX0 00002
XX16
XX16
0016
0016
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 41
of 83
4. Special Function Registers (SFR)
M32C/81 Group
<144-pin package>
Address
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Register
Port P14 register
Port P15 register
Port P14 direction register
Port P15 direction register
Symbol
P14
P15
PD14
PD15
Value after RESET
XX16
XX16
X000 00002
0016
Pull-up control register 2
Pull-up control register 3
Pull-up control register 4
PUR2
PUR3
PUR4
0016
0016
XXXX 00002
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
Pull-up control register 0
Pull-up control register 1
PUR0
PUR1
0016
XXXX 00002
Port control register
PCR
XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
Rev.1.00 Jun. 01, 2004
page 42 of 83
4. Special Function Registers (SFR)
M32C/81 Group
<100-pin package>
Register
Symbol
Value after RESET
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234(Note 2)
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
Address
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
Function select register C
Function select register A0
Function select register A1
Function select register B0
PSC
PS0
PS1
PSL0
0X00 00002
0016
0016
0016
Function select register B1
Function select register A2
Function select register A3
Function select register B2
Function select register B3
PSL1
PS2
PS3
PSL2
PSL3
0016
00X0 00002
0016
00X0 00002
0016
12345678901234567890123456789012123456789012345678901234(Note 2)
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234(Note 2)
12345678901234567890123456789012123456789012345678901234
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XX16
XX16
0016
0016
XX16
XX16
00X0 00002
0016
XX16
Port P10 direction register
PD10
0016
12345678901234567890123456789012123456789012345678901234(Note 2)
12345678901234567890123456789012123456789012345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
12345678901234567890123456789012123456789012345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890 (Note 1)
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234(Note 2)
12345678901234567890123456789012123456789012345678901234
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
(Note 1)
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
1234567
1234567
1234
1234
1234
1. 1234567
1234567 Set address spaces 03CB16, 03CE16 and 03CF16 to "FF16" in the 100-pin package.
2.
Address spaces 03A016, 03A116, 03B916, 03BC16, 03BD16, 03C916, 03CC16 and 03CD16 are not provided in
the 100-pin package.
Rev.1.00 Jun. 01, 2004
page 43
of 83
4. Special Function Registers (SFR)
M32C/81 Group
<100-pin package>
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
12345678901234567890123456789012123456789012345678901234
Address
Register
Symbol
Value after RESET
03D016
(Note 3)
03D116 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03D216 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 (Note 1)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03D316 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901
03D416
03D516
03D616
03D716
03D816
03D916
03DA16 Pull-up control register 2
PUR2
0016
03DB16 123456789012345678901234567890121234567890123456789012345678901212345678901234567
Pull-up control register 3
PUR3
0016
123456789012345678901234567890121234567890123456789012345678901212345678901234567
03DC16 123456789012345678901234567890121234567890123456789012345678901212345678901234567(Note 2)
03DD16
03DE16
03DF16
03E016 Port P0 register
P0
XX16
03E116 Port P1 register
P1
XX16
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
Pull-up control register 0
Pull-up control register 1
PUR0
PUR1
0016
XXXX 00002
Port control register
PCR
XXXX XXX02
X: Indeterminate
Blank spaces are reserved. No access is allowed.
NOTES:
123456
1. 123456
123456 Set address spaces 03D216 and 03D316 to "FF16" in the 100-pin package.
1234
2. 1234 Set address spaces 03DC16 to "0016" in the 100-pin package.
3.
123
123 Address space 03D016 and 03D116 are not provided in the 100-pin package.
Rev.1.00 Jun. 01, 2004
page 44 of 83
5. Electrical Characteristics
M32C/81 Group
5. Electrical Characteristics
Table 5.1 Absolute Maximum Ratings
Condition
Value
Unit
VCC
Symbol
Supply voltage
Parameter
VCC=AVCC
-0.3 to 6.0
V
AVCC
Analog supply voltage
VCC=AVCC
-0.3 to 6.0
V
VI
Input voltage
-0.3 to VCC+0.3
V
RESET, CNVSS, BYTE, P00-P07, P10-P17, P20-P27,
P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80P87, P90-P97, P100-P107, P110-P114, P120-P127,
P130-P137, P140-P146, P150-P157(1), VREF, XIN
P70, P71
VO
-0.3 to 6.0
Output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XOUT
P70, P71
Pd
Power Dissipation
Topr
Operating ambient temperature
Tstg
Storage temperature
NOTES:
1. P11 to P15 are provided in the 144-pin package.
2. This is an option that is on request basis.
Rev.1.00 Jun. 01, 2004
page 45 of 83
Topr=25° C
-0.3 to VCC+0.3
V
-0.3 to 6.0
V
500
mW
-20 to 85/-40 to 85(2) ° C
-65 to 150
°C
5. Electrical Characteristics
M32C/81 Group
Table 5.2 Recommended Operating Conditions (VCC = 3.0V to 5.5V at Topr = – 20 to 85oC/– 40 to 85oC(3))
Symbol
VCC
Parameter
Standard
Supply voltage (Through VDC)
Supply voltage (Not through VDC)
Analog supply voltage
Supply voltage
Analog supply voltage
Input high ("H") P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P72-P77, P80voltage
P87(4), P90-P97, P100-P107, P110-P114, P120-P127, P130-
AVCC
VSS
AVSS
VIH
VIL
Input low ("L")
voltage
IOH(peak)
IOH(avg)
IOL(peak)
Min
3.0
3.0
Typ
5.0
3.3
VCC
0
0
Unit
Max
5.5
3.6
V
V
V
V
V
V
0.8VCC
VCC
P137, P140-P146, P150-P157(5), XIN, RESET, CNVSS, BYTE
P70, P71
0.8VCC
6.0
P00-P07, P10-P17 (In single-chip mode)
0.8VCC
VCC
V
P00-P07, P10-P17
(In memory expansion mode and microprocesor mode)
P20-P27, P30-P37, P40-P47, P50-P57, P60-P67, P70-P77, P80P87(4), P90-P97, P100-P107, P110-P114, P120-P127, P130P137, P140-P146, P150-P157(5), XIN, RESET, CNVSS, BYTE
P00-P07, P10-P17 (In single-chip mode)
0.5VCC
VCC
V
0
0.2VCC
V
0
0.2VCC
V
0
0.16VCC
V
-10.0
mA
-5.0
mA
10.0
mA
5.0
mA
P00-P07, P10-P17
(In memory expansion mode and microprocesor mode)
Peak output
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60high ("H")
P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110current(2)
P114, P120-P127, P130-P137, P140-P146, P150-P157(5)
Average output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60high ("H")
P67, P72-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110current(1)
P114, P120-P127, P130-P137, P140-P146, P150-P157(5)
Peak output
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60low ("L")
P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110current(2)
P114, P120-P127, P130-P137, P140-P146, P150-P157(5)
IOL(avg)
Average output P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60low ("L")
P67, P70-P77, P80-P84, P86, P87, P90-P97, P100-P107, P110current(1)
P114, P120-P127, P130-P137, P140-P146, P150-P157(5)
f(XIN)
Main clock
Through VDC
input frequency
VCC=4.2 to 5.5V
0
32
MHz
VCC=3.0 to 5.5V
0
20
MHz
VCC=3.0 to 3.6V
0
20
MHz
f(XCIN)
Sub clock oscillation frequency
32.768
50
NOTES:
1. Output current is averaged with 100ms.
2. Total IOL(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be less than or equal to 80mA.
Total IOH(peak) for P0, P1, P2, P86, P87, P9, P10, P11, P14 and P15 must be less than or equal to -80mA.
kHz
Not through VDC
Total IOL(peak) for P3, P4, P5, P6, P7, P80 to P84, P12 and P13 must be less than or equal to 80mA.
Total IOH(peak) for P3, P4, P5, P6, P72 to P77, P80 to P84, P12 and P13 must be less than or equal to -80mA.
3. This is an option that is on request basis.
4. VIH and VIL reference for P87 applies to P87 used as a programmable input ports. It does not apply to P87 used as XCIN.
5. P11 to P15 are provided in the 144-pin package only.
Rev.1.00 Jun. 01, 2004
page 46 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Table 5.3 Electrical Characteristics (VCC=4.2 to 5.5V, VSS=0V
at Topr= –20 to 85oC, unless otherwise specified)
Symbol
VOH
Parameter
Output high ("H")
voltage
Condition
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1)
XOUT
XCOUT
VOL
Output low ("L")
voltage
VCC=5V
IOH=-5mA
Standard
Min
3.0
Typ
V
VCC=5V
IOH=-200µA
4.7
V
VCC=5V
IOH=-1mA
No load applied
3.0
V
3.3
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOL=5mA
P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1)
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOL=200µA
P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
VT+-VT-
Hysteresis
Unit
Max
P140-P146, P150-P157(1)
XOUT
IOL=1mA
XCOUT
No load applied
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-INT5,
ADTRG, CTS0-CTS4, CLK0-CLK4, TA0OUT-TA4OUT,
V
2.0
V
0.45
V
2.0
V
0
V
0.2
1.0
V
0.2
1.8
5.0
V
µA
-5.0
µA
167
kΩ
54
MΩ
MΩ
V
mA
NMI, KI0-KI3, RxD0-RxD4, SCL0-SCL4, SDA0-
IIH
SDA4
RESET
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=VCC
P57, P60-P67, P70-P77, P80-P87, P90-P97, P100-
Input high ("H")
current
P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XIN, RESET, CNVSS, BYTE
Input low ("L") current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V
P57, P60-P67, P70-P77, P80-P87, P90-P97, P100P107, P110-P114, P120-P127, P130-P137, P140-
IIL
RPULLUP
Pull-up resistance
P146, P150-P157(1), XIN, RESET, CNVSS, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V
P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
30
50
P100-P107, P110-P114, P120-P127, P130-P137,
RfXIN
RfXCIN
VRAM
ICC
Feedback resistance
Feedback resistance
RAM standby voltage
Power supply current
P140-P146, P150-P157(1)
XIN
XCIN
Through VDC
Measurement conditions:
In single-chip mode, output
pins are left open and other
pins are connected to VSS.
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Rev.1.00 Jun. 01, 2004
page 47 of 83
1.5
10
2.5
f(XIN)=32 MHz, square wave,
no division
f(XCIN)=32 kHz, with a wait state,
Topr=25° C
Topr=25° C when the clock stops
28
µA
470
0.4
20
µA
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Table 5.4 A/D Conversion Characteristics (VCC = AVCC = VREF = 4.2 to 5.5V, Vss = AVSS = 0V
at Topr = –20 to 85oC, nless otherwise specified)
Symbol
Parameter
Standard
Measurement condition
Min
-
Resolution
Typ
VREF=VCC
10
AN0 to AN7
ANEX0, ANEX1
INL
Integral nonlinearity error
±3
Bits
LSB
LSB
VREF=VCC=5V
External op-amp
connection mode
DNL
Unit
Max
±7
LSB
LSB
Differential nonlinearity error
±1
LSB
-
Offset error
±3
LSB
-
Gain error
±3
LSB
40
kΩ
RLADDER
Resistor ladder
tCONV
10-bit conversion time
2.1
µs
tCONV
8-bit conversion time
1.8
µs
tSAMP
Sample time
0.3
µs
VREF
Reference voltage
2
VCC
V
VIA
Analog input voltage
0
VREF
V
VREF=VCC
8
NOTES:
1. Divide f(XIN), if exceeding 10 MHz, to keep φAD frequency less than or equal to 10 MHz.
Table 5.5 D/A Conversion Characteristics (VCC = VREF = 4.2 to 5.5V, VSS = AVSS = 0V
at Topr = –20 to 85oC, unless otherwise specified)
Symbol
Parameter
Standard
Measurement condition
Min Typ
tSU
-
Resolution
-
Absolute accuracy
Unit
Max
8
Setup time
RO
Output resistance
IVREF
Reference power supply input current
4
(Note 1)
10
%
3
µs
20
kΩ
1.5
mA
NOTES:
1. Mesurement condition is that one of two D/A converters is used and the DAi register (i=0, 1) for the
unused D/A converter to "0016". The resistor ladder in the A/D converter is exclued.
IVREF flows even if the ADiCON1 register is set to "0" (no VREF connection).
Rev.1.00 Jun. 01, 2004
page 48 of 83
Bits
1.0
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Timing Requirements (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.6 External Clock Input
Symbol
Parameter
Standard
Min
Unit
Max
tc
External clock input cycle time
31.3
ns
tw(H)
External clock input high ("H") pulse width
13
ns
13
tw(L)
External clock input low ("L") pulse width
tr
External clock rising edge time
5
ns
ns
tf
External clock falling edge time
5
ns
Table 5.7 Memory Expansion and Microprocessor Modes
Symbol
Parameter
Standard
Min
Max
Unit
tac1(RD-DB)
Data input access time (RD standard, with no wait state)
(Note 1)
ns
tac1(AD-DB)
Data input access time (AD standard, CS standard, with no wait state)
(Note 1)
ns
tac2(RD-DB)
Data input access time (RD standard, with a wait state)
(Note 1)
ns
tac2(AD-DB)
Data input access time (AD standard, CS standard, with a wait state)
(Note 1)
ns
tac3(RD-DB)
Data input access time (RD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac3(AD-DB)
Data input access time (AD standard, CS standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac4(RAS-DB)
Data input access time (RAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAS-DB)
Data input access time (CAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAD-DB)
Data input access time (CAD standard, when accessing a DRAM space)
(Note 1)
ns
tsu(DB-BCLK)
Data input setup time
26
tsu(RDY-BCLK)
RDY input setup time
26
ns
tsu(HOLD-BCLK) HOLD input setup time
30
ns
th(RD-DB)
Data input hold time
0
ns
th(CAS-DB)
ns
ns
Data input hold time
0
th(BCLK-RDY) RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
td(BCLK-HLDA)
HLDA output delay time
25
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequecncy. Insert a wait state or use lower
f(BCLK) as an operation frequency if a calculated value is negative.
tac1(RD – DB) =
tac1(AD – DB) =
10 9
f(BCLK) X 2
10 9
f(BCLK)
– 35
[ns]
– 35
[ns]
– 35
[ns] (m=3 with 1 wait state, m=5 with 2 wait states
and m=7 with 3 wait states)
– 35
[ns] (n=2 with 1 wait state, n=3 with 2 wait states
and n=4 with 3 wait states)
9
10 X m
tac2(RD – DB) = f(BCLK) X 2
9
tac2(AD – DB) =
10 X n
f(BCLK)
9
10 X m
tac3(RD – DB) = f(BCLK) X 2 – 35
tac3(AD – DB) =
10 9 X n
– 35
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
[ns] (n=5 with 2 wait states and n=7 with 3 wait states)
tac4(RAS – DB) =
10 9X m
f(BCLK) X 2
– 35
[ns] (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS – DB) =
10 9 X n
f(BCLK) X 2
– 35
[ns] (n=1 with 1 wait state and n=3 when 2 wait states)
tac4(CAD – DB) =
10 9 X l
f(BCLK)
– 35
[ns] (l=1 with 1 wait state and l=2 with 2 wait states)
Rev.1.00 Jun. 01, 2004
page 49 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Timing Requirements
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.8 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Unit
Max
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high ("H") pulse width
40
ns
tw(TAL)
TAiIN input low ("L") pulse width
40
ns
Table 5.9 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min
Max
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high ("H") pulse width
200
ns
tw(TAL)
TAiIN input low ("L") pulse width
200
ns
Table 5.10 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high ("H") pulse width
100
ns
tw(TAL)
TAiIN input low ("L") pulse width
100
ns
Table 5.11 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tw(TAH)
TAiIN input high ("H") pulse width
100
ns
tw(TAL)
TAiIN input low ("L") pulse width
100
ns
Table 5.12 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(UP)
TAiOUT input cycle time
2000
ns
tw(UPH)
TAiOUT input high ("H") pulse width
1000
ns
tw(UPL)
TAiOUT input low ("L") pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
Rev.1.00 Jun. 01, 2004
page 50 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Timing Requirements
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.13 Timer B Input (Count Source Input in eEvent Counter Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high ("H") pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low ("L") pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high ("H") pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low ("L") pulse width (counted on both edges)
80
ns
Table 5.14 Timer B Input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high ("H") pulse width
200
ns
tw(TBL)
TBiIN input low ("L") pulse width
200
ns
Table 5.15 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high ("H") pulse width
200
ns
tw(TBL)
TBiIN input low ("L") pulse width
200
ns
Table 5.16 A/D trigger Input
Symbol
Standard
Parameter
Min
Unit
Max
tc(AD)
ADTRG input high ("H") pulse width (trigger available at minimum)
1000
ns
tw(ADL)
ADTRG input low ("L") pulse width
125
ns
Table 5.17 Serial I/O
Symbol
Parameter
Standard
Min
Max
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high ("H") pulse width
100
ns
tw(CKL)
CLKi input low ("L") pulse width
100
ns
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
0
80
ns
ns
tsu(D-C)
RxDi input hold time
30
ns
th(C-Q)
RxDi input hold time
90
ns
_______
Table 5.18 External Interrupt INTi Input
Symbol
Parameter
Standard
Min
Max
Unit
tw(INH)
INTi input high ("H") pulse width
250
ns
tw(INL)
INTi input low ("L") pulse width
250
ns
Rev.1.00 Jun. 01, 2004
page 51 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.19 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Symbol
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
Measurement
condition
Standard
Min
Unit
Max
18
-3
ns
ns
th(RD-AD)
Address output hold time (RD standard)
0
ns
th(WR-AD)
Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
-3
th(RD-CS)
Chip-select signal output hold time (RD standard)
0
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
td(BCLK-WR)
WR signal outpu hold time
18
See Figure 5.1
ns
18
ns
18
ns
18
ns
-2
ns
-5
-3
ns
ns
ns
td(DB-WR)
Data output delay time (WR standard)
(Note 1)
ns
th(WR-DB)
Data outpu hold time (WR standard)
(Note 1)
ns
tw(WR)
Write pulse width
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB – WR) =
10 9
f(BCLK)
– 20
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw(WR) =
10 9
f(BCLK) X 2
– 15
[ns]
Rev.1.00 Jun. 01, 2004
page 52 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.20 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory)
Symbol
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
Measurement
condition
Standard
Min
Unit
Max
18
-3
ns
ns
th(RD-AD)
Address output hold time (RD standard)
0
ns
th(WR-AD)
Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
-3
th(RD-CS)
Chip-select signal output hold time (RD standard)
0
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
18
See Figure 5.1
ns
ns
18
-2
ns
ns
18
-5
ns
ns
td(BCLK-WR)
WR signal output delay time
td(BCLK-WR)
WR signal outpu hold time
18
td(DB-WR)
Data output delay time (WR standard)
th(WR-DB)
Data outpu hold time (WR standard)
(Note 1)
ns
tw(WR)
Write pulse width
(Note 1)
ns
ns
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB – WR) =
10 9 X n
f(BCLK)
– 20
[ns] (n=1 with 1 wait state, n=2 with 2 wait states
and n=3 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw( WR) =
10 9 X n
f(BCLK) X 2
Rev.1.00 Jun. 01, 2004
– 15
[ns] (n=1 with 1 wait state, n=3 with 2 wait states
and n=5 with 3 wait states)
page 53 of 83
ns
-3
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.21 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting a Space with the
Multiplexed Bus)
Symbol
Measurement
condition
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
Standard
Min
Unit
Max
18
ns
-3
ns
th(RD-AD)
Address output hold time (RD standard)
(Note 1)
ns
th(WR-AD)
Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
th(RD-CS)
18
ns
-3
ns
Chip-select signal output hold time (RD standard)
(Note 1)
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)
(Note 1)
td(BCLK-RD)
RD signal output delay time
th(BCLK-AD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
ns
18
See Figure 5.1
-5
ns
ns
18
ns
td(BCLK-WR)
WR signal output hold time
-3
ns
td(DB-WR)
Data output delay time (WR standard)
(Note 1)
ns
th(WR-DB)
Data output hold time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
td(AD-ALE)
18
ns
-2
ns
ALE signal output delay time (address standard)
(Note 1)
ns
th(ALE-AD)
ALE signal output hold time (address standard)
(Note 1)
tdz(RD-AD)
Address output high-impedance time
ns
8
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
– 20
[ns]
– 10
[ns]
9
td(AD – ALE) =
th(ALE – AD) =
Rev.1.00 Jun. 01, 2004
10
9
f(BCLK) X 2
10
9
f(BCLK) X 2
page 54 of 83
ns
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
VCC = 5V
Switching Characteristics
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.22 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting the DRAM Area)
Symbol
Measurement
condition
Parameter
td(BCLK-AD)
Row address output delay time
th(BCLK-AD)
Row address output hold time (BCLK standard)
Standard
Min
18
-3
th(BCLK-CAD) Column address output delay time
th(RAS-RAD)
Row address output hold time after RAS output
tRP
RAS high ("H") hold time
ns
(Note 1)
ns
18
See Figure 5.1
ns
(Note 1)
ns
18
-3
td(BCLK-DW) DW output delay time (BCLK standard)
th(BCLK-DW) DW output hold time (BCLK standard)
tsu(DB-CAS)
CAS output setup time after DB output
th(BCLK-DB
DB signal output hold time (BCLK standard)
tsu(CAS-RAS) CAS output setup time before RAS output (refresh)
10 9
f(BCLK) X 2
tRP =
10 9
f(BCLK) X 2
tsu(DB – CAS) =
10 9
f(BCLK)
– 13
[ns]
X 3 – 20 [ns]
– 20
[ns]
9
tsu(CAS – RAS) =
Rev.1.00 Jun. 01, 2004
10
f(BCLK) X 2
– 13
page 55 of 83
[ns]
ns
ns
18
ns
-5
ns
(Note 1)
ns
-7
ns
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RAS – RAD) =
ns
-3
td(BCLK-CAS) CAS output delay time (BCLK standard)
th(BCLK-CAS) CAS output hold time (BCLK standard)
ns
-3
td(BCLK-RAS) RAS output delay time (BCLK standard)
th(BCLK-RAS) RAS output hold time (BCLK standard)
ns
ns
18
td(BCLK-CAD) Column address output hold time (BCLK standard)
Unit
Max
5. Electrical Characteristics
M32C/81 Group
P0
P1
P2
P3
P4
P5
P6
P7
30pF
P8
P9
P10
P11
P12
P13
Note 1
P14
P15
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Figure 5.1 P0 to P15 Measurement Circuit
Rev.1.00 Jun. 01, 2004
page 56 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Vcc=5V
Memory expansion mode and microprocessor mode (with no wait state)
Read timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
th(BCLK-CS)
18ns.max(1)
-3ns.min
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
-3ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
th(BCLK-RD)
tac1(RD-DB)(2)
-5ns.min
tac1(AD-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
th(RD-DB)
26ns.min(1)
0ns.min
NOTES:
1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. It varies with the operation frequency.
tac1(RD-DB)=(tcyc/2-35)ns.max
tac1(AD-DB)=(tcyc-35)ns.max
Write timing ( written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
-3ns.min
18ns.max
CSi
tcyc
th(WR-CS)(1)
td(BCLK-AD)
ADi
BHE
th(BCLK-AD)
18ns.max
-3ns.min
td(BCLK-WR)
18ns.max
th(WR-AD)(1)
tw(WR)(1)
WR,WRL,
WRH
th(BCLK-WR)
-3ns.min
td(DB-WR)(1)
th(WR-DB)(1)
DBi
NOTES:
1. It varies with the operation frequency.
td(DB-WR)=(tcyc-20)ns.min
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2-15)ns.min
Figure 5.2 VCC=5V Timing Diagram (1)
Rev.1.00 Jun. 01, 2004
page 57 of 83
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Vcc=5V
Memory expansion mode and microprocessor mode (with a wait state)
Read timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
-3ns.min
18ns.max(1)
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
ADi
BHE
th(BCLK-AD)
18ns.max(1)
-3ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
th(BCLK-RD)
tac2(RD-DB)(2)
-5ns.min
tac2(AD-DB)(2)
DB
Hi-Z
tsu(DB-BCLK)
26ns.min(1)
th(RD-DB)
0ns.min
Notes :
1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
2. It varies with the operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.)
Write timing (written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
-3ns.min
18ns.max
CSi
tcyc
th(WR-CS)(1)
th(BCLK-AD)
td(BCLK-AD)
ADi
BHE
WR,WRL,
WRH
-3ns.min
18ns.max
td(BCLK-WR)
18ns.max
tw(WR)(1)
th(WR-AD)(1)
th(BCLK-WR)
-3ns.min
td(DB-WR)(1)
th(WR-DB)(1)
DBi
NOTES:
1. It varies with the operation frequency.
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
Figure 5.3 VCC=5V Timing Diagram (2)
Rev.1.00 Jun. 01, 2004
page 58 of 83
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Memory expansion mode and microprocessor mode
Vcc=5V
(with a wait state, when accessing an external memory and using the multiplexed bus)
Read timing
BCLK
18ns.max
th(BCLK-ALE)
td(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
-3ns.min
18ns.max
th(RD-CS)(1)
CSi
td(AD-ALE)(1)
ADi
/DBi
th(ALE-AD)(1)
Address
Data input
tdz(RD-AD)
tsu(DB-BCLK)
td(BCLK-AD)
ADi
BHE
tac3(AD-DB)(1)
td(BCLK-RD)
th(BCLK-RD)
18ns.max
0ns.min
26ns.min
tac3(RD-DB)(1)
18ns.max
Address
th(RD-DB)
8ns.max
th(BCLK-AD)
-3ns.min
th(RD-AD)(1)
-5ns.min
RD
NOTES:
1. It varies with the operation frequency.
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write timing (written in 2 cycles with no wait state)
BCLK
18ns.max
th(BCLK-ALE)
td(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
th(WR-CS)(1)
18ns.max
CSi
th(ALE-AD)(1)
td(AD-ALE)(1)
ADi
/DBi
Data output
Address
td(DB-WR)(1)
td(BCLK-AD)
Address
th(WR-DB)(1)
td(BCLK-WR)
18ns.max
WR,WRL,
WRH
NOTES:
1. It varies with the operation frequency.
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
Figure 5.4 VCC=5V Timing Diagram (3)
Rev.1.00 Jun. 01, 2004
page 59 of 83
th(BCLK-AD)
-3ns.min
18ns.max
ADi
BHE
-3ns.min
th(BCLK-WR)
th(WR-AD)(1)
-3ns.min
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0.8V
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Memory expansion mode and microprocessor mode
Vcc=5V
(When accessing the DRAM area)
Read timing
BCLK
tcyc
td(BCLK-RAD) th(BCLK-RAD)
18ns.max -3ns.min
MAi
td(BCLK-CAD)
th(BCLK-CAD)
18ns.max(1)
-3ns.min
Column address
Row address
th(RAS-RAD)(2)
tRP(2)
RAS
td(BCLK-RAS)
18ns.max(1)
td(BCLK-CAS)
18ns.max(1)
CASL
CASH
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
-3ns.min
DW
tac4(CAS-DB)(2)
tac4(CAD-DB)(2)
tac4(RAS-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
26ns.min(1)
th(CAS-DB)
0ns.min
NOTES:
1. A value is guaranteed with no external factor. Maximum 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK).
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
2. It varies with the operation frequency.
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.5 VCC=5V Timing Diagram (4)
Rev.1.00 Jun. 01, 2004
page 60 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Memory expansion mode and microprocessor mode
Vcc=5V
(When accessing the DRAM area)
Write timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
MAi
th(BCLK-RAD)
-3ns.min
td(BCLK-CAD)
th(BCLK-CAD)
18ns.max
-3ns.min
Column address
Row address
th(RAS-RAD)(1)
tRP(1)
RAS
td(BCLK-RAS)
18ns.max
td(BCLK-CAS)
18ns.max
CASL
CASH
th(BCLK-RAS)
-3ns.min
th(BCLK-CAS)
td(BCLK-DW)
-3ns.min
18ns.max
DW
th(BCLK-DW)
tsu(DB-CAS)(1)
DB
-5ns.min
Hi-Z
th(BCLK-DB)
-7ns.min
NOTES:
1. It varies with the operation frequency.
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
tsu(DB-CAS)=(tcyc-20)ns.min
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.6 VCC=5V Timing Diagram (5)
Rev.1.00 Jun. 01, 2004
page 61 of 83
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Memory expansion mode and microprocessor mode
Refresh timing (CAS-before-RAS refresh)
Vcc=5V
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)(1)
CASL
CASH
-3ns.min
td(BCLK-CAS)
th(BCLK-CAS)
-3ns.min
18ns.max
DW
NOTES :
1. It varies with the operation frequency.
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Refresh timing (Self-refresh)
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)(1)
CASL
CASH
td(BCLK-CAS)
18ns.max
DW
NOTES:
1. It varies with the operation frequency.
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.7 VCC=5V Timing Diagram (6)
Rev.1.00 Jun. 01, 2004
page 62 of 83
-3ns.min
th(BCLK-CAS)
-3ns.min
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Vcc=5V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Counter increment/
decrement input)
In event counter mode
TAiIN input
th(TIN–UP)
(When counting on falling
edge is selected)
tsu(UP–TIN)
TAiIN input
(When counting on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 5.8 VCC=5V Timing Diagram (7)
Rev.1.00 Jun. 01, 2004
page 63 of 83
th(C–D)
5. Electrical Characteristics (VCC=5V)
M32C/81 Group
Vcc=5V
Memory expansion mode and microprocessor mode
(Valid only with a wait state)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
th(BCLK–RDY)
tsu(RDY–BCLK)
(Valid with a wait state or with no wait state)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
td(BCLK–HLDA)
Hi–Z
Measurement conditions
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=4.0V, VIL=1.0V
• Output high and low voltage: VOH=2.5V, VOL=2.5V
Figure 5.9 VCC=5V Timing Diagram (8)
Rev.1.00 Jun. 01, 2004
page 64 of 83
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Table 5.23 Electrical Characteristics (VCC=3.0 to 3.6V, VSS=0V at Topr = –20 to 85oC,
unless otherwise specified)
Symbol
VOH
VOL
VT+-VT-
IIH
IIL
RPULLUP
Parameter
Output high ("H")
voltage
Condition
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOH=-1mA
P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
Output low ("L")
voltage
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1)
XOUT
IOH=-0.1mA
XCOUT
No load applied
Standard
Min
2.7
Typ
V
2.7
V
3.3
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- IOL=1mA
P57, P60-P67, P70-P77, P80-P84, P86, P87, P90-P97,
Hysteresis
P100-P107, P110-P114, P120-P127, P130-P137,
P140-P146, P150-P157(1)
XOUT
IOL=0.1mA
XCOUT
No load applied
HOLD, RDY, TA0IN-TA4IN, TB0IN-TB5IN, INT0-INT5,
ADTRG, CTS0-CTS4, CLK0-CLK4, TA0OUT-TA4OUT,
NMI, KI0-KI3, RxD0-RxD4, SCL0-SCL4, SDA0SDA4
RESET
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=VCC
P57, P60-P67, P72-P77, P80-P87, P90-P97, P100-
Input high ("H")
current
Pull-up resistance
RfXIN
RfXCIN
VRAM
Feedback resistance
Feedback resistance
RAM standby voltage
ICC
Power supply current
P140-P146, P150-P157(1)
XIN
XCIN
Through VDC
Not through VDC
Measurement condition:
In single-chip mode, output
pins are left open and other
pins are connected to VSS.
NOTES:
1. P11 to P15 are provided in the 144-pin package only.
Rev.1.00 Jun. 01, 2004
page 65 of 83
V
0.5
V
0.5
V
0
V
0.2
1.0
V
0.2
1.8
4.0
V
µA
-4.0
µA
500
kΩ
P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XIN, RESET, CNVSS, BYTE
Input low ("L") current P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V
P57, P60-P67, P72-P77, P80-P87, P90-P97, P100P107, P110-P114, P120-P127, P130-P137, P140P146, P150-P157(1), XIN, RESET, CNVSS, BYTE
P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50- VI=0V
P57, P60-P67, P72-P77, P80-P84, P86, P87, P90-P97,
P100-P107, P110-P114, P120-P127, P130-P137,
Unit
Max
66
120
3.0
20.0
MΩ
MΩ
V
2.5
2.0
f(XIN)=20 MHz, square wave,
no division
f(XCIN)=32 kHz, with a wait state,
not through VDC, Topr=25° C
f(XCIN)=32 kHz, with a wait state,
through VDC, Topr=25° C
Topr=25° C when the clock stops
17
38
mA
5.0
µA
340
µA
0.4
20
µA
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Table 5.24 A/D Conversion Characteristics (VCC = AVCC = VREF = 3.0 to 3.6V,
at Topr = –20 to 85oC, unless otherwise specified)
Symbol
-
Measurement
condition
Parameter
VSS = AVSS = 0V
Standard
Min Typ
VREF=VCC
Resolution
Unit
Max
10
Bits
INL
Integral nonlinearity error
No S&H function (8-bit) VCC=VREF=3.3V
±2
LSB
DNL
Differential nonlinearity error
No S&H function (8-bit)
±1
LSB
-
Offset error
No S&H function (8-bit)
±2
LSB
-
Gain error
No S&H function (8-bit)
±2
LSB
40
kΩ
RLADDER
Resistor ladder
tCONV
8-bit conversion time
4.9
VREF
Reference voltage
3.0
VCC
V
VIA
Analog input voltage
0
VREF
V
VREF=VCC
8
µs
S&H: Sample and hold
NOTES:
1. Divide f(XIN), if exceeding 10 MHz, to keep φAD frequency less than or equal to 10 MHz.
Table 5.25 D/A Conversion Characteristics (VCC = VREF = 3.0 to 3.6V, VSS = AVSS = 0V
at Topr = –20 to 85oC, unless otherwise specified)
Symbol
Parameter
Standard
Measurement condition
Min Typ
-
Resolution
Unit
Max
8
Absolute accuracy
tSU
Setup time
RO
Output resistance
IVREF
Reference power supply input current
4
(Note 1)
10
1.0
%
3
µs
20
kΩ
1.0
mA
NOTES:
1. Mesurement condition is that one of two D/A converters is used and the DAi register (i=0, 1) for the
unused D/A converter to "0016". The resistor ladder in the A/D converter is exclued.
IVREF flows even if the ADiCON1 register is set to "0" (no VREF connection).
Rev.1.00 Jun. 01, 2004
page 66 of 83
Bits
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
Timing Requirements (VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to
85oC
VCC = 3.3V
unless otherwise specified)
Table 5.26 External Clock Input
Symbol
Parameter
Standard
Min
Unit
Max
tc
External clock input cycle time
50
ns
tw(H)
External clock input high ("H") pulse width
22
ns
tw(L)
External clock input low ("L") pulse width
22
tr
External clock rising-edge time
5
ns
tf
External clock falling-edge time
5
ns
ns
Table 5.27 Memory Expansion Mode and Microprocessor Mode
Symbol
Parameter
Standard
Min
Max
Unit
tac1(RD-DB)
Data input access time (RD standard, with no wait state)
(Note 1)
ns
tac1(AD-DB)
Data input access time (AD standard, CS standard, with no wait state)
(Note 1)
ns
tac2(RD-DB)
Data input access time (RD standard, with a wait state)
(Note 1)
ns
tac2(AD-DB)
Data input access time (AD standard, CS standard, with a wait state)
(Note 1)
ns
tac3(RD-DB)
Data input access time (RD standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac3(AD-DB)
Data input access time (AD standard, CS standard, when accessing a space with the multiplexed bus)
(Note 1)
ns
tac4(RAS-DB)
Data input access time (RAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAS-DB)
Data input access time (CAS standard, when accessing a DRAM space)
(Note 1)
ns
tac4(CAD-DB)
Data input access time (CAD standard, when accessing a DRAM space)
(Note 1)
ns
tsu(DB-BCLK)
Data input setup time
30
tsu(RDY-BCLK)
RDY input setup time
40
ns
tsu(HOLD-BCLK) HOLD input setup time
60
ns
th(RD-DB)
Data input hold time
0
ns
th(CAS-DB)
ns
ns
Data input hold time
0
th(BCLK-RDY) RDY input hold time
0
ns
th(BCLK-HOLD)
HOLD input hold time
0
ns
td(BCLK-HLDA)
HLDA output delay time
25
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequecncy. Insert a wait state or use lower
f(BCLK) as an operation frequency if a calculated value is negative.
tac1(RD – DB) =
tac1(AD – DB) =
10 9
f(BCLK) X 2
10 9
f(BCLK)
– 35
[ns]
– 35
[ns]
– 35
[ns] (m=3 with 1 wait state, m=5 with 2 wait states
and m=7 with 3 wait states)
– 35
[ns] (n=2 with 1 wait state, n=3 with 2 wait states
and n=4 with 3 wait states)
9
10 X m
tac2(RD – DB) = f(BCLK) X 2
9
tac2(AD – DB) =
10 X n
f(BCLK)
9
10 X m
tac3(RD – DB) = f(BCLK) X 2 – 35
tac3(AD – DB) =
10 9 X n
– 35
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
[ns] (n=5 with 2 wait states and n=7 with 3 wait states)
tac4(RAS – DB) =
10 9X m
f(BCLK) X 2
– 35
[ns] (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS – DB) =
10 9 X n
f(BCLK) X 2
– 35
[ns] (n=1 with 1 wait state and n=3 when 2 wait states)
tac4(CAD – DB) =
10 9 X l
f(BCLK)
– 35
[ns] (l=1 with 1 wait state and l=2 with 2 wait states)
Rev.1.00 Jun. 01, 2004
page 67 of 83
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Timing Requirements
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.28 Timer A Input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Unit
Max
tc(TA)
TAiIN input cycle time
100
ns
tw(TAH)
TAiIN input high ("H") pulse width
40
ns
tw(TAL)
TAiIN input low ("L") pulse width
40
ns
Table 5.29 Timer A Input (Gate Input in Timer Mode)
Standard
Symbol
Parameter
Min
Max
Unit
tc(TA)
TAiIN input cycle time
400
ns
tw(TAH)
TAiIN input high ("H") pulse width
200
ns
tw(TAL)
TAiIN input low ("L") pulse width
200
ns
Table 5.30 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TA)
TAiIN input cycle time
200
ns
tw(TAH)
TAiIN input high ("H") pulse width
100
ns
tw(TAL)
TAiIN input low ("L") pulse width
100
ns
Table 5.31 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tw(TAH)
TAiIN input high ("H") pulse width
100
ns
tw(TAL)
TAiIN input low ("L") pulse width
100
ns
Table 5.32 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(UP)
TAiOUT input cycle time
2000
ns
tw(UPH)
TAiOUT input high ("H") pulse width
1000
ns
tw(UPL)
TAiOUT input low ("L") pulse width
1000
ns
tsu(UP-TIN)
TAiOUT input setup time
400
ns
th(TIN-UP)
TAiOUT input hold time
400
ns
Rev.1.00 Jun. 01, 2004
page 68 of 83
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Timing Requirements
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.33 Timer B input (Count Source Input in Event Counter Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
100
ns
tw(TBH)
TBiIN input high ("H") pulse width (counted on one edge)
40
ns
tw(TBL)
TBiIN input low ("L") pulse width (counted on one edge)
40
ns
tc(TB)
TBiIN input cycle time (counted on both edges)
200
ns
tw(TBH)
TBiIN input high ("H") pulse width (counted on both edges)
80
ns
tw(TBL)
TBiIN input low ("L") pulse width (counted on both edges)
80
ns
Table 5.34 Timer B input (Pulse Period Measurement Mode)
Symbol
Parameter
Standard
Min
Max
Unit
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high ("H") pulse width
200
ns
tw(TBL)
TBiIN input low ("L") pulse width
200
ns
Table 5.35 Timer B input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min
Max
tc(TB)
TBiIN input cycle time
400
ns
tw(TBH)
TBiIN input high ("H") pulse width
200
ns
tw(TBL)
TBiIN input low ("L") pulse width
200
ns
Table 5.36 A/D Trigger Input
Symbol
Standard
Parameter
Min
Unit
Max
tc(AD)
ADTRG input high ("H") pulse width (trigger available at minimum)
1000
ns
tw(ADL)
ADTRG input low ("L") pulse width
125
ns
Table 5.37 Serial I/O
Symbol
Parameter
Standard
Min
Max
Unit
tc(CK)
CLKi input cycle time
200
ns
tw(CKH)
CLKi input high ("H") pulse width
100
ns
tw(CKL)
CLKi input low ("L") pulse width
100
ns
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
0
80
ns
ns
tsu(D-C)
RxDi input hold time
30
ns
th(C-Q)
RxDi input hold time
90
ns
_______
Table 5.38 External Interrupt INTi input
Symbol
Parameter
Standard
Min
Max
Unit
tw(INH)
INTi input high ("H") pulse width
250
ns
tw(INL)
INTi input low ("L") pulse width
250
ns
Rev.1.00 Jun. 01, 2004
page 69 of 83
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC, unless otherwise specified)
Table 5.39 Memory Expansion Mode and Microprocessor Mode (with No Wait State)
Symbol
Parameter
td(BCLK-AD)
Measurement
condition
Standard
Min
Address output delay time
Unit
Max
18
ns
th(BCLK-AD)
Address output hold time (BCLK standard)
0
ns
th(RD-AD)
Address output hold time (RD standard)
0
ns
(Note 1)
th(WR-AD)
Address output hold time (WR standard)
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
ns
18
0
ns
ns
th(RD-CS)
Chip-select signal output hold time (RD standard)
0
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
See Figure 5.1
18
ns
18
ns
-2
ns
-3
ns
td(BCLK-WR)
WR signal output delay time
td(BCLK-WR)
WR signal outpu hold time
18
td(DB-WR)
Data output delay time (WR standard)
th(WR-DB)
Data outpu hold time (WR standard)
(Note 1)
ns
tw(WR)
WR output width
(Note 1)
ns
ns
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB – WR) =
10 9
f(BCLK)
– 20
[ns]
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw(WR) =
10 9
f(BCLK) X 2
– 15
[ns]
Rev.1.00 Jun. 01, 2004
page 70 of 83
ns
0
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.40 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory)
Symbol
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
Measurement
condition
Standard
Min
Unit
Max
18
0
ns
ns
th(RD-AD)
Address output hold time (RD standard)
0
ns
th(WR-AD)
Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
0
th(RD-CS)
Chip-select signal output hold time (RD standard)
0
ns
th(WR-CS)
Chip-select signal output hold time (WR standard)
(Note 1)
ns
td(BCLK-ALE)
ALE signal output delay time
th(BCLK-ALE)
ALE signal output hold time
td(BCLK-RD)
RD signal output delay time
th(BCLK-RD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
td(BCLK-WR)
WR signal outpu hold time
18
See Figure 5.1
ns
18
ns
18
ns
18
ns
-2
ns
-3
0
ns
ns
ns
td(DB-WR)
Data output delay time (WR standard)
(Note 1)
ns
th(WR-DB)
Data outpu hold time (WR standard)
(Note 1)
ns
tw(WR)
WR output width
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
td(DB – WR) =
10 9 X n
f(BCLK)
– 20
[ns] (n=1 with 1 wait state, n=2 with 2 wait states
and n=3 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
tw( WR) =
10 9 X n
f(BCLK) X 2
Rev.1.00 Jun. 01, 2004
– 15 [ns] (n=1 with 1 wait state, n=3 with 2 wait states
and n=5 with 3 wait states)
page 71 of 83
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.41 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting a Space with the
Multiplexed Bus)
Symbol
Parameter
td(BCLK-AD)
Address output delay time
th(BCLK-AD)
Address output hold time (BCLK standard)
Measurement
condition
Standard
Min
Unit
Max
18
ns
0
ns
th(RD-AD)
Address output hold time (RD standard)
(Note 1)
ns
th(WR-AD)
Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS)
Chip-select signal output delay time
th(BCLK-CS)
Chip-select signal output hold time (BCLK standard)
th(RD-CS)
18
ns
0
ns
Chip-select signal output hold time (RD standard)
(Note 1)
ns
(Note 1)
th(WR-CS)
Chip-select signal output hold time (WR standard)
td(BCLK-RD)
RD signal output delay time
th(BCLK-AD)
RD signal output hold time
td(BCLK-WR)
WR signal output delay time
td(BCLK-WR)
WR signal output hold time
td(DB-WR)
See Figure 5.1
ns
18
-3
ns
ns
18
ns
0
ns
Data output delay time (WR standard)
(Note 1)
ns
(Note 1)
th(WR-DB)
Data output hold time (WR standard)
td(BCLK-ALE)
ALE signal output delay time (BCLK standard)
th(BCLK-ALE)
ALE signal output hold time (BCLK standard)
td(AD-ALE)
ns
18
ns
-2
ns
ALE signal output delay time (address standard)
(Note 1)
ns
th(ALE-AD)
ALE signal output hold time (address standard)
(Note 1)
tdz(RD-AD)
Address output high-impedance time
ns
8
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RD – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(WR – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
th(RD – CS) =
10 9
f(BCLK) X 2
–10
[ns]
th(WR – CS) =
10 9
f(BCLK) X 2
– 10
[ns]
td(DB – WR) =
10 X m
– 25
f(BCLK) X 2
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)
th(WR – DB) =
10 9
f(BCLK) X 2
– 10
[ns]
td(AD – ALE) =
10 9
f(BCLK) X 2
– 20
[ns]
th(ALE – AD) =
10 9
f(BCLK) X 2
– 10
[ns]
9
Rev.1.00 Jun. 01, 2004
page 72 of 83
ns
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
VCC = 3.3V
Switching Characteristics
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified)
Table 5.42 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting the DRAM Area)
Symbol
Measurement
condition
Parameter
td(BCLK-AD)
Row address output delay time
th(BCLK-AD)
Row address output hold time (BCLK standard)
th(BCLK-CAD)
Column address output delay time
td(BCLK-CAD)
Column address output hold time (BCLK standard)
th(RAS-RAD)
Row address output hold time after RAS output
td(BCLK-RAS)
RAS output delay time (BCLK standard)
th(BCLK-RAS)
RAS output hold time (BCLK standard)
tRP
RAS high ("H") hold time
td(BCLK-CAS)
CAS output delay time (BCLK standard)
th(BCLK-CAS)
CAS output hold time (BCLK standard)
Standard
Min
18
ns
18
ns
0
ns
0
ns
(Note 1)
ns
18
See Figure 5.1
Unit
Max
ns
0
ns
(Note 1)
ns
18
0
ns
ns
td(BCLK-DW)
DW output delay time (BCLK standard)
th(BCLK-DW)
DW output hold time (BCLK standard)
-3
ns
tsu(DB-CAS)
CAS output setup time after DB output
(Note 1)
ns
th(BCLK-DB
DB signal output hold time (BCLK standard)
tsu(CAS-RAS)
CAS output setup time before RAS output (refresh)
18
-7
ns
(Note 1)
ns
NOTES:
1. A value can be obtained from the following expressions according to the BCLK frequency.
th(RAS – RAD) =
10 9
f(BCLK) X 2
tRP =
10 9 X 3
f(BCLK) X 2
tsu(DB – CAS) =
tsu(CAS – RAS) =
Rev.1.00 Jun. 01, 2004
10 9
f(BCLK)
10
– 13
[ns]
– 20 [ns]
– 20
[ns]
9
f(BCLK) X 2
– 13
page 73 of 83
[ns]
ns
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
Vcc=3.3V
Memory expansion mode and microprocessor mode (with no wait state)
Read timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max(1)
CSi
th(RD-CS)
tcyc
0ns.min
td(BCLK-AD)
th(BCLK-AD)
18ns.max(1)
0ns.min
ADi
BHE
th(RD-AD)
0ns.min
td(BCLK-RD)
18ns.max
RD
tac2(RD-DB)(2)
th(BCLK-RD)
-3ns.min
tac2(AD-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
th(RD-DB)
30ns.min(1)
0ns.min
NOTES:
1. A value is guarantee with no external factor. Maximum 35ns is garanteed for td(BCLK-AD)+tsu(DB-BCLK).
2. It varies with the operation frequency.
tac2(RD-DB)=(tcyc/2-35)ns.max
tac2(AD-DB)=(tcyc-35)ns.max
Write timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max
CSi
th(WR-CS)(1)
tcyc
td(BCLK-AD)
th(BCLK-AD)
0ns.min
18ns.max
ADi
BHE
td(BCLK-WR)
18ns.max
tw(WR)(1)
WR,WRL,
WRH
th(WR-AD)(1)
th(BCLK-WR)
0ns.min
d(DB-WR)(1)
t
th(WR-DB)(1)
DBi
NOTES:
1. It varies with the operation frequency.
td(DB-WR)=(tcyc-20)ns.min
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2-15)ns.min
Figure 5.10 VCC=3.3V Timing Diagram (1)
Rev.1.00 Jun. 01, 2004
page 74 of 83
Measurement conditions
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
M32C/81 Group
5. Electrical Characteristics (VCC=3.3V)
Vcc=3.3V
Memory expansion mode and microprocessor mode (with a wait state)
Read timing
BCLK
18ns.max
td(BCLK-ALE) th(BCLK-ALE)
-2ns.min
ALE
td(BCLK-CS)
th(BCLK-CS)
18ns.max(1)
0ns.min
CSi
th(RD-CS)
tcyc
0ns.min
th(BCLK-AD)
td(BCLK-AD)
ADi
BHE
18ns.max(1)
0ns.min
td(BCLK-RD)
18ns.max
th(RD-AD)
0ns.min
RD
th(BCLK-RD)
tac2(RD-DB)(2)
tac2(AD-DB)
DB
Hi-Z
-3ns.min
(2)
tsu(DB-BCLK)
th(RD-DB)
30ns.min(1)
0ns.min
NOTES:
1. A value is guarantee with no external factor. Maximum 35ns is garanteed for td(BCLK-AD)+tsu(DB-BCLK).
2. It varies with the operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states)
Write timing
BCLK
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE
th(BCLK-CS)
td(BCLK-CS)
0ns.min
18ns.max
CSi
th(WR-CS)(1)
tcyc
td(BCLK-AD)
th(BCLK-AD)
18ns.max
0ns.min
ADi
BHE
td(BCLK-WR) tw(WR)(1)
WR,WRL,
WRH
th(WR-AD)(1)
18ns.max
th(BCLK-WR)
0ns.min
td(DB-WR)(1)
th(WR-DB)(1)
DBi
NOTES:
1. It varies with the operation frequency.
td(DB-WR)=(tcyc x n-20)ns.min
(n=1 when 1 wait, n=2 with 2 wait states and n=3 with 3 wait states)
th(WR-DB)=(tcyc/2-10)ns.min
th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait
states)
Figure 5.11 VCC=3.3V Timing Diagram (2)
Rev.1.00 Jun. 01, 2004
page 75 of 83
Measurement conditions
• VCC=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
Memory expansion mode and microprocessor mode
Vcc=3.3V
(with a wait state, when accessing an external memory and using the multiplexed bus)
Read timing
BCLK
td(BCLK-ALE)
th(BCLK-ALE)
18ns.max
-2ns.min
ALE
th(BCLK-CS)
tcyc
td(BCLK-CS)
0ns.min
18ns.max
th(RD-CS)(1)
CSi
td(AD-ALE)(1)
ADi
/DBi
th(ALE-AD)(1)
Address
th(RD-DB)
8ns.max
tsu(DB-BCLK)
td(BCLK-AD)
ADi
BHE
td(BCLK-RD)
tac3(AD-DB)(1)
0ns.min
th(BCLK-AD)
30ns.min
tac3(RD-DB)(1)
18ns.max
Address
Data input
tdz(RD-AD)
th(BCLK-RD)
18ns.max
0ns.min
th(RD-AD)(1)
-3ns.min
RD
NOTES:
1. It varies with the operation frequency.
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write Timing
BCLK
td(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
CSi
th(BCLK-CS)
tcyc
td(BCLK-CS)
th(WR-CS)(1)
18ns.max
0ns.min
td(AD-ALE)(1) th(ALE-AD)(1)
ADi
/DBi
td(DB-WR)(1)
td(BCLK-AD)
ADi
BHE
th(WR-DB)(1)
18ns.max
WR,WRL,
WRH
NOTES:
1. It varies with the operation frequency.
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
(m=3 with 2 wait states and m=5 with 3 wait states)
Figure 5.12 VCC=3.3V Timing Diagram (3)
page 76 of 83
th(BCLK-AD)
0ns.min
18ns.max
td(BCLK-WR)
Rev.1.00 Jun. 01, 2004
Address
Data output
Address
th(BCLK-WR)
th(WR-AD)()
0ns.min
Measurement conditions
• VCC=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
M32C/81 Group
5. Electrical Characteristics (VCC=3.3V)
Memory expansion mode and microprocessor mode
Vcc=3.3V
(With 2 wait states, when accessing the DRAM area)
Read timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
td(BCLK-CAD)
th(BCLK-RAD)
(1)
MAi
th(BCLK-CAD)
18ns.max(1)
0ns.min
0ns.min
Column address
Row address
(1)
th(RAS-RAD)
tRP(2)
RAS
td(BCLK-RAS)
18ns.max(1)
th(BCLK-RAS)
td(BCLK-CAS)
18ns.max(1)
CASL
CASH
0ns.min
th(BCLK-CAS)
0ns.min
DW
tac4(CAS-DB)(2)
tac4(CAD-DB)(2)
tac4(RAS-DB)(2)
Hi-Z
DB
tsu(DB-BCLK)
30ns.min(1)
th(CAS-DB)
0ns.min
NOTES:
1. A value is guaranteed with no external factor. Maximum 35ns is garanteed for the followings:
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
2. It varies with the operation frequency.
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Measurement conditions
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.13 VCC=3.3V Timing Diagram (4)
Rev.1.00 Jun. 01, 2004
page 77 of 83
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
Memory expansion mode and microprocessor mode
Vcc=3.3V
(With 2 wait states, when accessing the DRAM area)
Write timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
MAi
th(BCLK-RAD)
0ns.min
td(BCLK-CAD)
th(BCLK-CAD)
18ns.max
Row address
0ns.min
Column address
tRP(1)
th(RAS-RAD)(1)
RAS
td(BCLK-RAS) td(BCLK-CAS)
18ns.max
CASL
CASH
18ns.max
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
td(BCLK-DW)
0ns.min
18ns.max
DW
th(BCLK-DW)
tsu(DB-CAS)(1)
DB
-3ns.min
Hi-Z
th(BCLK-DB)
-7ns.min
NOTES:
1. It varies with the operation frequency.
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
tsu(DB-CAS)=(tcyc-20)ns.min
Figure 5.14 VCC=3.3V Timing Diagram (5)
Rev.1.00 Jun. 01, 2004
page 78 of 83
Measurement conditions
• VCC=3.0 to 3.6V
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
M32C/81 Group
5. Electrical Characteristics (VCC=3.3V)
Memory expansion mode and microprocessor mode Vcc=3.3V
Refresh timing (CAS-before-RAS refresh)
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
th(BCLK-RAS)
tsu(CAS-RAS)(1)
CASL
CASH
0ns.min
td(BCLK-CAS)
th(BCLK-CAS)
0ns.min
18ns.max
DW
NOTES:
1. It varies with the operation frequency.
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Refresh timing (Self-refresh)
BCLK
td(BCLK-RAS)
tcyc
18ns.max
RAS
tsu(CAS-RAS)(1)
CASL
CASH
td(BCLK-CAS)
18ns.max
DW
NOTES:
1. It varies with the operation frequency.
tsu(CAS-RAS)=(tcyc/2-13)ns.min
Measurement conditions
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.15 VCC=3.3V Timing Diagram (6)
Rev.1.00 Jun. 01, 2004
page 79 of 83
th(BCLK-RAS)
0ns.min
th(BCLK-CAS)
0ns.min
5. Electrical Characteristics (VCC=3.3V)
M32C/81 Group
Vcc=3.3V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Counter increment/
decrement input)
In event counter mode
TAiIN input
(When counting on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When counting on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
tw(INH)
Figure 5.16 VCC=3.3V Timing Diagram (7)
Rev.1.00 Jun. 01, 2004
page 80 of 83
th(C–D)
M32C/81 Group
5. Electrical Characteristics (VCC=3.3V)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(Valid only with a wait state)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
(Valid with a wait state and no wait state)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA) td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
P50 to P52
Hi–Z
Measurement conditions
• VCC=3.0 to 3.6V
• Input high or low voltage: VIH=2.4V, VIL=0.6V
• Output high or low voltage: VOH=1.5V, VOL=1.5V
Figure 5.17 VCC=3.3V Timing Diagram (8)
Rev.1.00 Jun. 01, 2004
page 81 of 83
th(BCLK–RDY)
Package Dimensions
M32C/81 Group
Package Dimensions
Recommended
EIAJ Package Code
LQFP144-P-2020-0.50
Plastic 144pin 20✕20mm body LQFP
Weight(g)
1.23
JEDEC Code
–
Lead Material
Cu Alloy
MD
e
144P6Q-A
b2
D
ME
HD
144
109
1
l2
Recommended Mount Pad
108
36
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
73
37
72
A
L1
F
e
L
M
Detail F
100P6S-A
Lp
Recommended
EIAJ Package Code
QFP100-P-1420-0.65
x
y
b2
I2
MD
ME
c
x
A1
b
y
A3
A2
A3
Dimension in Millimeters
Min
Nom
Max
1.7
–
–
0.125
0.2
0.05
1.4
–
–
0.17
0.22
0.27
0.105
0.125
0.175
19.9
20.0
20.1
19.9
20.0
20.1
0.5
–
–
21.8
22.0
22.2
21.8
22.0
22.2
0.35
0.5
0.65
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.08
0.1
–
–
0°
8°
–
0.225
–
–
0.95
–
–
20.4
–
–
20.4
–
–
Plastic 100pin 14✕20mm body QFP
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
81
1
b2
100
ME
HD
D
80
I2
Recommended Mount Pad
E
30
HE
Symbol
51
50
A
L1
c
A2
31
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
b
x
y
Rev.1.00 Jun. 01, 2004
page 82
of 83
M
A1
F
e
L
Detail F
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
3.05
0.1
0.2
0
–
–
2.8
0.25
0.3
0.4
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
–
0.65
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.13
–
–
0.1
–
0°
10°
–
–
0.35
1.3
–
–
14.6
–
–
–
–
20.6
Package Dimensions
M32C/81 Group
Recommended
Plastic 100pin 14✕14mm body LQFP
Weight(g)
0.63
JEDEC Code
–
Lead Material
Cu Alloy
MD
b2
HD
ME
EIAJ Package Code
LQFP100-P-1414-0.50
e
100P6Q-A
D
76
100
l2
Recommended Mount Pad
75
1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
51
25
26
50
A
L1
F
A3
y
M
L
Detail F
Rev.1.00 Jun. 01, 2004
page 83
of 83
Lp
c
x
A1
b
A3
A2
e
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
1.7
–
–
0.1
0.2
0
1.4
–
–
0.13
0.18
0.28
0.105
0.125
0.175
13.9
14.0
14.1
13.9
14.0
14.1
0.5
–
–
15.8
16.0
16.2
15.8
16.0
16.2
0.3
0.5
0.7
1.0
–
–
0.6
0.75
0.45
0.25
–
–
–
–
0.08
0.1
–
–
0°
10°
–
0.225
–
–
0.9
–
–
14.4
–
–
–
–
14.4
REVISION HISTORY
Rev.
M32C/81 Group Short Sheet/Data Sheet
Date
Description
Summary
Page
New Document
0.30 Sep. 30, 2003
Overview
2
- “1.2 Difference between the M32C/81 Group and the M32C/83 Group” has been
modified.
3 to 4
- “DRAMC” and “Oscillator stop detect function” have been added to Tables 1.1 and 1.2
10,14
- VREF pin has been changed from analog input pin to control pin.
16 to 18 - SDA0 to SDA4 pins have been changed from output pins to I/O pins.
17
- Description of intelligent I/O has been modified.
18
- OUTC30, OUTC32, ISTxD3 and ISRxD3 have been deleted from port P8.
19
- Intelligent I/O pin has been deleted from port P12.
19
- BEIN and BEOUT pins have been modified to IEIN and IEOUT pins in port P13.
SFR
25 to 34 - Details of addresses not modifiable by the user has been deleted.
- 001F16 to 002516 and 003016 to 003516 have been deleted.
24,25
- Value after RLVL register reset has been modified.
27
- Function select register A6 has been deleted.
41
Electrical Characteristics
- Maximum value of sub clock oscillation frequency has been added in Table 5.2.
46
- Value of 8-bit conversion time has been modified in Table 5.24
66
Words
standardized: On-chip oscillator, A/D converter and D/A converter
1.00 Jun. 01, 2004 All pages
0.20 Jun. 01, 2003
A-1
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