RENESAS R1RW0404D

R1RW0404D Series
4M High Speed SRAM (1-Mword × 4-bit)
REJ03C0115-0100Z
Rev. 1.00
Mar.12.2004
Description
The R1RW0404D is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed and high density
memory, such as cache and buffer memory in system. The R1RW0404D is packaged in 400-mil 32-pin
SOJ for high density surface mounting.
Features
• Single supply: 3.3 V ± 0.3 V
• Access time: 12 ns (max)
• Completely static memory
 No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
 All inputs and outputs
• Operating current: 100 mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current : 5 mA (max)
: 0.8 mA (max) (L-version)
• Data retention current: 0.4 mA (max) (L-version)
• Data retention voltage: 2 V (min) (L-version)
• Center VCC and VSS type pin out
Rev.1.00, Mar.12.2004, page 1 of 11
R1RW0404D Series
Ordering Information
Type No.
Access time
Package
R1RW0404DGE-2PR
12 ns
400-mil 32-pin plastic SOJ (32P0K)
R1RW0404DGE-2LR
12 ns
Pin Arrangement
32-pin SOJ
A0
A1
A2
A3
A4
CS#
I/O1
VCC
VSS
I/O2
WE#
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A19
A18
A17
A16
A15
OE#
I/O4
VSS
VCC
I/O3
A14
A13
A12
A11
A10
NC
(Top view)
Pin Description
Pin name
Function
A0 to A19
Address input
I/O1 to I/O4
Data input/output
CS#
Chip select
OE#
Output enable
WE#
Write enable
VCC
Power supply
VSS
Ground
NC
No connection
Rev.1.00, Mar.12.2004, page 2 of 11
R1RW0404D Series
Block Diagram
(LSB)
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
VCC
Row
decoder
(MSB)
1024-row × 64-column ×
16-block × 4-bit
(4,194,304 bits)
VSS
CS
Column I/O
I/O1
.
.
.
I/O4
Input
data
control
Column decoder
A8 A9 A19 A17 A18 A15 A0 A2 A4 A16
(LSB)
(MSB)
WE#
CS#
OE#
CS
Rev.1.00, Mar.12.2004, page 3 of 11
CS
R1RW0404D Series
Operation Table
CS#
OE#
WE#
Mode
VCC current
I/O
Ref. cycle
H
×
×
Standby
ISB, ISB1
High-Z

L
H
H
Output disable
ICC
High-Z

L
L
H
Read
ICC
DOUT
Read cycle (1) to (3)
L
H
L
Write
ICC
DIN
Write cycle (1)
L
L
L
Write
ICC
DIN
Write cycle (2)
Parameter
Symbol
Value
Supply voltage relative to VSS
VCC
−0.5 to +4.6
Voltage on any pin relative to VSS
VT
−0.5* to VCC + 0.5*
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
−55 to +125
°C
Storage temperature under bias
Tbias
−10 to +85
°C
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Unit
V
1
2
V
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter
Symbol
Supply voltage
Min
Typ
Max
Unit
3
3.0
3.3
3.6
V
4
0
0
0
VIH
2.0

VCC + 0.5*
VIL
−0.5*

0.8
VCC*
VSS*
Input voltage
Notes: 1.
2.
3.
4.
1
VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
Rev.1.00, Mar.12.2004, page 4 of 11
V
2
V
V
R1RW0404D Series
DC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter
Symbol
Min
Max
Unit
Test conditions
Input leakage current
IILII

2
µA
VIN = VSS to VCC
Output leakage current
IILOI

2
µA
VIN = VSS to VCC
Operation power supply current
ICC

100
mA
Min cycle
CS# = VIL, lOUT = 0 mA
Other inputs = VIH/VIL
Standby power supply current
ISB

40
mA
Min cycle, CS# = VIH,
Other inputs = VIH/VIL
ISB1

5
mA
f = 0 MHz
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
*
Output voltage
Note:
1
0.8*
1
VOL

0.4
V
IOL = 8 mA
VOH
2.4

V
IOH = −4 mA
1. This characteristics is guaranteed only for L-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Input capacitance*
1
Input/output capacitance*
Note:
1
Symbol
Min
Max
Unit
Test conditions
CIN

6
pF
VIN = 0 V
CI/O

8
pF
VI/O = 0 V
1. This parameter is sampled and not 100% tested.
Rev.1.00, Mar.12.2004, page 5 of 11
R1RW0404D Series
AC Characteristics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
1.5 V
DOUT Zo=50 Ω
3.3 V
RL=50 Ω
319Ω
DOUT
353Ω
30 pF
Output load (A)
5 pF
Output load (B)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW)
Read Cycle
R1RW0404D
-2
Parameter
Symbol
Read cycle time
tRC
Address access time
tAA
Chip select access time
tACS
Output enable to output valid
Max
Unit
12

ns

12
ns

12
ns
tOE

6
ns
Output hold from address change
tOH
3

ns
Chip select to output in low-Z
tCLZ
3

ns
1
Output enable to output in low-Z
tOLZ
0

ns
1
Chip deselect to output in high-Z
tCHZ

6
ns
1
Output disable to output in high-Z
tOHZ

6
ns
1
Rev.1.00, Mar.12.2004, page 6 of 11
Min
Notes
R1RW0404D Series
Write Cycle
R1RW0404D
-2
Parameter
Symbol
Min
Max
Unit
Write cycle time
tWC
12

ns
Notes
Address valid to end of write
tAW
8

ns
Chip select to end of write
tCW
8

ns
9
Write pulse width
tWP
8

ns
8
Address setup time
tAS
0

ns
6
Write recovery time
tWR
0

ns
7
Data to write time overlap
tDW
6

ns
Data hold from write time
tDH
0

ns
Write disable to output in low-Z
tOW
3

ns
1
Output disable to output in high-Z
tOHZ

6
ns
1
Write enable to output in high-Z
tWHZ

6
ns
1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. Address should be valid prior to or coincident with CS# transition low.
3. WE# and/or CS# must be high during address transition time.
4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS# or WE# going low.
7. tWR is measured from the earlier of CS# or WE# going high to the first address transition.
8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest
transition among CS# going low and WE# going low. A write ends at the earliest transition
among CS# going high and WE# going high. tWP is measured from the beginning of write to the
end of write.
9. tCW is measured from the later of CS# going low to the end of write.
Rev.1.00, Mar.12.2004, page 7 of 11
R1RW0404D Series
Timing Waveforms
Read Timing Waveform (1) (WE# = VIH)
tRC
Address
Valid address
tOH
tAA
tACS
tCHZ
CS#
tOE
tOHZ
OE#
tOLZ
tCLZ
DOUT
High impedance
Valid data
Read Timing Waveform (2) (WE# = VIH, CS# = VIL, OE# = VIL)
tRC
Address
Valid address
tAA
tOH
tOH
DOUT
Rev.1.00, Mar.12.2004, page 8 of 11
Valid data
R1RW0404D Series
Read Timing Waveform (3) (WE# = VIH, CS# = VIL, OE# = VIL)*
2
tRC
CS#
tACS
tCHZ
tCLZ
DOUT
High
impedance
Valid data
High
impedance
Write Timing Waveform (1) (WE# Controlled)
tWC
Valid address
Address
tWR
tAW
OE#
tCW
CS#*3
tAS
tWP
WE#*3
tOHZ
High impedance*5
DOUT
tDW
DIN
Rev.1.00, Mar.12.2004, page 9 of 11
*4
tDH
Valid data
*4
R1RW0404D Series
Write Timing Waveform (2) (CS# Controlled)
tWC
Valid address
Address
tWR
tCW
CS# *3
tAW
tWP
WE# *3
tAS
tWHZ
tOW
High impedance*5
DOUT
tDW
DIN
Rev.1.00, Mar.12.2004, page 10 of 11
*4
tDH
Valid data
*4
R1RW0404D Series
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Max
Unit
Test conditions
VCC for data retention
VDR
2.0

V
VCC ≥ CS# ≥ VCC − 0.2 V
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Data retention current
ICCDR

400
µA
VCC = 3 V, VCC ≥ CS# ≥ VCC − 0.2 V
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Chip deselect to data
retention time
tCDR
0

ns
See retention waveform
Operation recovery time
tR
5

ms
Low VCC Data Retention Timing Waveform
t CDR
Data retention mode
V CC
3.0 V
V DR
2.0 V
CS#
0V
Rev.1.00, Mar.12.2004, page 11 of 11
VCC ≥ CS# ≥ VCC − 0.2 V
tR
Revision History
Rev.
Date
R1RW0404D Series Data Sheet
Contents of Modification
Page
Description
0.01
Oct. 01, 2003

Initial issue
1.00
Mar.12.2004

Deletion of Preliminary
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
http://www.renesas.com
RENESAS SALES OFFICES
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501
Renesas Technology Europe Limited.
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom
Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900
Renesas Technology Europe GmbH
Dornacher Str. 3, D-85622 Feldkirchen, Germany
Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2003, 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .1.0