ETC R1LV0408C-I

R1LV0408C-I Series
Wide Temperature Range Version
4 M SRAM (512-kword × 8-bit)
REJ03C0098-0100Z
Rev. 1.00
Jul.24.2003
Description
The R1LV0408C-I is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LV0408C-I Series has
realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). The R1LV0408C-I Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin
TSOP II and 32-pin STSOP.
Features
• Single 3 V supply: 2.7 V to 3.6 V
• Access time: 55/70 ns (max)
• Power dissipation:
 Active: 6 mW/MHz (typ)
 Standby: 2.4 µW (typ)
• Completely static memory.
 No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
 Three state output
• Directly TTL compatible.
 All inputs and outputs
• Battery backup operation.
• Operating temperature: −40 to +85°C
Rev.1.00, Jul.24.2003, page 1 of 13
R1LV0408C-I Series
Ordering Information
Type No.
Access time
Package
R1LV0408CSP-5SI
55 ns
525-mil 32-pin plastic SOP (32P2M-A)
R1LV0408CSP-7LI
70 ns
R1LV0408CSB-5SI
55 ns
R1LV0408CSB-7LI
70 ns
R1LV0408CSA-5SI
55 ns
R1LV0408CSA-7LI
70 ns
Rev.1.00, Jul.24.2003, page 2 of 13
400-mil 32-pin plastic TSOP II (32P3Y-H)
8mm × 13.4mm STSOP (32P3K-B)
R1LV0408C-I Series
Pin Arrangement
32-pin SOP
32-pin TSOP
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin STSOP
VCC
A15
A17
WE#
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
(Top view)
Pin Description
Pin name
Function
A0 to A18
Address input
I/O0 to I/O7
Data input/output
CS# (CS)
Chip select
OE# (OE)
Output enable
WE# (WE)
Write enable
VCC
Power supply
VSS
Ground
Rev.1.00, Jul.24.2003, page 3 of 13
A11
A9
A8
A13
WE#
A18
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(Top view)
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
A1
A2
A3
R1LV0408C-I Series
Block Diagram
LSB
MSB
V CC
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
V SS
Row
Decoder
I/O0
•
•
•
•
•
Memory Matrix
2,048 × 2,048
•
•
Column I/O
Input
Data
Control
Column Decoder
I/O7
LSB A3 A2A1A0 A4 A5 A6 A7 MSB
••
CS#
WE#
Timing Pulse Generator
Read/Write Control
OE#
Rev.1.00, Jul.24.2003, page 4 of 13
•
•
R1LV0408C-I Series
Operation Table
WE#
CS#
OE#
Mode
VCC current
I/O0 to I/O7
Ref. cycle
×
H
×
Not selected
ISB, ISB1
High-Z

H
L
H
Output disable
ICC
High-Z

H
L
L
Read
ICC
Dout
Read cycle
L
L
H
Write
ICC
Din
Write cycle (1)
L
L
L
Write
ICC
Din
Write cycle (2)
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Power supply voltage relative to VSS
VCC
−0.5 to +4.6
Terminal voltage on any pin relative to VSS
VT
−0.5* to VCC + 0.5*
V
Power dissipation
PT
0.7
W
Operating temperature
Topr
−40 to +85
°C
Storage temperature range
Tstg
−65 to +150
°C
Storage temperature range under bias
Tbias
−40 to +85
°C
V
1
2
Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +7.0 V.
DC Operating Conditions
(Ta = −40 to +85°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.0
3.6
V
VSS
0
0
0
V
Input high voltage
VIH
2.2

VCC + 0.3
V
Input low voltage
VIL
−0.3*

0.6
V
Note:
1
1. VIL min: −3.0 V for pulse half-width ≤ 30 ns.
Rev.1.00, Jul.24.2003, page 5 of 13
R1LV0408C-I Series
DC Characteristics
Parameter
Symbol Min
1
Typ* Max Unit Test conditions
Input leakage current
|ILI|


1
µA
Vin = VSS to VCC
Output leakage current
|ILO|


1
µA
CS# = VIH or OE# = VIH or
WE# = VIL or VI/O = VSS to VCC
Operating current
ICC

5
10
mA
CS# = VIL,
Others = VIH/ VIL, II/O = 0 mA
Average operating current
ICC1

8
25
mA
Min. cycle, duty = 100%,
CS# = VIL, Others = VIH/VIL
II/O = 0 mA
ICC2

2
5
mA
Cycle time = 1 µs,
duty = 100%,
II/O = 0 mA, CS# ≤ 0.2 V,
VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V
ISB

0.1
0.3
ISB1








Standby current
Standby current
to +85°C
to +70°C
ISB1
to +40°C
ISB1
−40°C to +25°C
Output low voltage
Output high voltage
ISB1
CS# = VIH
µA
Vin ≥ 0 V, CS# ≥ VCC − 0.2 V
3
µA
2
µA
20*
10*
16*
µA
3
8*

0.7*

0.7*

mA
2
2
10*
3
3*
2
0.5*
2
µA
µA
3
2
10*
µA

0.5*
3*
µA
VOL


0.4
V
IOL = 2.1 mA
VOL2


0.2
V
IOL = 100 µA
VOH
2.4


V
IOH = −1.0 mA
VOH2
VCC − 0.2 

V
IOH = −0.1 mA
3
3
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. L version. (−7LI)
3. SL version. (−5SI)
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Min
Typ
Max
Unit
Test conditions
Note
Input capacitance
Cin


8
pF
Vin = 0 V
1
Input/output capacitance
CI/O


10
pF
VI/O = 0 V
1
Note:
1. This parameter is sampled and not 100% tested.
Rev.1.00, Jul.24.2003, page 6 of 13
R1LV0408C-I Series
AC Characteristics
(Ta = −40 to +85°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
• Input rise and fall time: 5 ns
• Input and output timing reference levels: 1.5 V
• Output load: 1 TTL Gate + CL (50 pF) (R1LV0408C-5I)
1 TTL Gate + CL (100 pF) (R1LV0408C-7I)
(Including scope and jig)
Read Cycle
R1LV0408C-I
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Read cycle time
tRC
55

70

ns
Address access time
tAA

55

70
ns
Chip select access time
tCO

55

70
ns
Output enable to output valid
tOE

30

35
ns
Chip select to output in low-Z
tLZ
10

10

ns
2
Output enable to output in low-Z
tOLZ
5

5

ns
2
Chip deselect to output in high-Z
tHZ
0
20
0
25
ns
1, 2
Output disable to output in high-Z
tOHZ
0
20
0
25
ns
1, 2
Output hold from address change
tOH
10

10

ns
Rev.1.00, Jul.24.2003, page 7 of 13
Notes
R1LV0408C-I Series
Write Cycle
R1LV0408C-I
-5
-7
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
55

70

ns
Chip selection to end of write
tCW
50

60

ns
4
Address setup time
tAS
0

0

ns
5
Address valid to end of write
tAW
50

60

ns
Write pulse width
tWP
40

50

ns
3, 12
Write recovery time
tWR
0

0

ns
6
Write to output in high-Z
tWHZ
0
20
0
25
ns
1, 2, 7
Data to write time overlap
tDW
25

30

ns
Data hold from write time
tDH
0

0

ns
Output active from end of write
tOW
5

5

ns
2
Output disable to output in high-Z
tOHZ
0
20
0
25
ns
1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS# going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem
of data bus contention. tWP ≥ tDW min + tWHZ max
Rev.1.00, Jul.24.2003, page 8 of 13
R1LV0408C-I Series
Timing Waveform
Read Timing Waveform (WE# = VIH)
tRC
Address
Valid address
tAA
tCO
CS#
tLZ
tHZ
tOE
tOLZ
OE#
tOHZ
Dout
High impedance
Valid data
tOH
Rev.1.00, Jul.24.2003, page 9 of 13
R1LV0408C-I Series
Write Timing Waveform (1) (OE# Clock)
tWC
Address
Valid address
tAW
tWR
OE#
tCW
CS#
*8
tWP
tAS
WE#
tOHZ
Dout
High impedance
tDW
Din
Rev.1.00, Jul.24.2003, page 10 of 13
Valid data
tDH
R1LV0408C-I Series
Write Timing Waveform (2) (OE# Low Fixed)
tWC
Address
Valid address
tCW
tWR
CS#
*8
tAW
tWP
WE#
tOH
tAS
tOW
tWHZ
*9
Dout
High impedance
tDW
tDH
*11
Din
Rev.1.00, Jul.24.2003, page 11 of 13
Valid data
*10
R1LV0408C-I Series
Low VCC Data Retention Characteristics
(Ta = −40 to +85°C)
4
3
Parameter
Symbol Min Typ* Max Unit Test conditions*
VCC for data retention
VDR
2


V
CS# ≥ VCC − 0.2 V, Vin ≥ 0 V
1


20
µA
VCC = 3.0 V, Vin ≥ 0 V
2


10
1


16
2


8
1

0.7
10
ICCDR*
2

0.7
3
−40°C to +25°C ICCDR*
1

0.5
10
2
ICCDR*

0.5
3
tCDR
0


ns


ns
Data retention current to +85°C
ICCDR*
ICCDR*
to +70°C
ICCDR*
ICCDR*
to +40°C
Chip deselect to data retention time
Operation recovery time
ICCDR*
tR
5
tRC*
CS# ≥ VCC − 0.2 V
µA
µA
µA
See retention waveform
Notes: 1. This characteristic is guaranteed only for L version.
2. This characteristic is guaranteed only for SL version.
3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode,
Vin levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
5. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS# Controlled)
tCDR
Data retention mode
VCC
4.5 V
2.4 V
VDR
CS#
0V
Rev.1.00, Jul.24.2003, page 12 of 13
CS# ≥ VCC – 0.2 V
tR
R1LV0408C-I Series
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Colophon 0.0
Rev.1.00, Jul.24.2003, page 13 of 13
R1LV0408C-I Series
Revision Record
Rev.
Date
Contents of Modification
1.00
Jul. 24, 2003
Initial issue
Rev.1.00, Jul.24.2003, page 14 of 13
Drawn by
Approved by