RENESAS R1LV0414CSB-7LI

R1LV0414C-I Series
Wide Temperature Range Version
4M SRAM (256-kword × 16-bit)
REJ03C0196-0201
Rev. 2.01
Nov.24.2005
Description
The R1LV0414C-I is a 4-Mbit static RAM organized 256-kword × 16-bit. R1LV0414C-I Series has realized higher
density, higher performance and low power consumption by employing CMOS process technology (6-transistor
memory cell). The R1LV0414C-I Series offers low power standby power dissipation; therefore, it is suitable for
battery backup systems. It has packaged in 44-pin TSOP II.
Features
• Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
• Fast access time: 55/70 ns (max)
• Power dissipation:
 Active: 5.0 mW/MHz (typ)(VCC = 2.5 V)
: 6.0 mW/MHz (typ) (VCC = 3.0 V)
 Standby: 1.25 µW (typ) (VCC = 2.5 V)
: 1.5 µW (typ) (VCC = 3.0 V)
• Completely static memory.
 No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
 Three state output
• Battery backup operation.
• Temperature range: −40 to +85°C
Ordering Information
Type No.
R1LV0414CSB-5SI
R1LV0414CSB-7LI
Access time
55 ns
70 ns
Rev.2.01, Nov.24.2005, page 1 of 11
Package
400-mil 44-pin plastic TSOP II (44P3W-H)
R1LV0414C-I Series
Pin Arrangement
44-pin TSOP
A4
A3
A2
A1
A0
CS#
I/O0
I/O1
I/O2
I/O3
V CC
V SS
I/O4
I/O5
I/O6
I/O7
WE#
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
(Top view)
Pin Description
Pin name
A0 to A17
I/O0 to I/O15
CS# (CS)
OE# (OE)
WE# (WE)
LB# (LB)
UB# (UB)
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Lower byte select
Upper byte select
VCC
VSS
NC
Power supply
Ground
No connection
Rev.2.01, Nov.24.2005, page 2 of 11
A5
A6
A7
OE#
UB#
LB#
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
R1LV0414C-I Series
Block Diagram
LSB
V CC
A12
A11
A10
V SS
A9
A8
A13
A14
Row
decoder
•
•
•
•
•
Memory matrix
2,048 x 2,048
A15
A16
MSB
A17
A7
I/O0
Column I/O
•
•
Input
data
control
Column decoder
I/O15
LSB A4 A3 A2 A1 A5 A6 A0 MSB
•
•
CS#
LB#
UB#
WE#
OE#
Rev.2.01, Nov.24.2005, page 3 of 11
Control logic
•
•
R1LV0414C-I Series
Operation Table
CS#
WE#
OE#
UB#
H
×
×
×
×
×
×
H
L
H
L
L
L
H
L
H
L
H
L
L
L
L
×
L
L
L
×
H
L
L
×
L
L
H
H
×
Note: H: VIH, L: VIL, ×: VIH or VIL
LB#
×
H
L
L
H
L
L
H
×
I/O0 to I/O7
High-Z
High-Z
Dout
Dout
High-Z
Din
Din
High-Z
High-Z
I/O8 to I/O15
High-Z
High-Z
Dout
High-Z
Dout
Din
High-Z
Din
High-Z
Operation
Standby
Standby
Read
Lower byte read
Upper byte read
Write
Lower byte write
Upper byte write
Output disable
Absolute Maximum Ratings
Parameter
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
Operating temperature
Storage temperature range
Storage temperature range under bias
Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +4.6 V.
Symbol
VCC
VT
PT
Topr
Value
−0.5 to +4.6
−0.5*1 to VCC + 0.3*2
0.7
−40 to +85
Unit
V
V
W
°C
Tstg
Tbias
−65 to +150
−40 to +85
°C
°C
DC Operating Conditions
(Ta = −40 to +85°C)
Parameter
Supply voltage
Input high voltage
Input low voltage
Note:
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.2 V to 2.7 V
VCC = 2.7 V to 3.6 V
Symbol
VCC
VSS
VIH
VIH
VIL
VIL
1. VIL min: −3.0 V for pulse half-width ≤ 30 ns.
Rev.2.01, Nov.24.2005, page 4 of 11
Min
2.2
0
2.0
2.2
−0.2
−0.3
Typ
2.5/3.0
0




Max
3.6
0
VCC + 0.3
VCC + 0.3
0.4
0.6
Unit
V
V
V
V
V
V
Note
1
1
R1LV0414C-I Series
DC Characteristics
Parameter
Input leakage current
Output leakage current
Symbol
|ILI|
|ILO|
Min


Typ


Operating current
ICC

5*1
Average operating current
ICC1

8*1
ICC2

2*1
ISB
ISB1
ISB1
ISB1
ISB1





0.1*1


0.7*2
0.5*1
Standby current
Standby current
−5SI
to +85°C
to +70°C
to +40°C
to +25°C
−7LI
to +85°C
to +70°C
to +40°C
to +25°C
Max Unit
Test conditions
1
µA Vin = VSS to VCC
1
µA CS# = VIH or OE# = VIH or WE# =
VIL or LB# = UB# = VIH,
VI/O = VSS to VCC
20 mA CS# = VIL, Others = VIH/VIL,
II/O = 0 mA
25 mA Min. cycle, duty = 100%,
II/O = 0 mA, CS# = VIL,
Others = VIH/VIL
5
mA Cycle time = 1 µs,
duty = 100%,
II/O = 0 mA, CS# ≤ 0.2 V,
VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V
0.3 mA CS# = VIH
10
µA Vin ≥ 0 V
8
µA (1) CS# ≥ VCC − 0.2 V
3
µA (2) LB# = UB# ≥ VCC − 0.2 V,
3
µA
CS# ≤ 0.2 V


20
µA


16
µA

0.7*2
10
µA

0.5*1
10
µA
Output high voltage VCC =2.2 V to 2.7 V
VOH
2.0
—
—
V IOH = −0.5 mA
VCC =2.7 V to 3.6 V
VOH
2.4
—
—
V IOH = −1 mA
VCC =2.2 V to 3.6 V
VOH2
VCC − 0.2
—
—
V IOH = −100 µA
Output low voltage VCC =2.2 V to 2.7 V
VOL
—
—
0.4
V IOL = 0.5 mA
VCC =2.7 V to 3.6 V
VOL
—
—
0.4
V IOL = 2 mA
VCC =2.2 V to 3.6 V
VOL2
—
—
0.2
V IOL = 100 µA
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
ISB1
ISB1
ISB1
ISB1
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Min
Input capacitance
Cin

Input/output capacitance
CI/O

Note: 1. This parameter is sampled and not 100% tested.
Rev.2.01, Nov.24.2005, page 5 of 11
Typ


Max
8
10
Unit
pF
pF
Test conditions
Vin = 0 V
VI/O = 0 V
Note
1
1
R1LV0414C-I Series
AC Characteristics
(Ta = −40 to +85°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: VIL = 0.4 V, VIH = 2.2 V (VCC = 2.2 V to 2.7 V)
: VIL = 0.4 V, VIH = 2.4 V (VCC = 2.7 V to 3.6 V)
• Input rise and fall time: 5 ns
• Input/output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V)
: 1.4 V (VCC = 2.7 V to 3.6 V)
• Output load: See figures (Including scope and jig)
VTM
1.4 V
R1
RL=500 Ω
Dout
Dout
R1 = 3070 Ω
30pF
R2
R2 = 3150 Ω
VTM = 2.3 V
50pF
Output load (B)
(VCC = 2.7 V to 3.6 V)
Output load (A)
(VCC = 2.2 V to 2.7 V)
Read Cycle
R1LV0414C-I
-5SI
Parameter
Read cycle time
Address access time
Chip select access time
Output enable to output valid
Output hold from address change
LB#, UB# access time
Chip select to output in low-Z
LB#, UB# disable to low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
LB#, UB# disable to high-Z
Output disable to output in high-Z
Rev.2.01, Nov.24.2005, page 6 of 11
Symbol
tRC
tAA
tACS
tOE
tOH
tBA
tCLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
Min
55



10

10
5
5
0
0
0
-7LI
Max

55
55
35

55



20
20
20
Min
70



10

10
5
5
0
0
0
Max

70
70
40

70



25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
2, 3
2, 3
2, 3
1, 2, 3
1, 2, 3
1, 2, 3
R1LV0414C-I Series
Write Cycle
R1LV0414C-I
-5SI
-7LI
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
tWC
55

70

ns
Address valid to end of write
tAW
50

60

ns
Chip selection to end of write
tCW
50

60

ns
5
Write pulse width
tWP
40

50

ns
4
LB#, UB# valid to end of write
tBW
50

55

ns
Address setup time
tAS
0

0

ns
6
Write recovery time
tWR
0

0

ns
7
Data to write time overlap
tDW
25

30

ns
Data hold from write time
tDH
0

0

ns
Output active from end of write
tOW
5

5

ns
2
Output disable to output in high-Z
tOHZ
0
20
0
25
ns
1, 2, 3
Write to output in high-Z
tWHZ
0
20
0
25
ns
1, 2
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
device to device.
4. A write occures during the overlap of a low CS#, a low WE# and a low LB# or a low UB#. A write begins at
the latest transition among CS# going low, WE# going low and LB# going low or UB# going low. A write ends
at the earliest transition among CS# going high, WE# going high and LB# going high or UB# going high. tWP
is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS# going low to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS# or WE# going high to the end of write cycle.
Parameter
Rev.2.01, Nov.24.2005, page 7 of 11
R1LV0414C-I Series
Timing Waveform
Read Timing Waveform (WE# = VIH)
t RC
Address
Valid address
tAA
tACS
CS#
tCLZ*2, 3
tCHZ*1, 2, 3
tBHZ*1, 2, 3
tBA
LB#, UB#
tBLZ*2, 3
tOHZ*1, 2, 3
tOE
OE#
tOLZ*2, 3
Dout
tOH
High impedance
Valid data
Write Timing Waveform (1) (WE# Clock)
tWC
Valid address
Address
tWR*7
tCW*5
CS#
tBW
LB#, UB#
tAW
tWP*4
WE#
tAS*6
tDW
tDH
Valid data
Din
tWHZ*1, 2
tOW*2
High impedance
Dout
Rev.2.01, Nov.24.2005, page 8 of 11
R1LV0414C-I Series
Write Timing Waveform (2) (CS# Clock, OE# = VIH)
tWC
Valid address
Address
tAW
tAS*6
tWR*7
tCW*5
CS#
tBW
LB#, UB#
tWP*4
WE#
tDW
tDH
Valid data
Din
High impedance
Dout
Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH)
tWC
Valid address
Address
tAW
tCW*5
tWR*7
CS#
tAS*6
tBW
LB#, UB#
tWP*4
WE#
tDW
Valid data
Din
High impedance
Dout
Rev.2.01, Nov.24.2005, page 9 of 11
tDH
R1LV0414C-I Series
Low VCC Data Retention Characteristics
(Ta = −40 to +85°C)
Parameter
VCC for data retention
Min
2
Typ

Max

Unit
Test conditions*3
V Vin ≥ 0V
(1) CS# ≥ VCC − 0.2 V or
(2) LB# = UB# ≥ VCC − 0.2 V,
CS# ≤ 0.2 V


10
µA VCC = 3.0 V, Vin ≥ 0V


8
µA (1) CS# ≥ VCC − 0.2 V or
2
 0.7*
3
µA (2) LB# = UB# ≥ VCC − 0.2 V,
CS# ≤ 0.2 V
1
 0.5*
3
µA
−7LI


20
µA


16
µA
2
 0.7*
10
µA
 0.5*1 10
µA
Chip deselect to data retention time
tCDR
0


ns See retention waveform
4
Operation recovery time
tR
tRC*


ns
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. Typical values are at VCC = 3.0 V, Ta = +40°C and specified loading, and not guaranteed.
3. CS# controls address buffer, WE# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS# controls data
retention mode, Vin levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. If LB#,
UB# controls data retention mode, LB#, UB# must be LB# = UB# ≥ VCC − 0.2 V, CS# must be CS# ≤ 0.2 V.
The other input levels (address, WE#, OE#, I/O) can be in the high impedance state.
4. tRC = read cycle time.
Data
retention
current
−5SI
Symbol
VDR
to +85°C
to +70°C
to +40°C
to +25°C
to +85°C
to +70°C
to +40°C
to +25°C
Rev.2.01, Nov.24.2005, page 10 of 11
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
ICCDR
R1LV0414C-I Series
Low VCC Data Retention Timing Waveform (1) (CS# Controlled) (VCC = 2.2 V to 2.7 V)
t CDR
Data retention mode
tR
V CC
2.2 V
V DR
2.0 V
CS# ≥ V CC – 0.2 V
CS#
0V
Low VCC Data Retention Timing Waveform (2) (CS# Controlled) (VCC = 2.7 V to 3.6 V)
t CDR
Data retention mode
tR
V CC
2.7 V
2.2 V
V DR
CS# ≥ V CC – 0.2 V
CS#
0V
Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled) (VCC = 2.2 V to 2.7 V)
t CDR
Data retention mode
tR
V CC
2.2 V
V DR
2.0 V
LB#, UB# ≥ VCC – 0.2 V
LB#, UB#
0V
Low VCC Data Retention Timing Waveform (4) (LB#, UB# Controlled) (VCC = 2.7 V to 3.6 V)
t CDR
Data retention mode
V CC
2.7 V
2.2 V
V DR
LB#, UB#
0V
Rev.2.01, Nov.24.2005, page 11 of 11
LB#, UB# ≥ VCC – 0.2 V
tR
Revision History
Rev.
Date
1.00
2.00
Mar. 10, 2004
May 26, 2004
2.01
Nov.24.2005
R1LV0414C-I Series Data Sheet
Contents of Modification
Description
Page

Initial issue
Absolute Maximum Ratings
5
Notes 2 : +7.0 V to +4.6 V
DC characteristics
6
−5SI and −7LI items’ description are divided.
AC characteristics
7
Read Cycle/Notes:
8
tCLZ/tBLZ/tOLZ : Addition of [2, 3]
tCHZ/tBHZ/tOHZ : Addition of [1, 2, 3]
9
Write Cycle/Notes:
tOHZ : Addition of [1, 2, 3]
14
Low VCC Data Retention Characteristics
−5SI and −7LI items’ description are divided.
Low VCC Data Retention Characteristics
−5SI and −7LI items’ description are divided.

Change of format
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