HEF4001B Quad 2-input NOR gate Rev. 9 — 21 November 2011 Product data sheet 1. General description The HEF4001B is a quad 2-input NOR gate. The outputs are fully buffered for the highest noise immunity and pattern insensitivity to output impedance. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +125 C Complies with JEDEC standard JESD 13-B Inputs and outputs are protected against electrostatic effects 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C Type number Package Name Description Version HEF4001BP DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 HEF4001BT SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 4. Functional diagram 1A 1 1B 2 2A 5 2B 6 3A 8 3B 9 4A 12 4B 13 3 1Y 4 2Y 10 3Y nA nB 11 4Y 001aag194 Fig 1. Functional diagram nY 001aag195 Fig 2. Logic diagram (one gate) HEF4001B NXP Semiconductors Quad 2-input NOR gate 5. Pinning information 5.1 Pinning 1A 1 14 VDD 1B 2 13 4B 1Y 3 12 4A 2Y 4 2A 5 2B 6 VSS 7 HEF4001B 11 4Y 10 3Y 9 3B 8 3A 001aag196 Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description nA 1, 5, 8, 12 input nB 2, 6, 9, 13 input nY 3, 4, 10, 11 output VSS 7 ground (0 V) VDD 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nY L L H L H L H L L H H L [1] H = HIGH voltage level; L = LOW voltage level. HEF4001B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 2 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage Conditions Min 0.5 VI < 0.5 V or VI > VDD + 0.5 V Unit +18 V 10 mA IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current - Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation P - Max 0.5 VO < 0.5 V or VO > VDD + 0.5 V VDD + 0.5 V - 10 mA - 10 mA 50 mA Tamb = 40 C to + 125 C power dissipation DIP14 [1] - 750 mW SO14 [2] - 500 mW - 100 mW per output [1] For DIP14 packages: above Tamb = 70 C, Ptot derates linearly with 12 mW/K. [2] For SO14 packages: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V HEF4001B Product data sheet Conditions All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 3 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter Conditions VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage IDD supply current input capacitance HEF4001B Product data sheet Max Min Max 3.5 - 3.5 - 3.5 - 3.5 - V - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A 5V all valid input combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 A - 0.5 - 0.5 - 15.0 - 15.0 A - 1.0 - 1.0 - 30.0 - 30.0 A - - - 7.5 - - - - pF IO < 1 A IO < 1 A input leakage current Min 7.0 LOW-level output voltage LOW-level output current Max 5V IO < 1 A HIGH-level output current Min 10 V HIGH-level output voltage II CI IO < 1 A Max All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 4 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; for waveforms see Figure 4; for test circuit see Figure 5; unless otherwise specified. Extrapolation formula[1] Symbol Parameter HIGH to LOW propagation delay tPHL LOW to HIGH propagation delay tPLH tTHL tTLH [1] VDD Min Typ Max Unit 33 + 0.55 CL 5V - 60 120 ns 14 + 0.23 CL 10 V - 25 50 ns 12 + 0.16 CL 15 V - 20 40 ns 23 + 0.55 CL 5V - 50 100 ns 14 + 0.23 CL 10 V - 25 45 ns 12 + 0.16 CL 15 V - 20 35 ns HIGH to LOW output transition time 10 + 1.00 CL 5V - 60 120 ns 9 + 0.42 CL 10 V - 30 60 ns 6 + 0.28 CL 15 V - 20 40 ns LOW to HIGH output transition time 10 + 1.00 CL 5V - 60 120 ns 9 + 0.42 CL 10 V - 30 60 ns 6 + 0.28 CL 15 V - 20 40 ns The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula Where 5 V PD = 1100 fi + (fo CL) VDD (W) 2 10 V PD = 5000 fi + (fo CL) VDD2 (W) fi = input frequency in MHz; fo = output frequency in MHz; 15 V PD = 14200 fi + (fo CL) VDD2 (W) CL = output load capacitance in pF; (fo CL) = sum of the outputs; VDD = supply voltage in V. HEF4001B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 5 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 11. Waveforms tr VI tf 90 % input VM 0V 10 % tPHL VOH tPLH 90 % output VM 10 % VOL tTHL tTLH 001aag197 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Propagation delay, output transition time Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD VDD VI VO G DUT CL RT 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 5. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF HEF4001B Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 6 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 6. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) HEF4001B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 7 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 7. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) HEF4001B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 8 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 13. Abbreviations Table 11. Abbreviations Acronym Description DUT Device Under Test 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4001B v.9 20111121 Product data sheet - HEF4001B v.8 Modifications: • • • Legal pages updated. Changes in “General description” and “Features and benefits”. Section “Applications” removed. HEF4001B v.8 20110913 Product data sheet - HEF4001B v.7 HEF4001B v.7 20091027 Product data sheet - HEF4001B v.6 HEF4001B v.6 20090618 Product data sheet - HEF4001B v.5 HEF4001B v.5 20080327 Product data sheet - HEF4001B v.4 HEF4001B v.4 20070731 Product data sheet - HEF4001B_CNV v.3 HEF4001B_CNV v.3 19950101 Product specification - HEF4001B_CNV v.2 HEF4001B_CNV v.2 19950101 Product specification - - HEF4001B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 9 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 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Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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All rights reserved. 10 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4001B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 21 November 2011 © NXP B.V. 2011. All rights reserved. 11 of 12 HEF4001B NXP Semiconductors Quad 2-input NOR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 21 November 2011 Document identifier: HEF4001B