UESD6V8S2B - Union Semiconductor

UESD6V8S2B
Dual Line ESD Protection Diode Array
UESD6V8S2B SOT523
General Description
The UESD6V8S2B of TVS diode array is designed to protect sensitive electronics from damage or
latch-up due to ESD and is for use in applications where board space is at a premium. It is
unidirectional device and may be used on lines where the signal polarities are above ground, each
device will protect up to two lines.
TVS diodes are solid-state devices feature large cross-sectional area junctions for conducting high
transient currents, specifically for transient suppression. It offers desirable characteristics for board
level protection including fast response time, low operating, low clamping voltage, and no device
degradation.
The UESD6V8S2B may be used to meet the immunity requirements of IEC 61000-4-2, ±15kV air,
±8kV contact discharge and MIL-STD-883 METHOD 3015, ±8kV HBM. The small package makes
them ideal for use in portable electronics such as cell phones, PDA’s, notebook computers, and digital
cameras.
Applications
Features
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Cellular Handsets & Accessories
Cordless Phones
Personal Digital Assistants (PDA’s)
Notebooks & Handhelds
Portable Instrumentation
Digital Cameras
Peripherals
MP3 Players
Pin Configurations
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Transient Protection for Data & Power Lines
to IEC 61000-4-2 (ESD) ±15kV (Air), ±8kV
(Contact)
MIL-STD-883 3015 (HBM) ±8 kV
Protect Two I/O Lines
Working Voltages: 5V
Low Leakage Current
Low Operating and Clamping Voltage
Solid-State Silicon Avalanche Technology
Top View
M: Month Code
UESD6V8S2B
SOT523
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UESD6V8S2B
Ordering Information
Part Number
Working
Voltage
Packaging Type
Channel
Marking
Code
Shipping Qty
UESD6V8S2B
5.0V
SOT523
2
5ZA
3000pcs/7Inch
Tape & Reel
Absolute Maximum Ratings
RATING
SYMBOL
VALUE
UNITS
Peak Pulse Power (tp = 8/20μs)
PPK
140
Watts
Peak Pulse Current (tp = 8/20μs)
IPP
11
A
Lead Soldering Temperature
TL
260(10 sec.)
°C
Operating Temperature
TJ
-55 to +125
°C
TSTG
-55 to +125
°C
TYP
MAX
UNIT
5
V
7.2
V
μA
Storage Temperature
Electrical Characteristics
PARAMETER
SYMBOL
Reverse Stand-Off Voltage
Reverse Breakdown
Voltage
Reverse Leakage Current
VRWM
MIN
VBR
It = 1mA
IR
VRWM = 5V, T=25°C
0.1
IPP =5A, tp = 8/20μs
9.1
IPP =11A, tp = 8/20μs
Pin 1,2 to 3
VR = 0V, f = 1MHz
Pin 1,2 to 3
VR = 2.5V, f = 1MHz
13
Clamping Voltage
VC
Junction Capacitance
CJ
Junction Capacitance
CJ
Reverse dynamic
resistance
Forward dynamic
resistance
CONDITIONS
Rdyn,rev
6
6.8
V
40
50
pF
30
40
pF
0.6
Ω
0.5
Ω
IPP=1A~5A
Rdyn,fwd
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UESD6V8S2B
Typical Operating Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
Clamping Voltage vs. Peak Pulse Current
1
Peak Pulse Power - Ppk(kW)
13
Clamping Voltage - Vc(V)
12
0.1
11
10
9
8
Waveform
parameters:
tr=8uS
td=20uS
7
0.02
0.04
0.1
1
10
100
6
1000
0
2
Pulse Duration - tp(uS)
Forward Voltage vs. Forward Current
6
8
10
Junction Capacitance vs. Reverse Voltage
50
5
4
3
Waveform
parameters:
tr=8uS
td=20uS
2
Junction Capacitance(pF)
6
Forward Voltage - Vf(V)
4
Peak Pulse Current - Ipp(A)
45
40
35
30
1
2
4
6
8
Forward Current - If(A)
10
0
1
2
3
4
5
Reverse Voltage (V)
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UESD6V8S2B
Application Information
UESD6V8S2B ESD protection diode is designed to protect dual data, I/O, or power supply line. The
device is unidirectional and may be used on lines where the signal polarity is above ground. The
cathode should be placed towards the line that is to be protected.
Device Connection for Protection of Dual Data Lines
The Dual TVS Diode Array is designed to protect up to two unidirectional data lines. The device is
connected as follows:
Unidirectional protection of two I/O lines is achieved by connecting pins 1 and 2 to the data lines. Pin
3 is connected to ground. The ground connection should be made directly to the ground plane for best
results. The path length is kept as short as possible to reduce the effects of parasitic inductance in the
board traces.
Circuit Board Layout Recommendations for Suppression of ESD
Good circuit board layout is critical for the suppression of ESD induced transients. The following
guidelines are recommended:
Place the TVS near the input terminals or connectors to restrict transient coupling.
Minimize the path length between the TVS and the protected line.
Minimize all conductive loops including power and ground loops.
The ESD transient return path to ground should be kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible. For multilayer printed-circuit boards, use ground vias.
Keep parallel signal paths to a minimum.
Avoid running protection conductors in parallel with unprotected conductor.
Minimize all printed-circuit board conductive loops including power and ground loops.
Avoid using shared transient return paths to a common ground point.
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UESD6V8S2B
Package Information
UESD6V8S2B SOT523
Outline Drawing
DIMENSIONS
MILLIMETERS
INCHES
Symbol
Min
Max
Min
Max
A
0.15
0.30
0.006 0.012
B
0.75
0.85
0.030 0.034
C
1.45
1.75
0.058 0.070
D
0.50TYP
0.020TYP
G
0.90
1.10
0.036 0.044
H
1.50
1.70
0.060 0.068
J
0.00
0.10
0.000 0.004
K
0.60
0.80
0.024 0.032
L
0.10
0.30
0.004 0.012
M
0.10
0.20
0.004 0.008
N
0.45
0.65
0.018 0.026
α
0°
8°
0°
8°
Land Pattern
1.29
0.75
1.00
0.30
NOTES:
1. Compound dimension: 1.60×0.80 ;
2. Unit: mm;
3. General tolerance ±0.05mm unless otherwise
specified;
4. The layout is just for reference.
5ZA
M
Tape and Reel Orientation
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UESD6V8S2B
IMPORTANT NOTICE
The information in this document has been carefully reviewed and is believed to be accurate.
Nonetheless, this document is subject to change without notice. Union assumes no
responsibility for any inaccuracies that may be contained in this document, and makes no
commitment to update or to keep current the contained information, or to notify a person or
organization of any update. Union reserves the right to make changes, at any time, in order to
improve reliability, function or design and to attempt to supply the best product possible.
Union Semiconductor, Inc
Add: Unit 606, No.570 Shengxia Road, Shanghai 201210
Tel: 021-51093966
Fax: 021-51026018
Website: www.union-ic.com
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