Preliminary Datasheet HD74LV166A R04DS0002EJ0400 (Previous: REJ03D0321-0300) Rev.4.00 Aug 16, 2010 Parallel-Load 8-bit Shift Register Description The HD74LV166A is 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LV166AFPEL SOP–16 pin(JEITA) PRSP0016DH-B (FP–16DAV) FP EL (2,000 pcs/reel) HD74LV166ATELL TSSOP–16 pin PTSP0016JB-A (TTP–16DAV) T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table CLR L H SH/LD X X H H H H L H H X Note: Inputs CLK INH CLK X X L L L L L H SER X X A ... H X X Internal outputs QA QB L L QA0 QB0 X H L X a ... h X X X a H L QA0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0 H: High level L: Low level : Low to high transition X: Immaterial a ... h: Parallel data Outputs remain unchanged. QA0 ... QH0: Data shifted from the previous stage on a positive edge at the clock input. QAn ... QGn: R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Page 1 of 9 HD74LV166A Preliminary Pin Arrangement 16 VCC SER 1 A 2 15 SH/LD B 3 14 H C 4 13 QH D 5 12 G CLK INH 6 11 F CLK 7 10 E 9 CLR GND 8 (Top view) R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Page 2 of 9 HD74LV166A Preliminary Absolute Maximum Ratings Item Supply voltage range Input voltage range*1 Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at 3 Ta = 25°C (in still air)* Storage temperature Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ±50 Unit V V V 785 500 –65 to 150 mW mA mA mA mA Conditions Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Recommended Operating Conditions Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH IOL Input transition rise or fall rate t /v Operating free-air temperature Ta Note: Min 2.0 0 0 — — — — — — — Max 5.5 5.5 VCC –50 –2 –6 –12 50 2 6 — 0 0 0 –40 12 200 100 20 85 Unit V V V A mA A mA ns/V Conditions H or L VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V °C Unused or floating inputs must be held high or low. R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Page 3 of 9 HD74LV166A Preliminary Logic Diagram A SER B C D E F CLR G H SH/LD CLK CLK INH R CP S CD Q R CP S Q CD QH Timing Diagram CLK CLK INH CLR SER SH/LD Parallel Inputs A H B L C H D L E H L F G H H H H Output QH Serial shift Clear R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Inhibit H L H L H L H L Serial shift Load Page 4 of 9 HD74LV166A Preliminary DC Electrical Characteristics (Ta = –40 to 85°C) Item Input voltage Symbol VIH Input current IIN VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 A IOL = –50 A IOL = –2 mA IOL = –6 mA IOL = –12 mA IOL = 50 A IOL = 2 mA IOL = 6 mA IOL = 12 mA VI = 5.5 V or GND Quiescent supply current ICC 5.5 — — 20 A VI = VCC or GND, IO = 0 Output leakage current Input capacitance IOFF 0 — — 5 µA VI or VO = 0 V to 5.5 V CIN 3.3 — 1.7 — pF VI = VCC or GND VIL Output voltage VOH VOL Note: Min 1.5 VCC 0.7 VCC 0.7 VCC 0.7 — — — — VCC –0.1 2.0 2.48 3.8 — — — — — Typ — — — — — — — — — — — — — — — — — Max — — — — 0.5 VCC 0.3 VCC 0.3 VCC 0.3 — — — — 0.1 0.4 0.44 0.55 ±1 Unit V V Test Conditions For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Page 5 of 9 HD74LV166A Preliminary Switching Characteristics (VCC = 2.5 ± 0.2 V) Item Symbol Maximum clock frequency fmax Propagation delay time tPLH/tPHL tPHL Setup time tsu Hold time th Pulse width tw Ta = 25°C Min Typ Max 50 80 — Ta = –40 to 85°C Min Max 45 — 40 — — — — 6.0 65 12.2 15.3 10.8 14.2 — — 19.8 23.3 16.0 19.5 — 35 1.0 1.0 1.0 1.0 7.0 — 22.0 26.0 18.0 22.0 — 7.0 6.5 7.0 — — — — — — 7.0 8.5 8.5 — — — 8.5 –0.5 –0.5 –0.5 — — — — — — — — 9.5 0.0 0.0 0.0 — — — — 8.0 8.5 — — — — 9.0 9.0 — — Unit Test Conditions MHz CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns FROM (Input) CLK TO (Output) QH CLR CLR inactive before CLK CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK ns CLR low CLK H or L ns (VCC = 3.3 ± 0.3 V) Item Symbol Maximum clock frequency fmax Propagation delay time tPLH/tPHL tPHL Setup time tsu Hold time th Pulse width tw R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Min 65 Ta = 25°C Typ Max 115 — Ta = –40 to 85°C Min Max 55 — 60 — — — — 4.0 90 8.6 10.9 7.9 10.4 — — 15.4 18.9 12.5 16.3 — 50 1.0 1.0 1.0 1.0 4.0 — 18.0 21.5 15.0 18.5 — 5.0 5.0 5.0 — — — — — — 5.0 6.0 6.0 — — — 5.0 0.0 0.0 0.0 6.0 6.0 — — — — — — — — — — — — 6.0 0.0 0.0 0.0 7.0 7.0 — — — — — — Unit Test Conditions MHz CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns ns ns FROM (Input) CLK TO (Output) QH CLR CLR inactive before CLK CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK CLR low CLK H or L Page 6 of 9 HD74LV166A Preliminary Switching Characteristics (cont) (VCC = 5.0 ± 0.5 V) Item Symbol Maximum clock frequency fmax tPLH/tPHL Propagation delay time tPHL Setup time tsu Hold time th Pulse width tw Ta = 25°C Min Typ Max 110 165 — Ta = –40 to 85°C Min Max 90 — 95 — — — — 3.5 125 6.0 7.7 5.4 6.9 — — 9.9 11.9 8.6 10.6 — 85 1.0 1.0 1.0 1.0 3.5 — 11.5 13.5 10.0 12.0 — 3.5 4.5 4.0 — — — — — — 3.5 4.5 4.0 — — — 4.0 1.0 1.0 1.0 — — — — — — — — 4.0 1.0 1.0 1.0 — — — — 5.0 4.0 — — — — 5.0 4.0 — — Unit Test Conditions MHz CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF ns FROM (Input) TO (Output) CLK QH CLR CLR inactive before CLK CLK INH before CLK Data before CLK SH/LD high before CLK SER before CLK PAR data after SH/LD SER data after CLK SH/LD high after CLK ns CLR low CLK H or L ns Operating Characteristics (CL = 50 pF) Item Symbol VCC (V) Min Ta = 25°C Typ Max Unit Power dissipation capacitance CPD 3.3 5.0 — — 36.1 37.5 — — pF Test Conditions f = 10 MHz Test Circuit Measurement point CL* Note: CL includes the probe and jig capacitance. R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Page 7 of 9 HD74LV166A Preliminary Waveforms tW VCC CLR 50%VCC 50%VCC tn tn+1 tn 0V tn+1 VCC tsu CLK 50%VCC 50%VCC 50%VCC 0V tW tsu Data 50%VCC 50%VCC th tsu 50%VCC th VCC 50%VCC 50%VCC 0V tPHL tPLH tPHL VOH Output QH 50%VCC 50%VCC 50%VCC VOL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t r ≤ 3 ns, t f ≤ 3 ns 2. The output are measured one at a time with one transition per measurement. R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 Page 8 of 9 HD74LV166A Preliminary Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 9 c HE *2 E bp Index mark Terminal cross section Reference Symbol ( Ni/Pd/Au plating ) 1 8 *3 e Z bp x M L1 A1 θ A S L y S Detail F JEITA Package Code P-TSSOP16-4.4x5-0.65 RENESAS Code PTSP0016JB-A *1 Previous Code TTP-16DAV Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.34 0.40 0.20 2.20 0.46 0.15 0.20 0.25 0° 7.50 0.50 7.80 1.27 0.70 1.15 8° 8.00 0.12 0.15 0.80 0.90 MASS[Typ.] 0.05g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters 9 *2 E HE c bp Terminal cross section Reference Symbol (Ni/Pd/Au plating) Index mark 8 1 Z *3 e L1 x M A1 θ A S bp y S R04DS0002EJ0400 Rev.4.00 Aug 16, 2010 L Detail F D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Dimension in Millimeters Min Nom 5.0 4.40 Max 5.3 0.03 0.07 0.15 0.20 0.10 1.10 0.25 0.10 0.15 0.20 0° 6.20 0.4 6.40 0.65 0.5 1.0 8° 6.60 0.13 0.10 0.65 0.6 Page 9 of 9 Notice 1. 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