New Product R2A20162NS/SA/SP 8-bit 2ch D/A Converter with Buffer R03DS0016EJ0100 Rev.1.00 2011.09.05 Description The R2A20162 is an integrated circuit semiconductor of CMOS structure with 2 channels of built in D/A converters with output buffer op-amps. It is the electrical characteristic improvement version of the M62342. Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD. Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements unnecessary and enabling configuration of a system with few component parts. Very small SON package is added to lineup. It is suitable for a small mounting and reduces the mounting area. Features Guarantee Differential Nonlinearity error : +/- 0.7LSB, Nonlinearity error : +/- 1.0LSB, Data transfer format: 10-bit serial data input type by 3 wire ( DI, SCK, LD ) Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V ) High output current capacity: +/- 1mA or Higher Very mall size package line-up: SON-8 (pin pitch: 0.5mm), TSSOP-8 (pin pitch 0.65mm) Application Conversion from digital data to analog control data for home-use and industrial equipment. Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor. Blurring correction control or various control of the interchangeable lens of digital camera for self adjustment by combination with microcomputer and EEPROM. (substitution of half fixed resistance) Block Diagram Vcc 4 LD 8 CLK 7 GND 5 DI 6 10-bit shift register Power on reset Channel decoder 8 8-bit latch 8-bit latch 8-bit upper segment R-2R 8-bit upper Segment R-2R 1 Ao1 R03DS0016EJ0100 Rev.1.00 2011.09.05 2 Ao2 3 N.C. Page 1 of 7 New Product R2A20162NS/SA/SP Pin Arrangement R2A20162NS (Top view) R2A20162SA/SP (Top view) Ao1 1 8 LD Ao1 1 8 LD Ao2 2 7 CLK Ao2 2 7 CLK N.C. 3 6 DI N.C. 3 6 DI 5 GND Vcc Vcc 4 4 N.C.: Not connected Outline: PWSN0008KA-A [NS] 5 GND N.C.: Not connected Outline: PRSP0008DE-C [SP] PTSP-0008JC-B [SA] Pin Description Pin No. Pin Name 6 DI Function Serial data input terminal. (Input serial data with a 10-bit data length.) Serial clock input terminal (Input signal from DI terminal is input to 10-bit shift register at rise of serial clock.) 7 CLK 8 LD 1 Ao1 2 A02 8-bit resolution D/A converter output terminals (After power-on, all channels are reset and DAC data 00h is output.) 3 N.C. Not connected 4 Vcc Power supply terminal 5 GND GND terminal Load terminal (When High level is input to LD terminal, value in 10-bit shift register is loaded into decoder and 8-bit latch.) R03DS0016EJ0100 Rev.1.00 2011.09.05 Page 2 of 7 New Product R2A20162NS/SA/SP Absolute Maximum Ratings Item (Ta= +25deg unless otherwise noted) Symbol Conditions Ratings Unit Supply voltage Vcc -0.3 to +6.5 V Input voltage Vin -0.3 to Vcc+0.3 <6.5 V Output voltage Vo -0.3 to Vcc+0.3 <6.5 V Buffer amplifier output current IAO Continuous -2.0 to +2.0 mA Power dissipation Pd Ta=85deg 270(NS) / 200(SA) / 272(SP) mW Ta>25deg Thermal derating factor K theta 6.75(NS) / 5.0(SA) / 6.8(SP) mW/deg Operating temperature Topr -30 to +85 deg Storage temperature Tstg -40 to +125 deg Electrical Characteristics Item ( Vcc= +5V +/-10%, GND=0V, Ta= -30 to +85deg unless otherwise noted) Symbol Test Conditions Vcc Supply voltage Supply current Icc Supply voltage rise-up time *1 Operating voltage of Internal resetting Limits Min. Typ. Max. Unit 2.7 5.0 5.5 V CLK = 1MHz operation, IAO=0µA, DATA: 6Ah (at maximum current) 0 0.7 2.5 mA SDA = SCL = GND, IAO=0µA 0 0.5 1.6 mA trVcc Vcc=0 to 2.7V 100 — — µs VccPOR Vcc=0 to 2.7V — 1.5 1.9 V tPOR Vcc < 0.1V 1 — — ms VIN= 0 to Vcc -10 — 10 µA Input low voltage IILK VIL 0 — 0.2Vcc V Input high voltage VIH 0.5Vcc 0.8Vcc — — Vcc Vcc V V Buffer amplifier output voltage range VAO IAO= +/-100µA 0.1 — Vcc-0.1 IAO= +/-500µA 0.2 — Vcc-0.2 Buffer amplifier output drive range IAO Upper side saturation voltage = 0.3V Lower side saturation voltage = 0.2V -1.0 — 1.0 mA -0.7 — 0.7 LSB -1.0 — 1.0 LSB -2.0 — 2.0 LSB -2.0 — 2.0 LSB — — 0.1 µF — 5.0 — ohm *1 Time period of re-power on (Power supply OFF ON) *1 Input leak current 4.0V < Vcc Vcc < 4.0V SDL SL SZERO SFULL Co Differential nonlinearity Nonlinearity Zero code error Full scale error Output capacitate load Buffer amplifier output impedance Vcc=5.12V (20mV/ LSB), without load (IAO= 0µA) Ro V *1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR). trVcc Vcc tPOR (equivalent to trVcc) VccPOR GND Internal Reset signal < 0.1V GND Resetting period R03DS0016EJ0100 Rev.1.00 2011.09.05 Resetting period Page 3 of 7 New Product R2A20162NS/SA/SP AC Characteristics Item ( Vcc = +5V +/-10deg, GND = 0V, Ta = -30 to +85deg unless otherwise noted ) Symbol Load high pulse width fCLK tCKH tCKL tCR tCF tDCH tCHD tCHL tLDC tLDH D/A output settling time tLDD Clock frequency Clock high pulse width Clock low pulse width Clock rise time Clock fall time Data setup time Data hold time Load setup time Load hold time Test Conditions Ta=25deg, CL<100pF, VAO: 0.54.5V, The time until the output becomes the final value of 1/2 LSB. Limits Unit Min. Typ. Max. - 1.0 10 MHz 40 - - ns 40 - - ns - - 200 ns - - 200 ns 5 - - ns 30 - - ns 40 - - ns 40 - - ns 40 - - ns - - 150 µs Timing Chart tCR tCKH tCF CLK tCKL DI tDCH tCHD tCHL tLDH tLDC LD tLDD D/A output (Note) Timing chart above is a schematic representation of the timing of each signal type. CLK signal input is High or Low regardless, LD signal High input is enabled. R03DS0016EJ0100 Rev.1.00 2011.09.05 Page 4 of 7 New Product R2A20162NS/SA/SP Digital Data Format Last LSB First MSB D0 D1 D2 D3 D4 D5 D6 D7 D8 DAC data D9 Channel Select data Channel select data D8 D9 Channel selection 0 0 Ao1 selected 1 0 Ao2 selected 0 1 Don’t care 1 1 Don’t care DAC data D0 D1 D2 D3 D4 D5 D6 D7 DAC output 0 0 0 0 0 0 0 0 Vcc/256 x 1 1 0 0 0 0 0 0 0 Vcc/256 x 2 0 1 0 0 0 0 0 0 Vcc/256 x 3 1 1 0 0 0 0 0 0 Vcc/256 x 4 : : : : : : : : : 0 1 1 1 1 1 1 1 Vcc/256 x 255 1 1 1 1 1 1 1 1 Vcc Data timing chart ( Model ) DI D9 D8 D7 D6 D5 D2 D1 D0 CLK Whether CLK input is “H” or “L”, High level input of LD signal is recognized. LD D/A output R03DS0016EJ0100 Rev.1.00 2011.09.05 Page 5 of 7 New Product R2A20162NS/SA/SP Precaution For use Supply voltage terminal (Vcc) is also used for D/A converter upper reference voltage setting. If ripple or spike is input this terminal, accuracy of D/A converter is down, So, when use this device, please connect capacitor among Vcc to GND for stable D/A conversion. This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when connect capacitor ( 0.1 µF Max ) among output to GND for every noise elimination. 1 Ao1 Analog output terminals 2 Ao2 3 N.C. 5V + 4 Vcc 10µF R2A20162NS / SA / SP Application Example LD 8 CLK 7 MCU DI 6 GND 5 Ordering Information Order part No. Package Name Package Code Package type No. Packing/Quantity R2A20162SP SOP-8 PRSP0008DE-C SP Embossed Taping/2,500 pcs. R2A20162SA TSSOP-8 RTSP0008JC-B SA Embossed Taping/3,000 pcs. R2A20162NS SON-8 PWSN0008KA-A NS Embossed Taping/5,000 pcs. Package Dimensions PWSN0008KA-A [NS] R03DS0016EJ0100 Rev.1.00 2011.09.05 Page 6 of 7 R2A20162NS/SA/SP New Product PRSP0008DE-C [SP] PTSP0008JC-B [SA] R03DS0016EJ0100 Rev.1.00 2011.09.05 Page 7 of 7 Notice 1. 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