FIN1215 / FIN1216 / FIN1217/ FIN1218 LVDS 21-Bit Serializers / De-Serializers Features Description The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low-Voltage TTL) data into three serial LVDS (Low-Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock, 21 bits of input LVTTL data are sampled and transmitted. Low Power Consumption 20MHz to 85MHz Shift Clock Support 50% Duty Cycle on the Clock Output of Receiver ±1V Common-mode Range ~1.2V Narrow Bus Reduces Cable Size and Cost High Throughput: 1.785Gbps Up to 595Mbps per Channel Internal PLL with No External Components Compatible with TIA/EIA-644 Specification Offered in 48-lead TSSOP Packages The FIN1216 and FIN1218 receives and converts the three serial LVDS data streams back into 21 bits of LVTTL data. Table 1 provides a matrix summary of the serializers and de-serializers available. For the FIN1217, at a transmit clock frequency of 85MHz, 21 bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Operating Part Number Temperature Range Eco Status Package Packing Method RoHS 48-Lead Thin Shrink Small Outline Package (TSSOP) Tape and Reel FIN1215MTDX FIN1216MTDX FIN1217MTDX -40 to + 85°C FIN1218MTDX (Preliminary) For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers September 2009 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Block Diagrams Figure 1. FIN1217 / FIN1215 Transmitter Functional Diagram Figure 2. FIN1218 / FIN1216 Receiver Functional Diagram Table 1. Serializers / De-Serializers Chip Matrix Part CLK Frequency LVTTL IN LVDS OUT FIN1215 66 21 3 FIN1216 66 FIN1217 85 21 3 FIN1218 85 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 LVDS IN LVTTL OUT Package 48-Lead TSSOP 3 21 48-Lead TSSOP 48-Lead TSSOP 3 21 48-Lead TSSOP www.fairchildsemi.com 2 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Transmitters Pin Configuration Figure 3. FIN1217 / FIN1215 (21:3 Transmitter) Pin Definitions Pin Names I/O Type # of Pins TxIn I 21 Description of Signals LVTTL Level Inputs TxCKLIn I 1 LVTTL Level Clock Input; the rising edge is for data strobe TxOut+ O 3 Positive LVDS Differential Data Output TxOut O 3 Negative LVDS Differential Data Output TxCLKOut+ O 1 Positive LVDS Differential Clock Output TxCLKOut- O 1 Negative LVDS Differential Clock Output /PwrDn I 1 LVTTL Level Power-Down Input; assertion (LOW) puts the outputs in highimpedance state PLL VCC I 1 Power Supply Pin for LVDS Outputs PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pins for LVDS Outputs LVDS GND I 3 Ground Pin for LVDS Outputs VCC I 4 Power Supply Pins for LVTTL Inputs GND I 5 Ground Pins for LVTTL Inputs NC © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 No Connect www.fairchildsemi.com 3 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Receivers Pin Configuration Figure 4. FIN1216 / FIN1218 (3:21 Receiver) Pin Definitions Pin Names I/O Type # of Pins Description of Signals RxIn I 3 Negative LVDS Differential Data Output RxIn+ I 3 Positive LVDS Differential Data Output RxCLKIn- I 1 Negative LVDS Differential Clock Output RxCLKIn+ I 1 Positive LVDS Differential Clock Output RxOut- O 21 LVTTL Level Data Outputs Goes HIGH for /PwrDn LOW RxCLKOut O 1 LVTTL Level Clock Output /PwrDn I 1 LVTTL Level Input; Refer to Transmitter and Receiver Power-up and Power-down Operation Truth Table PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pins for LVDS Inputs LVDS GND I 3 Ground Pin for LVDS Inputs VCC I 4 Power Supply Pins for LVTTL Outputs GND I 5 Ground Pins for LVTTL Outputs NC © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 No Connect www.fairchildsemi.com 4 Transmitter Inputs TxIn Outputs TxCLKIn PwrDn (1) TxOut± TxCLKOut± Active Active HIGH LOW / HIGH LOW / HIGH Active LOW / HIGH High Impedance HIGH LOW / HIGH Don’t Care Floating Active HIGH LOW LOW / HIGH Floating Floating HIGH LOW Don’t Care Don’t Care Don’t Care LOW High Impedance (2) (2) High Impedance Notes: 1. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V. 2. TxCLKOut± settles at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level LOW / HIGH / high-impedance. Receiver Inputs RxIn± RxCLKIn± Active Active Active Failsafe Condition Failsafe Condition (4) Failsafe Condition (4) Don’t Care Outputs (3) /PwrDn Don’t Care RxCLKOut HIGH LOW / HIGH LOW / HIGH (4) HIGH Last Valid State HIGH HIGH LOW / HIGH (4) HIGH Active Failsafe Condition RxOut HIGH LOW Last Valid State LOW (5) HIGH HIGH FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Truth Tables Notes: 3. The outputs of the transmitter or receiver remain in a high-impedance state until VCC reaches 2V. 4. Failsafe condition is defined as the input being terminated and un-driven, shorted, or open. 5. If RxCLKIn± is removed prior to the RxIn± date being removed, RxOut is the last valid state. If RxIn± data is removed prior to RxCLKIn± being removed, RxOut is HIGH. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Power Supply Voltage Min. Max. Unit -0.3 +4.6 V VTTL TTL/CMOS Input/Output Voltage -0.5 +4.6 V VLVDS LVDS Input/Output Voltage -0.3 +4.6 V IOSD LVDS Output Short-Circuit Current TSTG Storage Temperature Range Continuous +150 °C TJ Maximum Junction Temperature, Soldering 4 seconds +150 °C TL Lead Temperature +260 °C ESD Human Body Model, JESD22-A114 (1.5kΩ, 100pF) -65 LVDS I/O to Ground 10.0 All Pins (FIN1215, FIN1217) 6.5 kV Machine Model, JESD22-A115, 0Ω, 200pF FIN1215, FIN1217 Only >400 V Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Supply Voltage TA Operating Temperature VCCNPP Maximum Supply Noise Voltage (6) Min. Max. Unit 3.0 3.6 V -40 +85 °C 100 mVPP FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Absolute Maximum Ratings Note: 6. 100mV VCC noise should be tested for frequency at least up to 2MHz. All the specifications should be met under such a noise level. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com 6 Typical values are at TA=25°C and with VCC=3.3V; minimum and maximum are at over supply voltages and operating temperatures ranges, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Units Transmitter LVTTL Input Characteristics VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage GND 0.8 V VIK Input Clamp Voltage -0.79 -1.50 V IIN Input Current 1.8 10.0 Transmitter LVDS Output Characteristics VOD ΔVOD VOS ΔVOS IIK=-18mA VIN=0.4V to 4.6V VIN=GND -10.0 0 μA (7) 250 Output Differential Voltage VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage RL=100Ω, Figure 4 1.125 Offset Magnitude Change from Differential LOW-to-HIGH 1.250 450 mV 35 mV 1.375 V 25 mV IOS Short-Circuit Output Current VOUT=0V -3.5 -5.0 mA IOZ Disabled Output Leakage Current DO=0V to 4.6V, /PwrDn=0V ±1.0 ±10.0 μA Transmitter Supply Current ICCWT 21:3 Transmitter Power Supply Current (8, 9) for Worst-Case Pattern with Load RL=100Ω, Figure 7 33MHz 28.0 46.2 40MHz 29.0 51.7 65MHz 34.0 57.2 39.0 62.7 10.0 55.0 (10) 85MHz ICCPDT Powered-Down Supply Current /PwrDn=0.8V mA μA Notes: 7. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltages are referenced to ground unless otherwise specified (except ΔVOD and VOD). 8. The power supply current for both transmitter and receiver can be different with the number of active I/O channels. 9. The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. 10. FIN1217 only. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Transmitter DC Electrical Characteristics www.fairchildsemi.com 7 Typical values are at over supply voltages and operating temperatures ranges, unless otherwise specified. Symbol Parameter Conditions tTCP Transmit Clock Period tTCH Transmit Clock (TxCLKIn) HIGH Time tTCL Transmit Clock LOW Time tCLKT TxCLKIn Transition Time (Rising and Falling) tJIT TxCLKIn Cycle-to-Cycle Jitter tXIT TxIn Transition Time Figure 10 10% to 90% Figure 11 Min. Typ. Max. Units 11.76 T 50.00 ns 0.35 0.50 0.65 T 0.35 0.50 0.65 T 1.0 6.0 ns 3.0 ns 1.5 6.0 ns LVDS Transmitter Timing Characteristics tTLH Differential Output Rise Time (20% to 80%) tTHL Differential Output Fall Time (80% to 20%) tSTC TxIn Setup to TxCLNIn tHTC TxIn Holds to TCLKIn Figure 8 Figure 10 f=85MHz FIN1217 only 1.50 ns 1.50 ns 2.5 ns 0 ns (11) tTPDD Transmitter Power-Down Delay Figure 17 tTCCD Transmitter Clock Input to Clock Output Delay Figure 13 TA=25°C, VCC=3.3V Transmitter Output Data Jitter (f=40 MHz) 0.75 0.75 100 ns 2.8 5.5 6.8 ns (12) tTPPB0 Transmitter Output Pulse Position of Bit 0 -0.25 0 0.25 ns tTPPB1 Transmitter Output Pulse Position of Bit 1 a-0.25 a a+0.25 ns tTPPB2 Transmitter Output Pulse Position of Bit 2 2a-0.25 2a 2a+0.25 ns tTPPB3 Transmitter Output Pulse Position of Bit 3 3a-0.25 3a 3a+0.25 ns tTPPB4 Transmitter Output Pulse Position of Bit 4 4a-0.25 4a 4a+0.25 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.25 5a 5a+0.25 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.25 6a 6a+0.25 ns -0.2 0 0.2 ns Figure 20 1 a= f ×7 (12) FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Transmitter AC Electrical Characteristics Transmitter Output Data Jitter (f=65 MHz) tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 a-0.2 a a+0.2 ns tTPPB2 Transmitter Output Pulse Position of Bit 2 2a-0.2 2a 2a+0.2 ns tTPPB3 Transmitter Output Pulse Position of Bit 3 3a-0.2 3a 3a+0.2 ns tTPPB4 Transmitter Output Pulse Position of Bit 4 4a-0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.2 6a 6a+0.2 ns Figure 20 1 a= f ×7 Continued on following page… © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com 8 Symbol Parameter Conditions Transmitter Output Data Jitter (f=85 MHz, FIN1217 only) Min. Typ. Max. Units -0.2 0 0.2 ns (12) tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 a-0.2 a a+0.2 ns tTPPB2 Transmitter Output Pulse Position of Bit 2 2a-0.2 2a 2a+0.2 ns tTPPB3 Transmitter Output Pulse Position of Bit 3 3a-0.2 3a 3a+0.2 ns tTPPB4 Transmitter Output Pulse Position of Bit 4 4a-0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.2 6a 6a+0.2 ns tJCC Transmitter Clock Out Jitter, Cycle-to cycle Figure 23 tTPLLS Transmitter Phase Lock Loop Set Time Figure 20 1 a= f ×7 (13) f=40MHz 350 370 f=65MHz 210 230 f=85MHz FIN1217 only 110 150 Figure 15 (12) 10.0 ps ms Notes: 11. Outputs of all transmitters stay in 3-STATE until power reaches 2V. Clock and data output begins to toggle 10ms after VCC reaches 3V and /PwrDn pin is above 1.5V. 12. This output data pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit mapping difference (see Figure 19). Figure 20 shows the skew between the first data bit and clock output. A two-bit cycle delay is guaranteed when the MSB is output from transmitter. 13. This jitter specification is based on the assumption that PLL has a reference clock with cycle-to-cycle input jitter of less than 2ns. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Transmitter AC Electrical Characteristics (Continued) www.fairchildsemi.com 9 Typical values are at TA=25°C and with VCC=3.3V. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltages are referenced to ground unless otherwise specified (except ΔVOD and VOD). Minimum and maximum values are at over supply voltage and operating temperature ranges unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units LVTTL/CMOS DC Characteristics VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage GND 0.8 V VOH Output High Voltage IOH=-0.4mA VOL Output Low Voltage IOL=2mA VIK Input Clamp Voltage IIK=-18mA IIN Input Current VIN=0V to 4.6V IOFF Input/Output Power-Off Leakage Current VCC=0V, All LVTTL Inputs/Outputs 0V to 4.6V IOS Output Short-Circuit Current VOUT=0V 2.7 3.3 V 0.3 -10 -60 V -1.5 V 10 μA ±10 μA -120 μA 100 mV Receiver LVDS Input Characteristics VTH Differential Input Threshold HIGH Figure 6, Table 2 VTL Differential Input Threshold LOW Figure 6, Table 2 -100 VICM Input Common Mode Range Figure 6, Table 2 0.05 IIN Input Current mV 2.35 VIN=2.4V, VCC=3.6V or 0V ±10.0 VIN=0V, VCC=3.6V or 0V ±10.0 V μA Receiver Supply Current 33MHz ICCWR 3:21 Receiver Power Supply Current for Worst Case (14) Pattern with Load CL=8pF, Figure 7 40MHz 56 74 65MHz 75 102 92 125 NA 400 (15) 85MHz ICCPDR Powered Down Supply Current 66 /PwrDn=0.8V (RxOut stays LOW) FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Receiver DC Electrical Characteristics mA μA Notes: 14. The power supply current for the receiver can be different due to the number of active I/O channels. 15. 85MHz specification for FIN1218 only. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com 10 Values are at over supply voltages and operating temperatures, unless otherwise specified. Symbol tRCOL tRCOH Parameter Conditions RxCLKOut LOW Time RxCLKOut HIGH Time Figure 12 Rising Edge Strobe f=40MHz Min. Typ. Max. Units 10.0 11.0 ns 10.0 12.2 ns tRSRC RxOut Valid Prior to RxCLKOut 6.5 11.6 ns tRHRC RxOut Valid After RxCLKOut 6.0 11.6 ns tRCOP Receiver Clock Output (RxCLKOut) Period 15.0 T 50.0 ns tRCOL RxCLKOut LOW Time 5.0 7.8 9.0 ns tRCOH RxCLKOut HIGH Time 5.0 7.3 9.0 ns Figure 12 Rising Edge Strobe f=65MHz tRSRC RxOut Valid Prior to RxCLKOut 4.5 7.7 ns tRHRC RxOut Valid After RxCLKOut 4.0 8.4 ns tRCOP Receiver Clock Output (RxCLKOut) Period 11.76 T 50.00 ns tRCOL RxCLKOut LOW Time 4.0 6.3 6.0 ns tRCOH RxCLKOut HIGH Time 4.5 5.4 6.5 ns 3.5 6.3 ns 3.5 6.5 ns Figure 12 Rising Edge Strobe f=85MHz FIN1218 only tRSRC RxOut Valid Prior to RxCLKOut tRHRC RxOut Valid After RxCLKOut tROLH Output Rise Time (20% to 80%) tROHL Output Fall Time (80% to 20%) tRCCD Receiver Clock Input to Clock Output Delay Reference source not found.) Figure 18 CL=8pF, Figure 9 TA=25°C, VCC=3.3V (Error! Figure 14 3.5 2.2 5.0 ns 2.1 5.0 ns 6.9 7.5 ns tRPDD Receiver Power-Down Delay 1.0 ms tRSPB0 Receiver Input Strobe Position of Bit 0 1.00 2.15 ns tRSPB1 Receiver Input Strobe Position of Bit 1 4.5 5.8 ns tRSPB2 Receiver Input Strobe Position of Bit 2 8.10 9.15 ns tRSPB3 Receiver Input Strobe Position of Bit 3 11.6 12.6 ns tRSPB4 Receiver Input Strobe Position of Bit 4 15.1 16.3 ns tRSPB5 Receiver Input Strobe Position of Bit 5 18.8 19.9 ns tRSPB6 Receiver Input Strobe Position of Bit 6 22.5 23.6 ns Figure 21 f=40MHz FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Receiver AC Electrical Characteristics Continued on following page… © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com 11 Symbol Parameter tRSPB0 Receiver Input Strobe Position of Bit 0 tRSPB1 Receiver Input Strobe Position of Bit 1 tRSPB2 Receiver Input Strobe Position of Bit 2 tRSPB3 Receiver Input Strobe Position of Bit 3 tRSPB4 Max. Units 0.7 1.4 ns 2.9 3.6 ns 5.1 5.8 ns 7.3 8.0 ns Receiver Input Strobe Position of Bit 4 9.5 10.2 ns tRSPB5 Receiver Input Strobe Position of Bit 5 11.7 12.4 ns tRSPB6 Receiver Input Strobe Position of Bit 6 13.9 14.6 ns tRSPB0 Receiver Input Strobe Position of Bit 0 0.49 1.19 ns tRSPB1 Receiver Input Strobe Position of Bit 1 2.17 2.87 ns tRSPB2 Receiver Input Strobe Position of Bit 2 3.85 4.55 ns tRSPB3 Receiver Input Strobe Position of Bit 3 5.53 6.23 ns tRSPB4 Receiver Input Strobe Position of Bit 4 7.21 7.91 ns tRSPB5 Receiver Input Strobe Position of Bit 5 8.89 9.59 ns tRSPB6 Receiver Input Strobe Position of Bit 6 10.57 11.27 ns tRSKM tRPLLS RxIn Skew Margin (Error! Reference source not found.) Receiver Phase Lock Loop Set Time Conditions Figure 21 f=65MHz Figure 21 f=85MHz FIN1218 only Min. f=40MHz, Figure 22 490 f=65MHz, Figure 22 400 f=85MHz FIN1218 only Figure 22 252 Figure 16 Typ. ps 10.0 ms Notes: 16. Total channel latency from serializer to deserializer is (T + tTCCD) + (2•T + tRCCD). 17. Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Receiver AC Electrical Characteristics (Continued) www.fairchildsemi.com 12 Figure 5. Differential LVDS Output DC Test Circuit Notes: For all input pulses, tR or tF<=1ns. CL includes all probe and jig capacitance. Figure 6. Differential Receiver Voltage Definitions, Propagation Delay, and Transition Time Test Circuit Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) Resulting Differential Input Voltage (mV) Resulting Common Mode Input Voltage (V) VIA VIB VID VIC 1.25 1.15 100 1.20 1.15 1.25 -100 1.20 2.40 2.30 100 2.35 2.30 2.40 -100 2.35 0.10 0 100 0.05 0 0.10 -100 0.05 1.50 0.90 600 1.20 0.90 1.50 -600 1.20 2.40 1.80 600 2.10 1.80 2.40 -600 2.10 0.60 0 600 0.30 0 0.60 -600 0.30 © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Test Circuits www.fairchildsemi.com 13 Note: The worst-case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or failing edge data strobe. Figure 7. Worst-Case Test Pattern Figure 8. Transmitter LVDS Output Load and Transition Times Figure 9. Receiver LVTTL/CMOS Output Load and Transition Times Figure 10. FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers AC Loadings and Waveforms Transmitter Set-up/Hold and HIGH/LOW Times (Rising Edge Strobe) Figure 11. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Transmitter Input Clock Transition Time www.fairchildsemi.com 14 Figure 12. Figure 13. Transmitter Clock-In to Clock-Out Delay (Rising Edge Strobe) Figure 14. Receiver Clock-In to Clock-Out Delay (Rising Edge Strobe) Figure 15. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Receiver Set-up/Hold and HIGH/LOW Times FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers AC Loadings and Waveforms (Continued) Transmitter Phase-Lock-Loop Set Time www.fairchildsemi.com 15 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers AC Loadings and Waveforms (Continued) Figure 16. Receiver Phase Lock Loop Set Time Figure 17. Figure 18. Transmitter Power-down Delay Receiver Power-down Delay Note: This output date pulse position works for both transmitters with 21 TTL inputs, except the LVDS output bit mapping difference. Two-bit cycle delay is guaranteed with the MSB is output from transmitter. Figure 19. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Parallel LVTTL Inputs Mapped to Three Serial LVDS Outputs www.fairchildsemi.com 16 Figure 20. Transmitter Output Pulse Bit Position Figure 21. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers AC Loadings and Waveforms (Continued)] Receiver Strobe Bit Position www.fairchildsemi.com 17 Note: tRSKM is the budget for the cable skew and source clock skew plus Inter-Symbol Interference (ISI). The minimum and maximum pulse position values are based on the bit position of each of the seven bits within the LVDS data stream across PVT (Process, Voltage Supply, and Temperature). Figure 22. Receiver LVDS Input Skew Margin FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers AC Loadings and Waveforms (Continued) Note: This jitter pattern is used to test the jitter response (clock out) of the device over the power supply range with worst jitter ±ns (cycle-to-cycle) clock input. The specific test methodology is as follows: Switching input data TxIn0 to TxIn20 at 0.5MHz and the input clock is shifted to left -3ns and to the right +3ns when data is HIGH (by switching between CLK1 and CLK2 in Figure 11). The ±3ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst-case of clock edge jump (3ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise (VCC noise frequency <2MHz). Figure 23. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 Jitter Pattern www.fairchildsemi.com 18 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers Physical Dimensions Figure 24. 48-Lead Thin Shrink Small Outline Package (TSSOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com 19 FIN1215 / FIN1216 / FIN1217 — LVDS 21-Bit Serializers / De-Serializers © 2003 Fairchild Semiconductor Corporation FIN1215 / FIN1216 / FIN1217 • Rev. 1.0.3 www.fairchildsemi.com 20