Revised January 2004 FIN3385 • FIN3383 Low Voltage 28-Bit Flat Panel Display Link Serializers General Description Features The FIN3385 and FIN3383 transform 28 bit wide parallel LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock is transmitted in parallel with the data steam over a separate LVDS link. Every cycle of transmit clock 28 bits of input LVTTL data are sampled and transmitted. ■ Low power consumption These chipsets are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces. ■ Compatible with TIA/EIA-644 specification ■ 20 MHz to 85 MHz shift clock support ■ ±1V common-mode range around 1.2V ■ Narrow bus reduces cable size and cost ■ High throughput (up to 2.38 Gbps throughput) ■ Internal PLL with no external component ■ Devices are offered in 48- and 56-lead TSSOP packages Ordering Code: Package Number Package Description FIN3383MTD Order Number MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide FIN3385MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. TABLE 1. Display Panel Link Serializers/De-Serializers Chip Matrix Part CLK Frequency LVTTL IN LVDS OUT Package FIN3385 85 28 4 56 TSSOP FIN3383 66 28 4 56 TSSOP Block Diagram Functional Diagram for FIN3385 and FIN3383 © 2004 Fairchild Semiconductor Corporation DS500864 www.fairchildsemi.com FIN3385 • FIN3383 Low Voltage 28-Bit Flat Panel Display Link Serializers October 2003 FIN3385 • FIN3383 Pin Descriptions Pin Names I/O Type Number of Pins TxIn I 28/21 TxCLKIn I 1 Description of Signals LVTTL Level Inputs LVTTL Level Clock Input The rising edge is for data strobe. TxOut+ O 4/3 Positive LVDS Differential Data Output TxOut− O 4/3 Negative LVDS Differential Data Output TxCLKOut+ O 1 Positive LVDS Differential Clock Output TxCLKOut− O 1 Negative LVDS Differential Clock Output R_FB I 1 Rising Edge Clock (HIGH), Falling Edge Clock (LOW) PwrDn I 1 LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in High Impedance state. PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Outputs LVDS GND I 3 Ground Pins for LVDS Outputs VCC I 3 Power Supply Pins for LVTTL Inputs GND I 5 Ground pins for LVTTL Inputs NC No Connect Connection Diagram Truth Table Inputs Outputs TxIn TxCLKIn PwrDn (Note 1) TxOut± Active Active H L/H L/H Active L/H/Z H L/H X (Note 2) F Active H L L/H F F H L X (Note 2) X X L Z Z TxCLKOut± H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance F = Floating Note 1: The outputs of the transmitter or receiver will remain in a High Impedance state until VCC reaches 2V. Note 2: TxCLKOut± will settle at a free running frequency when the part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic level (L/H/Z). www.fairchildsemi.com 2 Recommended Operating Conditions Power Supply Voltage (VCC) -0.3V to +4.6V TTL/CMOS Input/Output Voltage −0.5V to +4.6V Supply Voltage (VCC) LVDS Input/Output Voltage -0.3V to +4.6V Operating Temperature (TA)(Note 3) LVDS Output Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Continuous Maximum Supply Noise Voltage −65°C to +150°C Maximum Junction Temperature (TJ) (VCCNPP) 150°C Lead Temperature (TL) ESD Rating (HBM, 1.5 kΩ, 100 pF) >10.0 kV I/O to GND >6.5 kV All Pins ESD Rating (MM, 0Ω, 200 pF) 100 mVP-P (Note 4) Note 3: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications. 260°C (Soldering, 4 seconds) 3.0V to 3.6V −10°C to +70°C Note 4: 100mV VCC noise should be tested for frequency at least up to 2 MHz. All the specification below should be met under such a noise. >400V DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 5) Symbol Parameter Test Conditions Min Typ Max Units V Transmitter LVTTL Input Characteristics VIH Input High Voltage 2.0 VCC VIL Input Low Voltage GND 0.8 V VIK Input Clamp Voltage −0.79 −1.5 V IIN Input Current 1.8 10.0 IIK = −18 mA VIN = 0.4V to 4.6V VIN = GND −10.0 0 250 TBD µA Transmitter LVDS Output Characteristics (Note 6) VOD Output Differential Voltage ∆VOD VOD Magnitude Change from Differential LOW-to-HIGH VOS Offset Voltage ∆VOS Offset Magnitude Change from Differential LOW-to-HIGH IOS Short Circuit Output Current VOUT = 0V −3.5 −5.0 mA IOZ Disabled Output Leakage Current DO = 0V to 4.6V, PwrDn = 0V ±1.0 ±10.0 µA RL = 100 Ω, See Figure 1 1.125 1.25 450 mV 35.0 mV 1.375 V mV Transmitter Supply Current ICCWT 28:4 Transmitter Power Supply Current 32.5 MHz 31.0 49.5 for Worst Case Pattern (With Load) RL = 100 Ω, 40.0 MHz 32.0 55.0 (Note 7) See Figure 2 66.0 MHz 37.0 60.5 85.0 MHz 42.0 66.0 10.0 55.0 32.5 MHz 29.0 41.8 ICCPDT Powered Down Supply Current ICCGT 28:4 Transmitter Supply Current for 16 Grayscale (Note 7) PwrDn = 0.8V See Figure 11 40.0 MHz 30.0 44.0 (Note 8) 65.0 MHz 35.0 49.5 85.0 MHz 39.0 55.0 mA µA mA Note 5: All Typical values are at TA = 25°C and with VCC = 3.3V. Note 6: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except ∆VOD and VOD). Note 7: The power supply current for both transmitter and receiver can be different with the number of active I/O channels. Note 8: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. 3 www.fairchildsemi.com FIN3385 • FIN3383 Absolute Maximum Ratings(Note 3) FIN3385 • FIN3383 AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter tTCP Transmit Clock Period tTCH Transmit Clock (TxCLKIn) HIGH Time tTCL Transmit Clock Low Time tCLKT TxCLKIn Transition Time (Rising and Failing) tJIT TxCLKIn Cycle-to-Cycle Jitter tXIT TxIn Transition Time Test Conditions See Figure 4 (10% to 90%) See Figure 5 Min Typ Max Units 11.76 T 50.0 ns 0.35 0.5 0.65 T 0.35 0.5 0.65 T 1.0 1.5 6.0 ns 3.0 ns 6.0 ns LVDS Transmitter Timing Characteristics tTLH Differential Output Rise Time (20% to 80%) tTHL Differential Output Fall Time (80% to 20%) See Figure 3 0.75 1.5 ns 0.75 1.5 ns tSTC TxIn Setup to TxCLNIn tHTC TxIn Holds to TCLKIn tTPDD Transmitter Power-Down Delay See Figure 7, (Note 9) 100 tTCCD Transmitter Clock Input to Clock Output Delay (TA = 25°C and with VCC = 3.3V) 5.5 Transmitter Clock Input to Clock Output Delay See Figure 6 2.8 −0.25 0 0.25 ns See Figure 9 a−0.25 a a+0.25 ns 1 2a−0.25 2a 2a+0.25 ns fx7 3a−0.25 3a 3a+0.25 ns See Figure 4 (f = 85 MHz) 2.5 ns 0 ns 6.8 ns ns Transmitter Output Data Jitter (f = 40 MHz) (Note 10) tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 tTPPB2 Transmitter Output Pulse Position of Bit 2 tTPPB3 Transmitter Output Pulse Position of Bit 3 tTPPB4 Transmitter Output Pulse Position of Bit 4 4a−0.25 4a 4a+0.25 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a−0.25 5a 5a+0.25 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a−0.25 6a 6a+0.25 ns a= Transmitter Output Data Jitter (f = 65 MHz) (Note 10) −0.2 0 0.2 ns a−0.2 a a+0.2 ns 1 2a−0.2 2a 2a+0.2 ns fx7 3a−0.2 3a 3a+0.2 ns Transmitter Output Pulse Position of Bit 4 4a−0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a−0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a−0.2 6a 6a+0.2 ns tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 tTPPB2 Transmitter Output Pulse Position of Bit 2 tTPPB3 Transmitter Output Pulse Position of Bit 3 tTPPB4 See Figure 9 a= Transmitter Output Data Jitter (f = 85 MHz) (Note 10) −0.2 0 0.2 ns a−0.2 a a+0.2 ns 1 2a−0.2 2a 2a+0.2 ns fx7 3a−0.2 3a 3a+0.2 ns Transmitter Output Pulse Position of Bit 4 4a−0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a−0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a−0.2 6a 6a+0.2 ns tJCC FIN3385 Transmitter Clock Out Jitter f = 40 MHz 350 370 (Cycle-to-Cycle) f = 65 MHz 210 230 See Figure 10 f = 85 MHz 110 150 Transmitter Phase Lock Loop Set Time (Note 11) See Figure 12, (Note 10) tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 tTPPB2 Transmitter Output Pulse Position of Bit 2 tTPPB3 Transmitter Output Pulse Position of Bit 3 tTPPB4 tTPLLS See Figure 9 a= 10.0 ps ms Note 9: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and Power-Down pin is above 1.5V. Note 10: This output data pulse position works for TTL inputs except the LVDS output bit mapping difference (see Figure 8). Figure 9 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter. Note 11: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns. www.fairchildsemi.com 4 FIN3385 • FIN3383 FIGURE 1. Differential LVDS Output DC Test Circuit AC Loading and Waveforms Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or falling edge data strobe. FIGURE 2. “Worst Case” Test Pattern FIGURE 3. Transmitter LVDS Output Load and Transition Times FIGURE 4. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe) 5 www.fairchildsemi.com FIN3385 • FIN3383 AC Loading and Waveforms (Continued) FIGURE 5. Transmitter Input Clock Transition Time FIGURE 6. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe) FIGURE 7. Transmitter Power-Down Delay Note: The information in this diagram shows the relationship between clock out and the first data bit. A 2-bit cycle delay is guaranteed when the MSB is output from the transmitter. FIGURE 8. 28 Parallel LVTTL Inputs Mapped to 4 Serial LVDS Outputs www.fairchildsemi.com 6 FIN3385 • FIN3383 AC Loading and Waveforms (Continued) FIGURE 9. Transmitter Output Pulse Bit Position Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter ±3ns (cycle-to-cycle) clock input. The specific test methodology is as follows: • Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left −3ns and to the right +3ns when data is HIGH. • The ±3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise (VCC noise frequency <2 MHz). FIGURE 10. Timing Diagram of Transmitter Clock Input with Jitter 7 www.fairchildsemi.com FIN3385 • FIN3383 AC Loading and Waveforms (Continued) Note: The 16-grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. FIGURE 11. “16 Grayscale” Test Pattern FIGURE 12. Transmitter Phase Lock Loop Time www.fairchildsemi.com 8 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com FIN3385 • FIN3383 Low Voltage 28-Bit Flat Panel Display Link Serializers Physical Dimensions inches (millimeters) unless otherwise noted