FSA831 — USB2.0 High-Speed (480Mbps) Charger Detection with Isolation Switch Features Description USB Battery Charging Rev. 1.2 Supports Data Contact Detect (DCD) Dead Battery Provision (DBP) with 30-Minute Timer USB Detection Isolation Switch Closes for Charging Downstream Port (CDP) Standard Downstream Port (SDP) Switch Type 28V Over-Voltage Tolerance -2V Under-Voltage Tolerance VBUS 10-Lead MicroPak™ 1.6 x 2.1mm, 0.5mm Pitch Package Ordering Information FSA831L10X Applications MP3, Mobile Internet Device (MID), Cell Phone, PDA, Digital Camera, Notebook and Netbook The FSA831 is a charger-detection IC with an integrated isolation switch for use with a micro/mini USB port. The FSA831 detects battery chargers and is compliant with USB Battery Charging Specification, Rev 1.2 (BC1.2). The algorithm incorporates Data Contact Detection (DCD), which ensures that the shorter, inner pins of the USB connector are making contact prior to continuing with battery charger detection. The device determines if a Dedicated Charging Port (DCP), Charging Downstream Port (CDP), or a typical PC host, called a Standard Downstream Port (SDP), is connected. If a charger is detected, the FSA831 determines whether the charger is a DCP or CDP. For SDP and CDP detection, an internal isolation switch is closed to connect the D+/D- lines of the USB cable to the resident USB transceiver within the portable device. The FSA831 conforms to all the constraints for the Dead Battery Provision (DBP) within the BC1.2 specification, including a 30-minute timer that cannot exceed 45 minutes, per BC1.2. Related Resources For samples and questions, please contact: [email protected]. Typical Application FSA831 CHG_AL_N System on Chip (SoC) GOOD_BAT DM_HOST USB PHY Regulator and Switch Control USB Port OVT V BUS DM_CON DP_CON DP_HOST V BUS_IN DD+ SW_OPEN Charger Detect Li+ Bat Charger ID GND GND CHG_DET Figure 1. Mobile Phone Example © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com FSA831 — USB2.0 High-Speed (480Mbps) Charger Detector with Isolation Switch July 2013 Pin Configurations CHG_DET 10 9 VBUS 2 8 DM_CON DP_HOST 3 7 DP_CON CHG_AL_N 4 6 GND SW_OPEN 1 DM_HOST Control 5 GOOD_BAT Figure 2. Pin Assignments (Top View) Pin Descriptions Name Pin # Description USB Interface DP_HOST 3 D+ signal connected to the resident USB transceiver on the phone DM_HOST 2 D- signal connected to the resident USB transceiver on the phone VBUS 9 Input voltage supply pin to be connected to the VBUS pin of the USB connector Connector Interface GND 6 Ground DP_CON 7 Connected to the USB connector D+ pin DM_CON 8 Connected to the USB connector D- pin CHG_DET 10 CMOS push/pull output connected to charger IC for indicating if a charger has been detected (LOW=charger not detected, HIGH=DCP or CDP charger has been detected). SW_OPEN 1 Open-drain output pin; requires pull-up resistor to I/O voltage supply (LOW=switch closed, Hi-Z=switch open). CHG_AL_N 4 CMOS open-drain output pin (LOW=VBUS is valid and charge is allowed to be drawn from VBUS, Hi-Z=VBUS is not at a valid voltage). 5 Input that indicates if the battery is a good battery or a dead battery (LOW=dead battery, HIGH=good battery). Status Outputs Input Pin GOOD_BAT © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 2 Table 1. Functionality Device Detected GOOD_ SW_ CHG_ CHG_ DP_HOST DM_HOST DP_CON DM_CON BAT OPEN AL_N DET DCP X Hi-Z LOW HIGH Hi-Z Hi-Z VDP_SRC Hi-Z(1) CDP HIGH LOW LOW HIGH DP_CON DM_CON DP_HOST DM_HOST CDP LOW Hi-Z LOW HIGH Hi-Z Hi-Z VDP_SRC Hi-Z SDP(2) HIGH LOW LOW LOW DP_CON DM_CON DP_HOST DM_HOST SDP(2) LOW Hi-Z LOW LOW Hi-Z Hi-Z VDP_SRC Hi-Z SDP, CDP, or DCP plugged in and after 30-minute timer expires LOW Hi-Z Hi-Z LOW Hi-Z Hi-Z Hi-Z Hi-Z VBUS < VBUS valid to VBUS > VBUS valid operation prior to completing detection of SDP, CDP, or DCP. Upon detection, all outputs switch as in rows above. X Hi-Z Hi-Z Hi-Z to LOW Hi-Z Hi-Z Hi-Z Hi-Z Notes: 1. Hi-Z is the internal state of DM_CON. Since a DCP has been detected, DM_CON is shorted to DP_CON externally and DM_CON is shorted to VDP_SRC. 2. Proprietary chargers that leave DP_CON and DM_CON floating are detected as SDP. Proprietary chargers that force DP_CON=2V and DM_CON=2.7V (or any other voltages) can be detected as CDP, DCP or SDP depending on the resistances of the resistor dividers on DP_CON and DM_CON used to create the voltages on those pins. Functional Description If a charger does not have a D+ pin on the USB connector DP_CON and DM_CON pins to pass through the switch to DP_HOST and DM_HOST, respectively. Since voltages on the PS/2 port can go as high as the VBUS voltage, the DP_HOST and DM_HOST pins can be pulled up to VBUS. The USB PHY connected to DP_HOST and DM_HOST must be equipped to handle these higher voltages. If the D+ pin is not shorted to D- pin on the connector, CHG_AL_N Output and Output Timing If D+ is pulled up to a supply CHG_AL_N output indicates that charge is allowed to be drawn from VBUS when CHG_AL_N is LOW. When FSA831 first powers up and prior to detection, the CHG_AL_N pin can follow VBUS up to 28V, which is the absolute maximum VBUS voltage allowed. Whenever VBUS is at GND, the FSA831 is completely off and the switches and all I/Os are in the Hi-Z state. When VBUS climbs above the valid VBUS threshold, detection occurs automatically and CHG_DET, SW_OPEN, and CHG_AL_N all simultaneously switch to the states indicated in Table 1 if GOOD_BAT is HIGH (see Dead Battery Provision description for GOOD_BAT = LOW). Data Contact Detect (DCD) DCD relies on the D+ and D- lines being present. DCD waits until the internal timeout (450ms typical) has expired in the following cases: If D+ does not have a sufficient path to ground to defeat a pull-up IDP_SRC (10µA typical) current source. The FSA831 proceeds with charger detection even though it is unlikely a charger is present. If there is no charger, the algorithm reports an SDP and closes the switch. If a device is pulling D+ HIGH, this voltage presents itself to the USB transceiver or Physical Layer Interface (PHY) block within a System on Chip (SoC) after the switch is closed If the DCD timeout was insufficient and the PHY block is so equipped, DCD and the charging algorithm can be repeated in the PHY block. The stipulation is that the total time from VBUS valid to USB transceiver connection with a 1.5kΩ pullup to 3.3V must be one (1) second, per USB 2.0 standards (USB 2.0 connect timing), provided the portable device does not have a dead battery. Dead Battery Provision BC1.2 and USB 2.0 allow a portable device (defined as a device with a battery) with a dead battery to take a maximum of 100mA from the USB VBUS line for a maximum of 45 minutes as long as the portable device forces the D+ line to VDP_SRC (0.6V typical). FSA831 starts detection when VBUS crosses the VBUSVLD threshold and, if it detects a CDP or SDP and GOOD_BAT is HIGH, automatically closes the switch and does not force the DP_CON pin to VDP_SRC. A typical PS/2 port (old PC mouse / keyboard port) has a resistive pull-up to VBUS. This can cause the DCD to exceed the maximum wait time (tDCD_TIMEOUT) and proceed to charger detection. The likely path through charger detection is classifying the PS/2 port as an SDP port. This results in closing the USB switches, which causes the voltage on the © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 Once the charger detection is completed, the FSA831 starts a 30-minute timer and forces the DP_CON pin to VDP_SRC until the timer elapses. During the 30 minute period, if www.fairchildsemi.com 3 GOOD_BAT is LOW, VDP_SRC is applied to DP_CON and the D+/D- switches are opened, If GOOD_BAT is HIGH, VDP_SRC is not applied to DP_CON and the D+/D- switches are closed, If GOOD_BAT is LOW when 30 minute timer expires; regardless of whether an SDP, CDP, or DCP was previously detected; the FSA831 removes VDP_SRC from DP_CON and forces CHG_DET LOW and CHG_AL_N to HiZ (SW_OPEN remains Hi-Z) To exit this fault condition, remove VBUS, wait for all the VBUS Printed Circuit Board (PCB) capacitance to discharge, and re-apply VBUS. Table 1 provides the functionality of the pins when the timer expires. SDP (depending on the resistances of the resistor dividers on DP_CON and DM_CON) and used to create the HIGH voltages on those pins. Any charger that lets both DP_CON and DM_CON signals float is detected as an SDP and CHG_DET stays de-asserted. In cases where the proprietary charger is detected as an SDP or CDP, since the switches are closed and access is made from the USB connector D+ and D- lines to the USB PHY block; the chargers can be detected within the PHY if so equipped Ground Drops When a DCP is detected, VDP_SRC is forced on DP_CON provided GOOD_BAT is HIGH or if GOOD_BAT is LOW and the DBP timer has not expired. For current up to 1.5A flowing into the VBUS and GND lines of the USB cable, this can translate to substantial ground drops that lift the ground of the portable device. This drop adds to the voltage at the DP_CON pin as seen from the DCP D+ pin. For the maximum ground drop of 375mV specified in the BC1.2 specification and for the maximum VDP_SRC of 0.7V, the voltage as seen by the DCP would be 1.075V. Smart DCPs that rely on this voltage detection to determine attach and detach detection need to take this into account. When GOOD_BAT is HIGH and the battery is removed from the portable device while VBUS is valid, bringing GOOD_BAT LOW; the FSA831 opens the isolation switches on DP_CON and DM_CON and forces the DP_CON pin to VDP_SRC. In this scenario, the timer generally expires because the SoC does not have a supply to bring GOOD_BAT HIGH unless the battery that was removed is re-inserted within 30 minutes from when the USB plug is inserted. If an SDP or CDP is inserted with GOOD_BAT HIGH during the 30-minute timer, then GOOD_BAT changes to LOW; SW_OPEN changes to Hi-Z and the counter continues counting until the 30 minutes expires. If GOOD_BAT then returns to HIGH, SW_OPEN changes to LOW and finishes out the 30-minute time. VBUS Tolerance When VBUS rises, an internal Power On Reset (POR) detects this voltage and prepares the FSA831 for charger detection. GOOD_BAT has an internal pull-down resistor to ensure it is LOW when the SoC is powered down. This input is designed to have very low thresholds to interface with low-voltage SoCs driven with 1.2V supplies. VBUS voltages up to 28V can be tolerated by the VBUS pin. VBUS can tolerate voltages up to -2V for cases where a charger is plugged in backwards. Proprietary Chargers Detection Flow Only legitimate USB chargers that force VDM_SRC (0.6V typical) on DM_CON when VDP_SRC is applied to DP_CON are detected by the FSA831 and cause CHG_DET signal to be asserted. Any charger that forces a HIGH on both DP_CON and DM_CON can be detected as CDP, DCP, or The flow diagram in Figure 3 shows how the FSA831 achieves battery charger detection consistent with BC1.2. © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 4 Check VBUS Else VBUS>VBUSVLD Start Timer Enable DCD Else D+ < VLGC for tDCD_DBNC OR tDCD_TIMEOUT Primary detection D+ = VDP_SRC, Wait TVDPSRC_ON D- > VDAT_REF AND D- < VLGC If VBUS<VBUSVLD FSA831 powers down D+ is the DP_CON pin D- is the DM_CON pin When SW_OPEN=Hi-Z, switches are open When SW_OPEN=L, switches are closed ( D- < VDAT_REF OR D- > VLGC) Secondary Detection D- = VDM_SRC, Wait TVDMSRC_ON D+ > VDAT_REF AND < VLGC D+ < VDAT_REF, OR > VLGC D+ = VDP_SRC DCP IDCP CDP ICDP CHG_AL_N=L, CHG_DET=H SW_OPEN=Hi-Z SDP IUNIT CHG_AL_N=L, CHG_DET=H CHG_AL_N=L, CHG_DET=L GOOD_BAT=H ~tDBP SW_OPEN=L, Remove VDP_SRC on D+ GOOD_BAT=L tDBP ~tDBP SW_OPEN=Hi-Z D+=VDP_SRC GOOD_BAT=H GOOD_BAT=L ~tDBP tDBP SW_OPEN=Hi-Z, CHG_AL_N=Hi-Z, CHG_DET=L, Remove VDP_SRC on D+ tDBP Wait for VBUS < VBUSVLD Figure 3. Battery Charger Detection © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 5 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VBUS Voltage from USB Connector VSW USB Switch I/O Voltage (DP_CON, DM_CON, DP_HOST, DM_HOST) Min. Max. Unit -2 28 V -0.5 6.0 V ISW USB Switch Current (DP_CON to DP_HOST, DM_CON to DM_HOST) -30 +30 mA VI/O Voltage from GOOD_BAT, CHG_AL_N, CHG_DET and SW_OPEN I/Os -0.5 6.0 V VCA Voltage from CHG_AL_N Output -0.5 28.0 V II/O CHG_AL_N, CHG_DET and SW_OPEN Outputs Sink/Source Current -5 +5 mA Storage Temperature Range -65 +150 C TJ Maximum Junction Temperature +150 C TL Lead Temperature (Soldering, 10 Seconds) +260 C TSTG Air Gap 15 Contact 8 Human Body Model, JEDEC JESD22-A114 All Pins 6 Charged Device Model, JEDEC JESD22-C101 All Pins 2 IEC 61000-4-2 System ESD USB Pins (DP_CON, DM_CON, VBUS) kV Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VBUS VBUS Input HIGH Voltage 4 6 V VSW Switch I/O Voltage for USB Path 0 3.6 V -40 +85 ºC TA Operating Temperature © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 6 DC Electrical Characteristics Unless otherwise indicated, VBUS=4V to 6V and TA=-40 to +85°C. Typical values are at TA=25ºC unless otherwise specified. Symbol Parameter Condition Min. Typ. Max. Unit Status Outputs VOHCD Output HIGH Voltage (CHG_DET) IOH=-2mA VOL Output LOW Voltage (CHG_DET, CHG_AL_N, SW_OPEN) IOL=2mA tDIFF Skew Between Any Output (CHG_DET, I =±2mA, CHG_AL_N=20kΩ to 5V, CHG_AL_N, SW_OPEN) Switching Relative to I/O SW_OPEN=10kΩ to 1.8V the Other Outputs Switching 2.0 V 0.4 V 100 ns 4.0 V VBUS Pin VBUSVLD VBUS Valid Detection Threshold(1) IBUSIN IVBUSACT tOUT 0.8 VBUS Input Leakage VBUS=0V to 0.8V 10 µA VBUS Active Mode Average Current USB Path Active, USB Switch Closed After Charger Detection 400 µA DP_CON pulled down to GND, 15kΩ, Time from VBUS Valid Asserted to CHG_DET, all voltages forced on VBUS, DP_CON, CHG_AL_N and SW_OPEN Outputs Valid DM_CON and GND simultaneously 250 ms 10 µA 9.0 Ω 0.5 V Switch Characteristics IOFF RONUSB Power Off Leakage Current USB Path VBUS=0V, VSW=0V or 3.6V, Figure 5 High-Speed USB Range Switch On Resistance(1) VDP_CON / VDM_CON=0V, 0.4V; ION=8mA; Figure 4; VBUS=4V to 6V 6.5 Control Input VIH Input HIGH Voltage (GOOD_BAT) VIL Input LOW Voltage (GOOD_BAT) 1.1 V RPD Pull Down Resistance (GOOD_BAT) IIN Input Leakage Current (GOOD_BAT) VBUS=5V, GOOD_BAT=0V to 4.4V 10 µA OFF State Leakage Current (GOOD_BAT) VBUS=0V, GOOD_BAT=0V to 4.4V 10 µA IIOFF 1 15 MΩ tDBP Dead Battery Provision (DBP) Timer 45 min tGB Time from GOOD_BAT Asserted to SW_OPEN De-Asserted, Switches Closed and Meet the RONUSB Specification 30 30 ms tDB Time from GOOD_BAT De-asserted to SW_OPEN Asserted, Switches Opened 65 ms Battery Charger Detection Parameters from BC1.2 Specification VDAT_REF Data Detect Voltage 0.25 0.40 V VDM_SRC D- Source Voltage(2) 0.5 0.7 V VDP_SRC D+ Source Voltage(2) 0.5 0.7 V Logic Threshold 0.8 2.0 V IDM_SINK D- Sink Current 25 175 µA IDP_SINK D+ Sink Current 25 175 µA IDP_SRC Data Contact Detect Current Source 7 13 µA VLGC tDCD_DBNC Data Contact Detect Debounce 10 tDCD_TOUT 300 Time for DCD to Timeout ms 450 900 ms tVDPSRC_ON D+ Voltage Source On Time 40 ms tVDMSRC_ON D- Voltage Source On Time 40 ms Notes: 1. Guaranteed by characterization; not production tested. 2. The voltage source, VDP_SRC / VDM_SRC, is able to source at least 250µA when the output voltage is in the specified range. This voltage source should not pull DP_CON / DM_CON below 2.2V when DP_CON / DM_CON is pulled to a voltage of 3.0V minimum or 3.6V maximum with a resistance of 900Ω minimum or 1575Ω maximum. © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 7 AC Electrical Characteristics Unless otherwise specified, values are at TA=-40 to +85°C; all typical values are for VCC=3.3V at TA=25°C. Symbol Parameter Condition Min. Typ. Max. Xtalk Active Channel Crosstalk, DP_CON to DM_CON(3) f=1MHz, RT=50Ω, CL=0pF -78 f=240MHz, RT=50Ω, CL=0pF -36 OIRR Off Isolation Rejection Ratio, DM_HOST to DM_CON, DP_HOST to DP_CON(3) f=1MHz, RT=50Ω, CL=0pF -84 f=240MHz, RT=50Ω, CL=0pF -34 Unit Figure dB Figure 7 dB Figure 6 Note: 3. Guaranteed by characterization; not production tested. Capacitance Unless otherwise specified, values are at TA=-40 to +85°C. Symbol Parameter Condition COFF (4) DP_CON, DM_CON Off Capacitance CON DP_CON, DM_CON On Capacitance(4) Typical Unit Figure VBIAS=0.2V, f=1MHz 3.9 pF Figure 8 VBIAS=0.2V, f=1MHz 7.2 pF Figure 9 Note: 4. Guaranteed by characterization; not production tested. © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 8 Test Diagrams VON I A(OFF) NC nBn A nA V IN GND Select V Sel = RON = VON / ION V IN I ON Select GND VSel = 0 or Vcc GND 0 orVcc **Each switch port is tested separately. Figure 4. On Resistance Figure 5. Off Leakage Network Analyzer NC RS Network Analyzer RS VS1, S2, S3 RS and RT are functions of the application environment (see AC/DC tables). GND RS and RT are functions of the application environment (see AC tables for values). Capacitance Meter nSn VSel = RT GND CROSSTALK = 20 Log (VOUT / VIN ) Figure 7. Active Channel Crosstalk nBn 0 or Vcc nBn nSn V Sel = f = 1MHz 0 orV cc nBn nBn Figure 8. Channel Off Capacitance © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 VOUT GND Figure 6. Channel Off Isolation f = 1MHz GND RT Off-Isolation = 20 Log (VOUT / VIN ) Capacitance Meter RT GND VOUT GND VS GND GND GND GND VIN VS GND RT VSel GND Figure 9. Channel On Capacitance www.fairchildsemi.com 9 Physical Dimensions 0.10 C 2.10 2X A 1.62 B KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED (0.11) 1.12 1.60 PIN1 IDENT IS 2X LONGER THAN OTHER LINES 0.56 0.10 C 2X TOP VIEW (0.35) 10X (0.25) 10X 0.50 RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C 0.05 C 0.05 0.00 C (0.20) 0.35 0.25 SIDE VIEW D 0.65 0.55 DETAIL A 0.35 0.25 4 1 0.35 0.25 DETAIL A 2X SCALE 0.56 5 10 (0.29) (0.15) (0.36) 6 9 0.50 0.25 9X 0.15 1.62 0.35 9X 0.25 0.10 0.05 C A B C ALL FEATURES BOTTOM VIEW NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD . B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. E. DRAWING FILENAME: MKT-MAC10Arev5. Figure 10. 10-Lead, MicroPak™ Part Number Top Mark Operating Temperature Range Package Description Packing Method FSA831L10X KY -40 to 85°C 10-Lead, MicroPak™ 1.6 x 2.1mm, 0.5mm Pitch Tape & Reel Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 10 © 2011 Fairchild Semiconductor Corporation FSA831 • Rev. 1.0.2 www.fairchildsemi.com 11