FAB1200 Class-G Ground-Referenced Headphone Amplifier with Integrated Buck Converter Features Description Class-G Headphone Amplifier Uses Multiple Rails for High Efficiency Integrated Inductive Buck Converter for Direct Battery Connection Differential Analog Inputs The FAB1200 is a stereo class-G headphone amplifier. A charge pump generates a negative supply voltage that allows its output to be ground centered. An integrated buck regulator adjusts the voltage supplies between two different levels based on the output signal level to reduce power consumption. Ground-Referenced Output I2C Controls Capable of Driving 16 Ω to 600 Ω Loads and Line Level Inputs VBATT 2.2µF Ground-Sense Input Eliminates Ground-Loop Noise AVDD SW HPVDD CPN Buck Converter 32-Step Volume Control Charge Pump CPP 2.2µF HPVSS INR- Channel-Independent Shutdown Control and Short-Circuit Protection 2.2µH 2.2µF 2.2µF 1µF OUTR INR+ Volume Control and Level Detector 1µF 16-Bump, 0.4 mm Pitch, 1.56 mm x 1.56 mm WLCSP Package INL- Class G Headphone Amplifiers OUTL 1µF SGND INL+ 1µF Applications SCL I2C SDA Cellular Handsets MP3 and Portable Media Players Personal Navigation Devices AGND Figure 1. Typical Application Circuit Ordering Information Part Number Operating Temperature Range FAB1200UCX -40 to +85°C © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 Package 16-Bump, 0.4 mm Pitch, 1,56 mm x 1.56 mm, Wafer-Level Chip-Scale Package (WLCSP) Packing Method 4000 Units on Tape & Reel www.fairchildsemi.com FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter June 2013 1 2 3 4 A SW AVDD OUTL INL- B AGND CPP HPVDD INL+ C CPN HPVSS SGND INR+ D SDA SCL OUTR INR- Figure 2. 16-Bump, 0.4 mm Pitch WLCSP Package (Top View) Pin Definitions WLCSP Name A1 SW Description Buck converter switching node Type Output A2 AVDD Power supply for the device; connect to battery Power A3 OUTL Left channel output Output A4 INL- B1 AGND B2 CPP B3 HPVDD B4 Left channel input, negative terminal Input Main ground Power Charge pump flying capacitor, positive terminal Power Power supply for headphone amplifier (DC-DC output) Power INL+ Left channel input, positive terminal Input C1 CPN Charge pump flying capacitor, negative terminal Power C2 HPVSS Charge pump output Power C3 SGND Ground sense; connect to headphone jack ground Input C4 INR+ Right channel input, positive terminal D1 SDA I2C Serial Data (SDA) line Bi-Directional D2 SCL I2C Serial Clock (SCL) line Input D3 OUTR D4 INR- Right channel output Output Right channel input, negative terminal © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 Input Input www.fairchildsemi.com 2 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol AVDD Parameter Supply Voltage HPVDD_AMP Amplifier Supply Voltage, HPVDD Pin VIA INL+, INL-, INR+, INR- Voltage 2 VI2C I C Voltage VOUT OUTL, OUTR Voltage IBKD Output Protection Diodes Breakdown Continuous Current Min. Max. Unit -0.3 6.0 V -0.3 2.5 V HPVSS - 0.3 HPVDD + 0.3 V -0.3 AVDD + 0.3 V -HPVSS - 0.3 HPVDD + 0.3 V 200 mA Reliability Information Symbol TJ TSTG TL JA Parameter Min. Junction Temperature Storage Temperature Range Storage Relative Humidity Range Peak Reflow Temperature Thermal Resistance, JEDEC Standard, Multilayer Test Boards, Still Air Typ. -65 15 Max. Unit +150 +85 70 +260 °C °C % °C 75 °C/W Electrostatic Discharge Capability Symbol Parameter Human Body Model, JESD22-A114 ESD Charged Device Model, JESD22-C101 Condition Level According to JESD22-A114-B Level 2, Compatible with IEC61340-3-1: 2002 Level 2 or ESD-STM5.12001 Level 2 or MIL-STD-883E 3015.7 Level 2 According to JESD22-C101-C Level III, Compatible with IEC61340-3-3 Level C4 or ESD-STM5.3.1-1999 Level C4 Unit ±4000 V ±1500 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA AVDD tSLEW Parameter Operating Temperature Range Supply Voltage Range Power Supply Slew Rate © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 Min. Max. Unit -40 2.5 +85 5.5 1 °C V V/µs www.fairchildsemi.com 3 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Absolute Maximum Ratings Unless otherwise noted, AVDD = 3.6 V, Gain = 0d B, RL = 15Ω + 32 Ω || 5 nF with audio measurements across the 32Ω || 5 nF load, f = 1 KHz, TA = 25°C. Symbol IDD IS Parameter Quiescent Current Supply Current ISD Shutdown Current tWK Wake-Up Time PO HPVDD Output Power Per Channel (Outputs In Phase) Condition Typ. Max. Unit Both Channels Enabled, No Audio Signal 1.2 2.2 mA Output: 2 x 100 µW at 3 dB Crest Factor, RL = 32 Only 2.6 3.5 Output: 2 x 500 µW at 3 dB Crest Factor, RL = 32 Only 4.4 5.5 Output: 2 x 1 mW at 3 dB Crest Factor, RL = 32 Only 5.7 7.5 HIZL = HIZR = 1 1.0 2.3 SWSBY = 1, Inputs AC Grounded, SCL and SDA Pulled HIGH 1.8 6.0 µA 1.5 5.0 ms AVDD = 2.7 V, THD < 1%, f = 1 KHz, RL = 32 Only 36 AVDD = 2.7V, THD < 10%, f = 1 KHz, RL = 32 Only 48 AVDD = 2.7V, THD < 1%, f = 1 KHz, RL = 16 Only 51 Outer Rail HIGH Rail Voltages Buck and CP Output 1.20 1.25 1.30 -1.80 -1.70 Inner Rail -1.30 -1.25 -1.20 0.01 0.02 Total Harmonic Distortion + Noise 700mVRMS, 1 KHz PSRR Power Supply Rejection Ratio(1) Gain 0 dB, 200 mVPP Ripple at 217Hz Input Voltage Range Input Stage Does Not Clip Common Mode Rejection Ratio 1 VPP, f = 1 KHz, Gain 0 dB, RL = 32 Only Signal-to-Noise Ratio 1 VRMS, f = 1 KHz, RL = 32 Only 80 100 PO = 15 mW, f = 1 KHz Channel Separation RL ≥ 16 DC-Out (1) Output Noise Gain 0dB, A-Weight, RL = 32 Only Output DC-Offset Both Channels Enabled Gain Matching Mute Attenuation HIZx = 1 % dB ±1.4 Vp 65 dB 106 dB 80 dB dB 80 4.7 -500 9.0 µVRMS 500 µV 1 MUTEx = 1 V 100 75 Line Out >10K Vn 1.90 -1.90 THD+N SNR 1.80 Outer Rail LOW Rail Voltages CMRR 1.70 mA mW Inner Rail HPVSS VIN Min. -110 % -80 -80 dB Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 4 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Electrical Characteristics Unless otherwise noted, AVDD = 3.6 V, Gain = 0 dB, RL = 15 + 32 || 5 nF with audio measurements across the 32 || 5 nF load, f = 1 KHz, TA = 25°C. Symbol ZIN ZOUT Parameter Condition Input Impedance Differential Differential Input Impedance Gain = 0dB, per Input Node Single Ended Input Impedance Gain = 0dB, per Input Node Output Impedance Min. Capacitive Load Max. Unit 20.0 HIZx = 1, SWSBY = 0 38 k 18 <40 kHz 10.0 11.5 kΩ 6 MHz 500 1200 Ω 800 Ω 75 380 Ω 0.8 5.0 13 MHz 36 MHz CLOAD Typ. ESD Protection, External Capacitor 100.0 nF TSD Thermal Shutdown Threshold 150 °C THYS Thermal Shutdown Hysteresis 55 °C Note: 1. Guaranteed by Characterization. © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 5 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Electrical Characteristics (Continued) Unless otherwise noted, AVDD = 2.5 V to 5.5 V and TA = 25°C. Symbol Parameter Conditions Fast Mode (400kHz) Min. Max. Unit 0.6 V VIL Low-Level Input Voltage AVDD 2.9 to 4.5 V -0.3 VIH High-Level Input Voltage AVDD 2.9 to 4.5 V 1.2 VOL Low-Level Output Voltage at 3mA Sink Current (Open-Drain or Open-Collector) 0 0.4 V IIH High-Level Input Current of Each I/O Pin Input Voltage = A VDD -1 1 µA IIL Low-Level Input Current of Each I/O Pin Input Voltage = 0 V -1 1 µA V I2C AC Electrical Characteristics Unless otherwise noted, AVDD = 2.5 V to 5.5 V and TA = 25°C. Symbol fSCL tHD;STA Fast Mode Parameter SCL Clock Frequency Min. Max. Unit 0 400 kHz Hold Time (Repeated) START Condition 0.6 µs tLOW LOW Period of SCL Clock 1.3 µs tHIGH HIGH Period of SCL Clock 0.6 µs tSU;STA Set-up Time for Repeated START Condition 0.6 µs tHD;DAT Data Hold Time tSU;DAT 0 (2) Data Set-up Time 0.9 100 (3) µs ns tr Rise Time of SDA and SCL Signals 20+0.1Cb 300 ns tf Fall Time of SDA and SCL Signals(3) 20+0.1Cb 300 ns tSU;STO tBUF Set-up Time for STOP Condition 0.6 µs Bus Free Time between STOP and START Conditions 1.3 µs tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns Notes: 2. A fast-mode I2C-Bus® device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥250ns LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr_max + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. 3. Cb equals the total capacitance of one bus line in pf. If mixed with high-speed mode devices, faster fall times are allowed according to the I2C specification. Figure 3. Definition of Timing for Full-Speed Mode Devices on the I2C Bus® All marks are the property of their respective owners. © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 6 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter I2C DC Characteristics 10 9 9 8 8 7 7 Supply Current (uA) Supply Current (mA) 10 6 5 4 6 5 4 3 3 2 2 1 1 0 0 2.5 3.0 3.5 4.0 Supply Voltage (V) 4.5 5.0 2.5 5.5 Figure 4. Quiescent Supply Current vs. Supply Voltage 100 RL = 32ohm f = 1KHz Outputs in-phase Avdd = 2.5V Avdd = 3.6V Avdd = 5.0V 10 1 0.001 0.01 0.1 1 Total Output Power (mW) 4.0 Supply Voltage (V) 4.5 5.0 5.5 RL = 16ohm f = 1KHz Outputs in-phase Avdd = 2.5V Avdd = 3.6V Avdd = 5.0V 10 1 0.001 100 10 3.5 Figure 5. Shutdown Supply Current vs. Supply Voltage Supply Current (mA) Supply Current (mA) 100 3.0 0.01 0.1 1 Total Output Power (mW) 100 10 Figure 6. Supply Current vs. Total Output Power 32 Ω Figure 7. Supply Current vs. Total Output Power 16 Ω 100 100 f = 1KHz RL= 16ohm 90 Outputs in-phase THD+N = 10% 80 THD+N = 1% f = 1KHz RL= 32ohm 90 Outputs in-phase THD+N = 10% 80 THD+N = 1% 70 Output Power (mW) Output Power (mW) 70 60 50 40 60 50 40 30 30 20 20 10 10 0 0 2.5 3.0 3.5 4.0 Supply Voltage (V) 4.5 5.0 2.5 5.5 Figure 8. Output Power vs. Supply Voltage at 32 Ω © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 3.0 3.5 4.0 Supply Voltage (V) 4.5 5.0 5.5 Figure 9. Output Power vs. Supply Voltage at 16 Ω www.fairchildsemi.com 7 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Typical Characteristics 10 10 AVDD = 2.5V to 5.5V f = 1KHz RL= 32ohm Outputs in-phase 1 THD+N (%) THD+N (%) 1 AVDD = 2.5V to 5.5V f = 1KHz RL= 16ohm Outputs in-phase 0.1 0.1 0.01 0.01 0.001 0.1 1 0.001 0.1 100 10 1 Figure 10. THD+N vs. Output Power at 32 Ω 10 1 100 10 Output Power (mW) Output Power (mW) Figure 11. THD+N vs. Output Power at 16 Ω 0 AVDD = 2.5V to 5.5V f = 1KHz RL= 15ohm + 32ohm || 5nF (measurement taken across 32ohm || 5nF) Outputs in-phase RL = 32ohm Supply Ripple = 200mVpp Avdd = 2.5V -20 Avdd = 3.6V Avdd = 5.0V PSRR (dB) THD+N (%) -40 0.1 -60 -80 0.01 -100 0.001 0.1 -120 1 100 10 20 100 Output Power (mW) Figure 12. THD+N vs. Output Power 1 20K Figure 13. PSRR vs. Frequency 1 AVDD = 2.5V to 5.5V RL= 32ohm AVDD = 2.5V to 5.5V RL= 16ohm 1mW per Channel 1mW per Channel 0.1 THD+N (%) THD+N (%) 0.1 10K 1K Frequency (Hz) 20mW per Channel 0.01 0.01 20mW per Channel 0.001 0.001 20 100 1K Frequency (Hz) 10K 20 20K Figure 14. THD+N vs. Frequency at 32 Ω © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 100 1K Frequency (Hz) 10K 20K Figure 15. THD vs. Frequency at 16 Ω www.fairchildsemi.com 8 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Typical Characteristics 0 0 PO = 15mW RL = 32ohm AVDD = 2.5V to 5.5V Ripple = 100mVPP -10 -20 -40 CMRR (dB) Crosstalk (dB) -20 -60 -30 -40 -50 -80 -60 -100 20 100 10K 1K Frequency (Hz) -70 20K 20 Figure 16. Crosstalk vs. Frequency at 32 Ω 0 100 1K Frequency (Hz) 10K Figure 17. CMRR vs. Frequency f = 1KHz RL = 32ohm Output (dBV) -30 -60 -90 -120 -150 0 5 10 Frequency (KHz) 15 20 Figure 18. Output vs. Frequency at 32 Ω © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 9 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Typical Characteristics Class G The FAB1200 uses a class-G headphone architecture for low power dissipation. An integrated converter creates the headphone amplifier positive supply voltage, HPVDD. A charge pump inverts HPVDD and creates an amplifier negative supply voltage, HPVSS. This allows the headphone amplifier output to be centered at 0 V and eliminates the need for DC blocking capacitors. Output Impedance The FAB1200 headphone outputs can be placed in high-impedance mode by setting the HIZx bits to 1. This can be useful if the system’s headphone jack is shared with other devices. For proper high-impedance operation, the device must not be in a shutdown or protection mode and voltages on OUTL and OUTR must not exceed ±1.8 V. Actual impedance values are shown in the Electrical Characteristics table. When the output signal amplitude is low, the buck converter generates a low HPVDD voltage. When needed, the buck converter generates a higher HPVDD to accommodate higher amplitude output signals. This change occurs faster than audio signals so no distortion or clipping is introduced. Applications Information Layout Considerations General layout and supply bypassing play a major role in analog performance and thermal characteristics. Fairchild offers a demonstration board to guide layout and aid device evaluation. Contact a Fairchild representative for demonstration board information. Following this layout configuration provides optimum performance for the device. For the best results, follow the steps and recommended routing rules listed below. Thermal and Current Protection If the junction temperature of the regulator or headphone amplifier exceeds limits (see the Electrical Characteristics table), the system is disabled for approximately one second and the THERM bit is set to one. After one second, the system is enabled. If the fault condition still exists, the system is disabled again. This cycle repeats until the fault condition is removed. The THERM bit stays set to 1 until the fault condition is removed and it is read. Recommended Routing/Layout Rules Do not run analog and digital signals in parallel. Use separate analog and digital power planes to Output current is limited to prevent internal damage. A signal that would exceeds current limits is clipped so that it falls within limits. supply power. Traces should always run on top of the ground plane. No trace should run over ground/power splits. Avoid routing at 90-degree angles. Place bypass capacitors within 0.1 inches of the Shutdown Setting the SWSBY bit to 1 places the device in a lowcurrent shutdown state. The I2C port is still active and register values are not lost. During shutdown, HPVDD and HPVSS are powered down. Therefore, no signal should be present at the inputs during shutdown. During shutdown, junction temperature is not monitored. If junction temperature exceeds limits during shutdown, the THERM bit does not set to 1. © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 device power pin. Minimize all trace lengths to reduce series inductance. www.fairchildsemi.com 10 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Functional Description Writing to and reading from the registers is accomplished via the I2C interface. The I2C protocol requires that one device on the bus initiates and controls all read and write operations. This device is called the “master” device. The master device also generates the SCL signal, which is the clock signal for all other “slave” devices on the bus. The FAB1200 is a slave device. Both the master and slave devices can send and receive data on the bus. bit. If the slave address matches the address of the FAB1200, the FAB1200 sends an ACK after receiving the read/write bit by pulling the SDA line LOW for one clock cycle. Setting the Pointer For all operations, the pointer stored in the command register must be pointing to the register to be written to or read from. To change the pointer value in the command register, the Read/Write bit following the address must be 0. This indicates that the master will write new information into the Command register. During I2C operations, one data bit is transmitted per clock cycle. All I2C operations follow a repeating nineclock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device. Note that there are no unused clock cycles during any operation; therefore, there must be no breaks in the stream of data and ACKs/NACKs during data transfers. After the FAB1200 sends an ACK in response to receiving the address and Read/Write bit, the master device must transmit an appropriate 8-bit pointer value, as explained in the I2C Registers section. The FAB1200 sends an ACK after receiving the new pointer data. For most operations, I2C protocol requires the serial data (SDA) line remain stable (unmoving) whenever serial clock line (SCL) is HIGH: transitions on the SDA line can only occur when SCL is LOW. The exceptions to this rule are when the master device issues a START or STOP condition. The slave device cannot issue a START or STOP condition. The pointer set operation is illustrated in Figure 21 and Figure 22. Any time a pointer set is performed, it must be immediately followed by a read or write operation. The Command register retains the current pointer value between operations; therefore, once a register is indicated, subsequent read operations do not require a pointer set cycle. Write operations always require the pointer be reset. START Condition: This condition occurs when the SDA line transitions from HIGH to LOW while SCL is HIGH. The master device uses this condition to indicate that a data transfer is about to begin. Reading If the pointer is already pointing to the desired register, the master can read from that register by setting the Read/Write bit (following the slave address) to 1. After sending an ACK, the FAB1200 begins transmitting data during the following clock cycle. The master should respond with a NACK, followed by a STOP condition (see Figure 19). STOP Condition: This condition occurs when the SDA line transitions from LOW to HIGH while SCL is HIGH. The master device uses this condition to signal the end of a data transfer. Acknowledge (ACK) and Not Acknowledge (NACK): When data is transferred to the slave device, it sends an acknowledge (ACK) after receiving every byte of data. The receiving device sends an ACK by pulling SDA LOW for one clock cycle. The master can read multiple bytes by responding to the data with an ACK instead of a NACK and continuing to send SCL pulses, as shown in Figure 20. The FAB1200 increments the pointer by one and sends the data from the next register. The master indicates the last data byte by responding with a NACK, followed by a STOP. When the master device is reading data from the slave device, the master sends an ACK after receiving every byte of data. Following the last byte, a master device sends a "not acknowledge" (NACK) instead of an ACK, followed by a STOP condition. A NACK is indicated by leaving SDA HIGH during the clock after the last byte. To read from a register other than the one currently indicated by the Command register, a pointer to the desired register must be set. Immediately following the pointer set, the master must perform a REPEAT START condition (see Figure 22), which indicates to the FAB1200 that a new operation is about to occur. If the REPEAT START condition does not occur, the FAB1200 assumes that a write is taking place and the selected register is overwritten by the upcoming data on the data bus. After the START condition, the master must again send the device address and Read/Write bit. This time, the Read/Write bit must be set to 1 to indicate a read. The rest of the read cycle is the same as described in the previous paragraphs for reading from a preset pointer location. Slave Address Each slave device on the bus has a unique address so the master can identify which device is sending or receiving data. The FAB1200 slave address is 1100000X binary where “X” is the read/write bit. Master write operations are indicated when X=0. Master read operations are indicated when X=1. Writing to and Reading from the FAB1200 All read and write operations must begin with a START condition generated by the master device. After the START condition, the master device must immediately send a slave address (7 bits), followed by a read/write © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 11 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter I2C Control All writes must be preceded by a pointer set, even if the pointer is already pointing to the desired register. As with reading, the master can write multiple bytes by continuing to send data. The FAB1200 increments the pointer by ones and accept data for the next register. The master indicates the last data byte by issuing a STOP condition. Immediately following the pointer set, the master must begin transmitting the data to be written. After transmitting each byte of data, the master must release the SDA line for one clock cycle to allow the FAB1200 to acknowledge receiving the byte. The write operation SCL SDA A7 A6 A5 START (from Master) A4 A3 A2 Slave Address (from Master) A1 R/W ACK D7 D6 D5 D4 ACK (from Slave) D3 D2 D1 D0 NACK NACK (from Master) Data (from Slave) STOP (from Master) Figure 19. I2C Read SCL SDA A7 A6 A5 A4 A3 A2 R/W ACK D7 D6 D5 ACK (from Slave) Slave Address (from Master) START (from Master) A1 D4 D3 D2 D1 D0 ACK D7 D6 D5 ACK (from Master) Data (from Slave) D4 D3 D2 D1 D0 NACK NACK (from Master) Data (from Slave) STOP (from Master) Figure 20. I2C Multiple-Byte Read SCL SDA A7 A6 A5 START (from Master) A4 A3 A2 Slave Address (from Master) A1 R/W ACK P7 P6 P5 ACK (from Slave) P4 P3 P2 P1 P0 ACK D7 D6 D5 ACK (from Slave) Pointer (from Master) D4 D3 D2 D1 D0 ACK ACK (from Slave) Data (from Master) STOP (from Master) Figure 21. I2C Write SCL SDA A7 A6 START (from Master) A5 A4 A3 A2 Slave Address (from Master) A1 R/W ACK (from Slave) ACK P7 P6 P5 P4 P3 P2 A2 Slave Address (from Master) P0 A7 ACK ACK (from Slave) Pointer (from Master) A3 P1 A1 R/W ACK A6 A5 Repeat START (from Master) D7 ACK (from Slave) D6 D5 D4 D3 Data (from Slave) A4 Slave Address (from Master) D2 D1 D0 NACK NACK (from Master) STOP (from Master) Figure 22. I2C Write Followed by Read © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 12 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter should be terminated by a STOP condition from the master (see Figure 21). Writing Table 1. Register Map Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x01 HPENL HPENR 0 0 0 0 THERM SWSBY 0x02 MUTEL MUTER VOL4 VOL3 VOL2 VOL1 VOL0 0 0x03 0 0 0 0 0 0 HIZL HIZR 0x04 ID ID 0 0 Revision 3 Revision 2 Revision 1 Revision 0 Notes: 4. Bits labeled “0” have no effect if written. When read, their value is always 0. 5. Bits not mentioned in the register map are for testing only. These bits should never be written. When read, they may return any value. Table 2. Register 0x01 Bit Label R/W Default Description 0 SWSBY R/W 1 1 = Low-power software standby. Charge pumps are turned off. I2C is still active. Register values are not lost during shutdown. 0 = Normal operation. 1 THERM R 0 1 = A thermal shutdown has occurred. This bit stays set until it is read. 0 = No thermal shutdown. 5:2 0 R 0000 Value is always 0. No effect if written. 6 HPENR R/W 0 1 = Enable right headphone amplifier. 0 = Disable right headphone amplifier. 7 HPENL R/W 0 1 = Enable left headphone amplifier. 0 = Disable left headphone amplifier. Table 3. Register 0x02 Bit Label R/W Default Description 0 0 R 0 5:1 VOL[4:0] R/W 00000 6 MUTER R/W 1 1 = Mute right channel. 0 = Un-mute right channel. 7 MUTEL R/W 1 1 = Mute left channel. 0 = Un-mute left channel. Value is always 0. No effect if written. 00000 : -59 dB 11111 : +4 dB Audio taper over entire range (see Table 6) Table 4. Register 0x03 Bit Label R/W Default 0 HIZR R/W 0 1 = 3-state right channel. 0 = Normal operation. 1 HIZL R/W 0 1 = 3-state left channel. 0 = Normal operation. 7:2 0 R 000000 © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 Description Value is always 0. No effect if written. www.fairchildsemi.com 13 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter I2C Registers Bit Label R/W Default 3:0 Revision[3:0] R 0101 5:4 0 R 00 Value is always 0. No effect if written. 7:6 ID[1:0] R 00 Supplier identification. Table 6. Description Denotes silicon revision. Volume Control Volume Control Word Gain (dB) Volume Control Word Gain (dB) 10xxxxxx Mute_L 0001111x -13 01xxxxxx Mute_R 0010000x -11 0000000x -59 0010001x -10 0000001x -55 0010010x -9 0000010x -51 0010011x -8 0000011x -47 0010100x -7 0000100x -43 0010101x -6 0000101x -39 0010110x -5 0000110x -35 0010111x -4 0000111x -31 0011000x -3 0001000x -27 0011001x -2 0001001x -25 0011010x -1 0001010x -23 0011011x 0 0001011x -21 0011100x +1 0001100x -19 0011101x +2 0001101x -17 0011110x +3 0001110x -15 0011111x +4 © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 14 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Table 5. Register 0x04 0.03 C E 2X F A B 0.40 A1 BALL A1 INDEX AREA (Ø0.20) Cu Pad D 0.40 (Ø0.30) Solder Mask Opening 0.03 C 2X RECOMMENDED LAND PATTERN (NSMD PAD TYPE) TOP VIEW 0.06 C 0.625 0.547 0.05 C C SEATING PLANE 0.378±0.018 0.208±0.021 E D SIDE VIEWS NOTES: A. NO JEDEC REGISTRATION APPLIES. 0.005 B. DIMENSIONS ARE IN MILLIMETERS. C A B Ø0.260±0.02 16X 0.40 D C B A 0.40 C. DIMENSIONS AND TOLERANCE PER ASME Y14.5M, 1994. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. (Y) ±0.018 E. PACKAGE NOMINAL HEIGHT IS 586 MICRONS ±39 MICRONS (547-625 MICRONS). F 1 2 3 4 (X) ±0.018 F. FOR DIMENSIONS D, E, X, AND Y SEE PRODUCT DATASHEET. BOTTOM VIEW G. DRAWING FILNAME: MKT-UC016AArev2. Figure 23. 16-Ball WLCSP, 4x4 Array, 0.4 mm Pitch, 250 µm Ball Product-Specific Dimensions Product D E X Y FAB1200UCX 1.56 mm 1.56 mm 0.18 mm 0.18 mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent version. Package specifications do not expand Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent packaging drawings and tape and reel specifications http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7 www.fairchildsemi.com 15 FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter Physical Dimensions FAB1200 — Ground-Referenced Class-G Headphone Amplifier with Integrated Buck Converter 16 www.fairchildsemi.com © 2010 Fairchild Semiconductor Corporation FAB1200 • Rev 1.2.7