The following document contains information on Cypress products. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM71-10110-5E FR30 32-BIT MICROCONTROLLER MB91150 Series HARDWARE MANUAL FR30 32-BIT MICROCONTROLLER MB91150 Series HARDWARE MANUAL Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development. FUJITSU LIMITED PREFACE ■ Objectives and Intended Reader The MB91150 Series, hereafter referred to as MB91150, is a member of the "32-bit single-chip microcontroller FR30" and has a CPU based on a new RISC architecture at its core. This singlechip microcontroller contains peripheral I/O resources suited for audio equipment and MD drives that require low-power consumption. This manual is for engineers who develop products incorporating the MB91150. It also describes the functions and operation of the MB91150. Read this manual thoroughly. For details on each instruction, see the Instructions Manual. ■ Trademarks FR is an abbreviation of FUJITSU RISC controller and a product of FUJITSU LIMITED. Embedded Algorithm is a trademark of Advanced Micro Devices Corporation. ■ License Purchase of FUJITSU I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. i ■ Structure of This Manual This manual contains 22 chapters and one appendix. CHAPTER 1 "OVERVIEW OF THE MB91150" This chapter provides basic items that are required to fully understand the MB91150, such as a description of MB91150 features, block diagrams, and an outline of functions. CHAPTER 2 "HANDLING THE DEVICE" This chapter provides notes on handling the MB91150. CHAPTER 3 "MEMORY SPACE, CPU, AND CONTROL UNIT" This chapter describes basic items that are required to understand the FR Series CPU core functions, its architecture, specifications, and instructions. CHAPTER 4 "BUS INTERFACE" This chapter describes the bus interface and bus operation. CHAPTER 5 "I/O PORTS" This chapter describes the I/O ports and provides the block diagrams of individual ports. It also describes the structure and functions of registers. CHAPTER 6 "8/16-BIT UP/DOWN COUNTER/TIMER" This chapter describes the 8-bit and 16-bit up/down counter/timer and provides their block diagrams. It also describes the structures and functions of registers and the operations of the 8-bit and 16-bit up/down counter/timer. CHAPTER 7 "16-BIT RELOAD TIMER" This chapter describes the 16-bit reload timer. It also describes the operations of the 16-bit reload timer, block diagram, and the structures and functions of the timer registers. CHAPTER 8 "PPG TIMER" This chapter describes the PPG timer. It also describes the operations of the PPG timer, block diagram, and the structures and functions of the timer registers. CHAPTER 9 "MULTIFUNCTIONAL TIMER" This chapter describes the multifunctional timer. It also describes the operations of the multifunctional timer, block diagram, and the structures and functions of the timer registers. CHAPTER 10 "EXTERNAL INTERRUPT CONTROL BLOCK" This chapter describes the external interrupt control block. It also describes the operation of the external interrupt control block and the structures and functions of the related registers. CHAPTER 11 "DELAYED INTERRUPT MODULE" This chapter describes the delayed interrupt module. It also describes the operation of the delayed interrupt module and the structures and functions of related registers. CHAPTER 12 "INTERRUPT CONTROLLER" This chapter describes the interrupt controller and provides its block diagram. It also describes the structures and functions of registers and the operation of the interrupt controller. CHAPTER 13 "8/10-BIT A/D CONVERTER" This chapter describes the 8/10-bit A/D converter and provides its block diagram. It also describes pins, structures and functions of registers, interrupts, device operation, and the A/ D conversion data protection function. The chapter also provides notes on using the 8/10-bit A/D converter. ii CHAPTER 14 "8-BIT D/A CONVERTER" This chapter describes the 8-bit D/A converter. It also describes the operation of the converter, block diagram, and the structures and functions of the converter registers. CHAPTER 15 "UART" This chapter describes the UART and provides its block diagram. It also describes pins, structures and functions of registers, interrupts, timing, baud rates, and device operation. The chapter also provides notes on using the UART. CHAPTER 16 "I2C INTERFACE" This chapter describes the I2C interface and provides its block diagram. It also describes register structures and functions and I2C interface operation. CHAPTER 17 "DMAC" This chapter describes the DMAC and provides its block diagram. It also describes lists/ details of registers, operation, DMA transfer sources, and DMAC timing. The chapter also provides notes on using the DMAC. CHAPTER 18 "BIT SEARCH MODULE" This chapter describes the bit search module. It also describes the structures and functions of bit search module registers, and the processing for saving and restoring. CHAPTER 19 "PERIPHERAL STOP CONTROL" This chapter describes peripheral stop control and structures and functions of the registers. CHAPTER 20 "CALENDAR MACROS" This chapter describes the calendar macros, structures and functions of registers, and the operation of the calendar macro. CHAPTER 21 "FLASH MEMORY" This chapter describes the flash memory, structures and functions of the registers, device operation, and the automatic algorithm. It also provides detailed information on flash memory writing and erasing. CHAPTER 22 "EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION" This chapter shows an example of a serial programming connection using the AF220/AF210/ AF120/AF110 Flash microcontroller Programmer by Yokogawa Digital Computer Corporation. APPENDIX The appendix contains I/O maps and information on the interrupt vectors, pin status for various CPU states, notes on using the little-endian area, and instruction lists. iii • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. Copyright ©2002-2006 FUJITSU LIMITED All rights reserved iv READING THIS MANUAL ■ Details Regarding the Manual Format An explanation of the most important terms in this manual is given in the table below. Term Meaning I-bus 16-bit bus for internal instructions. The FR Series employs internal Harvard architecture; there are independent buses for instructions and data. A bus converter is connected to the I-bus. D-bus Internal 32-bit data bus. An internal resource is connected to the D-bus. C-bus Internal multiplex bus. The C-bus is connected to both the I-bus and D-bus through a switch. An external interface module is connected to the C-bus. On external data buses, data and instructions are multiplexed. R-bus Internal 16-bit data bus. The R-bus is connected to the D-bus via an adapter. Various I/O devices, a clock generator, and an interrupt controller are connected to the R-bus. The R-bus has a bandwidth of 16 bits over which addresses and data are multiplexed; CPU access time of these resources is several cycles. E-unit Arithmetic execution unit φ System clock. It provides the clock signals output to each of the built-in resources connected to the R-bus from the clock generator. The maximum clock speed (cycle) is identical to the original clock oscillation. The clock cycle can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on the setting of the PCK1 and PCK0 bits of the GCR register in the clock generator. θ System clock. Clock used by the CPU and resources connected to a bus other than the R-bus. The maximum clock speed (cycle) is identical to the original clock oscillation. The clock cycle can be divided by 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) depending on the setting of the CCK1 and CCK0 bits of the GCR register in the clock generator. v vi CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER 2 2.1 2.2 2.3 OVERVIEW OF THE MB91150 .................................................................... 1 MB91150 Features ............................................................................................................................. 2 Block Diagrams ................................................................................................................................... 5 Package Dimensions .......................................................................................................................... 7 Pin Assignment ................................................................................................................................. 10 Pin Functions .................................................................................................................................... 13 I/O Circuit Types ............................................................................................................................... 21 HANDLING THE DEVICE .......................................................................... 25 Notes on Handling Devices .............................................................................................................. 26 Notes on Using Devices ................................................................................................................... 28 Power-On .......................................................................................................................................... 29 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ....................................... 31 3.1 Memory Space .................................................................................................................................. 3.2 CPU Architecture .............................................................................................................................. 3.3 Programming Model ......................................................................................................................... 3.4 Data Structure ................................................................................................................................... 3.5 Word Alignment ................................................................................................................................ 3.6 Special Memory Areas ...................................................................................................................... 3.7 Overview of Instructions ................................................................................................................... 3.7.1 Branch Instructions with Delay Slots ........................................................................................... 3.7.2 Branch Instructions without a Delay Slot ..................................................................................... 3.8 EIT (Exception, Interrupt, and Trap) ................................................................................................. 3.8.1 Interrupt Level .............................................................................................................................. 3.8.2 Interrupt Stack Operation ............................................................................................................ 3.8.3 EIT Vector Table .......................................................................................................................... 3.8.4 Multiple EIT Processing ............................................................................................................... 3.8.5 EIT Operation .............................................................................................................................. 3.9 Reset Sequence ............................................................................................................................... 3.10 Operation Mode ................................................................................................................................ 3.11 Clock Generator (Low-Power Consumption Mechanism) ................................................................. 3.11.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) ........................ 3.11.2 Standby Control Register (STCR) ............................................................................................... 3.11.3 Timebase Timer Clear Register (CTBR) ..................................................................................... 3.11.4 Gear Control Register (GCR) ...................................................................................................... 3.11.5 Watchdog Reset Generation Delay Register (WPR) ................................................................... 3.11.6 DMA Request Suppression Register (PDRR) ............................................................................. 3.11.7 PLL Control Register (PCTR) ...................................................................................................... 3.11.8 Watchdog Timer Function ........................................................................................................... 3.11.9 Gear Function .............................................................................................................................. 3.11.10 Retaining a Reset Source ............................................................................................................ 3.11.11 Example of Setting the PLL Clock ............................................................................................... vii 32 35 38 45 46 47 48 50 53 54 55 56 57 59 61 66 67 69 71 73 74 75 77 78 79 80 82 84 86 3.12 Low-Power Consumption Mode ........................................................................................................ 3.12.1 Stop Status .................................................................................................................................. 3.12.2 Sleep Status ................................................................................................................................ 3.12.3 Status Transition of the Low-power Consumption Mode ............................................................. CHAPTER 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.6 4.7 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 BUS INTERFACE ....................................................................................... 99 Outline of Bus Interface .................................................................................................................. Block Diagram of the Bus Interface ................................................................................................ Registers of the Bus Interface ........................................................................................................ Area Select Registers (ASR) and Area Mask Registers (AMR) ................................................ Area Mode Register 0 (AMD0) .................................................................................................. Area Mode Register 1 (AMD1) .................................................................................................. Area Mode Register 32 (AMD32) .............................................................................................. Area Mode Register 4 (AMD4) .................................................................................................. Area Mode Register 5 (AMD5) .................................................................................................. External Pin Control Register 0 (EPCR0) .................................................................................. External Pin Control Register 1 (EPCR1) .................................................................................. Little-endian Register (LER) ...................................................................................................... Bus Operation ................................................................................................................................. Relationship Between Data Bus Width and Control Signals ..................................................... Bus Access in Big-endian Mode ................................................................................................ Bus Access in Little-endian Mode ............................................................................................. Comparison of External Access in Big-endian and Little-endian Mode ..................................... Bus Timing ...................................................................................................................................... Basic Read Cycle ...................................................................................................................... Basic Write Cycle ...................................................................................................................... Read Cycle in Each Mode ......................................................................................................... Write Cycle in Each Mode ......................................................................................................... Mixed Read/Write Cycles .......................................................................................................... Automatic Wait Cycle ................................................................................................................ External Wait Cycle ................................................................................................................... External Bus Request ................................................................................................................ Internal Clock Multiply Operation (Clock Doubler) .......................................................................... Program Examples for the External Bus ......................................................................................... CHAPTER 5 89 91 94 97 100 102 103 104 106 108 109 110 111 112 115 116 117 118 119 124 128 133 134 136 138 140 142 143 144 145 146 148 I/O PORTS ................................................................................................ 151 Overview of I/O Ports ...................................................................................................................... Block Diagram of Basic I/O Port ..................................................................................................... Block Diagram of I/O Ports (Including the Pull-up Resistor) ........................................................... Block Diagram of I/O ports (Including the Open-drain Output Function and the Pull-up Resistor) . Block Diagram of I/O Port (With Open-Drain Output Function) ...................................................... Port Data Register (PDR2 to PDRL) ............................................................................................... Data Direction Register (DDR2 to DDRL) ....................................................................................... Pull-up Resistor Control Register (PCR6 to PCRI) ......................................................................... Open-Drain Control Register (OCRH, OCRI) ................................................................................. Analog Input Control Register (AICR) ............................................................................................. viii 152 153 154 155 157 158 159 160 161 162 CHAPTER 6 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.5 6.6 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 163 Overview of 8/16-bit Up/Down Counter/Timer ................................................................................ Block Diagram of the 8/16-bit Up/Down Counter/Timer .................................................................. List of Registers for the 8/16-bit Up/Down Counter/Timer .............................................................. Counter Control Register H/L ch.0 (CCRH0, CCRL0) ............................................................... Counter Control Register H/L ch.1 (CCRH1, CCRL1) ............................................................... Counter Status Register 0/1 (CSR0, CSR1) .............................................................................. Up/Down Count Register 0/1 (UDCR0, UDCR1) ....................................................................... Reload/Compare Register 0/1 (RCR0, RCR1) .......................................................................... Selection of Counting Mode ............................................................................................................ Reload and Compare Functions ..................................................................................................... Writing Data to the Up/Down Count Register (UDCR) ................................................................... CHAPTER 7 16-BIT RELOAD TIMER ........................................................................... 187 7.1 Overview of 16-bit Reload Timer .................................................................................................... 7.2 Block diagram of a 16-bit reload timer ............................................................................................ 7.3 Registers of 16-bit Reload Timer .................................................................................................... 7.3.1 Control Status Register (TMCSR0 to TMCSR3) ....................................................................... 7.3.2 16-bit Timer Register (TMR0 to TMR3) and 16-bit Reload Register (TMRLR0 to TMRLR3) .............................................................................................................. 7.4 Internal Clock Operation ................................................................................................................. 7.5 Underflow Operation ....................................................................................................................... 7.6 Counter Operation States ............................................................................................................... CHAPTER 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.4 8.5 8.6 8.7 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.4 188 189 190 191 193 194 195 197 PPG TIMER .............................................................................................. 199 Overview of PPG Timer .................................................................................................................. Block Diagram of PPG Timer .......................................................................................................... Registers of PPG Timer .................................................................................................................. Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5) ............................................. PWM Cycle Set Register (PCSR0 to PCSR5) ........................................................................... PWM Duty Set Register (PDUT0 to PDUT5) ............................................................................. PWM Timer Register (PTMR0 to PTMR5) ................................................................................ General Control Register 1 (GCN1) .......................................................................................... General Control Register 2 (GCN2) .......................................................................................... PWM Operation .............................................................................................................................. One-shot Operation ........................................................................................................................ PWM Timer Interrupt Source and Timing Chart ............................................................................. Activating Multiple Channels by Using the General Control Register ............................................. CHAPTER 9 164 166 168 169 173 174 176 177 178 181 185 200 201 203 205 209 210 211 212 215 216 218 220 222 MULTIFUNCTIONAL TIMER ................................................................... 225 Overview of Multifunctional Timer ................................................................................................... Block Diagram of the Multifunctional Timer ................................................................................... Registers of Multifunctional Timer .................................................................................................. Registers of 16-bit Free-run Timer ............................................................................................ Registers of the Output Compare .............................................................................................. Registers of Input Capture ......................................................................................................... Operations of Multifunctional Timer ................................................................................................ ix 226 228 229 230 233 236 238 9.4.1 9.4.2 9.4.3 Operation of 16-bit Free-run Timer ............................................................................................ 239 Operation of 16-bit Output Compare ......................................................................................... 241 Operation of 16-bit Input Capture .............................................................................................. 243 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK ........................................ 245 10.1 Overview of External Interrupt Control Block .................................................................................. 10.2 External Interrupt Control Block Registers ...................................................................................... 10.2.1 Interrupt Enable Register (ENIR0, ENIR1) ................................................................................ 10.2.2 External Interrupt Request Register (EIRR0, EIRR1) ................................................................ 10.2.3 External Interrupt Level Setting Register (ELVR0, ELVR1) ....................................................... 10.3 External Interrupt Control Block Operation ..................................................................................... 10.4 External Interrupt Request Level .................................................................................................... 246 247 248 249 250 251 252 CHAPTER 11 DELAYED INTERRUPT MODULE ........................................................... 255 11.1 11.2 11.3 Overview of Delayed Interrupt Module ........................................................................................... 256 Delayed Interrupt Control Register (DICR) ..................................................................................... 257 Operation of Delayed Interrupt Module ........................................................................................... 258 CHAPTER 12 INTERRUPT CONTROLLER ................................................................... 259 12.1 Overview of Interrupt Controller ...................................................................................................... 12.2 Block Diagram of the Interrupt Controller ....................................................................................... 12.3 List of Interrupt Control Registers ................................................................................................... 12.3.1 Interrupt Control Register (ICR00 to ICR47) ............................................................................. 12.3.2 Hold-Request Cancellation-Request Level-Set Register (HRCL) .............................................. 12.4 Priority Evaluation ........................................................................................................................... 12.5 Return from Standby (Stop or Sleep) Mode ................................................................................... 12.6 Hold-Request Cancellation Request ............................................................................................... 12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR) ..................................... 260 261 262 264 266 267 270 271 272 CHAPTER 13 8/10-BIT A/D CONVERTER ..................................................................... 275 13.1 Overview of the 8/10-bit A/D Converter .......................................................................................... 13.2 8/10-bit A/D Converter Block Diagram ............................................................................................ 13.3 8/10-bit A/D Converter Pins ............................................................................................................ 13.4 8/10-bit A/D Converter Registers .................................................................................................... 13.4.1 A/D Control Status Register 1 (ADCS1) .................................................................................... 13.4.2 A/D Control Status Register 0 (ADCS0) .................................................................................... 13.4.3 A/D Data Register (ADCR) ........................................................................................................ 13.5 8/10-bit A/D Converter Interrupt ...................................................................................................... 13.6 Operation of the 8/10-bit A/D Converter ......................................................................................... 13.7 A/D Converted Data Preservation Function .................................................................................... 13.8 Notes on Using the 8/10-bit A/D Converter .................................................................................... 276 277 279 281 282 285 288 290 291 293 294 CHAPTER 14 8-BIT D/A CONVERTER .......................................................................... 295 14.1 Overview of the 8-bit D/A Converter ............................................................................................... 14.2 8-bit D/A Converter Block Diagram ................................................................................................. 14.3 8-bit D/A Converter Registers ......................................................................................................... 14.3.1 D/A Control Registers (DACR0, DACR1, DACR2) .................................................................... x 296 297 298 299 14.3.2 D/A Data Registers (DADR2, DADR1, DADR0) ........................................................................ 300 14.4 8-bit D/A Converter Operation ........................................................................................................ 301 CHAPTER 15 UART ........................................................................................................ 303 15.1 Overview of the UART .................................................................................................................... 15.2 UART Block Diagram ...................................................................................................................... 15.3 UART Pins ...................................................................................................................................... 15.4 UART Registers .............................................................................................................................. 15.4.1 Control Register (SCR0 to SCR3) ............................................................................................. 15.4.2 Mode Register (SMR0 to SMR3) ............................................................................................... 15.4.3 Status Register (SSR0 to SSR3) ............................................................................................... 15.4.4 Input-data Register (SIDR0 to SIDR3), Output-data Register (SODR0 to SODR3) .................. 15.4.5 Communication Prescaler Control Register (CDCR0 to CDCR3) ............................................. 15.5 UART Interrupts .............................................................................................................................. 15.6 Receive-Interrupt Generation and Flag Set Timing ........................................................................ 15.7 Send-Interrupt Generation and Flag Set Timing ............................................................................. 15.8 Baud Rate ....................................................................................................................................... 15.8.1 Baud Rate Based on the Dedicated Baud-Rate Generator ....................................................... 15.8.2 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) .............................................. 15.8.3 Baud Rate Based on the External clock .................................................................................... 15.9 UART Operations ........................................................................................................................... 15.9.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) ................................................. 15.9.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 15.9.3 Bidirectional Communication Function (Normal Mode) ............................................................. 15.9.4 Master/Slave-type Communication Function (Multiprocessor Mode) ........................................ 15.10 Notes on Using UART .................................................................................................................... 304 306 308 311 312 314 316 318 320 322 324 326 327 329 332 334 335 337 340 342 344 347 CHAPTER 16 I2C INTERFACE ....................................................................................... 349 16.1 Overview of I2C Interface ................................................................................................................ 16.2 Block Diagram of I2C Interface ....................................................................................................... 16.3 Registers of I2C Interface ............................................................................................................... 16.3.1 Bus Control Register (IBCR) ..................................................................................................... 16.3.2 Bus Status Register (IBSR) ....................................................................................................... 16.3.3 Address Register (IADR)/Data Register (IDAR) ........................................................................ 16.3.4 Clock Control Register (ICCR) .................................................................................................. 16.4 Operation of I2C Interface ............................................................................................................... 350 351 352 353 361 364 365 367 CHAPTER 17 DMA CONTROLLER (DMAC) .................................................................. 369 17.1 Overview of the DMA Controller ..................................................................................................... 17.2 Block Diagram of the DMA Controller ............................................................................................. 17.3 Registers of the DMA Controller ..................................................................................................... 17.3.1 DMAC Parameter Descriptor Pointer (DPDP) ........................................................................... 17.3.2 DMAC Control Status Register (DACSR) .................................................................................. 17.3.3 DMAC Pin Control Register (DATCR) ....................................................................................... 17.3.4 Register of the Descriptor in RAM ............................................................................................. 17.4 Transfer Modes Supported by the DMA Controller ......................................................................... 17.4.1 Step Transfer (Single/Block Transfer) ....................................................................................... xi 370 371 372 373 374 376 378 381 384 17.4.2 Continuous Transfer .................................................................................................................. 17.4.3 Burst Transfer ............................................................................................................................ 17.4.4 Differences Because of DREQ Sense Mode ............................................................................. 17.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output ............................................ 17.6 Notes on the DMA Controller .......................................................................................................... 17.7 Timing Charts for the DMA Controller ............................................................................................. 17.7.1 Timing Charts for the Descriptor Access Section ...................................................................... 17.7.2 Timing Charts for the Data Transfer Section ............................................................................. 17.7.3 Timing Charts for Transfer Termination in Continuous Transfer Mode ..................................... 17.7.4 Timing Charts for the Transfer Termination Operation .............................................................. 385 386 387 389 390 392 393 395 396 398 CHAPTER 18 BIT-SEARCH MODULE ........................................................................... 401 18.1 18.2 18.3 Overview of the Bit-Search Module ................................................................................................ 402 Registers of the Bit-Search Module ................................................................................................ 403 Operation of the Bit-Search Module and Save/Return Processing ................................................. 405 CHAPTER 19 PERIPHERAL STOP CONTROL ............................................................. 409 19.1 19.2 Overview of Peripheral Stop Control .............................................................................................. 410 Peripheral Stop Control Registers .................................................................................................. 411 CHAPTER 20 CALENDAR MACROS ............................................................................. 415 20.1 20.2 20.3 Overview of Calendar Macros ........................................................................................................ 416 Registers of Calendar Macros ........................................................................................................ 417 Operation of Calendar Macros ........................................................................................................ 421 CHAPTER 21 FLASH MEMORY ..................................................................................... 423 21.1 Overview of Flash Memory ............................................................................................................. 21.2 Flash Memory Registers ................................................................................................................. 21.3 Flash Memory Operation ................................................................................................................ 21.4 Automatic Algorithm of Flash Memory ............................................................................................ 21.5 Checking the Automatic Algorithm Execution Status ...................................................................... 21.6 Writing and Erasing Flash Memory ................................................................................................. 21.6.1 Putting Flash Memory into Read/Reset Status .......................................................................... 21.6.2 Writing Data to Flash Memory ................................................................................................... 21.6.3 Erasing Data .............................................................................................................................. 424 427 430 433 436 439 440 441 443 CHAPTER 22 EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION .......................................................................................... 445 22.1 22.2 Basic Configuration ......................................................................................................................... 446 Examples of Serial Programming Connection ................................................................................ 449 APPENDIX ......................................................................................................................... 451 APPENDIX A APPENDIX B APPENDIX C APPENDIX D I/O Map ............................................................................................................................... Interrupt Vectors .................................................................................................................. Pin Status in Each CPU State .............................................................................................. Notes on Using the Little-Endian Area ................................................................................. xii 452 460 464 471 D.1 C Compiler (fcc911) ....................................................................................................................... D.2 Assembler (fasm911) ..................................................................................................................... D.3 Linker (flnk911) .............................................................................................................................. D.4 Debuggers (sim911, eml911, and mon911) ................................................................................... APPENDIX E Instruction Lists .................................................................................................................... E.1 FR Family Instruction Lists ............................................................................................................. 472 475 476 477 478 482 INDEX ................................................................................................................................. 499 xiii xiv Main changes in this edition Page Changes (For details, refer to main body.) − Register names are changed. (the port (PDR) → the port data register (PDR)) (Open-drain control register (ODCR) → Open-drain control register (OCR)) (Analog Input Control Register (AIC) → Analog Input Control Register (AICR)) (Analog Input Control Register (AICK) → Analog Input Control Register (AICR)) (timer control register (TCCS) → timer control status register (TCCS)) (Interrupt Controller Registers → Interrupt Control Registers) 4 ❍ Other features is changed (• Packages is changed) (The description of QFP-144 (MB91F155A) is added.) 5, 6 Figure 1.2-1 Block Diagram (MB91FV150, MB91F155A and MB91155) and Figure 1.2-2 Block Diagram (MB91154) are changed. (P50/A8 → P50/A08) (P47/A7 → P47/A07) (P40/A0 → P40/A00) (PH2/SCK0/T00 → PH2/SCK0/TO0) (PH5/SCK1/T01 → PH5/SCK1/TO1) (PI2/SCK2/T02 → PI2/SCK2/TO2) (PI5/SCK3/T03 → PI5/SCK3/TO3) (PD5/INT13/ZIN1 → PD5/INT13/ZIN1/TRG5) (PD4/INT12/ZIN0 → PD4/INT12/ZIN0/TRG4) (PD3/INT11/BIN1 → PD3/INT11/BIN1/TRG3) (PD2/INT10/AIN1 → PD2/INT10/AIN1/TRG2) (PD1/INT9/BIN0(I) → PD1/INT9/BIN0(I)/TRG1) (PD0/INT8/AIN0(I) → PD0/INT8/AIN0(I)/TRG0) 9 ■ Package Dimensions of FPT-144P-M01 is added. 15 Table 1.5-1 Functions of the MB91150 Pins (3/8) is changed. (Function description of Pin No.69 to 74 is changed.) ([AIN,BIN] → [ZIN0, ZIN1]) ([TRG] → [TRG0 to TRG5]) 18 Table 1.5-1 Functions of the MB91150 Pins (6/8) is changed. (Pin name of Pin No.116 is changed.) (The text that Can be used as a port when external transfer end output specification of the DMA controller is disabled. is added.) 21 to 24 Table 1.6-1 I/O Circuit Types is changed. (Pull-up resistance: about 50 KΩ (typically) of Classification H, O, P is deleted.) 27 ❍ Crystal oscillation circuit is changed. (The text that Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. is added.) 28 ■ Notes on During Operation of PLL Clock Mode is changed. (Descriptions are changed.) ■ Watchdog Timer Function is changed. (the watchdog function → "3.11.8 Watchdog Timer Function") 29 ❍ Treatment of unstable power supply voltage or when shutting off power supply is added. xv Page Changes (For details, refer to main body.) 48 ❍ Branch is changed. (The branch instructions are detailed later. → Refer to "3.7.1 Branch Instructions with Delay Slots" about details of the branch instructions.) 55 Table 3.8-1 Interrupt Level is changed. 58 Table 3.8-2 Vector Table is changed. (Explanation of Vector No.10 is changed.) (Instruction break exception → System-reserved) 62 ■ Operation for INT Instruction is changed. (The text that The INT #u8 instruction operates as follows: is deleted.) 63 ■ Operation for INTE Instruction is changed. (The text that The INTE instruction operates as follows: is deleted.) 69 Summary of 3.11 Clock Generator (Low-Power Consumption Mechanism) is changed. (• Built-in PLL (gradual-double circuit) → • Built-in PLL (multiplication circuit)) Figure 3.11-1 Registers of the Clock Generator is changed. (PLL → PLL control register) 82 Figure 3.11-6 Block Diagram of the Gear Control Block is changed. (CCK → CCK1,CCK0) (PCK → PCK1,PCK0) ((Gradually doubled) → (2 multiplication)) 86 Figure 3.11-9 Example of Setting the PLL Clock is changed. (DBLACK=1 → DBLAK=1) 87 Notes: of ■ Example of Setting the PLL Clock is changed. (• For a restart of PLL VC0, be sure to program a wait time of at least 300µs to ensure stabilization. → • For a restart of PLL, be sure to program a wait time of at least 300µs to ensure stabilization by the software.) 88 ■ Example of the Related Assembler Source Code (Example of Switching to the PLL System) is changed. (and R5,R3 ; PTCR->VSTP=1 ? → and R5,R3 ; PCTR->VSTP=1 ?) 91 Summary of 3.12.1 Stop Status is changed. (Stop status means the stoppage of all internal clocks and stoppage of the oscillation circuit. This status allows the minimizing of power consumption. → Stop status means the stoppage of all internal clocks and stoppage of the oscillation circuit. (However, the oscillation of 32kHz is not stopped.) This status allows the minimizing of power consumption.) 101 Table 4.1-1 Usable Interface Mode for Each area is changed. (sharing → division) 108 [bit 7]: MultiPleX bit (MPX) is changed. (time-sharing → time-division) (The description of (Normal bus interface) is deleted.) 120 Figure 4.4-6 Relationship Between Internal Register and External Data Bus for 8-bit Bus Width is changed. (The lower bytes of the output address → The lower bytes of the internal address) 123 Figure 4.4-9 Example of a Connection Between the MB91150 and External Devices is changed. ((0/1 = the lowest bit of the address. → (0 = the lowest bit of the address.) 141 Figure 4.5-12 Sample Write Cycle Timing Chart 5 is changed. (BA → BA2) 142 Figure 4.5-13 Sample Timing Chart for Mixed Read/Write Cycles is changed. (BA → BA2) xvi Page Changes (For details, refer to main body.) 158 Summary of 5.6 Port Data Register (PDR2 to PDRL) is changed. ((PDR2 to PDR1) → (PDR2 to PDRL)) ((DDR2 to DDR1) → (DDR2 to DDRL)) 159 Summary of 5.7 Data Direction Register (DDR2 to DDRL) is changed. ((DDR2 to DDR1) → (DDR2 to DDRL)) 164 Summary of 6.1 Overview of 8/16-bit Up/Down Counter/Timer is changed. (their control circuits → control circuits) ■ Characteristics of the 8/16-bit Up/Down Counter/Timer is changed. (0 and 255(decimal numbers) → 0 to 255 (00H toFFH)) (0 and 65535 (decimal numbers) → 0 to 65535 (0000H to FFFFH)) 166 Figure 6.2-1 Block Diagram of the 8/16-bit Up/Down Counter/Timer (ch.0) is changed. (C/GS → CGSC) (RCUT → CTUT) 167 Figure 6.2-2 Block Diagram of the 8/16-bit Up/Down Counter/Timer (ch.1) is changed. (C/GS → CGSC) (RCUT → CTUT) 168 Figure 6.3-1 List of Registers for the 8/16-bit Up/Down Counter/Timer is changed. (D17 D16 D15 D14 D13 D12 D11 D10 → D15 D14 D13 D12 D11 D10 D09 D08) (Count status register ch0,1(CSR0,1) → Counter status register ch.0,1(CSR0,1)) 176 ■ Up/down Count Register 0/1 (UDCR 0, UDCR 1) is changed. (bits in the figure are changed.) (D17 D16 D15 D14 D13 D12 D11 D10 → D15 D14 D13 D12 D11 D10 D09 D08) 179 ❍ Multiply-by-4 mode is changed. (detection edge with USS1, USS0, DSS1 and DSS0 is invalid. → detection edge with CES1 and CES0 of CCRM are invalid.) 189 Figure 7.2-1 Block Diagram of the 16-bit Reload Timer is changed. (The part of EXCK is deleted.) 200 Summary of 8.1 Overview of PPG Timer is changed. (The PPG timer can generate PWM waveforms with great precision and efficiency. → The PPG timer can generate PWM waveforms with high precision and efficiency.) 205 [bit 14] STGR: Software trigger bit is changed. ([Bit 14] TGR: Software trigger bit → [bit 14] STGR: Software trigger bit) 226 ❍ Output compare (x8) is changed. (• Two compare registers can be paired to control output pins in the sense that two compare registers are used to reverse the output pins. → • Two compare registers can be paired to control output pins in the sense that two compare registers are used to reverse the output levels.) 228 Figure 9.2-1 Block Diagram of Multifunctional Timer is changed. (MSI3 to 0 and the part of ICLR are deleted.) (ICRE → CST0) 232 [bit 4]: MODE is changed. (clear bit (bit 3: CLR) → clear bit (bit 3: SCLR)) 235 Note is changed. (• The write processing of the compare register → • The rewrite processing of the compare register) 236 Summary of 9.3.3 Registers of Input Capture is changed. (• Input capture control register (IPCP) → • Input capture control register (ICS01, ICS23)) xvii Page Changes (For details, refer to main body.) 241, 242 Figure 9.4-5 Example of the Output Waveform when Compare Registers 0 and 1 are Used (At the Beginning of Output, 0 is Assumed.) and Figure 9.4-6 Example of the Output Waveform when Compare Registers 0 and 1 are Used (At the Beginning of Output, 0 is Assumed.) are changed. (RT00 → Output compare 0) (RT01 → Output compare 1) Note is changed. (The write processing of the compare register → The rewrite processing of the compare register) 243 Figure 9.4-8 Example of Capture Timing for the 16-bit Input Capture is changed. (N0 → IN0) (N1 → IN1) 247 Figure 10.2-1 List of External Interrupt Control Block Registers is changed. (External interr upt enable register (ENIR1) is added.) (External interr upt source register (EIRR1) is added.) (Request level set register (ELVR1) is added.) 248 10.2.1 Interrupt Enable Register (ENIR0, ENIR1) is changed. (ENIRn → ENIR0, ENIR1) 249 10.2.2 External Interrupt Request Register (EIRR0, EIRR1) is changed. (EIRRn → EIRR0, EIRR1) 250 ■ External Level Register (ELVR0, ELVR1: External Level Register) is changed. (ELVR allocation table → external interrupt level setting) Table 10.2-1 External Interrupt Level Setting is changed. (LBx → LB15 to LB0) (LAx → LA15 to LA0) 251 ■ Setting Procedure for an External Interrupt is changed. (The text that 1.The general-purpose I/O port that is shared with the pin used as input of external interrupt is set to the input port is added.) 252 ■ Notes on using external interrupt to return from STOP state where clock oscillation is stopped is added. ■ Return operation from STOP state is added. 260 ■ Hardware Configuration of Interrupt Controller is changed. (• ICR register → • Interrupt control register (ICR register: ICR00 to ICR47)) 261 Figure 12.2-1 Block Diagram of the Interrupt Controller is changed. (The description of Resource interrupt is added.) 267, 268 Table 12.4-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels is changed. (The line of System-reserved is added.) (A/D (Sequential type) → A/D) 272 Figure 12.7-1 Sample Hardware Configuration for Using a Hold-request Cancellation-request is changed. (The description of HACK is added.) (The description of HACK: Hold acknowledge is added.) 277 Figure 13.2-1 8/10-bit A/D Converter Block Diagram is changed. (AVR± → AVRH, AVRL) 280 Figure 13.3-1 Block Diagram of the Pins PK0/AN0 to PK7/AN7 is changed. (The description of (HIZX=1) is deleted.) 282 Figure 13.4-2 Configuration and Functional Outline of A/D Control Status Register 1 (ADCS1).is changed. (timer → 16-bit reload timer) xviii Page Changes (For details, refer to main body.) 286 Note: of [bit 7, 6] MD1, MD0 (A/D conversion mode selection bits) is changed. (• Restart can be performed during A/D conversion when A/D conversion mode selection bits (MD1,MD0) are set to "00B". In this mode, only the software start-up option (STS1, STS0 = "00B") can be selected. Perform the restart in the following steps. (1) Clear the INT bit to 0. (2) Write "1" to the STRT bit at the same time as writing "0" to the INT bit. is added.) 287 Note is added to [bit 2, 1, 0] ANE2, ANE1, ANE0(A/D conversion end channel selection bits) 288 ■ A/D Data Register (ADCR) is changed. Figure 13.4-4 Configuration and Functional Outline of A/D Data Register (ADCR) is changed. ((0) (0) (1) (0) (1) (X) (X) → (0) (0) (1) (0) (1) (X) (X) (X)) (AD data bits → A/D data bits) (AD data bit → A/D conversion resolution selecting bit) 290 ■ 8/10-bit A/D Converter Interrupt is changed. (A/D control status register (ADCS1) → A/D control status register 1 (ADCS1)) 293 ■ A/D Converted Data Preservation Function is changed. (, data stored in the data register is stored externally and rewritten at the end of conversion. → , data stored in the data register is rewritten at the end of conversion.) 294 ❍ Analog input pin is changed. (The description of (AIx = 1) is deleted.) (The description of (AIx = 0) is deleted.) ❍ Restart during A/D conversion is added. 298 Figure 14.3-1 List of the 8-bit D/A Converter Registers is changed. (D/A converter data register → D/A data register) 300 [bit 23 to bit 16] DA27 to DA20 is changed. (DADR2 → DA27 to DA20) [bit 15 to bit 8] DA17 to DA10 is changed. (DADR1 → DA17 to DA10) [bit 7 to bit 0] DA07 to DA00 is changed. (DADR0 → DA07 to DA00) 301 ■ Operation of the 8-bit D/A Converter is changed. (When D/A output is disabled, the analog switches in the output blocks of the D/A converter channels are turned off. → When D/A output is disabled.) 313 (Note) of [bit 10] REC (Receive-error flag-clear bit) is changed. (only when the FRE, DRE, or PE flag → only when the FRE, ORE, or PE flag) 315 [bit 1] SCKE (Serial clock output-enable bit) is changed. (SCKn → SCK0 to SCK3) (Notes) of [bit 1] SCKE (Serial clock output-enable bit) is changed. (1. When using the SCKn pins → 1. When using the SCK0 to SCK3 pins) [bit 0] SOE (Serial data output-enable bit) is changed. (SOTn pins → SOT0 to SOT3 pins) 316 [bit 15] PE (Parity error flag bit) is changed. (mode register (SMR0-4) → control register (SCR0 to SCR3)) xix Page Changes (For details, refer to main body.) 317 [bit 14] ORE (Overrun error flag bit) and [bit 13] FRE (Framing error flag bit) are changed. (mode register (SMR0-3) → control register (SCR0 to SCR3)) (Note) of [bit 10] BDS (Transfer direction selection bit) is changed. (SDR register → SIDR0 to SIDR3 register) 320 [bit 15] MD (Machine clock divide mode select) is changed. ([Bit 15] MD (Machine clock device mode select) → [bit 15] MD (Machine clock divide mode select)) 321 Notes is changed. (• When the dedicated baud rate generator is used at the synchronous transmission, the following settings are prohibited. -- CS2 to CS0=000B -- CS2 to CS0=001B and DIV3 to DIV0=0000B are added.) 327 ❍ Baud-rate selection based on the dedicated baud-rate generator is changed. (The description of the BCH and is deleted.) ❍ Baud rate based on the internal timer is changed. (❍ Baud rate based on the internal clock → ❍ Baud rate based on the internal timer) 329 ❍ Division ratio based on the prescaler (common for asynchronous and synchronous modes) is changed. (CDCR register → communication prescaler control register) 330 Table 15.8-2 Selection of Synchronous Baud-rate Division Ratio is changed. (16M → −) (8M → −) (The column of SCKI is deleted.) Note is added to ❍ Synchronous transfer clock division ratio Table 15.8-3 Selection of Asynchronous Baud-rate Division Ratio is changed. (The column of SCKI is deleted.) 331 Note of ❍ Internal timer is deleted. (The sentence that In mode 2 (CLK-synchronous mode), SCKO is behind SCKI for a maximum of three clocks. The theoretically possible baud rate is one-third (1/3) the system clock frequency. In the actual specification, a quarter (1/4) should be used. is deleted.) 334 ■ Baud Rate Based on the External Clock is changed. (• The port for input the external clock is set to the input status. is added.) 337 ❍ Transfer-data format is changed. (In operation mode 0, data has either a fixed length of eight bits without parity or a fixed length of 8 bits with parity. → In a normal mode of operation mode 0, the data length can be set to 7 bits or 8 bits.) 343 Figure 15.9-8 Example of Bidirectional Communication Flow is changed. (UODR → SODR) 355 Note is added to [bit 12] MSS (Master Slave Select) 357 to 359 Note is added to [bit 8] INT (INTerrupt) 362 [bit 4] LRB (Last Received Bit) is changed. (Table is added.) 364 [bit 14 to bit 8] A6 to A0 (Slave address bit) is changed. (DAR register → IDAR register) 365 [bit 5] EN (ENable) is changed. (BSR and BCR registers → IBSR and IBCR registers) xx Page Changes (For details, refer to main body.) 367 Summary of 16.4 Operation of I2C Interface is changed. (make the wiring possible. → make the wiring logic possible.) ❍ Addressing is changed. (, bit 0 of the transmitted data (bit 0 of the posttransmission IDAR register) is set to the other value, which is stored in the TRX bit. → , bit 0 of the transmitted data (bit 0 of the posttransmission IDAR register) is inverted, which is stored in the TRX bit.) 371 Figure 17.2-1 Block Diagram of the DMA Controller is changed. (DREQ0-2 → DREQ0 to DREQ2) 374 [bit 31, bit 27, bit 23, bit 19, bit 15, bit 11, bit 7, and bit 3] DER7 to DER0 (DMA error) is changed. (DERn → DER7 to DER0) 375 [bit 30, bit 26, bit 22, bit 18, bit 14, bit 10, bit 06, and bit 02] DED7 to DED0 (DMA end) is changed. (DEDn → DED7 to DED0) [bit 29, bit 25, bit 21, bit 17, bit 13, bit 9, bit 5, and bit 1] DIE7 to DIE0 (DMA interrupt enable) is changed. (DIEn → DIE7 to DIE0) (DEDn → DED7 to DED0) [bit 28, bit 24, bit 20, bit 16, bit 12, bit 8, bit 4, and bit 0] DOE7 to DOE0 (DMA operation enable) is changed. (DOEn → DOE7 to DOE0) (DEDn → DED7 to DED0) 376 [bit 21, bit 20, bit 13, bit 12, bit 5, and bit 4] LS21, LS20, LS11, LS10, LS01 and LS00 for transfer request input detection level selection is changed. (LSn1,LSn0 → LS21, LS20, LS11, LS10, LS01 and LS00) (DREQn → DREQ2 to DREQ0) 377 [bit 19, bit 11, and bit 3] AKSE2, AKSE1, AKSE0 is changed. (AKSEn → AKSE2, AKSE1, AKSE0) [bit 18, bit 10, and bit 2] AKDE2, AKDE1, AKDE0 is changed. (AKDEn → AKDE2, AKDE1, AKDE0) [bit 17, bit 9, and bit 1] EPSE2, EPSE1, EPSE0 is changed. (EPSEn → EPSE2, EPSE1, EPSE0) [bit 16, bit 8, and bit 0] EPDE2, EPDE1, EPDE0 is changed. (EPDEn → EPDE2, EPDE1, EPDE0) 381 ■ Single/Block Transfer Mode is changed. (DOEn → DOE7 to DOE0) (DEDn → DED7 to DED0) 382 ■ Continuous Transfer Mode is changed. (DOEn → DOE7 to DOE0) (DEDn → DED7 to DED0) Burst Transfer Mode is changed. (DOEn → DOE7 to DOE0) 387 Figure 17.4-5 Level-mode Timing is changed. (Up to 1 cycle → Up to 1 tCYC) 389 ■ Transfer-acceptance Signal Output is changed. (AKSEn and AKDEn bits → AKSE2 to AKSE0 and AKDE2 to AKDE0 bits) ■ Transfer-end Signal Output is changed. (EPSEn and EPDEn bits → EPSE2 to EPSE0 and EPDE2 to EPDE0 bits) 391 ❍ Error status in the DMAC transfer request source is changed. (DERn → DER7 to DER0) xxi Page Changes (For details, refer to main body.) 393 ❍ Request pin input mode: Level, Descriptor address: External and ❍ Request pin input mode: Level, Descriptor address: Internal are changed. (DREQn → DREQ2 to DREQ0) (WRn → WR0,WR1) 394 ❍ Request pin input mode: Edge, Descriptor address: External and ❍ Request pin input mode: Edge, Descriptor address: Internal are changed. (DREQn → DREQ2 to DREQ0) (WRn → WR0,WR1) 395 ❍ Transfer source area: External, Transfer destination area: External, ❍ Transfer source area: External, Transfer destination area: Internal RAM and ❍ Transfer source area: Internal RAM, Transfer destination area: External are changed. (DREQn → DREQ2 to DREQ0) (WRn → WR0,WR1) 396 ❍ Transfer source area: External, Transfer destination area: External, ❍ Transfer source area: External, Transfer destination area: Internal RAM and ❍ Transfer source area: Internal RAM, Transfer destination area: External are changed. (DREQn → DREQ2 to DREQ0) (WRn → WR0,WR1) 397 ❍ Transfer source area: External, Transfer destination area: External, ❍ Transfer source area: External, Transfer destination area: Internal RAM and ❍ Transfer source area: Internal RAM, Transfer destination area: External are changed. (DREQn → DREQ2 to DREQ0) (WRn → WR0,WR1) 398 ❍ Bus width: 16 bits, Data length: 8/16 bits and ❍ Bus width: 16 bits, Data length: 32 bits are changed. (WRn → WR0,WR1) ❍ Bus width: 16 bits, Data length: 32 bits is changed. (DH → D) 399 ❍ Bus width: 16 bits, Data length: 8/16 bits and ❍ Bus width: 16 bits, Data length: 32 bits are changed. (WRn → WR0,WR1) ❍ Bus width: 16 bits, Data length: 32 bits is changed. (DH → D) 402 Figure 18.1-2 Registers of the Bit-search Module is changed. (Value change detection data register → Change point detection data register) 403 , 404 18.2 Registers of the Bit-Search Module is changed. (value change → change point) Summary of 18.2 Registers of the Bit-Search Module is changed. (• Value-change detection register (BSDC) → • Change point detection data register (BSDC)) 405 , 406 18.3 Operation of the Bit-Search Module and Save/Return Processing is changed. (value change → change point) xxii Page Changes (For details, refer to main body.) 416 Figure 20.1-2 Calendar Macro Registers is changed. (D7 - - D4 D3 D2 D1 D0 → RST - - - - - MD1 MD0) (- - D5 D4 D3 D2 D1 D0 → - - S5 S4 S3 S2 S1 S0) (- - D5 D4 D3 D2 D1 D0 → - - M5 M4 M3 M2 M1 M0) (- - - D4 D3 D2 D1 D0 → - - - H4 H3 H2 H1 H0) (- - - D4 D3 D2 D1 D0 → - - - DA4 DA3 DA2 DA1 DA0) (- - - - - D2 D1 D0 → - - - - - W2 W1 W0) (- - - - D3 D2 D1 D0 → - - - - MN3 MN2 MN1 MN0) (- D6 D5 D4 D3 D2 D1 D0 → - Y6 Y5 Y4 Y3 Y2 Y1 Y0) (D7 - - - - - D0 → TST - - - - - TST) 421 ■ Initialization Reset is changed. (TST pin → RST pin) 425 Figure 21.1-1 Block Diagram of the Flash Memory is changed. (RDY/BUSYX → RDY/BUSY) (RESETX → RESET) (BYTEX → BYTE) (OEX → OE) (WEX → WE) (CEX → CE) 429 [bit 0]: LPM (Low power mode) is changed.(table is changed) (CEX → CE) (CXE → CE) 433 Summary of 21.4 Automatic Algorithm of Flash Memory is changed. (The text that The Sector Erase command is further divided into a Sector Erase Temporary Stop command and a Sector Erase Restart command. is deleted.) Table 21.4-1 Command Sequence is changed. (The lines of Sector Erase Temporary Stop and Sector Erase Restart are deleted.) (The Sector Erase Temporary Stop command (B0H) and Sector Erase Restart command (30H) are valid only when a sector is being erased. is deleted.) 435 ❍ Sector Erase Temporary Stop command is deleted. 436 ■ Hardware Sequence Flags is changed. (Figure is changed.) (TOGGLE → −) (TOGGL2 → −) 437 Table 21.5-1 Hardware Sequence Flag Status is changed. (The part in the table is deleted.) (The description of [Bit 6]: TOGGLE (toggle bit) is deleted. (The description of[Bit 2]: TOGGL2 (toggle bit 2) is deleted.) (The description of ❍ At sector erase temporary stop is deleted.) (The description of[Bit 6]: TOGGLE (toggle bit flag) is deleted.) 438 ❍ At write/chip sector erase is changed. (The description of or toggle bit function is deleted.) (The description that Also, the toggle bit flag continues the toggle operation till the time limit is exceeded. The timing limit excess flag outputs 1. is deleted.) ❍ During sector erase operation is changed. ([Bit 2]: TOGGL2 (toggle bit flag 2) is deleted.) (❍ At sector erase temporary stop is deleted.) ❍ When a sector erase operation is changed. (❍ When a sector erase operation is stopped temporarily → ❍ When a sector erase operation) xxiii Page Changes (For details, refer to main body.) 439 Summary of 21.6 Writing and Erasing Flash Memory is changed. (The description of , sector erase temporary stop, and sector erase restart is changed.) ■ Overview of Writing and Erasing Flash Memory is changed. (The description of , sector erase temporary stop, or erase restart is deleted.) 441 ■ Procedure for Flash Memory Write is changed. (At the same time at which (TLOVER) changes to 1, the toggle-bit flag (TOGGLE) also stops the toggle operation. For this reason, (TOGGLE) must be rechecked. is deleted.) 443 ■ Chip Erase is changed. (table to target sectors in the flash memory. → Table 21.4-1 to target sectors in the flash memory.) ❍ Sector erase procedure is changed. (Here, the toggle bit flag (TOGGLE) is used to check for the end of erase processing. is deleted.) (When the timing limit excess flag (TLOVER) changes to 1, the toggle bit flag (TOGGLE) stops the toggle operation at the same time. For this reason, even if (TLOVER) is 1, (TOGGLE) must be rechecked. is deleted.) 444 Figure 21.6-2 Example of the Procedure for Flash Memory Sector Erase is changed. 444 21.6.4 Temporarily Stopping and Restarting Sector Erase is deleted. 445 CHAPTER 22 is added. 453, 455 Read/write attributes of the registers in Table A-1 I/O Map are changed. (SIDR0/SODR0, SIDR1/SODR1, SIDR2/SODR2, SIDR3/SODR3, PCNH0, PCNH1, PCNH2, PCNH3, PCNH4, PCNH5) 455 Block of Table A-1 I/O Map is changed. (A/D converter (serial type) → A/D converter ) 458 Address of PCTR Register in Table A-1 I/O Map is changed. (000488H → 000488H to 00048BH) 461, 462 465 to 470 Table B-1 Interrupt Vectors are changed. ( − → ICR09) ( − → ICR14) ( − → ICR25) (A/D (successive type) → A/D) ( − → ICR45) Table C-2 Pin Status in 16-bit Mode of the External Bus ,Table C-3 Pin Status in External Bus 8-bit Mode and Table C-4 Pin Status in Single-chip Mode are changed. (A0-7 → A00-07) (A8-15 → A08-15) ((BGRNT=1) → (BGRNT)) (The description of (RST=1) is deleted.) (SCK/TO2 → SCK2/TO2) 484 Table E.1-3 Logical Operation Instructions and Table E.1-4 Bit Manipulation Instructions are changed. (The column of RMW is added.) 492 Table E.1-13 Other Instructions is changed. (The column of RMW is added.) xxiv CHAPTER 1 OVERVIEW OF THE MB91150 This chapter provides basic information required to fully understand the MB91150, such as a description of MB91150 features, block diagrams, and an outline of functions. 1.1 MB91150 Features 1.2 Block Diagrams 1.3 Package Dimensions 1.4 Pin Assignment 1.5 Pin Functions 1.6 I/O Circuit Types 1 CHAPTER 1 OVERVIEW OF THE MB91150 1.1 MB91150 Features The MB91150 is a single-chip microcontroller with peripheral I/O resources suited for controlling devices such as audio equipment and MD drives that require operation with low-power consumption. The core of the MB91150 is a 32-bit RISC CPU (FR30). ■ MB91150 Features ❍ CPU • 32-bit RISC (FR30), load/store architecture, 5-stage pipeline • 32-bit general-purpose register x 16 • 16-bit fixed-length instructions (basic instruction), one instruction per cycle • Instructions for memory-to-memory transfer, bit processing, barrel shift, etc. The instructions are suited for embedded-type usage. • Instructions for entry/exit functions, multiple load/store instructions for the register contents, instructions for high-level language. • Register interlock function allowing simpler assembler code • Branch instruction with a delay slot allowing a decrease in overhead for branch processing • Built-in multiplier, supported on the instruction level • Signed 32-bit multiplication: 5 cycles • Signed 16-bit multiplication: 3 cycles • Interrupt (PC and PS saving): 6 cycles, 16 priority levels ❍ Bus interface • 24-bit address output, 8-bit and 16-bit data I/O • Basic bus cycle: 2 clock cycles • Interface for supporting various memory types • Unused data and address pins can be used as I/O port. • Support of little endian mode ❍ Internal ROM • MB91F155A, MB91FV150 • • MB91155 • • Mask product: 510 KB MB91154 • 2 FLASH product, EVA-FLASH product: 510 KB Mask product: 384 KB CHAPTER 1 OVERVIEW OF THE MB91150 ❍ Internal RAM Mask product, FLASH product, EVA-FLASH product: 2 KB ❍ Internal data RAM • MB91FV150, MB91F155A, MB91155 • • EVA-FLASH product, FLASH product, Mask product: 32 KB MB91154 • Mask product: 20 KB ❍ DMA controller (DMAC) • DMAC of the descriptor type according to which transfer parameters are allocated in main storage • Capable of transferring up to eight internal and external sources • External source: 3 channels ❍ Bit search module The bit search module makes a one-cycle search for the location of the first I/O bit change starting with the MSB of a word. ❍ Timer • 16-bit OCU x 8 channels, ICU x 4 channels, free-run timer x 1 channel • 8-bit or 16-bit up/down timer/counter (8-bit x 2 channels or 16-bit x 1 channel) • 16-bit PPG timer x 6 channels. The cycle and duty of an output pulse can be changed to an arbitrary value. • 16-bit reload timer x 4 channels ❍ D/A converter 8 bits x 3 channels ❍ A/D converter (successive approximation type) • 10 bits x 8 channels • Successive approximation type (conversion time: 5.0 µs@33 MHz) • Single and scan conversions can be selected, and single, continuous, and stop conversion modes can be set. • Hardware-driven or software-driven conversion start function ❍ Serial I/O • UART x 4 channels. Each UART can perform clock-synchronized serial transfer with the LSB/ MSB switching function. • Serial data output and serial clock output can be selected by open-drain or push-pull software. • Built-in 16-bit timer (U-Timer) as a dedicated baud rate generator, which can generate any baud rate 3 CHAPTER 1 OVERVIEW OF THE MB91150 ❍ I2C bus interface • 1-channel master/slave transmission/reception • Arbitration function and clock synchronization function • (As long as the customer uses this product in an I2C system conforming to the Standard Specifications prepared by Philips, the customer is granted a license of the patent of Philips.) I 2C I 2C ❍ Clock switching function The ratio of the operating clock to the base clock can independently be set with the gear function to 1:1. 1:2, 1:4, or 1:8 for the CPU and for each peripheral device. ❍ Clock function (calendar macro) • Built-in 32 kHz clock function • The 32 kHz oscillation clock function can operate in stop mode as well. • (32-kHz oscillation does not stop in stop mode.) ❍ Interrupt controller • External interrupt input (up to 16 channels) • • The leading edge, trailing edge, "H" level, or "L" level can be set. Internal interrupt source • Resource interrupt, delayed interrupt ❍ Other features • Reset sources • • Low-power consumption mode • • Power-on reset, watchdog timer, software reset, and external reset Sleep mode and stop mode Packages • PGA-299 (MB91FV150) • LQFP-144 (MB91F155A, MB91155, MB91154) • QFP-144 (MB91F155A) • CMOS technology (0.35 µm) • Power supply • 3.15 V to 3.6 V Note: MB91F155 is changed to MB91F155A. 4 CHAPTER 1 OVERVIEW OF THE MB91150 1.2 Block Diagrams This section provides MB91150 block diagrams separately for individual packages. ■ Block Diagram for MB91FV150, MB91F155A and MB91155 Figure 1.2-1 is a block diagram for the MB91FV150, MB91F155A and MB91155. Figure 1.2-1 Block Diagram (MB91FV150, MB91F155A and MB91155) M O D E MD0 MD1 MD2 FR30 CPU Core D-bus I-bus (4) RST Calendar P O R T 3 / 2 Data RAM 32KB … P30/D24 P27/D23 … DATA … … P37/D31(IO) (16) P50/A08 P47/A07 DMAC 8ch P O R T 6 / 5 / 4 Bit Search D-bus R-bus P O R T E (8) P O R T G (6) … Address … P60/A16 P57/A15 … … P20/D16 P67/A23(O) P40/A00 Bus Control DMAC Clock P86/CLK(O) P85/WR1(O) P84/WR0 P83/RD(O) P82/BRQ(I) P81/BGRNT(O) P80/RDY(I) PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0(O) PL1/DACK0(O) PL0/DREQ0(I) X0 (I) X1 (I) (24) P O R T 8 D-bus I-bus C-bus External Bus CTL (7) P O R T L (8) Up/Down Counter External Interrupt PD7/INT15/ATG(I) PD6/INT14/DEOP2 PD5/INT13/ZIN1/TRG5 PD4/INT12/ZIN0/TRG4 PD3/INT11/BIN1/TRG3 PD2/INT10/AIN1/TRG2 PD1/INT9/BIN0(I)/TRG1 PD0/INT8/AIN0(I)/TRG0 PC7/INT7/CS3 PC6/INT6/CS2 PC5/INT5/CS1 PC4/INT4/CS0 PC3/INT3 PC2/INT2 PC1/INT1 PC0/INT0(I) 16-bit Reload Timer 4ch RAM 2KB 16-bit Free RUN Timer 1ch ROM 510KB 16-bit PPG 6ch P O R T H (6) P O R T I (6) P O R T J (2) 16-bit OSC (2) P O R T D (8) 4ch P O R T 16-bit K Input Capture Clock Control A/D DMAC UART 4ch UTIMER 4ch Output Compare Interrupt 8ch 8-bit Up/Down Counter P O R T C (8) (8) Controller 10-bit 8input A/D converter External Interrupt I 2C Interface 16ch1ch P O R T F 2ch (5) 8-bit 3output D/A converter I 2C Interface X0A X1A OSC (2) D A (3) Clock PE7/OC7 PE6/OC6 PE5/OC5 PE4/OC4 PE3/OC3 PE2/OC2 PE1/OC1 PE0/OC0 Output Compare PG5/PPG5 PG4/PPG4 PG3/PPG3 PG2/PPG2 PG1/PPG1 PG0/PPG0 PPG PH0/SIN0 PH1/SOT0 PH2/SCK0/TO0 PH3/SIN1 PH4/SOT1 PH5/SCK1/TO1 PI0/SIN2 PI1/SOT2 PI2/SCK2/TO2 PI3/SIN3 PI4/SOT3 PI5/SCK3/TO3 PJ0/SCL PJ1/SDA PK0/AN0 PK1/AN1 PK2/AN2 PK3/AN3 PK4/AN4 PK5/AN5 PK6/AN6 PK7/AN7 PF4 PF3/IN3 PF2/IN2 PF1/IN1 PF0/IN0 UART TOX: Reload Timer I 2C A/D Input Capture DA2 DA1 DA0 1ch 5 CHAPTER 1 OVERVIEW OF THE MB91150 ■ Block Diagram for MB91154 Figure 1.2-2 is a block diagram for the MB91154. Figure 1.2-2 Block Diagram (MB91154) M O D E MD0 MD1 MD2 RST FR30 CPU Core D-bus I-bus (4) Calendar … … … P50/A08 P47/A07 DMAC 8ch P O R T 6 / 5 / 4 Bit Search D-bus R-bus P O R T E (8) P O R T G (6) … Address Data RAM 20KB (16) P20/D16 P67/A23(O) P60/A16 P57/A15 P O R T 3 / 2 … P30/D24 P27/D23 … DATA … … P37/D31(IO) P40/A00 P86/CLK(O) P85/WR1(O) Bus P84/WR0 Control P83/RD(O) P82/BRQ(I) P81/BGRNT(O) P80/RDY(I) DMAC Clock PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0(O) PL1/DACK0(O) PL0/DREQ0(I) X0 (I) X1 (I) (24) P O R T 8 D-bus I-bus C-bus External Bus CTL (7) L 16-bit Reload Timer 4ch RAM 2KB P O R T UART 4ch UTIMER 4ch 16-bit Free RUN Timer 1ch ROM 384KB 16-bit PPG 6ch (8) Input Capture DMAC Up/Down Counter External Interrupt 6 PD7/INT15/ATG(I) PD6/INT14/DEOP2 PD5/INT13/ZIN1/TRG5 PD4/INT12/ZIN0/TRG4 PD3/INT11/BIN1/TRG3 PD2/INT10/AIN1/TRG2 PD1/INT9/BIN0(I)/TRG1 PD0/INT8/AIN0(I)/TRG0 PC7/INT7/CS3 PC6/INT6/CS2 PC5/INT5/CS1 PC4/INT4/CS0 PC3/INT3 PC2/INT2 PC1/INT1 PC0/INT0(I) H (6) P O R T I (6) P O R T J (2) Clock 4ch P O R T 16-bit K Control A/D P O R T 16-bit OSC (2) P O R T Output Compare Interrupt 10-bit 8input A/D converter 8-bit Up/Down Counter P O R T C (8) (8) Controller D (8) 8ch External I 2CInterrupt Interface 16ch1ch P O R T F 2ch (5) 8-bit 3output D/A converter I 2C Interface 1ch X0A X1A OSC (2) D A (3) Clock PE7/OC7 PE6/OC6 PE5/OC5 PE4/OC4 PE3/OC3 PE2/OC2 PE1/OC1 PE0/OC0 Output Compare PG5/PPG5 PG4/PPG4 PG3/PPG3 PG2/PPG2 PG1/PPG1 PG0/PPG0 PPG PH0/SIN0 PH1/SOT0 PH2/SCK0/TO0 PH3/SIN1 PH4/SOT1 PH5/SCK1/TO1 PI0/SIN2 PI1/SOT2 PI2/SCK2/TO2 PI3/SIN3 PI4/SOT3 PI5/SCK3/TO3 PJ0/SCL PJ1/SDA PK0/AN0 PK1/AN1 PK2/AN2 PK3/AN3 PK4/AN4 PK5/AN5 PK6/AN6 PK7/AN7 PF4 PF3/IN3 PF2/IN2 PF1/IN1 PF0/IN0 DA2 DA1 DA0 UART TOX: Reload Timer I 2C A/D Input Capture CHAPTER 1 OVERVIEW OF THE MB91150 1.3 Package Dimensions Two types of MB91150 packages are provided. ■ Package Dimensions of PGA-299C-A01 (MB91FV150 Only) Figure 1.3-1 Package Dimensions of PGA-299C-A01 299-pin ceramic PGA Lead pitch 2.54mm(100mil) Pin matrix 20 Sealing method Metal seal (PGA-299C-A01) 299-pin ceramic PGA (PGA-299C-A01) 2.41 ± 0.10 (.095 ± .004) 1.65 ± 0.10 (.065 ± .004) 0.46 + 0.13 (.018 + .005 ) 30.48 ± 0.31 (1.200 ± .012) 35.56 ± 0.41 (1.400 ± .016) INDEX AREA 3.94 ± 0.10 (.155 ± .004) 52.32 ± 0.56 SQ (2.060 ± .022) 5.59 (.220) MAX C 1994 FUJITSU LIMITED R299001SC-2-2 2.54 (.100) MAX 1.27 (.050) DIA TYP (4 PLCS) 48.26 (19.00) REF 2.54 ± 0.25 (.100 ± .010) 1.27 ± 0.25 (.050 ± .010) 3.40 + 0.41 (.134 + .016 ) INDEX AREA Dimensions in mm (inches). 7 CHAPTER 1 OVERVIEW OF THE MB91150 ■ Package Dimensions of FPT-144P-M08 Figure 1.3-2 Package Dimensions of FPT-144P-M08 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) 0.50 mm Package width × package length 20.0 × 20.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX Weight 1.20g Code (Reference) P-LFQFP144-20×20-0.50 Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 22.00±0.20(.866±.008)SQ * 20.00±0.10(.787±.004)SQ 108 Lead pitch 0.145±0.055 (.006±.002) 73 109 72 0.08(.003) Details of "A" part +0.20 1.50 –0.10 +.008 .059 –.004 0˚~8˚ INDEX 144 37 "A" LEAD No. 1 36 0.50(.020) C 8 2003 FUJITSU LIMITED F144019S-c-4-6 0.22±0.05 (.009±.002) 0.08(.003) 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006) (Mounting height) 0.10±0.10 (.004±.004) (Stand off) 0.25(.010) M Dimensions in mm (inches). Note: The values in parentheses are reference values. CHAPTER 1 OVERVIEW OF THE MB91150 ■ Package Dimensions of FPT-144P-M01 (MB91F155A Only) Figure 1.3-3 Package Dimensions of FPT-144P-M01 144-pin plastic QFP Lead pitch 0.65 mm Package width × package length 28 × 28 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 3.85 mm MAX Code (Reference) P-QFP144-28×28-0.65 (FPT-144P-M01) 144-pin plastic QFP (FPT-144P-M01) Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 32.00±0.40(1.260±.016)SQ * 28.00±0.20(1.102±.008)SQ 0.17±0.06 (.007±.002) 73 108 109 72 0.10(.004) Details of "A" part 3.65±0.20 (Mounting height) (.144±.008) 0.25(.010) INDEX 0~8˚ 144 37 1 36 0.65(.026) C "A" 2003 FUJITSU LIMITED F144002S-c-5-5 0.32±0.05 (.013±.002) 0.13(.005) 0.80±0.20 (.031±.008) 0.88±0.15 (.035±.006) +0.10 0.30 –0.25 +.004 .012 –.010 (Stand off) M Dimensions in mm (inches). Note: The values in parentheses are reference values. 9 CHAPTER 1 OVERVIEW OF THE MB91150 1.4 Pin Assignment This section shows the MB91150 pin assignment for each type of package. ■ Pin Assignment of MB91FV150 (PGA-299C-A01) Figure 1.4-1 shows the MB91FV150 (PGA-299C-A01) pin assignment. Table 1.4-1 lists the correspondences between pin numbers and pin names. Figure 1.4-1 Pin Assignment (MB91FV150 (PGA-299C-A01)) 10 3 299 296 293 277 274 270 268 278 275 262 254 247 257 252 250 245 233 230 224 2 298 292 289 286 283 280 276 269 264 263 258 251 248 243 240 237 234 225 221 5 10 4 297 291 287 284 279 271 265 261 256 249 242 239 235 229 228 219 218 8 13 6 300 295 290 285 281 272 267 259 255 246 241 236 231 226 223 215 207 25 16 11 7 1 294 288 282 273 266 260 253 244 238 232 227 222 217 212 202 27 19 15 12 9 220 216 213 209 199 32 23 18 17 14 214 211 210 205 195 34 26 24 21 20 208 206 204 22 33 31 30 28 29 39 38 35 36 37 40 41 43 42 50 44 46 47 48 178 180 181 183 172 53 51 54 56 58 170 171 174 176 184 45 55 60 61 64 164 167 168 173 182 49 59 63 66 70 159 162 165 169 177 52 62 67 72 77 82 88 94 103 110 116 123 133 139 145 153 157 161 166 175 57 65 73 76 81 86 91 96 105 109 117 122 131 136 141 147 151 156 163 158 68 69 78 79 85 89 92 99 106 111 115 121 129 135 138 142 148 154 160 155 71 75 84 87 90 93 98 101 108 113 114 119 126 130 134 137 140 144 150 152 74 80 83 95 100 102 107 97 104 112 125 128 118 120 124 127 132 143 146 149 PGA-299C-A01 201 203 198 197 196 194 200 192 193 191 190 187 (Bottom View) 186 185 188 189 179 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.4-1 Correspondence Between Pin Numbers and Pin Names (MB91FV150 (PGA-299C-A01)) (Device: MB91FV150, Package: PGA-299C-A01) No. 1 2 3 Pin name P20/D16 VSS OPEN No. 51 52 53 Pin name P81/BGRNT P82/BRQ VCC No. 101 102 103 Pin name PK1/AN1 PK2/AN2 PK3/AN3 No. 151 152 153 Pin name PD4/INT12/ZIN0 VSS PD5/INT13/ZIN1 No. 201 202 203 Pin name OPEN OPEN VCC No. 251 252 253 Pin name OPEN OPEN OPEN 4 P21/D17 54 P83/RD 104 OPEN 154 PD6/INT14/DEOP2 204 IHIT3 254 VCC 5 VCC 55 P84/WR0 105 PK4/AN4 155 VCC 205 IHIT2 255 MODEN3 6 7 8 9 10 11 P22/D18 P23/D19 VSS P24/D20 P25/D21 P26/D22 56 57 58 59 60 61 P85/WR1 P86/CLK PL0/DREQ0 PL1/DACK0 PL2/DEOP0 PL3/DREQ1 106 107 108 109 110 111 PK5/AN5 PK6/AN6 PK7/AN7 DAVC DAVS DA0 156 157 158 159 160 161 PD7/INT15/ATG PE0/OC0 VSS PE1/OC1 PE2/OC2 PE3/OC3 206 207 208 209 210 211 IHIT1 IHIT0 OPEN OPEN OPEN VCC 256 257 258 259 260 261 MODEN2 MODEN1 MODEN0 OPEN OPEN OPEN 12 P27/D23 62 PL4/DACK1 112 VSS 162 PE4/OC4 212 MOD31 262 VSS 13 P30/D24 63 PL5/DEOP1 113 DA1 163 PE5/OC5 213 MOD30 263 VCC 14 15 16 P31/D25 P32/D26 P33/D27 64 65 66 PL6/DREQ2 PL7/DACK2 OPEN 114 115 116 DA2 PH0/SIN0 PH1/SOT0 164 165 166 PE6/OC6 PE7/OC7 VCC 214 215 216 MOD29 MOD28 MOD27 264 265 266 TEST X0A X1A 17 P34/D28 67 OPEN 117 PH2/SCK0/T00 167 PF0/IN0 217 MOD26 267 VSS 18 P35/D29 68 VCC 118 PH3/SIN1 168 PF1/IN1 218 VSS 268 OPEN 19 P36/D30 69 OPEN 119 PH4/SOT1 169 PF2/IN2 219 MOD25 269 VCC 20 21 P37/D31 P40/A00 70 71 OPEN VSS 120 121 PH5/SCK1/T01 PI0/SIN2 170 171 PF3/IN3 PF4 220 221 MOD24 VCC 270 271 OPEN OPEN 22 VCC 72 OPEN 122 PI1/SOT2 172 VCC 222 MOD23 272 OPEN 23 24 P41/A01 P42/A02 73 74 OPEN VCC 123 124 PI2/SCK2/T02 PI3/SIN3 173 174 PG0/PPG0 PG1/PPG1 223 224 MOD22 VSS 273 274 OPEN OPEN 25 P43/A03 75 OPEN 125 VCC 175 PG2/PPG2 225 MOD21 275 VCC 26 27 28 29 P44/A04 P45/A05 P46/A06 VSS 76 77 78 79 MD0 MD1 MD2 VCC 126 127 128 129 PI4/SOT3 PI5/SCK3/T03 VSS OPEN 176 177 178 179 PG3/PPG3 PG4/PPG4 PG5/PPG5 VSS 226 227 228 229 MOD20 MOD19 MOD18 MOD17 276 277 278 279 OPEN OPEN VSS OPEN 30 P47/A07 80 VSS 130 OPEN 180 OPEN 230 VCC 280 OPEN 31 32 33 P50/A08 P51/A09 P52/A10 81 82 83 X0 X1 VCC 131 132 133 OPEN OPEN PJ0/SCL 181 182 183 OPEN OPEN OPEN 231 232 233 MOD16 MOD15 VSS 281 282 283 OPEN OPEN OPEN 34 35 36 P53/A11 P54/A12 P55/A13 84 85 86 RST OPEN ICLK 134 135 136 PJ1/SDA VSS PC0/INT0 184 185 186 OPEN OPEN OPEN 234 235 236 MOD14 MOD13 MOD12 284 285 286 OPEN OPEN VCC 37 VCC 87 ICS0 137 PC1/INT1 187 VCC 237 MOD11 287 OPEN 38 39 40 P56/A14 P57/A15 P60/A16 88 89 90 ICS1 ICS2 ICD0 138 139 140 PC2/INT2 PC3/INT3 PC4/INT4/CS0 188 189 190 OPEN OPEN OPEN 238 239 240 MOD10 MOD9 VCC 288 289 290 OPEN OPEN OPEN 41 42 43 P61/A17 P62/A18 P63/A19 91 92 93 ICD1 ICD2 ICD3 141 142 143 PC5/INT5/CS1 PC6/INT6/CS2 VCC 191 192 193 MCLK MRST VCC 241 242 243 MOD8 MOD7 MOD6 291 292 293 OPEN OPEN VCC 44 45 P64/A20 P65/A21 94 95 BREAK AVCC 144 145 PC7/INT7/CS3 PD0/INT8/AIN0 194 195 DHIT5 DHIT4 244 245 MOD5 MOD4 294 295 OPEN OPEN 46 47 48 49 P66/A22 P67/A23 P80/RDY VCC 96 97 98 99 AVRH VSS AVRL AVSS 146 147 148 149 VSS PD1/INT9/BIN0 PD2/INT10/AIN1 VCC 196 197 198 199 DHIT3 DHIT2 DHIT1 DHIT0 246 247 248 249 MOD3 VSS MOD2 MOD1 296 297 298 299 VSS OPEN OPEN VCC 50 VSS 100 PK0/AN0 150 PD3/INT11/BIN1 200 VSS 250 MOD0 300 OPEN 11 CHAPTER 1 OVERVIEW OF THE MB91150 ■ Pin Assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) Figure 1.4-2 shows the MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) pin assignments. 12 AVRL AVRH AVCC DAVC DAVS DA0 DA1 DA2 VCC PL7/DACK2 PL6/DREQ2 PL5/DEOP1 PL4/DACK1 PL3/DREQ1 PL2/DEOP0 PL1/DACK0 PL0/DREQ0 PH0/SIN0 PH1/SOT0 PH2/SCK0/TO0 PH3/SIN1 PH4/SOT1 121 120 119 118 117 116 115 114 113 112 111 110 109 AVSS 131 130 129 128 127 126 125 124 123 122 132 PK2/AN2 PK1/AN1 PK0/AN0 135 134 133 PK5/AN5 PK4/AN4 PK3/AN3 VCC PK7/AN7 PK6/AN6 139 138 137 136 TEST 141 140 X1A X0A 142 144 143 VSS Figure 1.4-2 Pin Assignments (MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01)) P20/D16 1 108 PH5/SCK1/TO1 P21/D17 2 107 PI0/SIN2 P22/D18 3 106 PI1/SOT2 P23/D19 4 105 PI2/SCK2/TO2 P24/D20 5 104 PI3/SIN3 P25/D21 6 103 PI4/SOT3 P26/D22 7 102 PI5/SCK3/TO3 P27/D23 8 101 VSS VSS PJ0/SCL 9 100 P30/D24 10 99 PJ1/SDA P31/D25 11 98 VSS P32/D26 12 97 VCC P33/D27 13 96 PG5/PPG5 P34/D28 14 95 PG4/PPG4 P35/D29 15 94 PG3/PPG3 P36/D30 16 93 PG2/PPG2 92 PG1/PPG1 91 PG0/PPG0 P37/D31 17 P40/A00 18 P41/A01 19 90 PF4 P42/A02 20 89 P43/A03 21 88 PF3/IN3 PF2/IN2 P44/A04 22 87 PF1/IN1 P45/A05 23 86 PF0/IN0 P46/A06 24 85 PE7/OC7 P47/A07 25 84 PE6/OC6 VSS 26 83 PE5/OC5 VCC 27 82 PE4/OC4 P50/A08 28 81 PE3/OC3 P51/A09 29 80 PE2/OC2 P52/A10 30 79 PE1/OC1 P53/A11 31 78 PE0/OC0 P54/A12 32 77 VCC P55/A13 33 76 PD7/ATG/INT15 P56/A14 34 75 PD6/DEOP2/INT14 P57/A15 35 74 PD5/ZIN1/INT13/TRG5 P60/A16 36 73 PD4/ZIN0/INT12/TRG4 Top View 69 70 PD0/AIN0/INT8/TRG0 PD1/BIN0/INT9/TRG1 PD2/AIN1/INT10/TRG2 PD3/BIN1/INT11/TRG3 71 72 60 61 62 63 64 65 66 67 68 47 P82/BRQ P83/RD P84/WR0 PC0/INT0 PC1/INT1 PC2/INT2 PC3/INT3 PC4/INT4/CS0 PC5/INT5/CS1 PC6/INT6/CS2 PC7/INT7/CS3 VCC 45 46 P80/RDY P81/BGRNT X1 X0 VSS 42 43 44 P66/A22 P67/A23 VSS 50 51 52 53 54 55 56 57 58 59 40 41 P64/A20 P65/A21 P85/WR1 P86/CLK MD2 MD1 MD0 RST VCC 39 P63/A19 48 49 37 38 P61/A17 P62/A18 FPT-144P-M08 FPT-144P-M01 CHAPTER 1 OVERVIEW OF THE MB91150 1.5 Pin Functions Table 1.5-1 lists the functions of the MB91150 pins. ■ Functions of the MB91150 Pins Table 1.5-1 Functions of the MB91150 Pins (1/8) Pin No. Pin name Circuit type Function description 1 2 3 4 5 6 7 8 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 C External data bus bit 16 to bit 23 Effective only in external bus 16-bit mode. Can be used as a port in single chip and external bus 8-bit mode. 10 11 12 13 14 15 16 17 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 P37/D31 C External data bus bit 24 to bit 31 Can be used as a port in single chip mode. 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 P40/A00 P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07 P50/A08 P51/A09 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 F External address bus bit 0 to bit 15 Effective in external bus mode. Can be used as a port in single chip mode. 13 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 Pins (2/8) Pin No. Pin name Circuit type 36 37 38 39 40 41 42 43 P60/A16 P61/A17 P62/A18 P63/A19 P64/A20 P65/A21 P66/A22 P67/A23 O External address bus bit 16 to bit 23 Can be used as a port when the address bus is not used. 45 P80/RDY C External RDY input Effective when external RDY input is enabled. "0" is inputted if the bus cycle in progress fails to be completed. Can be used as a port when external RDY input is not used. 46 P81/BGRNT F External bus open acceptance output Effective when external bus open acceptance output is enabled. Outputs L when the external bus is opened. Can be used as a port when external bus open acceptance output is disabled. 47 P82/BRQ C External bus open request input Effective when external bus open request input is enabled. Input "1" to open the external bus. Can be used as a port when external bus open request input is disabled. 48 P83/RD F External bus read strobe output Effective when external bus read strobe output is enabled. Can be used as a port when external bus read strobe output is disabled. 49 P84/WR0 F External bus write strobe output Effective in external bus mode. Can be used as a port in single chip mode. 50 P85/WR1 F External bus write strobe output Effective when MB91150 is in external bus mode and bus width is 16 bits. Can be used as a port when MB91150 is in single chip mode or 8-bit external bus mode. 51 P86/CLK F System clock output Outputs a clock signal that is equal to the operating frequency of the external bus. Can be used as a port when the system clock is not used. 52 53 54 MD2 MD1 MD0 G Connect these pins directly to VCC or VSS. These pins set the basic MCU operation mode. Mode pins 14 Function description CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 Pins (3/8) Pin No. Pin name Circuit type Function description 55 RST B External reset input 57 58 X1 X0 A High-speed clock oscillation pins (16.5 MHz) 60 61 62 63 PC0/INT0 PC1/INT1 PC2/INT2 PC3/INT3 H External interrupt request inputs 0 to 3 These inputs are always in use while the corresponding external interrupts are enabled. Stop port output in advance unless the resulting processing is intentional. This port can be used to release the standby status because its input is enabled even during standby. Can be used as a port when the pin is not used for external interrupt request input. 64 65 66 67 PC4/INT4/CS0 PC5/INT5/CS1 PC6/INT6/CS2 PC7/INT7/CS3 H Used for both chip select outputs and external interrupt request inputs 4 to 7 Can be used for external interrupt request input or as a port when chip select output is disabled. These inputs are always in use while the corresponding external interrupts are enabled. Stop port output in advance unless the resulting processing is intentional. This port can be used to release the standby status because its input is enabled even during standby. Can be used as a port when the pin is not used for external interrupt request input and chip select output. 69 70 71 72 73 74 PD0/AIN0/INT8/TRG0 PD1/BIN0/INT9/TRG1 PD2/AIN1/INT10/TRG2 PD3/BIN1/INT11/TRG3 PD4/ZIN0/INT12/TRG4 PD5/ZIN1/INT13/TRG5 H External interrupt request inputs 8 to 13 These inputs are always in use while the corresponding external interrupts are enabled. Stop port output in advance unless the resulting processing is intentional. [ZIN0, ZIN1] Up/down timer input [TRG0 to TRG5] PPG external trigger input These inputs are always in use while they are enabled. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for external interrupt request input, up/down timer input, and PPG external trigger input. 75 PD6/DEOP2/INT14 H External interrupt request input 14 This input is always in use while the corresponding external interrupt is enabled. Stop port output in advance unless the resulting processing is intentional. [DEOP2] DMA external transfer end output Effective when DMAC external transfer end output specification is enabled. Can be used as a port when the pin is not used for external interrupt request input or DMA external transfer end output. 15 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 Pins (4/8) Pin No. Pin name Circuit type 76 PD7/ATG/INT15 H External interrupt request input 15 This input is always in use while the corresponding external interrupt is enabled. Stop port output in advance unless the resulting processing is intentional. [ATG] A/D converter external trigger input This input is always in use when the pin is selected as the A/D start source. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for external interrupt request input and A/D converter external trigger input. 78 79 80 81 82 83 84 85 PE0/OC0 PE1/OC1 PE2/OC2 PE3/OC3 PE4/OC4 PE5/OC5 PE6/OC6 PE7/OC7 F Output compare output Can be used as a port when output compare output specification is disabled. 86 87 88 89 PF0/IN0 PF1/IN1 PF2/IN2 PF3/IN3 F Input capture input Effective for input with input capture. Can be used as a port when the pin is not used as input capture input. 90 PF4 F General-purpose I/O port 91 92 93 94 95 96 PG0/PPG0 PG1/PPG1 PG2/PPG2 PG3/PPG3 PG4/PPG4 PG5/PPG5 F PPG timer output Effective when PPG timer output specification is enabled. Can be used as a port when PPG timer output specification is disabled. 99 PJ1/SDA Q I2C interface data I/O pin Effective when I2C interface operation is enabled. Set port output to Hi-Z while the I2C interface is operating. Can be used as a port when I2C is not used. 100 PJ0/SCL Q I2C interface I/O pin Effective when I2C interface operation is enabled. Set port output to Hi-Z while the I2C interface is operating. Can be used as a port when I2C is not used. 102 PI5/SCK3/TO3 P UART3 clock I/O, reload timer 3 output Acts as output for reload timer 3 when UART3 clock output is disabled and reload timer 3 output is enabled. Can be used as port when UART3 clock output and reload timer output are disabled. 16 Function description CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 Pins (5/8) Pin No. Pin name Circuit type Function description 103 PI4/SOT3 P UART3 data output Effective when UART3 data output specification is enabled. Can be used as a port when UART3 data output specification is disabled. 104 PI3/SIN3 P UART3 data input This input is always in use while UART3 is performing input processing. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for UART3 data input. 105 PI2/SCK2/TO2 P UART2 clock I/O, reload timer 2 output Acts as output for reload timer 2 when UART2 clock output is disabled and reload timer 2 output is enabled. Can be used as port when UART2 clock output and reload timer output are disabled. 106 PI1/SOT2 P UART2 data output Effective when UART2 data output specification is enabled. Can be used as a port when UART2 data output specification is disabled. 107 PI0/SIN2 P UART2 data input This input is always in use while UART2 is performing input processing. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for UART2 data input. 108 PH5/SCK1/TO1 P UART1 clock I/O, reload timer 1 output Acts as output for reload timer 1 when UART1 clock output is disabled and reload timer 1 output is enabled. Can be used as port when UART1 clock output and reload timer output are disabled. 109 PH4/SOT1 P UART1 data output Effective when UART1 data output specification is enabled. Can be used as a port when UART1 data output specification is disabled. 110 PH3/SIN1 P UART1 data input This input is always in use while UART1 is performing input processing. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for UART1 data input. 17 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 Pins (6/8) Pin No. Pin name Circuit type Function description 111 PH2/SCK0/TO0 P UART0 clock I/O, reload timer 0 output Acts as output for reload timer 0 when UART0 clock output is disabled and reload timer 0 output is enabled. Can be used as port when UART0 clock output and reload timer output are disabled. 112 PH1/SOT0 P UART0 data output Effective when UART0 data output specification is enabled. Can be used as a port when UART0 data output specification is disabled. 113 PH0/SIN0 P UART0 data input This input is always in use while UART0 is performing input processing. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for UART0 data input. 114 PL0/DREQ0 F DMA external transfer request input This pin is always in use when the pin is selected for a DMA controller transfer source. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for DMA external transfer request input. 115 PL1/DACK0 F DMA external transfer request acceptance output Effective when external transfer request acceptance output specification of the DMA controller is enabled. Can be used as a port when external transfer request acceptance output specification of the DMA controller is disabled. 116 PL2/DEOP0 F DMA external transfer end output Effective when external transfer end output specification of the DMA controller is enabled. Can be used as a port when external transfer end output specification of the DMA controller is disabled. 117 PL3/DREQ1 F DMA external transfer request input This pin is always in use when the pin is selected for a DMA controller transfer source. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used for DMA external transfer request input. 118 PL4/DACK1 F DMA external transfer request acceptance output Effective when external transfer request acceptance output specification of the DMA controller is enabled. Can be used as a port when external transfer request acceptance output specification of the DMA controller is disabled. 18 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 Pins (7/8) Pin No. Pin name Circuit type Function description 119 PL5/DEOP1 F DMA external transfer end output Effective when external transfer end output specification of the DMA controller is enabled. Can be used as a port when external transfer end output specification of the DMA controller is disabled. 120 PL6/DREQ2 F DMA external transfer request input This pin is always in use when the pin is selected for a DMA controller transfer source. Stop port output in advance unless the resulting processing is intentional. Can be used as a port when the pin is not used as DMA external transfer request input. 121 PL7/DACK2 F DMA external transfer request acceptance output Effective when external transfer request acceptance output specification of the DMA controller is enabled. Can be used as a port when external transfer request acceptance output specification of the DMA controller is disabled. 123 124 125 DA2 DA1 DA0 - D/A converter output Effective when D/A converter output specification is enabled. 126 DAVS - Power supply pin of D/A converter 127 DAVC - Power supply pin of D/A converter 128 AVCC - VCC power supply for A/D converter 129 AVRH - A/D converter reference voltage (high potential side) Be sure to turn on or off this pin when a potential of AVRH or higher is applied to VCC. 130 AVRL - A/D converter reference voltage (low potential side) 131 AVSS - VSS power supply for A/D converter 132 133 134 135 136 137 138 139 PK0/AN0 PK1/AN1 PK2/AN2 PK3/AN3 PK4/AN4 PK5/AN5 PK6/AN6 PK7/AN7 N A/D converter analog input Effective when the AICR register specifies analog input. Can be used as a port when A/D converter analog input is not used. 141 TEST G Always connect the pin to the VCC power supply. 142 143 X0A X1A K Oscillation pins for low-speed clock frequency (32 kHz) 27, 56, 68, 77, 97, 122, 140 VCC - Power supply pin of digital circuit Be sure to connect the power supply to all VCC pins. 19 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.5-1 Functions of the MB91150 Pins (8/8) Pin No. Pin name 9,26, 44, 59, 98, 101, 144 VSS Circuit type - Function description Ground level of digital circuit Be sure to ground the power supply to all VSS pins. Note: For most of the above pins, port I/O and resource I/O are multiplexed as in xxxx/Pxx. If port and resource outputs compete at these pins, resource output precedes port output. 20 CHAPTER 1 OVERVIEW OF THE MB91150 1.6 I/O Circuit Types Table 1.6-1 shows the MB91150 I/O circuit types. ■ I/O Circuit Types Table 1.6-1 I/O Circuit Types Classification Circuit Remarks • High-speed oscillation circuit (16.5 MHz) Oscillation feedback resistor: about 1 MΩ • CMOS hysteresis input pin CMOS hysteresis input (Without standby control) With pull-up resistance • CMOS level I/O pin CMOS level output CMOS level input (With standby control) IOL=4mA X1 Xout A X0 Standby control signal B Digital input Pout C Nout CMOS input Standby control 21 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.6-1 I/O Circuit Types Classification Circuit Remarks • CMOS hysteresis I/O pin CMOS level output CMOS hysteresis input (With standby control) IOL=4mA • CMOS level input pin CMOS level input (Without standby control) • CMOS hysteresis I/O pin with pull-up control CMOS level output CMOS hysteresis input (Without standby control) IOL=4mA • Clock oscillation circuit (32 kHz) Pout F Nout CMOS Hysteresis input Standby control G Digital input Pull-up control R Pout H Nout CMOS Hysteresis input X1A Xout K 22 X0A CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.6-1 I/O Circuit Types Classification Circuit Remarks Pout • Analog/CMOS level I/O pin CMOS level output CMOS level input (With standby control) Analog input (Analog input is enabled when the bit corresponding AICR register is 1.) IOL=4mA • CMOS hysteresis I/O pin with pull-up control CMOS level output CMOS hysteresis input (With standby control) IOL=4mA • CMOS hysteresis I/O pin with pull-up control CMOS level output (With open-drain control) CMOS hysteresis input (With standby control) IOL=4mA Nout N CMOS input Standby control Analog input Pull-up control R Pout O Nout CMOS Hysteresis input Standby control Pull-up control R P Open-drain control Nout CMOS Hysteresis input Standby control 23 CHAPTER 1 OVERVIEW OF THE MB91150 Table 1.6-1 I/O Circuit Types Classification Circuit Remarks • • • Nout Q CMOS Hysteresis input Standby control 24 Open-drain I/O pin 5 V dielectric strength CMOS hysteresis input (With standby control) IOL=15mA CHAPTER 2 HANDLING THE DEVICE This chapter provides notes on handling the MB91150. 2.1 Notes on Handling Devices 2.2 Notes on Using Devices 2.3 Power-On 25 CHAPTER 2 HANDLING THE DEVICE 2.1 Notes on Handling Devices This section describes latch-up prevention, pin processing, and circuit handling. ■ Latch-up Prevention CMOS ICs may suffer a latch-up when a higher voltage than VCC or a lower voltage than VSS is applied to an input or output pin or when a voltage exceeding the applicable rating is applied between VCC and VSS. This latch-up may rapidly increase power supply current, resulting in thermal damage to an element. For this reason, ensure that the voltage to be applied does not exceed the maximum ratings. ■ Pin Processing ❍ Unused pin processing Leaving unused input pins open may result in a malfunction; pull them up or down. ❍ OPEN pin processing Be sure to open the OPEN pin when using it. ❍ Output pin processing Connecting one output pin with another, connecting an output pin with the power supply, or connecting a large capacity load may cause flow of high current. Over a long period, this condition results in device deterioration. For this reason, ensure that the current does not exceed the maximum ratings. ❍ Mode pins (MD0 to MD2) Connect the MD0 to MD2 pins direct to VCC or VSS when using them. To prevent MB91150 from entering the test mode mistakenly due to noise, make the pattern length between each mode pin and VCC or VSS on a PC board as short as possible and connect these in low impedance. ❍ Power supply pins If there are several VCC and VSS pins, those that must be set to the same potential in the device are connected to each other in device design to prevent such malfunctions as latch-up. To prevent the strobe signal from malfunctioning due to fluctuations in background radiation and increase in ground level current or to observe the total output current regulations, be sure to externally connect all these power supply pins to the power supply and ground. Also, connect the power supply pins from the current supply source to the VCC and VSS pins of this device at low impedance as far as possible. In addition, a ceramic capacitor of about 0.1µF should be connected between VCC and VSS pins near this device as a bypass capacitor. 26 CHAPTER 2 HANDLING THE DEVICE ■ Circuit Handling ❍ Crystal oscillation circuit Noise near the X0, X1, X0A, or X1A pin causes this device to malfunction. Design PC boards so that the X0 and X1 (X0A and X1A) pins, crystal oscillators (or ceramic oscillators), and bypass capacitors to the ground can be placed as close as possible. In the interest of stable operation, it is strongly recommended that a PC board artwork that encloses the surroundings of the X0, X1, X0A, and X1A pins with the ground should be used. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. The MB91FV150 has a feedback resistor in the 32 kHz oscillation circuit (X0A, X1A), but the MB91F155A, MB91155, and MB91154 do not. Therefore, when the clock function is used, connect an external resistor as shown in Figure 2.1-1. Figure 2.1-1 Resistor Connection X0A X0A X1A MB91FV150 X1A MB91F155A MB91155/MB91154 27 CHAPTER 2 HANDLING THE DEVICE 2.2 Notes on Using Devices This section provides notes on using external reset input and external clocks. ■ External Reset Input To securely put the device into the reset state, at least five machine cycles of L level input to the RST pin are required. ■ External Clock When an external clock is used, feed the clock to the X0 pin and antiphase clock to the X1 pin simultaneously. However, when the STOP mode (oscillation stop mode) is also used, the X1 pin stops with H output in STOP mode. To prevent output collision, provide an external resistor of about 1 kΩ. Figure 2.2-1 shows an example of using an external clock. Figure 2.2-1 Example of Using an External Clock X0 X1 MB91150 ■ Notes on During Operation of PLL Clock Mode On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. ■ Watchdog Timer Function The watchdog timer supported by the FR family monitors the program that performs the reset delay operation for a specified time. If the program hangs and the reset delay operation is not performed, the watchdog timer resets the CPU. Therefore, once the watchdog timer is enabled, operation continues until the CPU is reset. As an exception, a reset delay automatically occurs if the CPU stops program execution. For the conditions that apply to this exception, refer to "3.11.8 Watchdog Timer Function". 28 CHAPTER 2 HANDLING THE DEVICE 2.3 Power-On This section provides notes on power-on and notes applicable when the power-on and clock function are not used. ■ Notes on Power-on ❍ Power-on At power-on, be sure to start the RST pin at the L level. After the power supply level becomes the VCC level, wait until the time for at least five cycles of the internal operating clock has elapsed, then set the RST pin to the H level. ❍ Oscillation input At power-on, be sure to continue inputting clock signals until the oscillation stabilization wait status is released. ❍ Power-on reset Be sure to perform a power-on reset to turn on power. Perform a power-on reset also when powering on again if the power supply voltage has dropped to less than the voltage for assuring operation. ❍ Power on order Turn on power in the order of VCC --> AVCC --> AVRH and turn off power in the reverse order. ❍ A/D converter Even when the A/D converter is not used, connect AVCC to the VCC level and AVSS to the VSS level. ❍ D/A converter Even when the D/A converter is not used, connect DAVC to the VCC level and DAVS to the VSS level. ❍ Treatment of unstable power supply voltage or when shutting off power supply When the power supply voltage is lower than the under limit of the operation assurance voltage, initialize a device using one of the following methods because the internal status of the device becomes undefined. • Method 1: Input an external reset for source oscillation of 221 cycles or more. • Method 2: Turn on the power supply from the voltage (VCC = 0.2V or less) that power-on reset occurs. 29 CHAPTER 2 HANDLING THE DEVICE ■ When the Clock Function (Calendar Macro) is not Used When the clock function is not used, arrange the clock oscillation pins as shown in Figure 2.3-1. Figure 2.3-1 Arrangement of Clock Oscillation Pins when the Clock Function is not Used X0A RELEASE X1A MB91150 Note: The crystal oscillator for the clock used in this type of product cannot be stopped by software. 30 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT This chapter provides basic information regarding the architecture, specifications, instructions, and other topics, that is required to understand the CPU core functions of the FR family. 3.1 Memory Space 3.2 CPU Architecture 3.3 Programming Model 3.4 Data Structure 3.5 Word Alignment 3.6 Special Memory Areas 3.7 Overview of Instructions 3.8 EIT (Exception, Interrupt, and Trap) 3.9 Reset Sequence 3.10 Operation Mode 3.11 Clock Generator (Low-Power Consumption Mechanism) 3.12 Low-Power Consumption Mode 31 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.1 Memory Space The logical address space of the FR family is 4G bytes (232 addresses). The CPU accesses this space linearly. ■ Direct Addressing Area The following area of the address space is used for I/O operations. This area is called the direct addressing area. The addresses of the operand can be directly specified in an instruction. The size of the direct area varies depending on the size of data to be accessed as follows: 32 • Byte data access: 000H to 0FFH • Half word data access: 000H to 1FFH • Word data access: 000H to 3FFH CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Memory Map for MB91FV150, MB91F155A and MB91155 Figure 3.1-1 shows the memory map for the MB91FV150, MB91F155A and MB91155. Figure 3.1-1 Memory Map for MB91FV150, MB91F155A and MB91155 External ROM external bus mode Internal ROM external bus mode Single-chip mode 0000 0000 H I/O I/O I/O I/O I/O I/O Access disabled Access disabled Access disabled Built-in RAM 32KB Built-in RAM 32KB Built-in RAM 32KB Access disabled Access disabled Access disabled External area Access disabled Built-in RAM 2KB Built-in RAM 2KB Built-in ROM 510KB Built-in ROM 510KB External area Access disabled Direct addressing area 0000 0400 H I/O map reference 0000 0800 H 0000 1000 H 0000 9000 H 0001 0000 H 0001 0000 H 0008 0000 H External area FFFF FFFFH 0008 0800 H 0010 0000 H FFFF FFFFH Note: Single-chip mode disables access to the external area. 33 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Memory Map for MB91154 Figure 3.1-2 shows the memory map for the MB91154. Figure 3.1-2 MB91154 Memory Map External ROM external bus mode Internal ROM external bus mode Single-chip mode 0000 0000 H I/O I/O I/O I/O I/O I/O Access prohibited Access prohibited Access prohibited Built-in RAM 20KB Built-in RAM 20KB Built-in RAM 20KB Access prohibited Access prohibited Access prohibited External area Access prohibited Built-in RAM 2KB Built-in RAM 2KB Access prohibited Access prohibited Built-in ROM 384KB Built-in ROM 384KB External area Access prohibited Direct addressing area 0000 0400 H I/O map reference 0000 0800 H 0000 1000 H 0000 6000 H 0001 0000 H 0001 0000H External area FFFF FFFFH 0008 0000H Note: Access to the external area is prohibited in single-chip mode. 34 0008 0800H 000A 0000H 0010 0000 H FFFF FFFFH CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.2 CPU Architecture The FR CPU is a high-performance core employing RISC architecture and using highlevel function instructions for insertion. ■ Features ❍ Use of the RISC architecture ❍ Basic instructions, one instruction for one cycle ❍ 32-bit architecture • 32-bit general-purpose registers: 16 ❍ Linear 4G byte memory space ❍ Multiplier mounted • Multiplication of 32 bits x 32 bits: 5 cycles • Multiplication of 16 bits x 16 bits: 3 cycles ❍ Enforced interrupt processing functions • High-speed response (6 cycles) • Multiple interrupts supported • Level mask function (16 levels) ❍ Enforced I/O operation instructions • Memory-to-memory transfer instructions • Bit processing instructions ❍ High code efficiency • Word length of a basic instruction: 16 bits ❍ Low-power consumption • Sleep mode and stop mode 35 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Internal Architecture The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are mutually independent. The bus converter for 32 bits <--> 16 bits is connected to the data bus (D-bus) to provide the interface between the CPU and peripheral resources. The bus converter for Harvard <--> Princeton is connected to both I-bus and D-bus to provide the interface between the CPU and bus controller. Figure 3.2-1 shows the internal architecture of the device. Figure 3.2-1 Internal Architecture FR CPU D-bus I-bus Harvard Princeton 32bits Bus-Converter 16bits Bus-Converter R-bus C-bus Bus-Controller Resource ❍ CPU The FR architecture of 32-bit RISC is compactly implemented in the CPU of this product. The CPU uses the 5-stage instruction pipeline method to execute one instruction per cycle. The pipeline consists of the following stages: • Instruction fetch (IF) : Outputs an instruction address and fetches the instruction. • Instruction decode (ID): Decodes the fetched instruction. Also reads a register. • Execution (EX) • Memory access (MA) : Accesses the memory (loads or stores data in the memory). • Write back (WB) : Executes arithmetic operations. : Writes the arithmetic operation results (or loaded memory data) to the register. Figure 3.2-2 shows the instruction pipeline. 36 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT Figure 3.2-2 Instruction Pipeline CLK Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 WB MA EX ID IF WB MA EX ID IF WB MA EX ID WB MA EX WB MA WB Instructions are not executed out of sequence. In other words, when instruction A enters the pipeline before instruction B, it will reach the write back stage before instruction B. Instructions are generally executed at the speed of one instruction per cycle. However, the following instructions require multiple cycles for their execution: load and store instructions accompanied by memory wait, branch instructions having no delay slot, and instructions having multiple cycles. In addition, the instruction execution speed decreases when the instruction supply is slow. ❍ Bus converter for conversion between 32 bits and 16 bits Provides an interface between the D-bus for high-speed 32-bit access and the R-bus for 16-bit access to enable the CPU to access the built-in peripheral circuits. When a 32-bit access is instructed from the CPU, this bus converter converts it into two 16-bit accesses for R-bus access. Some built-in peripheral circuits have restrictions with respect to the access width. ❍ Bus converter for conversion between Harvard and Princeton architecture Matches instruction and data accesses of the CPU to provide a smooth interface with external buses. The CPU employs the Harvard architecture, in which the instruction and data buses are mutually independent. The bus controller that controls the external buses employs the Princeton architecture and has a single bus. This bus converter assigns priority to instruction and data accesses of the CPU to control accesses to the bus controller. With this function, the order of bus accesses to the outside is always optimized. This bus converter has a two-word write buffer for eliminating the bus wait time of the CPU and a one-word prefetch buffer for fetching instructions. 37 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.3 Programming Model This section describes the basic programming model and each register of the device. ■ Basic Programming Model Figure 3.3-1 shows the basic programming model. Figure 3.3-1 Basic Programming Model 32 bits [Initial value] R0 R1 General-purpose register 38 R12 R13 R14 R15 … … … XXXX XXXX H XXXX XXXX H XXXX XXXX XXXX 0000 AC FP SP XXXX H XXXX H XXXX H 0000 H Program counter Program status Table base register PC PS TBR Return pointer RP XXXX XXXX H System stack pointer SSP 0000 0000 H User stack pointer USP XXXX XXXX H Multiplication or division result register MDH MDL XXXX XXXX H XXXX XXXX H ⎯ ILM ⎯ XXXX XXXX H SCR CCR 000F FC00 H CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ General-purpose Registers Figure 3.3-2 shows the configuration of the general-purpose register. Figure 3.3-2 General-purpose Register Configuration 32 Bits R0 R1 : R12 R13 R14 R15 [Initial value] XXXX XXXX XXXX XXXX : AC FP SP : XXXX XXXX XXXX XXXX XXXX XXXX 00000000 Registers R0 to R15 are general-purpose registers. They are used as accumulators for various types of operation and as for storing memory access pointers. Of the 16 registers, those shown below are supposed to be used for special purposes, and therefore some instructions have been enhanced. • R13: Virtual accumulator • R14: Frame pointer • R15: Stack pointer The initial values of R0 to R14 after resetting are undefined. The initial value of R15 is 00000000H (SSP value). 39 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Program Status (PS) This register stores the program status. It is divided into three parts: ILM, SCR, and CCR. All the undefined bits in the figure are reserved. They always return 0 in read access. Writing operations have no effect. bit 31 20 16 10 8 7 0 PS ILM SCR CCR ❍ Condition code register (CCR) bit 7 bit 6 CCR bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 S I N Z V C [Initial value] --00XXXXB [bit 5] S: Stack flag Specifies the stack pointer to be used as R15. Value Content 0 SSP is used as R15. When EIT is generated, the flag is automatically set to 0. (However, the value to be saved on the stack is the value before clearing.) 1 USP is used as R15. The flag is cleared to 0 by resetting. To execute the RETI instruction, select SSP. [bit 4] I: Interrupt enable flag Allows or prohibits user interrupt requests. Value 0 1 Content Disables user interrupts. The flag is cleared to 0 when an INT instruction is executed. (However, the value to be saved on the stack is the value before clearing.) Enables user interrupts. Masking of user interrupt requests is controlled by the value stored in the ILM. The flag is cleared to 0 by resetting. 40 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT [bit 3] N: Negative flag Indicates the sign when the arithmetic operation result is assumed to be an integer represented in twos-complement form. Value Content 0 Indicates that the result of an arithmetic operation was a positive value. 1 Indicates that the result of an arithmetic operation was a negative value. The initial value after resetting is undefined. [bit 2] Z: Zero flag Indicates whether the result of an arithmetic operation is "0". Value Content 0 Indicates that the result of an arithmetic operation is not 0. 1 Indicates that the result of an arithmetic operation is 0. The initial value after resetting is undefined. [bit 1] V: Overflow flag Indicates whether an overflow occurred as a result of an arithmetic operation, assuming that the operand for the arithmetic operation is an integer represented in twos-complement form. Value Content 0 Indicates that no overflow occurred as the result of an arithmetic operation. 1 Indicates that an overflow occurred as the result of an arithmetic operation. The initial value after resetting is undefined. [bit 0] C: Carry flag Indicates whether a carry or borrow from the highest bit occurred during operation. Value Content 0 Indicates that neither a carry nor borrow occurred. 1 Indicates that a carry or borrow occurred. The initial value after resetting is undefined. 41 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ❍ System condition code register (SCR) The system condition code register (SCR) is configured as follows: SCR bit 10 bit 9 bit 8 D1 D0 T [Initial value] XX0 B [bit 10 and bit 9] D1, D0: Step division flag Stores intermediate data when executing step division. The flag must not be changed during the division operation. When another operation is performed while step division is being executed, the restart of the step division operation is assured by saving and restoring the value of the PS register. The initial status after resetting is undefined. This flag is set after referring a divisor and dividend when a DIV0S instruction is executed. This flag is forcibly cleared by the DIV0U instruction. [bit 8] T: Step trace trap flag Specifies whether to make the step trace trap instruction effective. Value Content 0 Disables the step trace trap instruction. 1 Makes the step trace trap instruction effective. In this case, all user NMIs and user interrupts are disabled. This flag is initialized to 0 by resetting. The emulator uses the step trace trap function. When the emulator is used, the step trace trap function cannot be used in a user program. ❍ ILM bit 20 ILM bit 19 bit 18 bit 17 bit 16 ILM4 ILM3 ILM2 ILM1 ILM0 [Initial value] 01111B This register stores an interrupt level mask value that is used for level masking. An interrupt request to be inputted to the CPU is accepted only when the associated interrupt level is higher than the level indicated by this ILM. The highest level value is 0 (00000B) and the lowest level value is 31 (11111B). Restrictions apply to the value that can be set from programs. If the original values are 16 to 31, the values that can be set as new ones are 16 to 31. When an instruction that sets 0 to 15 is executed, the value that is transferred is the result of adding 16 to the specified value. If the original values are 0 to 15, any value from 0 to 31 can be set. The register value is initialized to 15 (01111B) by resetting. 42 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Program Counter (PC) 31 [Initial value] 0 PC XXXXXXXXH This register indicates the address of the instruction being executed. Bit 0 is set to 0 when updating the PC during instruction execution. Bit 0 may be set to 1 only when an odd address is specified as a branch destination address. However, bit 0 is invalid in this case, and the instruction must be placed at an address that is a multiple of 2. The initial value at reset is undefined. ■ Table Base Register (TBR) 31 [Initial value] 000FFC00H 0 TBR This register stores the starting address of the vector table used for EIT processing. The initial value at reset is 000FFC00H. ■ Return Pointer (RP) 31 [Initial value] XXXXXXXXH 0 RP This register stores the address for return from a subroutine. When the CALL instruction is executed, a PC value is transferred to this register. When the RET instruction is executed, the content of the RP is transferred to the PC. The initial value at reset is undefined. ■ System Stack Pointer (SSP) 31 SSP 0 [Initial value] 00000000H The SSP is a system stack pointer. When the S flag is 0, this register functions as R15. The SSP can be explicitly specified. At EIT generation, this register is also used for the stack pointer specifying the stack for saving the values of the PS and PC. The initial value at reset is 00000000H. 43 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ User Stack Pointer (USP) 31 0 USP [Initial value] XXXXXXXXH The USP is a user stack pointer. When the S flag is 1, this register functions as R15. The USP can be explicitly specified. The initial value at reset is undefined. To use the RETI instruction, use the SSP. ■ Multiplication and Division Result Registers (MDH and MDL) 31 Multiplication and division result register MDH MDL 0 [Initial value] XXXXXXXXH XXXXXXXXH These registers are used for multiplication and division. Each of them is 32 bits long. Their initial values at reset are undefined. ❍ For multiplication For a multiplication of 32 bits x 32 bits, the arithmetic operation result of a 64-bit length is stored in the multiplication and division result storage registers as follows: • MDH: Higher 32 bits • MDL: Lower 32 bits For a multiplication of 16 bits x 16 bits, the result is stored as follows: • MDH: Undefined • MDL: Result of 32 bits ❍ For division At the start of the operation, the dividend is stored in the MDL. When a division is performed by executing the DIV0S, DIV0U, DIV1, DIV2, DIV3, and DIV4 instructions, the result is stored in the MDL and MDH. 44 • MDH: Remainder • MDL: Quotient CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.4 Data Structure The following data structures are used in the FR family: • Bit ordering: Little endian • Byte ordering: Big endian ■ Bit Ordering FR family uses little-endian bit ordering. Figure 3.4-1 shows the bit configuration of data items according to the specified bit ordering. Figure 3.4-1 Bit Configuration of Data Items According to Bit Ordering bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MSB 0 LSB ■ Byte Ordering FR family uses big-endian byte ordering. Figure 3.4-2 shows the byte configuration of data items according to byte ordering. Figure 3.4-2 Byte Configuration According to Byte Ordering MSB bit 31 Memory bit 7 LSB bit 23 bit 15 bit 7 bit 0 10101010 11001100 11111111 00010001 bit 0 10101010 11001100 11111111 Address (n + 3) 0 0 0 1 0 0 0 1 Address n Address (n + 1) Address (n + 2) 45 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.5 Word Alignment Instructions and data are accessed in units of bytes. The address structure depends on the instruction length and data width. ■ Program Access An FR program must be located at an address that is a multiple of "2". Bit 0 of the PC is set to 0 when the PC is updated during instruction execution. Bit 0 of the PC may be set to 1 only when an odd address is specified as a branch destination address. However, bit 0 is invalid in this case, and the instruction must be placed at an address that is a multiple of "2". There is exception allowing odd addresses. ■ Data Access For data access, the FR family performs the following forcible alignment of addresses in accordance with the bandwidth for data access: Word access: Addresses are a multiple of "4" (the lowest two bits are forcibly set to "00".) Half word access: Addresses are a multiple of "2" (the lowest bit is forcibly set to "0".) Byte access: At word or half word data access, some bits are forcibly set to "0" for calculating the effective address. For example, in the addressing mode of @ (R13, Ri), the register value before addition is used for calculation (even if the LSB is "1") and the lower bits of the addition result are masked. Register before the calculation is not masked. [Example] LD @ (R13, R2), R0 R13 R2 00002222H 00000003H Addition result 00002225H +) Lower two bits forcibly masked Address pin 46 00002224H CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.6 Special Memory Areas This section shows a memory map of the MB91150. ■ MB91150 Memory Map The address space for special memory areas is a 32-bit linear space. Figure 3.6-1 shows a memory map of the MB91150. Figure 3.6-1 MB91150 Memory Map 0000 0000H Byte data 0000 0100H Halfword data Direct addressing area 0000 0200H Word data 0000 0400H 000F FC00H Vector table initialization area 000F FFFFH FFFF FFFFH ❍ Direct addressing area The following area of the address space is an I/O area. This area enables an operand address to be directly specified in an instruction by direct addressing. The size of the address area for which direct addressing is possible differs for each data length. • Byte data (8 bits): 000H to 0FFH • Half word data (16 bits): 000H to 1FFH • Word data (32 bits): 000H to 3FFH ❍ Vector table initialization area The area of 000FFC00H to 000FFFFFH is an EIT vector table initialization area. The vector table used for EIT processing can be located at any address by rewriting the contents of the TBR. However, it is located at this address after initialization by reset. 47 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.7 Overview of Instructions In addition to the general RISC instruction system, the FR family supports logical operation instructions and bit operation instructions that were optimized for insertion, and direct addressing instructions. See for the list of the instruction set. Each instruction is at least 16 bits long (some instructions are 32 or 48 bits long), which makes for excellent memory use efficiency. The instruction sets can be divided into the following functional groups: • Arithmetic operation • Load and store • Branch • Logical operation and bit operation • Direct addressing • Others ■ Overview of Instructions ❍ Arithmetic operation This functional group includes the standard arithmetic operation instructions (addition, subtraction, and comparison) and shift instructions (logical shift and arithmetic operation shift). The operations for addition and subtraction that are supported include operations with carry used in multi-word length operations, and operations in which flag values that are used to support address calculation remain unchanged. In addition, multiplication instructions of 32 bits x 32 bits and of 16 bits x 16 bits and the step division instruction of 32 bits divided by 32 bits are provided. The immediate data transfer instructions for setting immediate data in registers and the registerto-register transfer instructions are also provided. The arithmetic operation instructions can use all of the general-purpose registers and multiplication and division registers in the CPU. ❍ Load and store The load and store instructions are used for read and write-accesses to external memory. They are also used for read and write-accesses to the peripheral circuit (I/O) on the chip. The load and store instructions support three types of access lengths: byte, half word and word. In addition to indirect memory addressing between general registers, some instructions support register indirect memory addressing with displacement or with register increment and decrement. ❍ Branch This functional group includes branch, call, interrupt, and return instructions. Some branch instructions have delay slots and others do not, which allows optimization in accordance with usage. Refer to "3.7.1 Branch Instructions with Delay Slots" about details of the branch instructions. 48 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ❍ Logical operation and bit operation The logical operation instructions can perform the logical operations AND, OR, and EOR between general-purpose registers and between a general-purpose register and memory (and I/O). The bit operation instructions can directly change the contents of the memory (and I/O). General register indirect memory addressing is supported. ❍ Direct addressing The direct addressing instructions are used for accesses between I/O and general-purpose registers and between I/O and memory. High-speed and high-efficiency accesses can be implemented by directly specifying an I/O address in an instruction, not by using register indirect memory addressing. Some instructions support register indirect memory addressing with register increment and decrement. ❍ Others The following other instructions are supported: Instructions for setting flags in the PS register, instructions for stack operations, instructions for sign and zero expansion, instructions for function entry and exit that support high-level languages, and instructions for register multiload and multistore. 49 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.7.1 Branch Instructions with Delay Slots This section explains the branch instructions with delay slots. During operations with delay slots, a branch occurs at an instruction immediately after a branch instruction (called a delay slot) before the branch destination instruction is executed. ■ Branch Instructions with Delay Slots The following branch instructions with delay slots are provided: JMP:D BRA:D BC:D BV:D BLE:D @Ri label9 label9 label9 label9 CALL:D BNO:D BNC:D BNV:D BGT:D label12 label9 label9 label9 label9 CALL:D BEQ:D BN:D BLT:D BLS:D @Ri label9 label9 label9 label9 RET:D BNE:D BP:D BGE:D BHI:D label9 label9 label9 label9 ■ Explanation of the Operation for Branch Instructions with Delay Slots During operation with delay slots, a branch occurs after an instruction immediately after the branch instruction (called a delay slot) is executed before a branch destination instruction is executed. A delay slot instruction is executed before the branch operation. Consequently, the execution speed appears to be one cycle. If an effective instruction cannot be placed in a delay slot, the NOP instruction must be placed instead. [Example] ; Instruction list ADD R1, R2 ; BRA:D LABEL ; Branch instruction MOV R2, R3 ; Delay slot: Executed before a branch. ... LABEL : ST R3, @R4 ; Branch destination In a conditional branch instruction, an instruction placed in a delay slot is executed regardless of whether a branch condition is met. For the delayed branch instruction, the execution order of some instructions appears to be reversed. However, this appearance of reversal applies only for the PC update operation. In other operations (register update and reference, etc.), the instructions are executed in the specified order. A specific example is given below. 50 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ❍ Ri to be referred by the JMP:D @Ri or CALL:D @Ri instruction is not affected even if an instruction in a delayed slot updates Ri. [Example] LDI:32 JMP:D LDI:8 ... #Label, R0 @R0 #0, R0 ; Branch to Label ; No effect on the branch destination address ❍ RP to be referred by the RET:D instruction is not affected even if an instruction in a delayed slot updates the RP. [Example] RET:D MOV R8, RP ... ; Branch to the address indicated by the previous value of the RP ; No effect on the return operation ❍ The flag to be referred by the Bcc: D rel instruction is not affected by a delayed slot instruction. [Example] ADD BC:D #1, R0 Overflow ANDCCR #0 ; Flag change ; Branch is made in accordance with the execution result of the above instruction. ; The above branch instruction does not refer this flag update. ... ❍ When an instruction in the delayed slot of the CALL:D instruction refers the RP, the content updated by the CALL:D instruction is read. [Example] CALL:D Label MOV RP, R0 ; Branch after RP is updated ; Transfer of RP as an execution result of the above CALL:D ... 51 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Restrictions on Branch Instructions with Delay Slots ❍ Instructions that can be placed in delay slots Only instructions that satisfy the following conditions can be executed in delay slots: • One-cycle instructions • Instructions other than branch instructions • Instructions that do not affect the operation although the execution order changes A one-cycle instruction is indicated by writing 1, a, b, c, or d in the cycle count column of the instruction list. ❍ Step trace trap No step trace trap occurs between the execution of a branch instruction with the delay slot and the delay slot. ❍ Interrupt and NMI An interrupt and NMI are not accepted between the execution of a branch instruction with the delay slot and the delay slot. ❍ Undefined instruction exception No undefined instruction exception occurs if an undefined instruction exists in the delay slot. In this case, the undefined instruction operates as the NOP instruction. 52 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.7.2 Branch Instructions without a Delay Slot This section explains the branch instructions without delay slot. During operation without a delay slot, the instructions are executed in the order of the instruction list. ■ Branch Instructions without a Delay Slot The following branch instructions without a delay slot are supported: JMP BRA BC BV BLE @Ri label9 label9 label9 label9 CALL BNO BNC BNV BGT label12 label9 label9 label9 label9 CALL BEQ BN BLT BLS @Ri label9 label9 label9 label9 RET BNE BP BGE BHI label9 label9 label9 label9 ■ Explanation of Operation for Branch Instructions without a Delay Slot During operation without a delay slot, the instructions are executed in the order of the instruction list. The succeeding instruction is not executed before a branch. [Example] ; Instruction ADD BRA MOV ... LABEL ST list R1, R2 LABEL R2, R3 ; ; Branch instruction (without a delay slot) ; Not executed R3, @R4 ; Branch destination The execution cycle count of a branch instruction without a delay slot is two cycles for an instruction with a branch and one cycle for an instruction without a branch. This increases the instruction code efficiency as compared with branch instructions with a delay slot for which NOP was specified because an appropriate instruction could not be entered in the delay slot. When an effective instruction can be placed in the delay slot, the operation with a delay slot is selected. If not, the operation without a delay slot is selected. This enables improvements with respect to both execution speed and code efficiency. 53 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.8 EIT (Exception, Interrupt, and Trap) EIT indicates that a program being executed is suspended by an event for the purpose of executing another program. EIT is the generic name for exception, interrupt, and trap. ■ EIT ❍ Exception An exception is an event that is thrown in accordance with the context of program execution. Execution resumes later, starting at the instruction that caused the exception. ❍ Interrupt An interrupt is an event that is thrown by hardware with no relationship to the context of the program execution. ❍ Trap A trap is an event that is thrown in accordance with the context of the program execution. As with system calls, some traps are instructed by the program. Execution resumes, beginning from the instruction following the instruction that caused the trap. ■ EIT Sources The EIT sources are as follows: • Reset • User interrupt (internal source, external interrupt) • Delayed interrupt • Undefined instruction exception • Trap instruction (INT) • Trap instruction (INTE) • Step trace trap • Coprocessor absence trap • Coprocessor error trap ■ Return from EIT Use the RETI instruction to return from EIT. ■ Notes on EIT • Delay slot EIT restrictions apply to the delay slots of branch instructions. For more information, see Section "3.7.1 Branch Instructions with Delay Slots". 54 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.8.1 Interrupt Level The interrupt levels are 0 to 31 and are controlled with five bits. ■ Interrupt Level Table 3.8-1 shows the assignment of each interrupt level. Table 3.8-1 Interrupt Level Interrupt level Binary number Decimal number Interrupt factor 00000 0 - 00001 1 - 00010 2 - 00011 3 - 00100 4 INTE instruction, step trace trap 00101 to 01110 5 to 14 01111 15 10000 to 11110 16 to 30 11111 31 Precautions When the original value of the ILM is 16 to 31, the values in this range cannot be set in the ILM with a program. (System-reserved) (System-reserved: NMI) User interrupt is disabled while making the ILM settings. Interrupt - Interrupt is disabled while making the ICR settings. Operation is possible for levels 16 to 31. Undefined instruction exceptions, coprocessor absence traps, coprocessor error traps, and INT instructions are not affected by the interrupt levels. The level does not change the ILM, either. ■ Level Mask for Interrupts If an interrupt request occurs, the interrupt level of the interrupt source is compared with the level mask value stored in the ILM. When the following condition is met, the interrupt request is masked and is not accepted: Interrupt level of the source greater than or equal to level mask value 55 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.8.2 Interrupt Stack Operation This area is indicated by the system stack pointer (SSP). PC and PS values are saved in, or restored from this area. After an interrupt, the PC is stored at the address indicated by the SSP, and the PS is stored at the address of (SSP + 4). ■ Interrupt Stack Figure 3.8-1 gives an example of using of the interrupt stack. Figure 3.8-1 Interrupt Stack Operation [Example] SSP [Before the interrupt] 80000000H [Example] [After the interrupt] SSP Memory 80000000H 7FFFFFFCH 7FFFFFF8H 56 7FFFFFF8H Memory 80000000H 7FFFFFFCH 7FFFFFF8H PS PC CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.8.3 EIT Vector Table The table base register (TBR) indicates the first address of the EIT vector table. The vector area for EIT is a 1-Kbyte area starting at the address indicated by the table base register (TBR). ■ Vector Table The size per vector is four bytes. The relationship between a vector number and vector address can be expressed as follows: vctadr = TBR + vctofs = TBR + (03FCH - 4 x vct) vctadr: Vector address vctofs: Vector offset vct: Vector number The lower two bits of the addition result are always handled as 00. The area of 000FFC00H to 000FFFFFH is the initial area of the vector table for reset. Some vectors are assigned special functions. Table 3.8-2 shows the vector table for the architecture. 57 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT Table 3.8-2 Vector Table Vector No. Vector address Explanation 0 00H 000FFFFCH Reset 1 01H TBR + 03F8H System-reserved 2 02H TBR + 03F4H System-reserved 3 03H TBR + 03F0H System-reserved 4 04H TBR + 03ECH System-reserved 5 05H TBR + 03E8H System-reserved 6 06H TBR + 03E4H System-reserved 7 07H TBR + 03E0H Coprocessor absence trap 8 08H TBR + 03DCH Coprocessor error trap 9 09H TBR + 03D8H INTE instruction 10 0AH TBR + 03D4H System-reserved 11 0BH TBR + 03D0H Operand break trap 12 0CH TBR + 03CCH Step trace trap 13 0DH TBR + 03C8H System-reserved NMI (for emulator) 14 0EH TBR + 03C4H Undefined instruction exception 15 0FH TBR + 03C0H System-reserved (NMI) 16 10H TBR + 03BCH Interrupt source that can be masked #0 (IRQ0) 17 to 63 11H to 3FH TBR + 03B8H to TBR + 0300H Interrupt source that can be masked #1 (IRQ2) to Interrupt source that can be masked #47 (IRQ47) 64 40H TBR + 02FCH System-reserved (used for REALOS) 65 41H TBR + 02F8H System-reserved (used for REALOS) 66 to 255 42H to FFH TBR + 02F4H to TBR + 0000H INT instruction 58 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.8.4 Multiple EIT Processing If two or more EIT sources occur at the same time, the CPU selects and accepts one EIT source. After executing the EIT sequence, the CPU repeats detecting for EIT sources. If no acceptable EIT source can be found at EIT source detection, the CPU executes the instruction of the handler for the EIT source it accepted last. Therefore, if two or more EIT sources occur at the same time, the handler execution order of the sources depends on the following two elements: • EIT source acceptance priority • How other sources were masked when the source was accepted ■ EIT Source Acceptance Priority EIT source acceptance priority means the order in which a source for EIT sequence execution is selected after the PS and PC are saved, the PC updated as necessary, and other sources masked. The handler of the source previously accepted is not always executed first. Table 3.8-3 shows the EIT source acceptance priority. Table 3.8-3 EIT Source Acceptance Priority and Masking of Other Sources Acceptance priority Source Masking for other sources 1 Reset Other sources are discarded. 2 Undefined instruction exception Canceled INT instruction I flag = 0 3 Coprocessor absence trap None Coprocessor error trap 4 User interrupt ILM = level of the accepted source 5 (NMI) ILM=15 7 INTE instruction ILM=4 8 Step trace trap ILM=4 Table 3.8-4 shows the execution order of the handlers for the concurrent EIT sources, considering the mask processing for other EIT sources after an EIT source is accepted. 59 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT Table 3.8-4 EIT Handler Execution Order Handler execution order Source 1 Reset*1 2 Undefined instruction exception 3 Step trace trap*2 4 INTE instruction*2 5 (NMI) 6 INT instruction 7 User interrupt Coprocessor absence trap 8 Coprocessor error trap *1: The other sources are discarded. *2: If the INTE instruction is subject to step execution, only the EIT for the step trace trap occurs. Sources caused by INTE are ignored. Figure 3.8-2 gives an example for multiple EIT processing. Figure 3.8-2 Example for Multiple EIT Processing Main routine NMI handler Priority (High) NMI generation INT instruction handler (1) Executed first (Low) INT instruction execution 60 (2) Executed next CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.8.5 EIT Operation This section describes EIT operation. Assume that the PC of the transfer source in the explanation below indicates the address of the instruction for which an EIT source was detected. "Address of the next instruction" means that the instruction for which EIT was detected satisfies the following conditions: • LDI:32: PC + 6 • LDI:20, COPOP, COPLD, COPST, and COPSV: PC + 4 • Other instructions: PC + 2 ■ User Interrupt Operation If a user interrupt request occurs, the system determines whether the request can be accepted in the following order: ❍ Determination of whether the interrupt request can be accepted 1. The interrupt levels of concurrent requests are compared with each other. The request with the highest level (smallest value) is selected. For an interrupt that can be masked, the value stored by the associated ICR is used as the level for comparison. 2. If two or more interrupt requests with the same level occur, the interrupt request having the smallest number is selected. 3. The interrupt level of the selected interrupt request is compared with the level mask value determined by the ILM. • In case the interrupt level is equal to or greater than the level mask value, the interrupt request is masked and is not accepted. • If the interrupt level is smaller than the level mask value, the system proceeds with step 4. 4. When the selected interrupt request can be masked and the I flag is 0, the interrupt request is masked and is not accepted. • If the I flag is 1, the system proceeds with step 5. 5. When the above condition is met, the interrupt request is accepted at a pause of instruction processing. 61 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ❍ Operation When a user interrupt request is accepted at EIT request detection, the CPU operates as shown below while using the interrupt number associated with the accepted interrupt request. The items in parentheses in 1. to 7. below show the address indicated by the register. 1. SSP-4 --> SSP 2. PS --> (SSP) 3. SSP-4 --> SSP 4. Address of the next instruction --> (SSP) 5. Interrupt level of the accepted request --> ILM 6. 0 --> S flag 7. (TBR + vector offset of the accepted interrupt request) --> PC At the end of the interrupt sequence, the CPU detects a new EIT before executing the first instruction of the handler. If there is an acceptable EIT at this time, the CPU proceeds with the EIT processing sequence. ■ Operation for INT Instruction Control branches to the interrupt handler of the vector indicated by INT #u8:u8. Each item in parentheses in 1. to 7. below shows the address indicated by the register. ❍ Operation 1. SSP-4 --> SSP 2. PS --> (SSP) 3. SSP-4 --> SSP 4. PC + 2 --> (SSP) 5. 0 --> I flag 6. 0 --> S flag 7. (TBR + 3FCH - 4 x u8) --> PC 62 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Operation for INTE Instruction Control branches to the interrupt handler of the vector with INTE : vector number 9. Each item in parentheses in 1. to 7. below shows the address indicated by the register. ❍ Operation 1. SSP-4 --> SSP 2. PS --> (SSP) 3. SSP-4 --> SSP 4. PC + 2 --> (SSP) 5. 00100 --> ILM 6. 0 --> S flag 7. (TBR + 3D8H) --> PC Do not use the INTE instruction within another INTE instruction or in the step trace trap processing routine. No EIT is generated by INTE during step execution. ■ Operation for Step Trace Trap If the T flag in SCR of the PS is set and the step trace function is enabled, a trap occurs and a break in processing occurs each time one instruction is executed. ❍ The conditions for detecting a step trace trap are as follows: 1. T flag = 1 2. The instruction in execution is not a delayed branch instruction 3. An operation other than execution of the INTE instruction or the step trace trap processing routine is being executed. 4. When the above conditions are met, a processing break occurs at a pause in operation for the instruction. ❍ Operation Each item in parentheses in 1. to 7. below shows the address indicated by the register. 1. SSP-4 --> SSP 2. PS --> (SSP) 3. SSP-4 --> SSP 4. Address of the next instruction --> (SSP) 5. 00100 --> (ILM) 6. 0 --> S flag 7. (TBR + 3CCH) --> PC When the T flag is set and the step trace trap is enabled, both user NMI and user interrupt are disabled. No EIT is generated by the INTE instruction in this case. 63 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Operation for an Undefined Instruction Exception If an undefined instruction is detected at instruction decoding, an undefined instruction exception occurs. ❍ The conditions for detecting the undefined instruction exception are as follows: 1. An undefined instruction is detected at instruction decoding. 2. The instruction is located outside the delay slot (not immediately after the delayed branch instruction). 3. When the above conditions are met, an undefined instruction exception occurs, causing a break. ❍ Operation Each item in parentheses in 1. to 6. below shows the address indicated by the register. 1. SSP-4 --> SSP 2. PS --> (SSP) 3. SSP-4 --> SSP 4. PC --> (SSP) 5. 0 --> S flag 6. (TBR + 3C4H) --> PC The address of the instruction that detected the undefined instruction exception is saved in the PC. ■ Coprocessor Absence Trap If there is an attempt to execute a coprocessor instruction for a coprocessor that is not mounted, a coprocessor absence trap occurs. ❍ Operation Each item in parentheses in 1. to 6. below shows the address indicated by the register. 1. SSP-4 --> SSP 2. PS --> (SSP) 3. SSP-4 --> SSP 4. Address of the next instruction --> (SSP) 5. 0 --> S flag 6. (TBR + 3E0H) --> PC 64 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Coprocessor Error Trap Assume that an error occurred while the coprocessor was used. When a coprocessor instruction using that coprocessor is executed next, a coprocessor error trap occurs. Note: The MB91150 is not equipped with a coprocessor. ❍ Operation Each item in parentheses in 1. to 6. below shows the address indicated by the register. 1. SSP-4 --> SSP 2. PS --> (SSP) 3. SSP-4 --> SSP 4. Address of the next instruction --> (SSP) 5. 0 --> S flag 6. (TBR + 3DCH) --> PC ■ Operation for RETI Instruction The RETI instruction returns from the EIT processing routine. ❍ Operation Each item in parentheses in 1. to 4. below shows the address indicated by the register. 1. (R15) --> PC 2. R15 + 4 --> R15 3. (R15) --> PS 4. R15 + 4 --> R15 Note that the stack pointer to be referred for restoring the PS and PC is selected in accordance with the content of the S flag. To execute the instruction that manipulates R15 (stack pointer) in the interrupt handler, set the S flag to 1 to use the USP as R15. In this case, be sure to return the S flag to 0 before executing the RETI instruction. 65 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.9 Reset Sequence This section describes the reset operation for placing the CPU in operation status. ■ Reset Sources The causes for reset are as follows: • Input from an external reset pin • Software reset by the SRST bit operation of the standby control register (STCR) • Count-up of the watchdog timer • Power-on reset ■ Initialization by Reset If a reset source occurs, the CPU is initialized. ❍ Releasing the reset source from an external reset pin or software reset • Set the pin to the specified status. • Set each resource in the device to reset status. The control register is initialized to the predetermined value. • The slowest gear is selected as a clock. ■ Reset Sequence When a reset source is released, the CPU executes the following reset sequence: (000FFFFCH) --> PC Note: After reset, the operating mode must be set via the mode register. 66 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.10 Operation Mode The FR family controls the operation mode using the mode pins (MD2, MD1, MD0) and mode register (MODR). ■ Operation Mode Two operation modes, bus mode and access mode, are used. Bus mode Access mode Single chip Internal ROM external bus 32-bit bus width 16-bit bus width 8-bit bus width External ROM external bus ❍ Bus mode In bus mode, the FR series controls the operations of the internal ROM and external access function. The mode setting pins (MD2, MD1, MD0) and the M1 and M0 bits of the mode register (MODR) are used to specify the bus mode. ❍ Access mode In access mode, the FR series controls the width of the external data bus. The mode setting pins (MD2, MD1, MD0) and BW1 and BW0 bits of AMD0, AMD1, AMD32, AMD4, and AMD5 address mode registers are used to specify the access mode. ■ Mode Pins Three pins MD2, MD1, and MD0 are used to specify operation modes as shown in Table 3.10-1. Table 3.10-1 Mode Pins and Setting Mode Mode pin Mode name Reset vector access area Width of external data bus MD2 MD1 MD0 0 0 0 External vector mode 0 External 8 bits 0 0 1 External vector mode 1 External 16 bits 0 1 0 External vector mode 2 External 32 bits Cannot be used in this model 0 1 1 Internal vector mode Internal (Mode register) Single chip mode 1 - - - - External ROM external bus mode - Cannot be used 67 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Mode Data The data written at "0000 07FFH" by the CPU after a reset is called mode data. A mode register (MODR) is allocated at "0000 07FFH". After data is set in this register, the system runs in the mode specified by this register. Data can be written to the mode register only once after resetting. The setting in this register becomes effective immediately after writing. bit MODR 7 6 M1 5 M0 * 4 3 * 2 * * 1 * 0 Initial value Access * XXXXXXXXB W Address : 0000 07FFH Bus mode setting bits [bit 7, bit 6] M1, M0 These bits set the bus mode. Specify the bus mode to be used after mode register writing. M1 M0 Function 0 0 Single chip mode 0 1 Internal ROM external bus mode 1 0 External ROM external bus mode 1 1 - Remarks This setting is not allowed [bit 5 to bit 0] * These bits are reserved for the system. Note: Keep these bits set to 0. ❍ Notes on writing to MODR Before writing to MODR, be sure to set AMD0-AMD5 to decide the bus width of each chip select (CS) area. MODR has no bits for setting the bus width. As for bus width, the value set for mode pins MD2 to MD0 is effective before MDR writing, and the value set in BW1 and BW0 of AMD0-AMD5 is effective after MODR writing. For instance, an external reset vector is normally handled in Area 0 (in which CS0 is active) and the bus width is determined by mode pins MD2 to MD0. Suppose MD2 to MD0 are set to determine the bus width as 32 bits or 16 bits, while nothing is set in AMD0 (default bus width of 8 bits). If MODR is written under this condition, area 0 enters 8-bit bus mode, which results in a malfunction. To prevent this problem, always set AMD0-AMD5 before writing to MODR. MODR writing RST (reset) Bus width specification: MD2 to MD0 → BW1, 0 of AMD0-AMD5 68 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11 Clock Generator (Low-Power Consumption Mechanism) The clock generator is a module for the following functions: • CPU clock generation (this includes the gear function) • Peripheral clock generation (this includes the gear function) • Generating resets and storing sources • Standby function • Built-in PLL (multiplication circuit) ■ Register Configuration of Clock Generator Figure 3.11-1 shows the registers of the clock generator. Figure 3.11-1 Registers of the Clock Generator Address 000480 H 000481 H 000482 H 000483 H 000484 H 000485 H 000488 H 7 0 RSRR/WTCR STCR PDRR CTBR GCR WPR PCTR Reset source and watchdog cycle control register Standby control register DMA request suppression register Timebase timer clear register Gear control register Watchdog reset generation delay register PLL control register 69 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Block Diagram of the Clock Generator Figure 3.11-2 shows the block diagram of the clock generator. Figure 3.11-2 Block Diagram of the Clock Generator [Gear control block] GCR register CPU gear Peripheral gear 1/2 Oscillation circuit X0 X1 PLL M P X Internal clock generation circuit CPU Clock Internal bus clock Internal peripheral clock [Stop and sleep control block] Internal interrupt Internal reset STCR register DMA request PDRR register STOP status SLEEP status CPU hold request Status transition control circuit Reset generation F/F Power-on detection circuit [Reset source circuit] VCC R GND RSRR register RST pin [Watchdog control block] WPR register Watchdog F/F Count clock CTBR register Timebase timer 70 Internal reset CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.1 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) The reset source register (RSRR) is used to store the type of the generated reset. The watchdog cycle control register (WTCR) is used to specify the cycle of the watchdog timer. ■ Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) The reset source register (RSRR) and watchdog cycle control register (WTCR) are configured as follows: bit RSRR/WTCR 7 PONR 6 5 WDOG 4 ERST 3 SRST 2 1 WT1 0 WT0 000480H ( R ) ( − ) (R ) (R) (R) ( −) ( W) ( W) Initial value after power-on 1-XX X-00B [bit 7]: PONR If this bit is 1, the last reset was a power-on reset, and bits other than this bit are invalid. [bit 6]: (Reserved) This bit is a reserved bit. Its value during read accesses is undefined. [bit 5]: WDOG If this bit is 1, the last reset was a watchdog reset. [bit 4]: ERST If this bit is 1, the last reset was caused by the external reset pin. [bit 3]: SRST If this bit is 1, the last reset was caused by a software reset request. [bit 2]: (Reserved) This bit is reserved. Its value during read accesses is undefined. [bit 1 and bit 0]: WT1 and WT0 These bits specify the watchdog cycle. The relationship between these bits and the cycle to be selected is shown below. These bits are initialized by all resets. 71 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT Minimum interval required for writing to WPR to suppress watchdog reset generation Time from writing the last 5AH to the WPR to watchdog reset generation WT1 WT0 0 0 φ x 215 0 1 φ x 217 φ x 217 to φ x 218 1 0 φ x 219 φ x 219 to φ x 220 1 1 φ x 221 φ x 221 to φ x 222 [Initial value] φ x 215 to φ x 216 However, for GCR CHC = 1, the cycle of φ is two cycles of X0. For GCR CHC = 0, it is one cycle of X0. 72 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.2 Standby Control Register (STCR) The standby control register (STCR) controls standby operation and specifies the oscillation stabilization wait time. ■ Standby Control Register (STCR) The register is configured as follows: bit STCR 000481H 7 STOP ( R/W) 6 SLEP (R/W) 5 HIZX (R/W) 4 3 SRST ( W) OSC1 (R/W) 2 OSC0 (R/W) 1 0 ( - ) ( - ) Initial value 0001 11-- B [bit 7]: STOP If this bit is set to 1, the stop status is entered to stop the internal peripheral clock, internal CPU clock, and oscillation. [bit 6]: SLEP If this bit is set to 1, the standby status is entered to stop the internal CPU clock. If both the STOP bit and this bit are set to 1, the STOP bit is given priority and stop status is entered. [bit 5]: HIZX If the stop status is entered while this bit is 1, the device pin is set to high impedance. [bit 4]: SRST If this bit is set to 0, a software reset request is generated. Its value during read access is undefined. [bit 3 and bit 2]: OSC1 and OSC0 These bits specify the oscillation stabilization wait time. The relationship between these bits and the cycle to be selected is shown below. These bits are initialized by power-on reset and are not affected by other reset sources. OSC1 OSC0 Oscillation stabilization wait time 0 0 φ x 23 80ms x 2 x 8 0 1 φ x 216 1 0 φ x 218 1 1 φ x 213 [Initial value] However, for GCR CHC = 1, the cycle of φ is two cycles of X0. For GCR CHC = 0, it is one cycle of X0. [bit 1 and bit 0]: (Reserved) These bits are reserved. These values during read accesses are undefined. 73 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.3 Timebase Timer Clear Register (CTBR) This register is used to initialize the timebase timer to 0. ■ Timebase Timer Clear Register (CTBR) The register is configured as follows: 7 D7 ( W) CTBR 000483H 6 D6 ( W) 5 D5 ( W) 4 D4 ( W) 3 D3 ( W) 2 D2 ( W) 1 D1 ( W) 0 D0 ( W) Initial value XXXX XXXXB [bit 7 to bit 0]: D7 to D0 If A5H and 5AH are consecutively written to this register, the timebase timer is cleared to "0" immediately after 5AH was written. The value of this register during read accesses is undefined. There are no restrictions with respect to the time between writing A5H and 5AH. Note: If the timebase timer is cleared by using this register, the oscillation stabilization wait interval, watchdog cycle, and peripheral cycle using timebase timer change temporarily. 74 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.4 Gear Control Register (GCR) This register controls the gear function of the CPU and peripheral system clocks. ■ Gear Control Register (GCR) The register is configured as follows: 7 CCK1 ( R/W ) GCR 000484H 4 5 6 CCK0 DBLAK DBLON (R/W ) ( R ) ( R/W ) 3 2 1 PCK1 (R/W) PCK0 (R/W) ( - ) 0 CHC ( R/W) Initial value 110011-1B [bit 7 and bit 6]: CCK1 and CCK0 These bits specify the CPU system gear cycle. The relationship between these bits and the cycle to be selected is shown below. These bits are initialized at reset. CPU machine clock (oscillation: input frequency from X0) CCK1 CCK0 CHC 0 0 0 PLL x 1 0 1 0 PLL x 1/2 1 0 0 PLL x 1/4 1 1 0 PLL x 1/8 0 0 1 Oscillation x 1/2 0 1 1 Oscillation x 1/2 x 1/2 1 0 1 Oscillation x 1/2 x 1/4 1 1 1 Oscillation x 1/2 x 1/8 [Initial value] [bit 5] DBLAK This bit indicates a clock doubler operation status. This bit is read-only, and attempts to access it for writing are ignored. The bit is initialized at reset. A time lag occurs when switching the bus frequency. However, this bit allows checking whether switching was actually performed. DBLAK Internal operating frequency: same as external operating frequency 0 Operating in 1:1 relationship [Initial value] 1 Operating in 2:1 relationship 75 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT [bit 4] DBLON This bit specifies the operation status of the clock doubler. It is initialized at reset. DBLON Internal operating frequency: same as external operating frequency 0 Operating in 1:1 relationship [Initial value] 1 Operating in 2:1 relationship [bit 3 and bit 2]: PCK1 and PCK0 These bits specify the peripheral system gear cycle. The relationship between these bits and the cycle to be selected is shown below. These bits are initialized at reset. Peripheral system machine clock (oscillation: input frequency from X0) PCK1 PCK0 CHC 0 0 0 PLL x 1 0 1 0 PLL x 1/2 1 0 0 PLL x 1/4 1 1 0 PLL x 1/8 0 0 1 Oscillation x 1/2 0 1 1 Oscillation x 1/2 x 1/2 1 0 1 Oscillation x 1/2 x 1/4 1 1 1 Oscillation x 1/2 x 1/8 [Initial value] [bit 0]: CHC This bit specifies the divided-by-2 system or PLL system of the oscillation circuit as the basic clock. Setting this bit to 1 specifies the divided-by-2 system. Setting this bit to 0 specifies the PLL system. 76 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.5 Watchdog Reset Generation Delay Register (WPR) The watchdog reset generation delay register (WPR) is used for clearing the watchdog timer flip-flop. It can delay the watchdog reset generation. ■ Watchdog Reset Generation Delay Register (WPR) The register is configured as follows: Initial value WPR 000485H D7 D6 (W) (W) D5 D4 (W) (W) D3 (W) D2 (W) D1 (W) D0 XXXX XXXXB (W) [bit 7 to bit 0]: D7 to D0 When A5H and 5AH are consecutively written to this register, the watchdog timer flip-flop is cleared to 0 immediately after 5AH in order to delay watchdog reset generation. The value of this register during read accesses is undefined. The time between A5H and 5AH is not restricted. However, if neither of these values is written within the period listed in the table below, a watchdog reset occurs. STCR Minimum interval required for writing to WPR to suppress watchdog reset generation Time from the last time 5AH was written to the WPR to watchdog reset generation WT1 WT0 0 0 φ x 215 φ x 215 to φ x 216 0 1 φ x 217 φ x 217 to φ x 218 1 0 φ x 219 φ x 219 to φ x 220 1 1 φ x 221 φ x 221 to φ x 222 However, for GCR CHC = 1, the cycle of φ is two cycles of X0. For GCR CHC = 0, it is a one cycle of PLL. 77 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.6 DMA Request Suppression Register (PDRR) The DMA request suppression register (PDRR) temporarily suppresses a DMA request so as to enable CPU operation. ■ DMA Request Suppression Register (PDRR) The register is configured as follows: bit PDRR 000482H 15 - 14 - 13 - 12 - 11 D3 10 D2 9 D1 8 D0 (-) (-) (-) (-) (R/W) (R/W) (R/W) ( R/W) Initial value ——0000B [bit 11 to bit 8]: D3 to D0 If these bits are set to a value other than 0, DMA transfer from subsequent DMAs to the CPU is suppressed. Afterwards, DMA can be used only when these bits are set to "0". Note: Do not use the PDRR register alone. Be sure to use it together with HRCL register. 78 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.7 PLL Control Register (PCTR) The PLL control register (PCTR) controls PLL oscillations. The setting of this register can be changed only when GCR CHC is "1". ■ PLL Control Register (PCTR) The PLL control register (PCTR) has the following configuration: bit 15 SLCT1 (R/W) PCTR 000488H 14 SLCT0 (R/W) 13 - 12 - (-) (-) 11 VSTP (R/W) 10 - 9 - 8 - (-) (-) (-) Initial value 00XX0XXXB [bit 15 and bit 14]: SLCT1 and SLCT0 These bits control the multiply ratio of the PLL. They are initialized only at power-on. The setting of these bits indicates the internal operating frequency when GCR CHC is set to 0. SLCT1 SLCT0 Internal operating frequency (oscillation: 16.5 MHz) 0 0 8.25 MHz operation [Initial value] 0 1 16.5 MHz operation 1 X 33.0 MHz operation [bit 13, bit 12, and bit 10 to bit 8]: Reserved Always set these bits to 0. Their values during read access are undefined. [bit 11]: VSTP This bit controls the PLL oscillation. It is initialized at power-on and an external reset. If PLL is used in stopped state, it must be stopped every time the reset is canceled. VSTP PLL operation 0 Oscillation [Initial value] 1 Stop of oscillation Note: When the stop mode is entered, the PLL stops regardless of the setting for this bit. 79 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.8 Watchdog Timer Function The watchdog function can detect a "program crashed" status. Assume that A5H and 5AH could not be written to the watchdog reset delay register within the given time due to a program crash. In this case, the watchdog timer generates a watchdog reset request. ■ Block Diagram of the Watchdog Control Block Figure 3.11-3 shows a block diagram of the watchdog control block. Figure 3.11-3 Block Diagram of the Watchdog Control Block M P X Edge Detect Reset generation F/F Watchdog F/F Timebase timer Latch Status decoder Reset status transition request signal clear CTBR WT1, WT0 Internal reset Status transition control circuit WPR A5&5A RSRR WDOG Internal bus ■ Setting the Watchdog Timer The watchdog timer starts its operation when a value is written to the watchdog control register (WTCR). The interval time of the watchdog timer is set with bits WT1 and WT0. Only the time set in the first writing operation becomes valid as the interval time. Subsequent settings are ignored. [Example] LDI:8 LDI:32 STB 80 #10000000b,R1 ; WT1,0=10 #WTCR,R2 R1,@R2 ; Watchdog activation CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Delaying Reset Generation Once the watchdog timer is activated, the program must periodically write A5H and 5AH to the watchdog reset delay register (WPR). The watchdog reset flip-flop stores the falling edge of the tap selected by the timebase timer. If this flip-flop is not cleared at the second falling edge, a reset is generated. Figure 3.11-4 shows the timing of watchdog timer operation. Figure 3.11-4 Timing of Watchdog Timer Operation Timebase timer overflow Watchdog flip-flop WPR write Watchdog activation Watchdog clear Watchdog reset generation ■ Causes of Reset Delays Other than Programs The watchdog timer automatically delays the reset generation by the following causes. 1. Stop or sleep state 2. DMA transfer 3. A break occurs when the emulator debugger or the monitor debugger is being used. 4. The INTE instruction is executed. 5. Step trace trap (a break occurs at each instruction by specifying 1 for T in the PS register) Notes: • There is no rule for the writing interval between the first A5H and the next 5AH. The watchdog reset can be delayed only when the interval between two instances of writing 5AH is within the time specified by the WT1, WT0 bit and A5H is written at least once between these two instances of writing 5AH. • If a value other than 5AH is written after the first A5H, the first A5H written is invalidated. In this case, A5H must be written again. ■ Timebase Timer The timebase timer is used for supplying clock pulses to the watchdog timer and for waiting for oscillation stabilization. For GCR:CHC = 1, the cycle of the operating clock φ is two cycles of X0. For GCR:CHC = 0, it is one cycle of X0. Figure 3.11-5 shows the configuration of the timebase timer. Figure 3.11-5 Timebase Timer Configuration 1/21 1/2 2 1/2 3 . . . . . . 1/2 18 1/2 19 1/2 20 1/2 21 81 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.9 Gear Function The gear function allows the elimination of some clock pulses from clock signals. It has two independent circuits: A CPU and a peripheral circuit. These circuits allow the exchange of data between the CPU and peripherals even when the gear ratio is different. This function also allows to specify whether to use the same clock cycle as that of the oscillation circuit or that from the divided-by-2 circuit. ■ Block Diagram of the Gear Control Block Figure 3.11-6 shows a block diagram of the gear control block. Figure 3.11-6 Block Diagram of the Gear Control Block CPU clock system gear interval generation circuit CCK1, CCK0 Internal bus PCK1, PCK0 CHC Oscillation circuit 1/2 (2 multiplication) PLL Selection circuit X0 X1 Peripheral clock system gear interval generation circuit Internal clock generation circuit selection circuit CPU system gear interval indication signal Peripheral system gear interval specification signal 82 CPU clock Internal bus clock Internal peripheral clock CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Settings of the Gear Function For the CPU clock control, the desired gear ratio can be set by setting the CCK1 and CCK0 bits of the gear control register (GCR) to the desired values. For the peripheral clock control, the desired gear ratio can be set by setting the PCK1 and PCK0 bits of that register to the desired values. [Example 1] LDI:32 #GCR,R2 LDI:8 #11111100b,R1 ; CCK=11,PCK=11,CHC=0 STB R1,@R2 ; CPU clock=1/8f, Peripheral clock=1/8f, f=direct LDI:8 #01111000b,R1 ; CCK=01,PCK=10,CHC=0 STB R1,@R2 ; CPU clock=1/2f, Peripheral clock=1/4f, f=direct LDI:8 #00111000b,R1 ; CCK=00,PCK=10,CHC=0 STB R1,@R2 ; CPU clock=f, Peripheral clock=1/4f, f=direct LDI:8 #00110000b,R1 ; CCK=00,PCK=00,CHC=0 STB R1,@R2 ; CPU clock=f, Peripheral clock=f, f=direct LDI:8 #10110000b,R1 ; CCK=10,PCK=00,CHC=0 STB R1,@R2 ; CPU clock=1/4f, Peripheral clock=f, f=direct When the CHC bit of the gear control register is set to 1, the output of the divided-by-2 circuit is selected as the original clock. When it is set to 0, the same clock cycle as that from the oscillation circuit is used. To switch the original clock, the change with respect to the CPU and peripheral system is made at the same time. [Example 2] LDI:8 LDI:32 STB LDI:8 STB LDI:8 STB #01110001b,R1 #GCR,R2 R1,@R2 #00110001b,R1 R1,@R2 #00110000b,R1 R1,@R2 ; CCK=01,PCK=00,CHC=1 ; ; ; ; ; CPU clock=1/2f, Peripheral clock=f, f=1/2xtal CCK=00,PCK=00,CHC=1 CPU clock=f, Peripheral clock=f, f=1/2xtal CCK=00,PCK=00,CHC=0 CPU clock=f, Peripheral clock=f, f=direct Figure 3.11-7 shows the timing for gear switching. Figure 3.11-7 Timing for Gear Switching Original clock CPU clock (a) CPU clock (b) Peripheral clock (a) Peripheral clock (b) CHC CCK value PCK value 01 00 00 83 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.10 Retaining a Reset Source The reset source retention circuit stores the last generated reset source. All related flags are set to 0 during a read access. A source flag that was set remains as long as it is not read. ■ Block Diagram of the Reset Source Retention Circuit Figure 3.11-8 shows the block diagram of the reset source retention circuit. Power-on detection PONR PONR WDOG WDOG ERST ERST SRST SRST watch-dog Timer reset detect Circuit RST pin Reset input circuit Internal bus Figure 3.11-8 Block Diagram of the Reset Source Retention Circuit SRST Status transition circuit decoder .or. ■ Setting No special setting is required to use this function. Set the instruction for reading the reset source register and the instruction for branching to an appropriate program at the beginning of the program to be stored at the reset entry address. [Example] RESET-ENTRY LDI:32 #RSRR,R10 LDI:8 #10000000B,R2 LDUB @R10,R1 MOV R1,R10 AND R2,R10 BNE PONR-RESET LSR #1,R2 MOV R1,R10 AND R2,R10 BNE WDOG-RESET ... 84 ; GET RSRR VALUE INTO R1 ; R10 USED AS A TEMPORARY REGISTER ; WAS PONR RESET? ; POINT NEXT BIT ; R10 USED AS A TEMPORARY REGISTER ; WAS WATCH DOG RESET? CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT Notes: • If the PONR bit is "1", consider the other bits as being undefined. When a check of reset sources is to be performed afterwards, be sure to place the instruction for confirming power-on reset at the beginning. • Any reset source check other than a power-on reset check can be performed at any location. The priority of the sources depends on the order in which the check was performed. 85 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.11.11 Example of Setting the PLL Clock This section gives an example of setting the PLL clock and also provides an example of the related assembler source code. ■ Example of Setting the PLL Clock Figure 3.11-9 gives an example of the procedure for switching to 33-MHz operation using the PLL. Figure 3.11-9 Example of Setting the PLL Clock CHC = 1 Yes DBLON = 1 Yes No Before making the PLL-related settings, be sure to switch to the clock signal of the divided-by-2 system. CHC <-- 1 No DBLON <-- 1 DBLAK = 1 No The gear is fixed to CPU = 1/1 by setting the doubler to ON. The peripheral system can be set arbitrarily. (Note: If no external bus is used, the doubler need not be used. In this case, the CPU gear can arbitrarily be set as well.) Yes VSTP = 0 Yes No VSTP <-- 0 If the PLL stops, it restarts automatically. However, for PLL restart, the software needs a stabilization wait time of 300 s or more. WAIT 300 s SLCT1 <-- 1 CHC <-- 0 86 The output tap from the PLL is switched to 33 MHz. The clock is switched from the divided-by-2 system to the PLL system. CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT Notes: • No particular setting order of the DBLON, VSTP, and SLCT1 bits shown here was specified in the example. • For a restart of PLL, be sure to program a wait time of at least 300µs to ensure stabilization by the software. Ensure that the wait time does not become insufficient by cache ON or OFF operations. ■ Reference Chart for the Clock System Figure 3.11-10 shows reference chart for the clock system. Figure 3.11-10 Reference Chart for the Clock System 1/2 16.5MHz Divided by 2 system input PLL system input Oscillation input PLL 1/2 VSTP 1/2 33MHz 16.5MHz SLCT1,0 1x 01 00 1/2 8..25 MHz PCTR register CHC 1 0 CCK1,0 1/1 1/2 1/4 1/8 DBLON CPU system Bus system CPU system gear Peripheral system gear PCK1,0 1/1 1/2 1/4 1/8 Peripheral system GCR register 87 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Example of the Related Assembler Source Code (Example of Switching to the PLL System) ; ******************************************* ; PLL Sample Program ; ******************************************* ; Load Setting Data ldi:20 #GCR, R0 ldi:20 #PCTR,R1 ldi:8 #GCR_MASK,R2 ; GCR_MASK = 0000 0001 b ldi:8 #PCTR_MASK,R3 ; PCTR_MASK = 0000 1000 b ldub @R0,R4 ; read GCR register ldub @R1,R5 ; read PCTR register st PS,@-R15 ; push processor status stilm #0x0 ; disable interrupt ; and R4,R2 beq CHC_0 bra CHC_1 CHC_0: borl #0001B,@r0 ; to 1/2 clock @r0=GCR register CHC_1: call VCO_RUN call DOUBLER_ON PLL_SET_END: ld @R15+,PS ; pop processor status ; ******************************************* ; VCO Setting ; ******************************************* VCO_RUN: st R3,@-R15 ; push R3 ldi:8 #PCTR _MASK,R3 ; PCTR_MASK = 0000 1000 b and R5,R3 ; PCTR->VSTP=1 ? beq LOOP_300US_END ; if VSTP = 0 return st R2, @-R15 ; push R2 for Loop counter bandl #0111B,@r1 ; set VSTP = 0 ldi:20 #0x41A,R2 ; wait 300µS WAIT_300US: ; 300µs = 160ns(6.25MHz) * 7 * 300 (834)cycle add2 #(-1),R2 ; 834h/2 = 41Ah (if cache on) bne WAIT_300US ; ld @R15+,R2 ; Pop R2 LOOP_300US_END: ld @R15+,R3 ; Pop R3 ret ; ******************************************* ; doubler ON ; ******************************************* DOUBLER_ON: borh #0001B,@r0 ; doubler ON LOOP_DBLON1: btsth #0010B,@r0 ; check DBLACK beq LOOP_DBLON1 ; loop while DBLACK = 0 bandl #1110B,@r0 ; to 1/1(PLL) clock nop nop nop nop nop nop ret 88 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.12 Low-Power Consumption Mode The low-power consumption mode has stop and sleep status. ■ Overview of the Stop Status The stop status means a state in which all internal clocks and oscillation circuit operation (except 32 kHz oscillation) are stopped. It can minimize power consumption. To enter the stop status, use an instruction to write to the standby control register (STCR). To return from the stop status, use one of the following methods: • Set an interrupt request (However, there are restrictions with respect to the peripherals that can generate interrupt requests even in stop status.) • Applying the "L" level to the RST pin In stop status, all internal clocks stop. In this state, built-in peripherals other than those that can generate a return interrupt enter stop status. ■ Overview of the Sleep Status The sleep status means a status in which the CPU clock and internal bus clock are stopped. It can suppress power consumption to some extent in a situation in which no CPU operation is required. To enter the sleep status, use an instruction to write to the standby control register (STCR). To return from the sleep status, use one of the following methods: • Setting an interrupt request • Generate a reset source In sleep status, operation of the peripheral clock resumes. This allows releasing an interrupt caused by the built-in circuits for peripherals. 89 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Low-power Consumption Mode Operations Table 3.12-1 lists the low-power consumption mode operations. Table 3.12-1 Low-power Consumption Mode Operations Oscillator Operation status Transition condition Run Internal clock Peripheral Pin O O O Standard CPU and internal bus Peripheral O O Release method Sleep STCR SLEP =1 O X O O O Reset Interrupt Stop STCR STOP =1 X X X X * External reset External interrupt O: Operation X: Stop Note: * : STCR HIZX = 0: The previous status is retained. STCR HIZX = 1: High impedance status is set. 90 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.12.1 Stop Status Stop status means the stoppage of all internal clocks and stoppage of the oscillation circuit. (However, the oscillation of 32kHz is not stopped.) This status allows the minimizing of power consumption. ■ Block Diagram of the Stop Control Block Figure 3.12-1 shows a block diagram of the stop control block. Figure 3.12-1 Block Diagram of the Stop Control Block STOP status transition request signal Stop signal Internal interrupt Internal reset CPU Hold Enable CPU Hold Request STOP status display signal CPU clock generation Internal bus clock generation Internal DMA clock generation Internal peripheral clock generation Clock stop request signal CPU clock Internal clock generation circuit clear Status decoder STOP Status transition control circuit STCR Internal bus Internal bus clock Internal DMA clock External bus clock Internal peripheral clock Clock release request signal 91 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Transition to Stop Status ❍ Method of setting the stop status by using an instruction To enter stop status, set bit 7 of STCR to 1. After a stop request is issued, the CPU enters a status in which it is not using the internal bus. The clocks then stop in the following order: CPU clock --> internal bus clock --> internal DMA clock --> internal peripheral clock The oscillation circuit stops simultaneously with the internal peripheral clock. Note: To enter the stop status by using an instruction, be sure to use the following routines: 1. Before writing to STCR, set the [CCK1, CCK0] and [PCK1, PCK0] bits of GCR to the same value and set the same gear ratios for the CPU system clock and peripheral system clock. 2. In this case, be sure to set the GCR CHC bit to 1 to select the divided-by-2 system clock. Never enter the stop status with the GCR CHC bit set to 0. 3. At least six consecutive NOP instructions are required immediately after writing to STCR. 4. Set the clock doubler to OFF before entering the stop status. [Setting method] LDI:8 LDI:32 STB LDI:8 LDI:32 STB NOP NOP NOP NOP NOP NOP 92 #00000001b,R1 #GCR,R2 R1,@R2 #10010000b,R1 #STCR,R2 R1,@R2 ; CPU=Peripheral gear ratio,CHC=1 ; STOP=1 ; ; ; ; ; ; CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ■ Return from the Stop Status A return from the stop status can be achieved by an interrupt or by reset generation. ❍ Return with an interrupt When the interrupt enable bit for the peripheral function is valid, a return from the stop status is performed by generating a peripheral interrupt. The status changes from stop status to ordinary operation status in the following order: 1. Interrupt generation 2. Restart of oscillation circuit operation 3. Wait for oscillation stabilization 4. Restart of supplying the internal peripheral clock signal after stabilization 5. Restart of supplying the internal bus clock signal 6. Restart of supplying the internal CPU clock signal After the oscillation stabilization wait time elapses, the program is executed as follows: • When the ILM I flag of the CPU permits the level of the generated interrupt: After register saving, the interrupt vector is fetched and then the program is executed from the interrupt processing routine. • When the ILM I flag of the CPU does not allow the level of the generated interrupt: The program is executed from the next instruction after the instruction at which the stop status was entered. ❍ Return with the RST pin The stop status is changed to the ordinary operation status in the following procedure: 1. Applying of the "L" level to the RST pin 2. Internal reset generation 3. Restart of the oscillation circuit operation 4. Wait for the oscillation stabilization 5. Restart of the internal peripheral clock supply after stabilization 6. Restart of the internal bus clock supply 7. Restart of the internal CPU clock supply 8. Fetching the reset vector 9. Restart of the instruction execution from the reset entry address Note: • If an interrupt request was already generated from a peripheral, the stop status is not entered and the writing operation is ignored. • At a reset other than the power-on reset, no internal clock signal is supplied during the oscillation stabilization wait time. Because the power-on reset requires an initialization of all internal status, signals from all internal clocks are supplied. 93 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.12.2 Sleep Status Sleep status means the stoppage of the CPU clock and internal bus clock. This status can reduce power consumption to some extent when no CPU operation is necessary. ■ Block Diagram of the Sleep Control Block Figure 3.12-2 shows a block diagram of the sleep control block. Figure 3.12-2 Block Diagram of the Sleep Control Block clear Internal interrupt Internal reset CPU clock generation Internal bus clock generation Internal DMA clock generation External bus clock generation Internal peripheral clock generation Sleep status display signal Clock stop request signal CPU clock Internal clock generation circuit STCR SLEP Status decoder Internal bus Status transition control circuit Sleep status transition request signal Stop signal Internal bus clock Internal DMA clock External bus clock Internal peripheral clock Clock release request signal ■ Transition to the Sleep Status To enter the sleep status, set bit 7 of STCR to 0 and bit 6 to 1. After a sleep request is issued, the CPU enters a status in which it is not using the internal bus. After this, the clocks stop in the following order: CPU clock --> internal bus clock Note: To enter the sleep status, be sure to use the following routines: 1. Before writing to STCR, set the [CCK1, CCK0] and [PCK1, PCK0] bits of GCR to the same value and then set the gear ratios of the CPU system clock and peripheral system clock to the same value. 2. The value of the GCR CHC bit is arbitrary. 3. At least six consecutive NOP instructions are required immediately after writing to STCR. 94 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT [Setting method] LDI:8 LDI:32 STB LDI:8 LDI:32 STB NOP NOP NOP NOP NOP NOP #11001100b,R1 ; CPU=Peripheral gear ratio(The following is an example of oscillation x 1/8), The value of CHC is arbitrary. #GCR,R2 R1,@R2 #01010000b,R1 ; SLEP=1 #STCR,R2 R1,@R2 ; ; ; ; ; ; ■ Return from the Sleep Status The return from the sleep status can be performed with an interrupt and by reset generation. ❍ Return with an interrupt When the interrupt enable bit for the peripheral function is valid, a return from sleep status is performed by generating a peripheral interrupt. The system changes from sleep status to ordinary operation status in the following order: 1. Interrupt generation 2. Restart of supplying the internal bus clock signal 3. Restart of supplying the internal CPU clock signal After the required clock signals are supplied, the program is executed as follows: • When the ILM I flag of the CPU permits the level of the generated interrupt: After register saving, the interrupt vector is fetched and then the program is executed from the interrupt processing routine. • When the ILM I flag of the CPU does not allow the level of the generated interrupt: The program is executed from the next instruction after the instruction at which the sleep status was entered. 95 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT ❍ Return by a reset request The system status changes from sleep status to ordinary operation status in the following order: 1. Internal reset generation 2. Restart of supplying the internal bus clock signal 3. Restart of supplying the internal CPU clock signal 4. Fetching the reset vector 5. Restart of instruction execution from the reset entry address Notes: 96 • An instruction following the instruction for writing to STCR may be able to complete its operation. So, if an interrupt request cancellation instruction or branch instruction is issued immediately after that instruction, the operation results appear to be other than expected. • If an interrupt request was already generated from a peripheral, sleep status is not entered. • The DMA transfer operation during the sleep status can not be used. Be sure to disable the DMA transfer operation before entering to the sleep status. • Set the clock doubler to OFF before the sleep status is entered. CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 3.12.3 Status Transition of the Low-power Consumption Mode Figure 3.12-3 shows the status transition of the low-power consumption mode. ■ Status Transition of the Low-power Consumption Mode Figure 3.12-3 Status Transition of the Low-power Consumption Mode Power ON Reset status Oscillation stabilization wait Start of main oscillation Start of 32 kHz oscillation (1) Calendar operation CPU in stop status Stop of main oscillation 32 kHz oscillation (2) Reset status Main oscillation 32 kHz oscillation (2) Sleep Main oscillation 32 kHz oscillation (5) (2) Calendar operation Oscillation stabilization CPU in stop status Start of main oscillation 32 kHz oscillation (2) (1) (6) (3) (9) (4) 1/2 division clock operation Main oscillation 32 kHz oscillation (7) (8) (1) (2) (3) (4) (5) (6) (7) (8) (9) End of oscillation stabilization Resetting Cancel of resetting Interrupt External interrupt Stop mode PLL 1/2 frequency division Sleep mode PLL clock operation Main oscillation 32 kHz oscillation (2) 97 CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT 98 CHAPTER 4 BUS INTERFACE This chapter provides an outline of the bus interface and describes bus operation. 4.1 Outline of Bus Interface 4.2 Block Diagram of the Bus Interface 4.3 Registers of the Bus Interface 4.4 Bus Operation 4.5 Bus Timing 4.6 Internal Clock Multiply Operation (Clock Doubler) 4.7 Program Examples for the External Bus 99 CHAPTER 4 BUS INTERFACE 4.1 Outline of Bus Interface The bus interface controls the interface with external memory and external I/O units. ■ Bus Interface Features • 24-bit (16M bytes) address output • A bus width of 16 or 8-bit can be specified • Insertion of programmable automatic memory wait (up to seven cycle) • Support of little-endian mode • Unused addresses and data pins can be used as I/O ports • Use of an external bus exceeding 25 MHz is prohibited. • When a clock doubler is used, the bus speed is half the CPU speed. ■ Chip Select area Six types of chip select areas are provided in the bus interface. Each area can be allocated as desired in minimum units of 64K bytes in a 4G bytes space by using the area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5). Note: Area 0 is allocated in a space other than the areas specified by ASR1 to ASR5. When the system is reset, area 0 is allocated in an external area other than 00010000H to 0005FFFFH. (This model uses only four chip select output pins of chip select areas 0 to 3.) Figure 4.1-1(a) shows an example of allocating areas 1 to 5 in units of 64K bytes from 00100000H to 0014FFFFH. Figure 4.1-1(b) shows an example of allocating area 1 of 512K bytes from 00000000H to 0007FFFFH and areas 2 to 5 in units of 1M bytes from 00100000H to 004FFFFFH. 100 CHAPTER 4 BUS INTERFACE Figure 4.1-1 Examples of Allocating Chip Select Areas 00000000 H 00000000 H 00080000 H CS1 (512K byte) CS0 (512K byte) 00080000 H CS0 (1M byte) 000FFFFF H CS2 (1M byte) 000FFFFFH 001FFFFF H CS1 (64K byte) 0010FFFF H CS3 (1M byte) CS2 (64K byte) 0011FFFF H 002FFFFF H CS3 (64K byte) 0012FFFF H CS4 (1M byte) CS4 (64K byte) 0013FFFF H 003FFFFF H CS5 (64K byte) 0014FFFF H CS5 (1M byte) 004FFFFF H CS0 CS0 (a) (b) ■ Bus Interface The bus interface only operates in a predetermined area in normal bus interface mode. Table 4.1-1 lists the correspondence between each chip select area and usable interface functions. The area mode register (AMD) determines which interface mode is to be used. Table 4.1-1 Usable Interface Mode for Each area Selectable bus interface mode Area Remark Normal bus Time division DRAM 0 O - - - 1 to 3 O - - - 4 to 5 O - - - Note: For the MB91150, time division and DRAM mode cannot be used. ❍ Bus Size Specification The required bus width for each area can be specified by a register. 101 CHAPTER 4 BUS INTERFACE 4.2 Block Diagram of the Bus Interface Figure 4.2-1 shows a block diagram of the bus interface. ■ Bus Interface Block Diagram Figure 4.2-1 Block Diagram of the Bus Interface Block DATA BUS ADDRESS BUS A-Out External write buffer switch read buffer switch DATA Bus DATA BLOCK ADDRESS BLOCK +1 or +2 address buffer External Address Bus shifter inpage comparator ASR AMR External pin control block 4 3 CS0-CS3 RD WR0, WR1 Control of all blocks Registers & Control 102 4 BRQ BGRNT RDY CLK CHAPTER 4 BUS INTERFACE 4.3 Registers of the Bus Interface Figure 4.3-1 shows the registers of the bus interface. ■ Registers of the Bus Interface Figure 4.3-1 Registers of the Bus Interface Address bit 000 60CH 000 60EH 000 610H 000 612H 000 614H 000 616H 000 618H 000 61AH 000 61CH 000 61EH 000 620H 000 622H 000 624H 000 626H 15 8 7 ASR1 AMR1 ASR2 AMR2 ASR3 AMR3 ASR4 AMR4 ASR5 AMR5 DMCR4 DMCR5 DRAM Control Register 4 DRAM Control Register 5 AMD1 AMD4 EPCR1 External Pin Control Register 0 External Pin Control Register 1 MODR Little Endian Register / MODe Register EPCR0 000 628H 000 62AH 000 7FEH RFCR Area Select Register 1 Area Mask Register 1 Area Select Register 2 Area Mask Register 2 Area Select Register 3 Area Mask Register 3 Area Select Register 4 Area Mask Register 4 Area Select Register 5 Area Mask Register 5 Area Mode Register 0 / Area Mode Register 1 Area Mode Register 32 / Area Mode Register 4 Area Mode Register 5 ReFresh Control Register AMD0 AMD32 AMD5 000 62CH 000 62EH 0 LER Note: Since the MB91150 does not have function pins that would correspond to the shaded registers, do not access these registers. 103 CHAPTER 4 BUS INTERFACE 4.3.1 Area Select Registers (ASR) and Area Mask Registers (AMR) The area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5) specify the ranges at which chip select areas 1 to 5 are allocated in address space. ■ Area Select Registers (ASR) and Area Mask Registers (AMR) The configurations of the ASRs and AMRs are as follows. ❍ ASR1 to ASR5 bit 15 ASR1 ASR2 ASR3 ASR4 ASR5 bit 13 bit 12 •••••••• bit 2 bit 1 bit 0 A30 A30 A30 A30 A30 A29 A29 A29 A29 A29 •••• •••••••• •••• •••••••• •••• •••••••• •••• •••••••• •••• •••••••• A18 A18 A18 A18 A18 A17 A17 A17 A17 A17 A16 A16 A16 A16 A16 bit 15 bit 14 bit 13 bit 12 •••••••• bit 2 bit 1 bit 0 A31 A31 A31 A31 A31 A30 A30 A30 A30 A30 A29 A29 A29 A29 A29 •••• •••••••• •••• •••••••• •••• •••••••• •••• •••••••• •••• •••••••• A18 A18 A18 A18 A18 A17 A17 A17 A17 A17 A16 A16 A16 A16 A16 A31 A31 A31 A31 A31 bit 14 Initial value 0001 0002 0003 0004 0005 Access W W W W W ❍ AMR1 to AMR5 AMR1 AMR2 AMR3 AMR4 AMR5 Initial value 0000 0000 0000 0000 0000 Access W W W W W ASR1 to ASR5 and AMR1 to AMR5 specify the ranges at which chip select areas 1 to 5 are allocated in address space. ASR1 to ASR5 specify the higher 16 bits (A31 to A16) of an address and AMR1 to AMR5 mask the corresponding address bits. Each bit of AMR1 to AMR5 indicates "care" if it is set to 0. The bit indicates "don’t care" if it is set to 1. "care" indicates that a value of 0 or 1 in the corresponding ASR bit is treated as such in the selection of the address space. On the other hand, "don’t care" indicates that the address space for both 0 and 1 is selected regardless of the actual value of the corresponding ASR bit. Some examples of chip select area specification with the ASR and AMR are shown below. Example 1 ASR1 = 00000000 00000011B AMR1 = 00000000 00000000B In this example, a 64K bytes area in address space is allocated to area 1 as follows because the ASR1 bits are set to 1 and the corresponding AMR1 bits are set to 0: 00000000 00000011 00000000 00000000B (00030000H) | 00000000 00000011 11111111 11111111B (0003FFFFH) 104 CHAPTER 4 BUS INTERFACE Example 2 ASR2 = 00001111 11111111B AMR2 = 00000000 00000011B In this example, "care" is set for the ASR2 bit when the corresponding AMR2 bit is 0, and a value of "1" or "0" in the ASR2 bits is therefore used as such. When the corresponding AMR2 bit is 1, "don’t care" is set for the ASR2 bit and it does not matter whether the bit value is 0 or 1. Consequently, a 256-KB area is allocated in address space as follows. 00001111 11111100 00000000 00000000B (0FFC0000H) | 00001111 11111111 11111111 11111111B (0FFFFFFFH) Areas 1 to 5 can be allocated in the 4G bytes address space in units of 64K bytes based on the values of ASR1 to ASR5 and AMR1 to AMR5. If area 1 of the areas specified by these registers is accessed through the bus, the output of the corresponding read/write pins (RD, WR0, WR1) is set to the "L" level. Area 0 is allocated at a location excluding the areas specified by ASR1 to ASR5 and AMR1 to AMR5. To be more precise, area 0 is allocated at a location excluding the space from area 1 starting with address 0001000H to area 5 starting with 0005FFFFH according to the initial values of ASR1 to ASR5 and AMR1 to AMR5 when the system is reset. Note: Be sure to ensure that chip select areas do not overlap with each other. Figure 4.3-2 shows an example of mapping chip select areas. Figure 4.3-2 Example of Chip Select area Mapping (Initial value) (Examples 1 and 2) 00000000 00000000 Area 0 00010000 Area 0 Area 1 64K byte 00030000 00020000 Area 2 Area 1 64K byte 00040000 00030000 Area 3 Area 0 64K byte 0FFC0000 00040000 Area 4 64K byte 00050000 Area 2 Area 5 256 K byte 64K byte 10000000 00060000 Area 0 Area 0 FFFFFFFF 64K byte FFFFFFFF 105 CHAPTER 4 BUS INTERFACE 4.3.2 Area Mode Register 0 (AMD0) This register specifies the operating mode of chip select area 0 (area excluding the areas specified by ASR1 to ASR5 and AMR1 to AMR5). Area 0 is selected when the system is reset. ■ Area Mode Register 0 (AMD0) The configuration of area mode register 0 (AMD0) is as follows: bit 7 bit 6 bit 5 AMD0 bit 4 bit 3 bit 2 bit 1 bit 0 BW1 BW0 WTC2 WTC1 WTC0 Initial value - --00111B Access R/W Address : 000 620 H [bit 4 and bit 3]: Bus Width bits (BW1, BW0) BW1 and BW0 specify the bus width of area 1. BW1 BW0 Bus width 0 0 8 bits 0 1 16 bits 1 0 Reserved 1 1 Reserved Note: The initial values of BW1 and BW0 are 0, however, the levels of the MD1 and MD0 pins are read until writing to the MODR during reading. 106 CHAPTER 4 BUS INTERFACE [bit 2 to bit 0]: Wait Cycle bits (WTC2 to WTC0) WTC2 to WTC0 specify the number of wait cycles to be automatically inserted during normal bus interfacing. WTC2 WTC1 WTC0 Number of wait cycles to be inserted 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 Note: WTC2 to WTC0 of AMD0 are set to 111B when the system is reset. Seven wait cycles are automatically inserted when the bus is accessed immediately after the reset is released. Notes: • Be sure to set BW1 and BW0 of the area mode register to be used (AMD0 to AMD5) before writing to the MODR. • After the mode register (MODR) is set, the bus width specified by AMD0 to AMD5 is valid for external areas. • Be sure not to change the settings of BW1 and BW0 after writing to the MODR. Otherwise, operation errors may occur. MODR write RST (reset) The contents of the AMD0 to AMD5 registers are valid. 107 CHAPTER 4 BUS INTERFACE 4.3.3 Area Mode Register 1 (AMD1) This register specifies the operating mode of the chip select area 1 (specified by ASR1 and AMR1). ■ Area Mode Register 1 (AMD1) The configuration of area mode register 1 (AMD1) is as follows: bit 7 AMD1 Address : 000621 H bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value BW1 BW0 WTC2 WTC1 WTC0 0--00000B bit 5 MPX Access R/W [bit 7]: MultiPleX bit (MPX) The MPX controls the time-division I/O interface of address or data input and output. 0 Normal bus interface 1 Setting is prohibited. [bit 4 and bit 3]: Bus Width bits (BW1 and BW0) The BW1 and BW0 specify the bus width of area 1. BW1 BW0 Bus width 0 0 8 bits 0 1 16 bits 1 0 Reserved 1 1 Reserved [bit 2 to bit 0]: Wait Cycle bits (WTC2 to WTC0) WTC2 to WTC0 specify the number of wait cycles to be automatically inserted during normal bus interface operation. This operation is the same as that of WTC2 to WTC0 of AMD0 except that WTC2 to WTC0 are initialized to 000B and the number of wait cycles to be inserted becomes 0 when the system is reset. 108 CHAPTER 4 BUS INTERFACE 4.3.4 Area Mode Register 32 (AMD32) This register specifies the operating mode of chip select area 2 (specified by ASR2 and AMR2) and chip select area 3 (specified by ASR3 and AMR3). BW1 and BW0 bits control the common bus width for areas 2 and 3. The number of wait cycles to be inserted can be set separately for areas 2 and 3. ■ Area Mode Register 32 (AMD32) The configuration of area mode register 32 (AMD32) is as follows: AMD32 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 BW1 BW0 WT32 WT31 WT30 WT22 WT21 WT20 Initial value 00000000B Access R/W Address : 000622 H [bit 7 and bit 6]: Bus Width bits (BW1 and BW0) These bits specify the bus width of areas 2 and 3. BW1 BW0 Bus width 0 0 8 bits 0 1 16 bits 1 0 Reserved 1 1 Reserved [bit 5 to bit 3]: Wait Cycle bits (WT32 to WT30) These bits specify the number of wait cycles to be automatically inserted during memory access of area 3. The operation is the same as that of WTC2 to WTC0 of AMD0 except that these bits are initialized to 000 and the number of wait cycles to be inserted becomes 0 when the system is reset. [bit 2 to bit 0]: Wait Cycle bits (WT22 to WT20) These bits specify the number of wait cycles to be automatically inserted during memory access of area 2. The operation is the same as that of WTC2 to WTC0 of AMD0 except these bits are initialized to 000 and the number of wait cycles to be inserted becomes 0 when the system is reset. 109 CHAPTER 4 BUS INTERFACE 4.3.5 Area Mode Register 4 (AMD4) This register specifies the operating mode of chip select area 4 (specified by ASR4 and AMR4). ■ Area Mode Register 4 (AMD4) The configuration of area mode register 4 (AMD4) is as follows: bit 7 AMD4 Address : 000623 H bit 6 bit 5 DRME bit 4 bit 3 BW1 BW0 bit 2 bit 1 WTC2 WTC1 bit 0 Initial value Access WTC0 0--00000B R/W [bit 7]: DRaM Enable bit (DRME) This bit selects whether to use the normal bus interface or DRAM interface for area 4. 0 Normal bus interface 1 Setting is prohibited. [bit 4 and bit 3]: Bus Width bits (BW1, BW0) These bits specify the bus width of area 4. BW1 BW0 Bus width 0 0 8 bits 0 1 16 bits 1 0 Reserved 1 1 Reserved [bit 2 to bit 0]: Wait Cycle bits (WTC2 to WTC0) These bits specify the number of wait cycles to be automatically inserted during normal bus interface operation. The operation is the same as that of WTC2 to WTC0 of AMD0, except that these bits are initialized to 000B and the number of wait cycles to be inserted becomes 0 when the system is reset. 110 CHAPTER 4 BUS INTERFACE 4.3.6 Area Mode Register 5 (AMD5) This register specifies the operating mode of chip select area 5 (specified by ASR5 and AMR5). ■ Area Mode Register 5 (AMD5) The configuration of area mode register 5 (AMD5) is as follows: bit 7 AMD5 DRME bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value BW1 BW0 WTC2 WTC1 WTC0 0--00000B Access R/W Address : 000624 H Each bit has the same meaning as the corresponding bit of AMD4. See Section "4.3.5 Area Mode Register 4 (AMD4)". 111 CHAPTER 4 BUS INTERFACE 4.3.7 External Pin Control Register 0 (EPCR0) This register controls output of each signal. If output is allowed, a signal is outputted with the required timing in each bus mode. If input is enabled, inputs signal from an external circuit are accepted. If output is inhibited and input is disabled, the corresponding pin can be used as an I/O port. ■ External Pin Control Register 0 (EPCR0) The configuration of external pin control register 0 (EPCR0) is as follows: bit 15 bit 14 bit 13 bit 12 EPCR0 bit 7 bit 6 bit 5 CKE bit 11 bit 10 bit 9 bit 8 WRE RDXE RDYE BRE bit 4 bit 3 bit 2 bit 1 bit 0 COE3 COE2 COE1 COE0 Initial value - -- -1100B Access W Initial value -1111111B Access W Address : 000 628 H [bit 11]: WRite pulse output Enable bit (WRE) This bit selects whether write pulses WR0 and WR1 are to be outputted. The output becomes enabled when the system is reset. 0 Output prohibited 1 Output allowed (initial value) Even if the WRE bit is set to 1, a write pulse can be used as an I/O port, depending on the bus width set by the AMD. (For example, in the 8-bit mode, the WR1 is not outputted and the corresponding pin can be used as an I/O port.) [bit 10]: ReaDX pulse output Enable bit (RDXE) This bit specifies whether read pulse RD is to be outputted. The output becomes enabled when the system is reset. 0 Output inhibited (setting prohibited) 1 Output allowed (initial value) [bit 9]: ReaDY input Enable bit (RDYE) This bit controls RDY input as follows. The input becomes disabled when the system is reset. 112 0 RDY input disabled (initial value) 1 RDY input enabled CHAPTER 4 BUS INTERFACE [bit 8]: Bus Request Enable bit (BRE) This bit controls BRQ and BGRNT as follows. BRQ input is disabled and BGRNT output is inhibited when the system is reset. 0 BRQ input disabled, BGRNT output inhibited (The pins function as I/O ports.) (Initial value) 1 BRQ input enabled, BGRNT output allowed [bit 6]: ClocK output Enable bit (CKE) This bit enables output of the CLK (external bus operating clock waveform) 0 Output inhibited 1 Output allowed (initial value) This bit is initialized to 1 when the system is reset and output of the CLK is allowed. [bit 5, bit 4] These bits are not used. Writing to these bits has no effect. The default value is 1. [bit 3]: Chip select Output Enable (COE3) COE3 controls CS3 output. Output is enabled after resetting. 0 Output prohibited 1 Output allowed (initial value) [bit 2]: Chip select Output Enable (COE2) COE2 controls CS2 output. Output is enabled after resetting. 0 Output prohibited 1 Output allowed (initial value) [bit 1]: Chip select Output Enable (COE1) COE1 controls CS1 output. Output is enabled after resetting. 0 Output prohibited 1 Output allowed (initial value) 113 CHAPTER 4 BUS INTERFACE [bit 0]: Chip select Output Enable (COE0) COE0 controls CS0 output. Output is enabled after resetting. 0 Output prohibited (setting prohibited) 1 Output allowed (initial value) In this model, keep this bit set to 1. 114 CHAPTER 4 BUS INTERFACE 4.3.8 External Pin Control Register 1 (EPCR1) This register controls output of address signals. ■ External Pin Control Register 1 (EPCR1) The configuration of external pin control register 1 (EPCR1) is as follows: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value - -- -----B Access W Initial value 11111111B Access W EPCR1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 Address : 00062A H [bit 7 to bit 0]: Address output Enable 23 to 16 (AE23 to AE16) These bits specify whether the corresponding addresses are to be outputted. If output is inhibited, the pins can be used as I/O ports. 0 Output inhibited 1 Output allowed (initial value) AE23 to AE16 are initialized to FFH when the system is reset. 115 CHAPTER 4 BUS INTERFACE 4.3.9 Little-endian Register (LER) The MB91150 ordinarily accesses the bus while treating all areas as big- endian areas. However, making the required settings in this register enables one of the areas 1 to 5 to be treated as a little-endian area. Note that area 0 cannot be treated as a little-endian area. This register can be written only once after the system is reset. ■ Little-endian Register (LER) The configuration of little-endian register (LER) is as follows: bit 7 bit 6 bit 5 bit 4 LER bit 3 bit 2 bit 1 bit 0 LE2 LE1 LE0 Initial value -----000B Access W Address : 0007FE H [bit 2 to bit 0]: LE2 to LE0 As listed in Table 4.3-1, a little-endian area is specified by the combination of the LE2, LE1, and LE0 bits. Table 4.3-1 Mode Setting by the Combination of the LE2, LE1, and LE0 Bits LE2 LE1 LE0 Mode 0 0 0 Initial value after reset. No little-endian area is set. 0 0 1 Area 1 is set as a little-endian area and areas 0 and 2 to 5 are set as big-endian areas. 0 1 0 Area 2 is set as a little-endian area and areas 0, 1, and 3 to 5 are set as big-endian areas. 0 1 1 Area 3 is set as a little-endian area and areas 0 to 2, 4, and 5 are set as big-endian areas. 1 0 0 Area 4 is set as a little-endian area and areas 0 to 3, and 5 are set as big-endian areas. 1 0 1 Area 5 is set as a little-endian area and areas 0 to 4 are set as big-endian areas. ■ Mode Register (MODR) MODR (MODe Register) For the mode register (MODR), see Section "3.10 Operation Mode". 116 CHAPTER 4 BUS INTERFACE 4.4 Bus Operation This section describes the bus operation based on the following topics: • Relationship between data bus width and control signals • Big-endian bus access • Little-endian bus access • Comparison of external access ■ Relationship Between Data Bus Width and Control Signals The relationship between the data bus width and control signals is described for the normal bus interface. ■ Big-endian Bus Access External access is described based on the following topics: • Data format • Data bus width • External bus access • Example of a connection with external devices ■ Little-endian Bus Access External access is described based on the following topics: • Differences between little-endian and big-endian mode • Data format • Data bus width • Examples of connection with external devices ■ Comparison of External Access in Big-endian and Little-endian Mode Word access, half word access, and byte access are described for the various bus widths to compare external access in big-endian and little-endian mode. 117 CHAPTER 4 BUS INTERFACE 4.4.1 Relationship Between Data Bus Width and Control Signals Control signals WR0 and WR1 always correspond to byte positions of the data bus in a one to one relationship regardless of whether the mode is big-endian or little-endian, and regardless of the data bus width. ■ Relationship Between Data Bus Width and Control Signals The following figure shows the byte positions on the data bus of the MB91150 to be used with the set data bus width and the associated control signals. Figure 4.4-1 Data Bus Width and Control Signals for a Normal Bus Interface (a) 16-bit bus width data bus D31 (b) 8-bit bus width Control signals data bus D31 WR0 Control signals WR0 D24 WR1 D16 (D23 to D16 are not used.) 118 CHAPTER 4 BUS INTERFACE 4.4.2 Bus Access in Big-endian Mode Areas not specified in the LER are accessed through an external bus as a big-endian area. The FR family ordinarily uses big-endian access. ■ Data Format The following figures show the relationship between internal registers and the external data bus for each data format. ❍ Word access (when an LD or ST instruction is executed) Figure 4.4-2 Relationship Between Internal Register and External Data Bus for Word Access Internal register External bus D31 D23 D15 D07 AA AA CC BB BB DD D31 D23 CC DD ❍ Half word access (when an LDUH or STH instruction is executed) Figure 4.4-3 Relationship Between Internal Register and External Data Bus for Half Word Access Internal register External bus D31 AA D23 D15 D07 BB D31 D23 AA BB 119 CHAPTER 4 BUS INTERFACE ❍ Byte access (when an LDUB or STB instruction is executed) Figure 4.4-4 Relationship Between Internal Register and External Data Bus for Byte Access (a) The lower byte of the output address is 0. (b) The lower byte of the output address is 1. Internal register External bus D31 AA D23 Internal register External bus D31 D31 D23 D23 D15 D07 D31 AA D23 D15 D07 AA AA ■ Data Bus Width The following figures show the relationship between internal registers and the external data bus for each data bus width. ❍ Relationship Between Internal Register and External Bus for 16-bit Bus Width Figure 4.4-5 Relationship Between Internal Register and External Data Bus for 16-bit Bus Width Internal register External bus The lower bytes of the output address "00" "10" D31 D23 D15 D07 AA Read/Wr ite BB AA CC BB DD D31 D23 CC DD ❍ Relationship Between Internal Register and External Bus for 8-bit Bus Width Figure 4.4-6 Relationship Between Internal Register and External Data Bus for 8-bit Bus Width Internal register External bus The lower bytes of the internal address "00" "01" "10" "11" D31 D23 D15 D07 120 AA BB CC DD Read/Wr ite AA BB CC DD D31 CHAPTER 4 BUS INTERFACE ■ External Bus Access Figure 4.4-7 and Figure 4.4-8 show external bus accesses under the following conditions: • Data bus width: 16 bits and 8 bits • Data format: Word, halfword, and byte These figures also show the access byte location, program address and output address, and bus access count under each condition. The MB91150 cannot detect misalignment errors. Therefore, for word access, even if the lower two bits of the address specified by a program are 00, 01, 10, or 11, the lower two bits of the output address are always 00. For half word access, 00 is outputted if the two bits are 00 or 01, and 10 is outputted if the bits are 10 or 11. ❍ 16-bit bus width Figure 4.4-7 External Bus Access in Big-endian Mode (16-bit Bus Width) (A) Word access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (2) Output A1/A0 = "10" (2) Output A1/A0 = "10" (2) Output A1/A0 = "10" (2) Output A1/A0 = "10" MSB LSB (1) 00 01 (1) 00 01 (1) 00 01 (1) 00 01 (2) 10 11 (2) 10 11 (2) 10 11 (2) 10 11 16-bit (B) Half-word access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0 = "10" (1) Output A1/A0 = "10" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (1) 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 (C) Byte access (a) PA1/PA0="00" (b) PA1/PA0="01" (c) PA1/PA0="10" (d) PA1/PA0="11" (1) Output A1/A0 = "01" (1) Output A1/A0 = "11" (1) Output A1/A0 = "00" (1) Output A1/A0 = "10" (1) 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 (1) 00 01 10 11 PA1/PA0: The lower two bits of the address specified by a program Output A1/A0: The lower two bits of the address to be outputted : Leading byte position of an address to be outputted + (1) to (4) : Data byte position to be accessed : Bus access count 121 CHAPTER 4 BUS INTERFACE ❍ 8-bit bus width Figure 4.4-8 External Bus Access in Big-endian Mode (8-bit Bus Width) (A) Word access (a)PA1/PA0="00" (b)PA1/PA0="01" (c)PA1/PA0="10" (d)PA1/PA0="11" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (1) Output A1/A0 = "00" (2) Output A1/A0 = "01" (2) Output A1/A0 = "01" (2) Output A1/A0 = "01" (2) Output A1/A0 = "01" (3) Output A1/A0 = "10" (3) Output A1/A0 = "10" (3) Output A1/A0 = "10" (3) Output A1/A0 = "10" (4) Output A1/A0 = "11" (4) Output A1/A0 = "11" (4) Output A1/A0 = "11" (4) Output A1/A0 = "11" MSB LSB (1) 00 (1) 00 (1) 00 (1) 00 (2) 01 (2) 01 (2) 01 (2) 01 (3) 10 (3) 10 (3) 10 (3) 10 (4) 11 (4) 11 (4) 11 (4) 11 8-bit (B) Half-word access (a)PA1/PA0="00" (b)PA1/PA0="01" (c)PA1/PA0="10" (d)PA1/PA0="11" (1) Output A1/A0 = "00" (1) Output A1/A0 = "10" (1) Output A1/A0 = "10" (1) Output A1/A0 = "00" (2) Output A1/A0 = "01" (2) Output A1/A0 = "11" (2) Output A1/A0 = "11" (2) Output A1/A0 = "01" (1) 00 (1) 00 00 00 (2) 01 (2) 01 01 01 10 10 (1) 10 (1) 10 11 11 (2) 11 (2) 11 (C) Byte access (a)PA1/PA0="00" (b)PA1/PA0="01" (c)PA1/PA0="10" (d)PA1/PA0="11" (1) Output A1/A0 = "11" (1) Output A1/A0 = "00" (1) Output A1/A0 = "01" (1) Output A1/A0 = "10" (1) 00 01 (1) 00 00 00 01 01 01 10 10 10 10 11 11 PA1/PA0: the lower two bits of the address specified by a program Output A1/A0: the lower two bits of the address to be outputted : Leading byte position of an address to be outputted + (1) to (4) 122 : Data byte position to be accessed : Bus access count (1) 11 (1) 11 CHAPTER 4 BUS INTERFACE ■ Example of Connection with External Devices Figure 4.4-9 shows an example of connecting the MB91150 with external devices. Figure 4.4-9 Example of a Connection Between the MB91150 and External Devices MB91150 D31 D24 D23 WR0 0 D15 D16 WR1 *) For 16- and 8-bit devices, the data bus on the side of the MSB is used. 1 D08 D07 D00 *) 16-bit device X D07 D00 *) 8-bit device (0 = the lowest bit of the address. X indicates that it does not matter whether the lowest bit of the address is 0 or 1.) 123 CHAPTER 4 BUS INTERFACE 4.4.3 Bus Access in Little-endian Mode An area specified in the LER is accessed as a little-endian area through the external bus. The MB91150 accesses a little-endian area in the same bus access operation as for a big-endian area. The order of output addresses and control signals are basically the same as those for a big-endian area, but the byte positions of the data bus are swapped in accordance with the bus width. Note that big-endian areas and little-endian areas should kept physically separated during connection. ■ Differences and Similarities of Access in Little-endian and in Big-endian Mode The order of output addresses are the same for access in big-endian and in little-endian mode. The data bus control signals used for a bus width of 16 or 8 bits are also the same for access in big-endian and in little-endian mode. Differences between the data formats are shown below: ❍ Word access Byte data on the side of the MSB, which corresponds to address 00B in big-endian mode, is treated as byte data on the side of the LSB in little-endian mode. In word access, all byte positions of the four bytes in a word are reversed as follows. 00 --> 11, 01 -- > 10, 10 --> 01, 11 --> 00 ❍ Half word access Byte data on side of the MSB corresponding to address 0 in big-endian mode becomes byte data on side of the LSB in little-endian mode. For half word access, the byte positions of the two bytes in a half word are reversed. 0 -->1, 1 --> 0 ❍ Byte access There is no difference in byte access between big-endian and little-endian mode. 124 CHAPTER 4 BUS INTERFACE ■ Data Format Figure 4.4-10 to Figure 4.4-12 show the relationship between the internal register and external data bus for each data format. ❍ Word access (when an LD or ST instruction is executed) Figure 4.4-10 Relationship Between Internal Register and External Data Bus (in Word Access) Internal register D31 D23 D15 D07 External bus AA DD BB BB CC AA D31 D23 CC DD ❍ Half word access (when an LDUH or STH instruction is executed) Figure 4.4-11 Relationship Between Internal Register and External Data Bus (in Half Word Access) Internal register D31 BB D23 D15 D07 External bus AA D31 D23 AA BB ❍ Byte access (when an LDUB or STB instruction is executed) Figure 4.4-12 Relationship Between Internal Register and External Data Bus (in Byte Access) (a) The lower byte of the output address is 0. Internal register D31 D15 D07 External bus AA D23 (b) The lower byte of the output address is 1. Internal register D31 D31 D23 D23 External bus D31 AA D23 D15 AA D07 AA 125 CHAPTER 4 BUS INTERFACE ■ Data Bus Width Figure 4.4-13 to Figure 4.4-14 show the relationship between the internal register and external data bus for each data bus width. ❍ 16-bit bus width Figure 4.4-13 Relationship Between Internal Register and External Data Bus (16-bit Bus Width) Internal register External bus Lower bytes of an output address '00' '10' D31 D23 D15 D07 AA Read/Write DD BB CC AA BB D31 D23 CC DD ❍ 8-bit bus width Figure 4.4-14 Relationship Between Internal Register and External Bus (8-bit Bus Width) Internal register External bus Lower bytes of an output address '00' '01' '10' '11' D31 D23 D15 D07 126 AA BB CC DD Read/Write DD CC BB AA D31 CHAPTER 4 BUS INTERFACE ■ Examples of Connection with External Devices Figure 4.4-15 and Figure 4.4-16 show examples of connecting the MB91150 with external devices. ❍ 16-bit bus width Figure 4.4-15 Example of Connecting the MB91150 with External Devices (16-bit Bus Width) MB91150 D31 D24 D23 WR0 D16 WR1 Little-endian area Bigendian area WR0 D31-24 MSB D15 WR1 D23-16 LSB D08 D07 D00 MSB WR1 WR0 D23-16 D31-24 LSB D15 D08 D07 D00 ❍ 8-bit bus width Figure 4.4-16 Example of Connecting the MB91150 with External Devices (8-bit Bus Width) MB91150 D31 D23 D24 WR0 D16 WR1 Bigendian area D07 Little-endian area D00 D07 D00 Note: Because the MB91150 has no chip select output, addresses must be decoded externally. 127 CHAPTER 4 BUS INTERFACE 4.4.4 Comparison of External Access in Big-endian and Little-endian Mode Table 4.4-1 to Table 4.4-3 compare external accesses between big-endian and littleendian modes in terms of each data bus width and data format. ■ Word Access Table 4.4-1 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Word Access) Bus width 16-bit bus width Big-endian mode Internal register External pins Little-endian mode Control pins Internal register address: "0" "2" D31 AA D31 AA CC BB CC BB DD External pins address: "0" "2" D31 WR0 AA D31 D16 CC CC AA WR0 WR1 D16 DD D00 D00 (1) (2) Internal register External pins address: "0" "1" "2" "3" D31 D31 AA AA BB CC DD BB (1) (2) Control pins Internal register External pins D31 WR0 AA BB CC CC DD DD D31 DD CC BB AA D24 D00 (1) (2) (3) (4) Control pins address: "0" "1" "2" "3" D24 D00 128 DD BB BB WR1 DD 8-bit bus width Control pins (1) (2) (3) (4) WR0 CHAPTER 4 BUS INTERFACE ■ Half Word Access Table 4.4-2 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Half Word Access) (1/2) Bus width 16-bit bus width Big-endian mode Little-endian mode Internal register External pins Control pins address: "0" D31 D31 AA WR0 BB AA Internal register External pins address: "0" D31 D31 AA WR1 D16 AA WR0 WR1 D16 BB BB D00 D00 (1) Internal register D31 BB Control pins External pins Control pins address: "2" D31 CC DD CC (1) WR0 Internal register External pins Control pins address: "2" D31 D31 DD WR0 CC WR1 WR1 CC D16 D16 DD DD D00 D00 (1) (1) 129 CHAPTER 4 BUS INTERFACE Table 4.4-2 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Half Word Access) (2/2) Bus width 8-bit bus width Big-endian mode Little-endian mode Internal register External pins Control pins address: "0" "1" D31 D31 AA BB WR0 D24 Internal register External pins Control pins address: "0" "1" D31 D31 BB AA WR0 D24 AA AA BB BB D00 D00 D00 D00 (1) (2) Internal register D31 External pins address: "2" "3" D31 CC DD (1) (2) Control pins WR0 Internal register D31 address: "2" "3" D31 DD CC D24 D24 CC CC DD D00 DD D00 (1) (2) 130 External pins Control pins D00 D00 (1) (2) WR0 CHAPTER 4 BUS INTERFACE ■ Byte Access Table 4.4-3 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Byte Access) (1/2) Bus width 16-bit bus width Big-endian mode Internal register External pins Little-endian mode Control pins Internal register D31 D31 D31 AA External pins address: "0" D31 AA address: "0" WR0 Control pins WR0 D16 D16 AA AA D00 D00 (1) (1) Internal register External pins Control pins address: "1" D31 D31 BB Internal register External pins Control pins address: "1" D31 D31 BB WR1 D16 WR1 D16 BB BB D00 D00 (1) Internal register (1) External pins Control pins address: "2" D31 D31 CC WR0 Internal register External pins Control pins address: "2" D31 D31 CC D16 WR0 D16 CC CC D00 D00 (1) Internal register External pins (1) Control pins Internal register D31 D31 D31 DD External pins Control pins address: "3" address: "3" D31 DD WR1 WR1 D16 D16 DD DD D00 D00 (1) (1) 131 CHAPTER 4 BUS INTERFACE Table 4.4-3 Comparison of External Accesses Between Big-endian and Little-endian Modes (in Byte Access) (2/2) Bus width 8-bit bus width Big-endian mode Internal register Little-endian mode External pins Control pins Internal register address: "0" D31 D31 AA External pins Control pins address: "0" D31 D31 WR0 D24 WR0 D24 AA AA D00 D00 (1) Internal register (1) External pins Control pins Internal register address: "1" D31 D31 BB External pins Control pins address: "1" D31 D31 WR0 BB WR0 D24 D24 BB BB D00 D00 (1) (1) Internal register External pins Control pins address: "2" D31 D31 CC WR0 D24 Internal register External pins Control pins address: "2" D31 D31 CC WR0 D24 CC CC D00 D00 (1) Internal register External pins address: "3" D31 D31 DD (1) Control pins WR0 Internal register External pins address: "3" D31 D31 DD D24 D24 DD DD D00 D00 (1) 132 AA (1) Control pins WR0 CHAPTER 4 BUS INTERFACE 4.5 Bus Timing This section provides detailed information on bus access operations in each of the following modes: • Normal bus access • Wait cycle • External bus request ■ Normal Bus Access With a normal bus interface, a basic bus cycle contains two clock cycles for both the read and write cycles. This manual refers to the two cycles as BA1 and BA2. Normal bus access includes the following cycles: • Basic read cycle • Basic write cycle • Read cycle in each mode • Write cycle in each mode • Mixed read/write cycles ■ Wait Cycle In the wait cycle mode, the preceding cycle is continued. The BA1 cycle is repeated until wait is canceled. This device has two types of wait cycles: • An automatic wait cycle that is set by the WTC2 to WTC0 bits in the AMD register • An external wait cycle that is set by the RDY pin ■ External Bus Request The following two types of external bus requests are used: • Release of bus right • Acquisition of bus right 133 CHAPTER 4 BUS INTERFACE 4.5.1 Basic Read Cycle This section describes the operations of the basic read cycle. ■ Basic Read Cycle Timing Chart Figure 4.5-1 shows an example of basic read cycle timing under the following conditions: • Bus width: 16 bits • Access type: in words • Access to CS0 area Note: This model does not use CS4 and CS5 outputs. Figure 4.5-1 Example of a Timing Chart of the Basic Read Cycle BA1 BA2 BA1 BA2 CLK A23-00 D31-24 D23-16 #0 #2 #0 #1 #2 #3 RD WR0 WR1 (CS0) (CS1) (CS2) (CS3) (DACK0) (DEOP0) Access to the Access to the higher halfword lower halfword of an address of an address Notes: The sharp-symbol (#) of A23-A00 indicates the lower two bits of an address. The sharp-symbol (#) of D31 to D16 indicates the byte address for read data. (DACK0) and (DEOP0) indicate DMAC bus cycles. The arrow-symbol ( ) indicates the timing of fetching read data. 134 CHAPTER 4 BUS INTERFACE [Operation] • The CLK outputs the pulses for the operating clock of the external bus. If the clock doubler is off, the operating clocks of the CPU and that of the external bus are in 1:1 relationship and the clock pulses output from the CLK have the same frequency as the clock pulses of the CPU. If the clock doubler is on, the operating clocks of the CPU and that of the external bus are in 1:1/ 2 relationship and the clock pulses output from the CLK have a frequency that is half that of the CPU clock pulses. If the gear is set, the CLK frequency is decreased according to the gear ratio. • A23 to A00 (address 23 to address 00) output the address of a leading byte location during word, half word or byte access in a read cycle starting with the start of a bus cycle (BA1). In the above example, a word is accessed in 16-bit bus width, and the address of the higher 16 bits of the word to be accessed (the lower two bits, indicating 0) is therefore outputted in the first bus cycle, while the address of the lower 16 bits is outputted in the second bus cycle (the lower two bits, indicating 2). • D31 to D16 (data 31 to data 16) indicate read data from external memory and I/O. In a read cycle, D31 to D16 are read when the RD rises. Moreover, in a read cycle, all of D31 to D16 are read when the RD rises regardless of bus width and whether the access in units of words, half words, or bytes. Whether the read data is valid is checked in the chip. • The RD is the read strobe signal of the external data bus. This signal is asserted when the BA1 falls and negated when the BA2 falls. • In a read cycle, WR0 and WR1 are negated. • The CS0 to CS3 (area chip select) signals are asserted from the beginning of the bus cycle (BA1) with the same timing as for A23 to A00. CS0 to CS3 are generated by decoding address output. These signals are changed only if the address output changes and the chip select area set by the ASR and AMR registers are changed. • The DACK0 to DACK2 and DEOP0 to DEOP2 are outputted during external bus cycles of the DMA. Whether they are outputted is determined by DMA controller register settings. Their output timing is the same as that of the RD. 135 CHAPTER 4 BUS INTERFACE 4.5.2 Basic Write Cycle This section describes the operations of the basic write cycle. ■ Basic Write Cycle Timing Chart Figure 4.5-2 shows an example of basic write cycle timing under the following conditions: • Bus width: 8 bits • Access type: in words • Access to CS0 area Note: This model does not use CS4 and CS5 outputs. Figure 4.5-2 Example of a Timing Chart of Basic Write Cycle BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 RD WR0 WR1 (CS0) (CS1) (CS2) (CS3) (DACK0) (DEOP0) #0 #0 #1 #1 #2 #2 #3 #3 Byte access when the lower two bits of the address indicate 0 Byte access when the lower two bits of the address indicate 1 Byte access when the lower two bits of the address indicate 2 Byte access when the lower two bits of the address indicate 3 [Operation] 136 • A23 to A00 (address 23 to address 00) output the address of the leading byte location for word, half word, or byte access during a write cycle starting from the beginning of a bus cycle (BA1). In the above example, because a word is accessed in a bus width of eight bits, the address of the leading byte of the word access (the lower bits of the address indicate 0) is outputted. Then, the address for the leading byte address plus 1 (1), the address of the leading byte address plus 2 (2), and the address for the leading byte address plus 3 (3) are outputted in sequence. • D31 to D16 (data 31 to data 16) indicate write data for the external memory and I/O. In a write cycle, write data is outputted starting from the beginning of a bus cycle (BA1) and set to Hi-Z CHAPTER 4 BUS INTERFACE at the end of the bus cycle (end of the BA2). In the above example, write data is outputted to D31 to D24 because the data bus has a width of 8 bits. • The RD is negated during a write cycle. • WR0 and WR1 are write strobe signals for the external bus data. They are asserted when BA1 falls and negated when BA2 falls. D31 to D24 and D23 to D16 are asserted in accordance with WR0 and WR1, respectively and the width of their data buses. In the above example, only WR0 is asserted because the data bus has a width of eight bits. • If the maximum bus width of chip select areas 0 to 5 is eight bits, that is, all of the set areas are set to 8-bit mode, D23 to D16 and WR1 automatically become I/O ports and turn to Hi-Z. In the above example, D23 to D16 and WR1 are used as I/O ports. Note that D23 to D16 and WR1 cannot be used as I/O ports if the bus width for even one of chip select areas 0 to 5 is 16 bits. Table 4.5-1 Setting the maximum bus width Maximum bus width • Pin D31 to D24 WR0 D23 to D16 WR1 16 bits D31 to D24 WR0 D23 to D16 WR1 8 bits D31 to D24 WR0 I/O port DACK0 to DACK2 and DEOP0 to DEOP2 are outputted during an external bus cycle of the DMA. Whether they are outputted is determined by DMA controller register settings. The output timing is the same as that of WR0 and WR1. 137 CHAPTER 4 BUS INTERFACE 4.5.3 Read Cycle in Each Mode Figure 4.5-3 to Figure 4.5-7 show examples of the read cycle timing in each mode. ■ Timing Chart of Read Cycles in Each Mode ❍ Bus width: 16 bits Access: In units of half words Figure 4.5-3 Sample Read Cycle Timing Chart 1 BA1 BA2 BA1 BA2 CLK #0 A23 to 00 D31 to 24 D23 to 16 RD #2 #0 #1 #2 #3 ❍ Bus width: 16 bits Access: In units of bytes Figure 4.5-4 Sample Read Cycle Timing Chart 2 BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 RD #0 #1 #0 X #2 X #1 #3 #2 X X #3 X: Input of invalid data ❍ Bus width: 8 bits Access: In units of words Figure 4.5-5 Sample Read Cycle Timing Chart 3 BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 RD 138 #0 #1 #0 #2 #1 #3 #2 #3 CHAPTER 4 BUS INTERFACE ❍ Bus width: 8 bits Access: In units of half words Figure 4.5-6 Sample Read Cycle Timing Chart 4 BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 RD #0 #1 #0 #2 #1 #3 #2 #3 ❍ Bus width: 8 bits Access: In units of bytes Figure 4.5-7 Sample Read Cycle Timing Chart 5 BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 RD #0 #1 #0 #2 #1 #3 #2 #3 139 CHAPTER 4 BUS INTERFACE 4.5.4 Write Cycle in Each Mode Figure 4.5-8 to Figure 4.5-12 show examples of the write cycle timing in each mode. ■ Write Cycle Timing in Each Mode ❍ Bus width: 16 bits Access: In units of words Figure 4.5-8 Sample Write Cycle Timing Chart 1 BA1 BA2 BA1 BA2 CLK #0 #0 #1 A23 to 00 D31 to 24 D23 to 16 WR0 WR1 #2 #2 #3 ❍ Bus width: 16 bits Access: In units of half words Figure 4.5-9 Sample Write Cycle Timing Chart 2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 WR0 WR1 #0 #0 #1 #2 #2 #3 ❍ Bus width: 16 bits Access: In units of bytes Figure 4.5-10 Sample Write Cycle Timing Chart 3 BA1 BA2 BA1 BA2 BA1 BA2 BA1 CLK A23 to 00 D31 to 24 D23 to 16 WR0 WR1 #0 #0 X #1 X #1 #2 #2 X X: Output of invalid data 140 #3 X #3 BA2 CHAPTER 4 BUS INTERFACE ❍ Bus width: 8 bits Access: In units of half words Figure 4.5-11 Sample Write Cycle Timing Chart 4 BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 WR0 WR1 #0 #0 #1 #1 #2 #2 #3 #3 ❍ Bus width: 8 bits Access: In units of bytes Figure 4.5-12 Sample Write Cycle Timing Chart 5 BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2 CLK A23 to 00 D31 to 24 D23 to 16 WR0 WR1 #0 #0 #1 #1 #2 #2 #3 #3 141 CHAPTER 4 BUS INTERFACE 4.5.5 Mixed Read/Write Cycles This section describes the operations of the mixed read/write cycle. ■ Timing Chart for Mixed Read/Write Cycles Figure 4.5-13 shows examples of mixed read/write cycle timing under the following conditions: • • CS0 area • Bus width: 16 bits • Access type: reading in units of words CS1 area • Bus width: 8 bits • Access type: Writing in units of half words Note: This model does not use CS4 and CS5 outputs. Figure 4.5-13 Sample Timing Chart for Mixed Read/Write Cycles BA1 BA2 BA1 BA2 Idle BA2 BA1 BA1 BA2 Idle CLK A23 to 00 D31 to 24 D23 to 16 #0 #2 #0 #1 #0 #0 X #2 #3 #1 #1 X RD WR0 WR1 (CS0) (CS1) Halfword write cycle Word read cycle CS0 area CS1 area [Operation] 142 • In the above example, an idle cycle (in which no bus cycle is provided) is inserted when a chip select area is switched. If an idle cycle is inserted between bus cycles, the address of the preceding bus cycle is kept as output until the next bus cycle starts. Accordingly, the CS0 to CS3 corresponding to the output address are kept asserted. • In the above example, the 16-bit bus and 8-bit bus are mixed. Because the maximum bus width is 16 bits, D23 to D16 and WR1 cannot be used as I/O ports even for an 8-bit access area (CS3 area). The output of D23 to D16 is undefined and WR1 is negated. CHAPTER 4 BUS INTERFACE 4.5.6 Automatic Wait Cycle This section describes the operations of the automatic wait cycle. ■ Automatic Wait Cycle Timing Chart Figure 4.5-14 shows an example of automatic wait cycle timing under the following conditions: • Bus width: 16 bits • Access type: Reading/writing in half words Figure 4.5-14 Sample Timing Chart for an automatic Wait Cycle BA1 BA1 BA2 BA1 BA1 BA2 CLK A23 to 00 D31 to 16 RD WR0,WR1 (DACK0) (DEOP0) #0 #0:1 wait Read #2 #2,3 wait Write [Operation] • Automatic wait cycles can be implemented by setting the WTC2 to WTC0 bits of the AMD register in each chip select area. • In the above example, the WTC2 to WTC0 bits are set to 001B to insert one wait bus cycle to normal bus cycles. The bus cycle includes three clock cycles (two clock cycles for normal bus cycle plus one clock cycle for wait cycle). Up to seven clock cycles can be set for one automatic wait cycle (accordingly, one normal bus cycle contains nine clock cycles). 143 CHAPTER 4 BUS INTERFACE 4.5.7 External Wait Cycle This section describes the operation of the external wait cycle. ■ Timing Chart of External Wait Cycle Figure 4.5-15 shows an example of external wait cycle timing under the following conditions: • Bus width: 16 bits • Access type: In half words Figure 4.5-15 Sample Timing Chart for an External Wait Cycle BA1 BA1 BA1 BA1 BA1 BA2 CLK A23 to 00 Read D31 to 16 RD Write D31 to 16 WR0,WR1 #0 #0:1 #0,1 wait wait wait RDY RDY Automatic wait Wait set by the RDY Bus cycle [Operation] 144 • An external wait cycle can be set by setting the RDYE bit of the EPCR0 to 1 and enabling input of the external RDY pin. • To use the external RDY, set an automatic wait cycle containing one clock cycle or more (set 001B or a larger value via the WTC2 to WTC0 bits of the AMD). The RDY is detected in the last cycle of an automatic wait. • Input the external RDY, synchronizing it with a falling edge of the CLK pin output. A wait cycle follows if the external RDY is low level when the CLK goes low and the same BA1 cycle is repeated. If the external RDY is high level, the wait cycle is assumed to have ended and transit to the BA2 cycle. CHAPTER 4 BUS INTERFACE 4.5.8 External Bus Request This section describes the operations of external bus requests. ■ Releasing Bus Right Figure 4.5-16 shows the sample timing chart for releasing bus right. Figure 4.5-16 Sample Timing Chart for Releasing Bus Right CLK A23 to 00 D31 to 16 RD #0:1 #0:1 Hi-Z Hi-Z Hi-Z BRQ BGRNT One cycle [Operation] • Bus arbitration by the BRQ and BGRNT can be implemented by setting the BRE bit of the EPCR0 to 1. • When bus right is released, assert the BGRNT one cycle after the pin is set to Hi-Z. ■ Bus Right Acquisition Figure 4.5-17 shows an example of bus right acquisition timing. Figure 4.5-17 Sample Timing Chart for Bus Right Acquisition CLK A23 to Z00 D31 to 16 RD Hi-Z Hi-Z Hi-Z BRQ BGRNT One cycle [Operation] • Bus arbitration by the BRQ and BGRNT can be implemented by setting the BRE bit of the EPCR0 to 1. • Activate each pin one clock after negating the BGRNT. 145 CHAPTER 4 BUS INTERFACE 4.6 Internal Clock Multiply Operation (Clock Doubler) The MB91150 has a clock multiply circuit. The CPU internally operates at a frequency obtained by multiplying the bus interface frequency by one or two. The bus interface operates in synch with the CLK output pin regardless of the selected frequency. If an external access request is made from the CPU, external access starts after the CLK output goes high. ■ Clock Selection Method For the method of selecting multiply-by-one or multiply-by-two clock frequencies, see Section "3.11.4 Gear Control Register (GCR)". A selected clock can be changed even during chip operation. Bus operation is suspended while clock selection is changed. When the system is reset, the clock obtained by multiplying the bus interface frequency by 1 is assumed. ❍ Multiply-by-two clock Figure 4.6-1 shows an example of multiply-by-two clock timing under the following conditions: • Bus width: 16 bits • Access type: In words Figure 4.6-1 Example of Multiply-by-two Clock Timing Internal clock Internal instruction address N+2 N Internal instruction data D D+2 CLK output External address bus External data bus N N+4 N+2 D D+2 External RD External access (instruction fetch) Prefetch ❍ Multiply-by-one clock Figure 4.6-2 shows an example of multiply-by-one clock timing under the following conditions: 146 • Bus width: 16 bits • Access type: In words CHAPTER 4 BUS INTERFACE Figure 4.6-2 Example of Multiply-by-one Clock Timing Internal clock Internal instruction address N N+2 Internal instruction data D D+2 CLK output External address bus External data bus N+2 N D N+4 D+2 External RD External access (instruction fetch) Prefetch 147 CHAPTER 4 BUS INTERFACE 4.7 Program Examples for the External Bus This section shows simple sample programs for operating the external bus. ■ Specification Example of a Program for External Bus Operation ❍ Registers are set as follows: • • Areas • Area 0 (AMD0): 16 bits, normal bus, automatic wait - 0 • Area 1 (AMD1): 16 bits, normal bus, automatic wait - 2 • Area 2 (AMD32): 16 bits, normal bus, automatic wait - 1 • Area 3 (AMD32): 16 bits, normal bus, automatic wait - 1 • Area 4 (AMD4): 16 bits, DRAM, page size 256, 1CAS/2WE, with wait, CBR refresh • Area 5 (AMD5): 16 bits, DRAM, page size 512, 2CAS/1WE, without wait, CBR refresh Other buses • Refresh (RFCR): Without wait, 1/8 setting • External pin (EPCR0):External RDY acceptance, BRQ, BGRNT arbitration • External pin (DSCR): DRAM pin setting • Little-endian (LER): Area 2 ❍ Note the following points: • MD2 to MD0: 001B. External vector: 16-bit mode • Set the same bus width for area 0, then set the mode register (MODR). • Set areas 1 to 5 so that they do not overlap each other. Note: This model does not support the DRAM control function and chip select output. 148 CHAPTER 4 BUS INTERFACE ■ Program Example for External Bus Operation The explanation of this program assumes that writing to a byte register is performed in units of bytes while writing to half word registers is performed in units of half words. ***** Program example ***** //Setting of each register init_epcr ldi:20 #0xffff,r0 ldi:20 sth ldi:8 #0x628,r1 r0,@r1 #0xff,r0 ldi:20 stb init_amd0 ldi:8 ldi:20 stb init_amd1 ldi:8 ldi:20 stb init_amd32 ldi:8 #0x625,r1 r0,@r1 #0x08,r0 #0x620,r1 r0,@r1 #0x0a,r0 #0x621,r1 r0,@r1 #0x49,r0 ldi:20 stb init_amd4 ldi:8 ldi:20 stb init_amd5 ldi:8 ldi:20 stb init_dmcr4 ldi:20 #0x622,r1 r0,@r1 #0x88,r0 #0x623,r1 r0,@r1 #0x88,r0 #0x624,r1 r0,@r1 #0x0c90,r0 ldi:20 sth init_dmcr5 ldi:20 #0x62c,r1 r0,@r1 #0x10c0,r0 init_dscr ldi:20 sth init_rfcr ldi:20 ldi:20 sth init_asr ldi:32 ldi:32 ldi:32 ldi:32 ldi:32 ldi:20 ldi:20 ldi:20 ldi:20 ldi:20 st st st st st #0x62e,r1 r0,@r1 #0x0205,r0 #0x626,r1 r0,@r1 #0x0013001,r0 #0x0015001,r1 #0x0017001,r2 #0x0019001,r3 #0x001b001,r4 #0x60c,r5 #0x610,r6 #0x614,r7 #0x618,r8 #0x61C,r9 r0,@r5 r1,@r6 r2,@r7 r3,@r8 r4,@r9 // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // // External pin setting External RDY wait, BRQ, BGRNT path arbitration epcr0 register address setting epcr0 register write DRAM pin setting RAS,CAS,WE dscr register address setting dscr register write 16-bit bus, 0 wait cycles amd0 register address setting amd0 register write 16-bit bus, two wait cycles amd1 register address setting amd1 register write Normal, 16-bit bus, one wait cycle amd32 register address setting amd32 register write DRAM, 16-bit bus amd4 register address setting amd4 register write DRAM, 16-bit bus amd5 register address setting amd5 register write page size=256,Q1/Q4-wait,Page 1CAS-2WE,CBR,without parity dmcr4 register address setting dmcr4 register write page size=512,Q1/Q4 - without wait, Page 2CAS-1WE,CBR, without parity dmcr5 register address setting dmcr5 register write REL=2,R1W/R3W - without wait,refresh, 1/8 rfcr register address setting rfcr register write asr1, amr1 register set value asr2, amr2 register set value asr3, amr3 register set value asr4, amr4 register set value asr5, amr5 register set value asr1, amr1 register address setting asr2, amr2 register address setting asr3, amr3 register address setting asr4, amr4 register address setting asr5, amr5 register address setting asr1, amr1 register write asr2, amr2 register write asr3, amr3 register write asr4, amr4 register write asr5, amr5 register write 149 CHAPTER 4 BUS INTERFACE init_ler ldi:8 ldi:20 stb init_modr ldi:8 ldi:20 stb //External bus access adr_set ldi:32 ldi:32 ldi:32 ldi:32 ldi:32 ldi:32 ldi:32 ldi:32 bus_acc ld lduh ld ldub st sth st stb 150 #0x02,r0 #0x7fe,r1 r0,@r1 #0x80,r0 #0x7ff,r1 r0,@r1 #0x00136da0, #0x00151300, #0x00196434, #0x0019657c, #0x00196600, #0x001a6818, #0x001a6b8c, #0x001a6c00, @r0,r8 @r1,r9 @r2,r10 @r3,r11 r8,@r4 r9,@r5 r10,@r6 r11,@r7 // // // // // // r0 r1 r2 r3 r4 r5 r6 r7 CS2 little-endian ler register address setting ler register write External ROM external bus modr register address setting modr register write // // // // // // // // // // // // // // // // CS1 CS2 CS4 CS4 CS4 CS5 CS5 CS5 CS1 CS2 CS4 CS4 CS4 CS5 CS5 CS5 address address address (in page) address (in page) address (not in page) address (in page) address (in page) address (not in page) data word load data half word load data word load data byte load data word store data half word store data word store data byte store CHAPTER 5 I/O PORTS This chapter describes the I/O ports and provides the block diagrams of individual ports. It also describes the register configurations. 5.1 Overview of I/O Ports 5.2 Block Diagram of Basic I/O Port 5.3 Block Diagram of I/O Ports (Including the Pull-up Resistor) 5.4 Block Diagram of I/O ports (Including the Open-drain Output Function and the Pull-up Resistor) 5.5 Block Diagram of I/O Port (With Open-Drain Output Function) 5.6 Port Data Register (PDR2 to PDRL) 5.7 Data Direction Register (DDR2 to DDRL) 5.8 Pull-up Resistor Control Register (PCR6 to PCRI) 5.9 Open-Drain Control Register (OCRH, OCRI) 5.10 Analog Input Control Register (AICR) 151 CHAPTER 5 I/O PORTS 5.1 Overview of I/O Ports This section provides I/O port block diagrams for the device and an outline of registers. ■ I/O Port Block Diagrams The MB91150 supports using a pin as an I/O port when the pin is not set to be used for input or output of the resource corresponding to the pin. When a pin is set to be used as input port, the level of the pin is read as the read value of the port data register (PDR). When a pin is set to be used as output port, the value of a data register is used as read value. This applies also to the read value for read modify write operations. Before the pin setting is changed from input to output, the output data must be specified in advance in the respective data register. Note that if an instruction of the read modify write system (such as a bit set) is used in this situation, the data to be read is input data from a pin instead of the latch value of the data register. The MB91150 has the following types of I/O ports: • Basic I/O port • I/O port with pull-up resistor • I/O port with open-drain output function and pull-up resistor • I/O port with open-drain output function ■ I/O Port Registers The I/O ports are configured with the following registers: 152 • Port data register (PDR) • Data direction register (DDR) • Pull-up resistor control register (PCR) • Open-drain control register (OCR) • Analog input control register (AICR) CHAPTER 5 I/O PORTS 5.2 Block Diagram of Basic I/O Port This section provides a block diagram of a basic I/O port. ■ Block Diagram of Basic I/O Port Figure 5.2-1 shows the block diagram of the basic I/O ports. Figure 5.2-1 Block Diagram of Basic I/O Ports Data Bus Resource input 0 1 PDR read pin 0 PDR Resource output DDR 1 Resource output enabled PDR : Port Data Register DDR : Data Direction Register I/O ports contain a port data register (PDR) and a data direction register (DDR). • Input mode (DDR = 0): PDR read: The level of the corresponding external pin is read. PDR write: The setting value is written to the PDR. • Output mode (DDR = 1): PDR read: The value of the PDR is read. PDR write: The value of the PDR is outputted to the corresponding external pin. The ports that have these functions are P20 to P27, P30 to P37, P40 to P47, P50 to P57, P80 to P86, PE0 to PE7, PF0 to PF4, PG0 to PG5, PK0 to PK7, and PL0 to PL7. Note: • The analog input control register of port-K (AICR) is used for control of switching between using the analog pins (A/D) as resources or ports. AICR controls whether port K is used for analog input or as general-purpose port. 0: General-purpose port 1: Analog input (A/D) 153 CHAPTER 5 I/O PORTS 5.3 Block Diagram of I/O Ports (Including the Pull-up Resistor) This section provides a block diagram of an I/O port with a pull-up resistor. ■ Block Diagram of I/O Port with a Pull-up Resistor Figure 5.3-1 shows a block diagram of an I/O port with a pull-up resistor. Figure 5.3-1 Block Diagram of a Port Including the Pull-up Resistor Data Bus Resource input 0 Pull-up resistor (approximately 50 k ) 1 PDR read pin 0 PDR Resource output DDR 1 Resource output enabled PCR PDR : Port Data Register DDR : Data Direction Register PCR : Pull-up Resistor Control Register The ports that have this functions are P60 to P67, PD0 to PD7, and PC0 to PC7. Notes: • Pull-up resistor control register (PCR): Specifies whether to turn the pull-up resistor on or off. 0: Pull-up resistor is OFF 1: Pull-up resistor is ON 154 • In stop mode, the setting of the pull-up resistor control register is prioritized. • When the pin is used as an external bus pin, the pull-up resistor control function cannot be used. Do not write 1 to this register. CHAPTER 5 I/O PORTS 5.4 Block Diagram of I/O ports (Including the Open-drain Output Function and the Pull-up Resistor) This section provides a block diagram of an I/O port with open-drain output function and a pull-up resistor. ■ Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor Figure 5.4-1 shows a block diagram of an I/O port with open-drain output function and a pull-up resistor. Figure 5.4-1 Block Diagram of a Port Including the Open-drain Output Function and the Pull-up Resistor Data Bus Resource input 0 1 PDR read pin 0 PDR Resource output DDR 1 Resource output enabled ODCR PCR PDR : Port Data Register DDR : Data Direction Register ODCR : Open-drain Control Register PCR : Pull-up Resistor Control Register The ports that have the above function are PH0 to PH5 and PI0 to PI5. 155 CHAPTER 5 I/O PORTS Notes: • Pull-up resistor control register (PCR): Specifies whether to turn the pull-up resistor on or off. 0: Pull-up resistor is OFF 1: Pull-up resistor is ON • Open-drain control register (ODCR): Specifies whether the port is used for standard output or open-drain output. 0: Standard output port (in output mode) 1: Open-drain output port (in output mode) In input mode, these settings have no effect (output Hi-Z). Whether input or output mode is applied is determined based on the value in the data direction register (DDR). 156 • In stop mode, the setting of the pull-up resistor control register is prioritized. • When this pin is used as an external bus pin, neither the pull-up resistor control function nor open-drain control function can be used. Do not write 1 to these registers. CHAPTER 5 I/O PORTS 5.5 Block Diagram of I/O Port (With Open-Drain Output Function) This section provides a block diagram of an I/O port with open-drain output function. ■ Block Diagram of I/O Port with Open-drain Output Function Figure 5.5-1 shows a block diagram of an I/O port with open-drain output function. Figure 5.5-1 Block Diagram of I/O Port with Open-drain Output Function Data Bus RMW Resource output Resource input RMW = 0 RMW = 1 pin PDR read PDR PDR : Port Data Register The ports that have the above function are PJ0 and PJ1. Note: • When the pin is used as input port or for resource input, set the PDR and resource output to 1. • In RMW read mode, the PDR value, not the pin value, is read. 157 CHAPTER 5 I/O PORTS 5.6 Port Data Register (PDR2 to PDRL) The port data registers (PDR2 to PDRL) are I/O data registers of the I/O ports. The corresponding data direction registers (DDR2 to DDRL) control input and output. ■ Port Data Register (PDR) The register configuration of the port data register (PDR) is shown below. PDR2 Address: 000001H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 P27 P26 P25 P24 P23 P22 P21 PDR3 Address: 000000H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 P37 P36 P35 P34 P33 P32 P31 PDR4 Address: 000007H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 P47 P46 P45 P44 P43 P42 P41 PDR5 Address: 000006H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 P57 P56 P55 P54 P53 P52 P51 PDR6 Address: 000005H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 P67 P66 P65 P64 P63 P62 P61 PDR8 Address: 00000BH 158 bit 7 - bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 P86 P85 P84 P83 P82 P81 PDRC Address: 000013 H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PDRD Address: 000012 H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PDRE Address: 000011 H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 PE7 PE6 PE5 PE4 PE3 PE2 PDRF Address: 000010 H bit 7 bit 6 bit 5 bit 4 bit 3 - - - PF4 PF3 PDRG Address: 000017 H bit 7 bit 6 PDRH Address: 000016 H bit 7 PDRI Address: 000015 H bit 7 PDRJ Address: 000014 H bit 7 - - - - bit 6 bit 6 bit 6 - bit 0 Initial value P20 XXXXXXXXB Access R/W bit 0 Initial value P30 XXXXXXXXB Access R/W bit 0 Initial value P40 XXXXXXXXB Access R/W bit 0 Initial value P50 XXXXXXXXB Access R/W bit 0 Initial value P60 XXXXXXXXB Access R/W bit 0 Initial value P80 -XXXXXXX B Access R/W bit 0 Initial value Access PC0 XXXXXXXXB R/W bit 0 Initial value PD0 XXXXXXXXB Access R/W PE1 bit 0 Initial value PE0 XXXXXXXX B Access R/W bit 2 bit 1 bit 0 PF2 PF1 bit 5 bit 4 bit 3 bit 2 bit 1 PG5 PG4 PG3 PG2 PG1 Initial value PF0 ---XXXXX B Access R/W bit 0 Initial value PG0 --XXXXXX B Access R/W bit 5 bit 4 bit 3 bit 2 bit 1 PH5 PH4 PH3 PH2 PH1 bit 0 Initial value PH0 -- XXXXXX B Access R/W bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PI5 PI4 PI3 PI2 PI1 PI0 Initial value --XXXXXX B Access R/W bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - PJ1 PJ0 Initial value ------11 B Access R/W bit 0 Initial value Access PK0 XXXXXXXXB R/W PDRK Address: 00001BH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 PK7 PK6 PK5 PK4 PK3 PK2 PK1 PDRL Address: 00001A H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 PL7 PL6 PL5 PL4 PL3 PL2 PL1 bit 0 Initial value PL0 XXXXXXXXB Access R/W CHAPTER 5 I/O PORTS 5.7 Data Direction Register (DDR2 to DDRL) The data direction registers (DDR2 to DDRL) control in units of bits whether the corresponding I/O ports perform input or output. When 0 is set, input is performed, when 1 is set, output is performed. ■ Data Direction Register (DDR) The register configuration of the data direction register (DDR) is shown below. DDR2 Address: 000601H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P27 P26 P25 P24 P23 P22 P21 P20 DDR3 Address: 000600 H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P37 P36 P35 P34 P33 P32 P31 P30 DDR4 Address: 000607 H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P47 P46 P45 P44 P43 P42 P41 P40 DDR5 Address: 000606 H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P57 P56 P55 P54 P53 P52 P51 P50 DDR6 Address: 000605 H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P67 P66 P65 P64 P63 P62 P61 P60 DDR8 Address: 00060BH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - P86 P85 P84 P83 P82 P81 P80 DDRC Address: 0000FFH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 PC7 PC6 PC5 PC4 PC3 PC2 DDRD Address: 0000FEH bit 7 bit 6 bit 5 bit 4 bit 3 PD7 PD6 PD5 PD4 PD3 DDRE Address: 0000FDH bit 7 bit 6 bit 5 bit 4 PE7 PE6 PE5 PE4 DDRF Address: 0000FCH bit 7 bit 6 bit 5 - - - DDRG Address: 000103H bit 7 bit 6 - - DDRH Address: 000102H bit 7 bit 6 bit 5 - - PH5 DDRI Address: 000101H bit 7 bit 6 bit 5 - TEST PI5 DDRK Address: 000107H bit 7 bit 6 PK7 PK6 DDRL Address: 000106H bit 7 PL7 Initial value 00000000 B Access W Initial value 00000000 B Access W Initial value 00000000 B Access W Initial value 00000000 B Access W Initial value 00000000 B Access W Initial value -0000000 B Access W bit 0 PC1 Initial value PC0 00000000 B Access R/W bit 2 bit 1 bit 0 PD2 PD1 Initial value PD0 00000000B Access R/W bit 3 bit 2 bit 1 bit 0 PE3 PE2 PE1 PE0 Initial value 00000000 B Access R/W bit 4 bit 3 bit 2 bit 1 bit 0 PF4 PF3 PF2 PF1 PF0 Initial value ---00000B Access R/W bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PG5 PG4 PG3 PG2 PG1 Initial value PG0 --000000 B Access R/W bit 4 bit 3 bit 2 bit 1 bit 0 PH4 PH3 PH2 PH1 PH0 Initial value -- 000000 B Access R/W bit 4 bit 3 bit 2 bit 1 bit 0 PI4 PI3 PI2 PI1 PI0 Initial value - 0000000B Access R/W bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PK5 PK4 PK3 PK2 PK1 PK0 Initial value 00000000 B Access R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PL6 PL5 PL4 PL3 PL2 PL1 PL0 Initial value 00000000 B Access R/W Note: DDRI bit 6 is a test bit. Always set the bit to 0. The value read from this bit is always 0. 159 CHAPTER 5 I/O PORTS 5.8 Pull-up Resistor Control Register (PCR6 to PCRI) Each of the pull-up resistor control registers (PCR6 to PCRI) specifies controls of the pull-up resistor for the corresponding I/O port in input mode. • PCR = 0: Disables the pull-up resistor in input mode. • PCR = 1: Enables the pull-up resistor in input mode. The PCR has no meaning in output mode (no pull-up resistor disabled). ■ Pull-up Resistor Control Register (PCR6 to PCRI) The bit configuration of the pull-up resistor control register (PCR6 to PCRI) is shown below: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 P67 P66 P65 P64 P63 P62 P61 P60 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PCRH Address: 0000F4H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PH5 PH4 PH3 PH2 PH1 PH0 PCRI Address: 0000F5H bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PI5 PI4 PI3 PI2 PI1 PI0 PCR6 Address: 000631H PCRC Address: 0000F7H PCRD Address: 0000F6H 160 - - bit 6 - Initial value 00000000 B Access R/W Initial value 00000000 B Access R/W Initial value 00000000 B Access R/W Initial value --000000 B Access R/W Initial value --000000 B Access R/W CHAPTER 5 I/O PORTS 5.9 Open-Drain Control Register (OCRH, OCRI) Each of the open-drain control registers (OCRH, OCRI) specifies whether the corresponding I/O port is used for standard output or open-drain output while the port is used in output mode. • OCR = 0: Standard output port in output mode • OCR = 1: Open-drain output port The OCR has no meaning in input mode (Hi-Z output). ■ Open-drain Control Register (OCRH, OCRI) The structure of the open-drain control register (OCRH, OCRI) is shown below: OCRH Address: 0000F8H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - PH5 PH4 PH3 PH2 PH1 PH0 OCRI Address: 0000F9H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - PI 5 PI 4 PI3 PI 2 PI1 PI0 Initial value --000000 B Access R/W Initial value --000000B Access R/W 161 CHAPTER 5 I/O PORTS 5.10 Analog Input Control Register (AICR) The analog input control register (AICR) controls the pins of the corresponding I/O port as follows: • AICR = 0: Port input mode • AICR = 1: Analog input mode The AICR is cleared to 0 by resetting. ■ Analog Input Control Register (AICR) The structure of the analog input control register (AICR) is shown below: AICR Address: 0000EB H 162 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value Access PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 00000000B R/W CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER This chapter describes the 8/16-bit up/down counter/timer, their block diagram, their configurations and functions of the registers, as well as the operation of the 8/16-bit up/down counter/timer. 6.1 Overview of 8/16-bit Up/Down Counter/Timer 6.2 Block Diagram of the 8/16-bit Up/Down Counter/Timer 6.3 List of Registers for the 8/16-bit Up/Down Counter/Timer 6.4 Selection of Counting Mode 6.5 Reload and Compare Functions 6.6 Writing Data to the Up/Down Count Register (UDCR) 163 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.1 Overview of 8/16-bit Up/Down Counter/Timer The 8/16-bit up/down counter/timer consist of six event input pins, two 8-bit up/down counters, two 8-bit reload/compare registers, and control circuits. ■ Characteristics of the 8/16-bit Up/Down Counter/Timer • With the 8-bit count register, counting can be performed in a range between 0 to 255 (00H to FFH). In 16-bit x 1 operation mode, counting can be performed in a range between 0 to 65535 (0000H to FFFFH). • The following four count modes can be selected for the count clock: • • Timer mode • Up/down counter mode • Phase difference count mode (multiply-by-2) • Phase difference count mode (multiply-by-4) In timer mode, one of the following internal clocks can be selected for the count clock during 33.3 MHz operation: • 60ns (16.67MHz:1/2 division) • 240ns (4.17MHz:1/8 division) The following four detection edges of the external pin input signal can be selected in up and in down counting mode. • Detection of trailing edges • Detection of leading edges • Detection of both trailing and leading edges • Edge detection disabled • The phase difference counting mode is suitable for counting for an encoder, such as for a motor. Using one of A phase output, B phase output, and Z phase output for the encoder as input allows to count rotation angle and number of rotations easily and with high precision. • Two different functions can be selected for the ZIN pin (this applies for all modes). • 164 • • Counter clear function • Gate function The compare function and reload function are available. These functions can be used separately or combined. By combining these functions, counting up or down can be performed with an arbitrary width. • Compare function (compare interrupt request output) • Compare function (compare interrupt request output and counter clearing) • Reload function (underflow interrupt request output and reloading) • Compare and reload function (compare interrupt request output, counter clearing, underflow interrupt request output, and reloading) CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER • Compare and reload disabled • With the count direction flag, the counting direction immediately before the current count can be identified. • The generation of interrupts when a compare match occurs, at reload (underflow), at overflow, or when the counting direction changes, can be controlled individually. 165 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.2 Block Diagram of the 8/16-bit Up/Down Counter/Timer This section provides block diagrams of the 8/16-bit up/down counter/timer. ■ Block Diagram of the 8/16-bit Up/Down Counter/Timer ❍ ch.0 Figure 6.2-1 shows a block diagram of the 8/16-bit up/down counter/timer (for ch.0). Figure 6.2-1 Block Diagram of the 8/16-bit Up/Down Counter/Timer (ch.0) Data bus 8-bit CGE1 ZIN0 CGE0 RCR0 (Reload/compare register 0) CGSC CTUT Control reload UCRE RLDE Detects edge or level Clear counter UDCC 8-bit UDCR0 (Up/down count register 0) Carry CES1 CES0 CMS1 CMS0 UDFF CITE Count clock AIN0 BIN0 Select up or down count clock Prescaler UDF1 UDF0 CDCF CFIE CSTR Output interrupt CLKS 166 UDIE OVFF CMPF CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER ❍ ch.1 Figure 6.2-2 shows a block diagram of the 8/16-bit up/down counter/timer (for ch.1). Figure 6.2-2 Block Diagram of the 8/16-bit Up/Down Counter/Timer (ch.1) Data bus 8-bit CGE1 ZIN1 CGE0 RCR1 (Reload/compare register 1) CGSC CTUT Control reload UCRE RLDE Detects edge or level Clear counter UDCC 8-bit UDCR1 (Up/down count register 1) CMPF UDFF CMS1 CMS0 CES1 CES0 OVFF M16E CITE UDIE Carry Count clock AIN1 BIN1 Select up or down count clock Prescaler UDF1 UDF0 CDCF CFIE CSTR Output interrupt CLKS 167 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3 List of Registers for the 8/16-bit Up/Down Counter/Timer This section provides a listing of 8/16-bit up/down counter/timer registers. ■ List of Registers for the 8/16-bit Up/Down Counter/Timer Figure 6.3-1 lists the registers of the 8/16-bit up/down counter/timer. Figure 6.3-1 List of Registers for the 8/16-bit Up/Down Counter/Timer bit 31 24 16 15 8 7 RCR0 CCRH0 CCRL0 CSR0 CCRH1 CCRL1 CSR1 Address: 00005EH Address: 00005DH Address: 00005CH UDCR1 0 RCR1 Address: 00005FH Address: 000063H 23 UDCR0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D07 D06 D05 D04 D03 D02 D01 D00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 D15 D14 D13 D12 D11 D10 D09 D08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D07 D06 D05 D04 D03 D02 D01 D00 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 D15 D14 D13 D12 D11 D10 D09 D08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Up/down count register ch.0 (UDCR0) Up/down count register ch.1 (UDCR1) Reload compare register ch.0 (RCR0) Reload compare register ch.1 (RCR1) Counter status register ch.0,1 (CSR0,1) 000067H Address: 000061H Counter control register ch.0,1 (CCRL0,1) 000065H Address: 000060H Address: 000064H 168 Counter control register ch.0 (CCRH0) Counter control register ch.1 (CCRH1) CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.1 Counter Control Register H/L ch.0 (CCRH0, CCRL0) This section describes the counter control register H/L (ch.0). ■ Counter Control Register H/L ch.0 (CCRH0, CCRL0) The structure of the counter control register H/L (ch.0) is shown below: bit 15 Address: 000060 H 000061 H bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W R/W R/W W R/W R/W Initial value 00000000B Initial value -000X000B R/W [bit 15] M16E: 16-bit mode permission setting bit 8 bits x 2 channels/16 bits x 1 channel operation mode selection (switching) bit M16E 16-bit mode permission setting 0 8 bits x 2 channels operation mode (initial value) 1 16 bits x 1 channel operation mode 169 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [bit 14] CDCF: Count direction change flag This flag is set when the count direction is changed. When the count direction is changed from up to down or down to up during counting, this flag is set to 1. Writing 0 clears the setting. Writing 1 is ignored. The value of this bit is not changed. CDCF Direction change detection 0 Direction has not been changed (initial value). 1 Direction has been changed once or more. [bit 13] CFIE: Count direction change interrupt enable bit This bit controls the interrupt output for the CPU when CDCF is set. An interrupt occurs if the count direction is changed at least once during counting. CFIE Direction change interrupt output 0 Disables direction change interrupt output (initial value). 1 Enables direction change interrupt output. [bit 12] CLKS: Internal prescaler selection bit When timer mode is selected, this bit selects the frequency of the internal prescaler. This bit is effective only in timer mode and only for down counting. CLKS Selected internal clock 0 Two machine cycles (initial value) 1 Eight machine cycles [bit 11 and bit 10] CMS1 and CMS0: Counting mode selection bit These bits select counting mode. 170 CMS1 CMS0 Counting mode 0 0 Timer mode [down count] (initial value) 0 1 Up or down counting mode 1 0 Phase difference counting mode, 2 multiplication 1 1 Phase difference counting mode, 4 multiplication CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [bit 9 and bit 8] CES1 and CES0: Count clock edge selection bit In up/down counting mode, these bits select the detection edge of external pins AIN and BIN. This setting is invalid in modes other than up or down counting mode. CES1 CES0 Selection edge 0 0 Disables edge detection (initial value). 0 1 Detects falling edge. 1 0 Detects rising edge. 1 1 Detects rising and falling edges. [bit 6] CTUT: Counter write bit This bit transfers data from RCR to UDCR. When this bit is set to 1, data is transferred from RCR to UDCR. Writing 0 to this bit has no effect. The read value is always 0. Do not set this bit to 1 during counting (when the CSTR bit of the CSR is 1). [bit 5] UCRE: UDCR clear enable bit This bit controls the compare operation that clears UDCR. UDCR clear functions other than clearing due to comparing (such as due to the ZIN pin), are not affected. UCRE Counter clear by compare 0 Disables counter clear (initial value). 1 Enables counter clear. [bit 4] RLDE: Reload enable bit This bit controls the start of the reload function. When the reload function is started if UDCR leads the underflow, this bit transfers the value of RCR to UDCR. RLDE Reload function 0 Disables the reload function (initial value). 1 Enables the reload function. [bit 3] UDCC: UDCR clear bit This bit clears the UDCR. When this bit is set to 0, the UDCR is cleared to 0000H. Writing 1 to this bit has no effect. The read value is undefined. 171 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [bit 2] CGSC: Counter clear/gate selection bit This bit selects the function of the external pin ZIN. CGSC ZIN function 0 Counter clear function (initial value) 1 Gate function [bit 1 and bit 0] CGE1 and CGE0: Counter clear/gate edge selection bit These bits select the detection edge/level of the external pin ZIN. 172 CGE1 CGE0 When counter clear function is selected When gate function is selected 0 0 Disables edge detection (initial value). Disables level detection (count disable) 0 1 Falling edge "L" level 1 0 Rising edge "H" level 1 1 Setting not allowed Setting not allowed CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.2 Counter Control Register H/L ch.1 (CCRH1, CCRL1) This section describes the counter control register H/L (ch.1). ■ Counter Control Register H/L ch.1 (CCRH1, CCRL1) The structure of the counter control register H/L (ch.1) is shown below: bit 15 Address: 000064H bit 7 000065H bit 8 Initial value CLKS CMS1 CMS0 CES1 CES0 -0000000B bit 14 bit 13 CDCF CFIE R/W R/W R/W R/W R/W R/W R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 -000X000B R/W R/W bit 12 R/W bit 11 W bit 10 R/W bit 9 R/W R/W For details of the individual bits, see Section "6.3.1 Counter Control Register H/L ch.0 (CCRH0, CCRL0)". 173 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.3 Counter Status Register 0/1 (CSR0, CSR1) The register configuration of counter status register 0/1 (CSR0, CSR1) is shown below. ■ Counter Status Register 0/1 (CSR0, CSR1) The structure of counter status register 0/1 is shown below: bit 7 Address: 000063H bit 6 bit 5 CSTR CITE UDIE bit 0 Initial value CMPF OVFF UDFF UDF1 UDF0 00000000B bit 4 bit 3 bit 2 bit 1 000067H R/W R/W R/W R/W R/W R/W R R [bit 7] CSTR: Count start bit This bit controls the start and stop of UDCR counting. CSTR Operation 0 Stops the counting operation (initial value) 1 Starts the counting operation [bit 6] CITE: Compare interrupt output control bit This bit controls whether to enable or disable interrupt output to the CPU when a compare detection flag (CMPF) is set (during a compare operation). CITE Compare interrupt output 0 Disables compare interrupt output (initial value). 1 Enables compare interrupt output. [bit 5] UDIE: Overflow/underflow interrupt output control bit This bit controls whether to enable or disable interrupt output to the CPU when OVFF/UDFF is set (when overflow or underflow occurs). UDIE 174 Overflow/underflow interrupt output 0 Disables overflow/underflow interrupt output (initial value). 1 Enables overflow/underflow interrupt output. CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER [bit 4] CMPF: Compare detection flag This flag indicates that the comparison result of the UDCR value and RCR value is that the values are equal. In write operations, the flag can only be set to 0, not to 1. CMPF Meaning of flag 0 Comparison result does not match (initial value). 1 Comparison result matches. [bit 3] OVFF: Overflow detection flag This flag indicates the occurrence of an overflow. During write operations, this flag can only be set to 0, not to 1. OVFF Meaning of flag 0 No overflow (initial value) 1 Overflow [bit 2] UDFF: Underflow detection flag This flag indicates that an underflow occurs. During write operations, this flag can only be set to 0, not to 1. UDFF Meaning of flag 0 No underflow (initial value) 1 Underflow [bit 1 and bit 0] UDF1 and UDF0: Up/down flag These bits indicate the type of a counting operation (up or down) immediately preceding the current operation. Only reading is allowed. No writing is allowed. UDF1 UDF0 Detection edge 0 0 No input (initial value) 0 1 Down count 1 0 Up count 1 1 Both up and down counting was performed simultaneously. 175 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.4 Up/Down Count Register 0/1 (UDCR0, UDCR1) The register configuration of the up/down count register 0/1 (UDCR 0, UDCR 1) is shown below. ■ Up/down Count Register 0/1 (UDCR 0, UDCR 1) The structure of the up/down count register 0/1 is shown below: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 D15 D14 D13 D12 D11 D10 D 09 D 08 R bit 7 R bit 6 R bit 5 R bit 4 R bit 3 R bit 2 R bit 1 R bit 0 00005FH D07 D06 D05 D04 D03 D02 D01 D00 UDCR0 R R R R R R R R Address: 00005EH UDCR1 Initial value 00000000B Initial value 00000000B This register is an 8-bit count register. Up/down counting is performed with an internal prescaler or an input through the AIN pin or BIN pin. In 16-bit counting mode, this bit operates as a 16-bit count register. In this case, the setting value in the control register for the higher 8 bits is invalid for the operation. Values cannot be written to this register directly. To write a value to this register, the RCR must be used. First write the value to write to this register to the RCR, then set the CTUT bit of the CCRL register to 1. The value will then be transferred from the RCR to this register (in a reloadoperation by software). In 16-bit mode, perform a 16-bit read operation for this register once. 176 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.3.5 Reload/Compare Register 0/1 (RCR0, RCR1) The register configuration of the reload/compare register 0/1 (RCR0, RCR1) is shown below. ■ Reload/Compare Register 0/1 (RCR 0, RCR 1) The structure of the reload/compare register 0/1 is shown below: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 D15 D14 D13 D12 D11 D10 D09 D08 W bit 7 W bit 6 W bit 5 W bit 4 W bit 3 W bit 2 W bit 1 W bit 0 00005DH D07 D06 D05 D04 D03 D02 D01 D00 RCR0 W W W W W W W W Address: 00005CH RCR1 Initial value 00000000B Initial value 00000000B This register is an 8-bit reload/compare register. This register sets the reload value and compare value. The reload value and compare value are the same. Starting the reload function and compare function enables counting up or down between 00H and the value of this register (In 16bit operation mode: counting up and down between 0000H and the value of this register). Only writing is allowed for this register. This register cannot be read. By setting the CTUT bit of the CCR H/L register to 1 while counting is stopped, the value of this register can be transferred to the UDCR (reloaded by software). Write a 16-bit value to this register once. 177 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.4 Selection of Counting Mode This timer/counter has four counting modes. The CMS1 and CMS0 bits of the CCR register can be used to select these counting modes. ■ Selecting Counting Mode Table 6.4-1 lists the count modes that can be selected by the CMS1 and CMS0 bits. Table 6.4-1 Selecting Counting Mode CMS1, CMS0 Counting mode 00B Timer mode [down count] 01B Up/down counting mode 10B Phase difference counting mode, 2 multiplication 11B Phase difference counting mode, 4 multiplication ■ Timer Mode [Down Count] In timer mode, the output of the internal prescaler is used for counting down. For the internal prescaler, either two machine cycles or eight machine cycles can be selected with the CLKS bit of the CCRH register. ■ Up/down Counting Mode In up/down counting mode, counting up/down is performed by counting the input through external pin AIN and BIN. The input through the AIN pin controls counting up and the input through the BIN pin controls counting down. The inputs through the AIN pin and BIN pin are subject to edge-detected. The edge detection can be selected by the CES1 and CES0 bits of the CCRH register. Table 6.4-2 Selecting the Detection Edge CES1, CES0 178 Detection edge 00B Disables the edge detection. 01B Detects rising edge. 10B Detects falling edge. 11B Detects both falling and rising edges. CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER ■ Phase Difference Counting Mode (Two Multiplication/Four Multiplication) In phase difference counting mode, to count the phase difference between phase A and phase B of the output signal for the encoder, detect the input level of the BIN pin at input edge detection of the AIN pin and detect the input level of the AIN pin at input edge detection of the BIN pin. For the phase difference between AIN pin input and BIN pin input in two multiplication or four multiplication mode, count up if the AIN pin is faster, and count down if the BIN pin is faster. ❍ Multiply-by-2 mode In two multiplication mode, counting is performed by detecting the value of the AIN pin in the period between the rising and falling edges of the BIN pin. In this case, counting is performed as follows: • When the value of the AIN pin detected at the rising edge of the BIN pin is H, count up. • When the value of the AIN pin detected at the rising edge of the BIN pin is L, count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is H, count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is L, count up. Figure 6.4-1 shows the overview of the phase difference counting mode (two multiplication) operation. Figure 6.4-1 Overview of the Phase Difference Counting Mode (Two Multiplication) Operation AIN pin BIN pin Count value 0 +1 +1 +1 +1 +1 -1 +1 -1 -1 -1 -1 -1 1 2 3 4 5 4 5 4 3 2 1 0 ❍ Multiply-by-4 mode In four-multiplication mode, counting is performed by detecting the value of the AIN pin at the rising and falling edges of the BIN pin, and detecting the value of the BIN pin at the rising and falling edges of the AIN pin. In this case, counting is performed as follows: • When the value of the AIN pin detected at the rising edge of the BIN pin is H, count up. • When the value of the AIN pin detected at the rising edge of the BIN pin is L, count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is H, count down. • When the value of the AIN pin detected at the falling edge of the BIN pin is L, count up. • When the value of the BIN pin detected at the rising edge of the AIN pin is H, count down. • When the value of the BIN pin detected at the rising edge of the AIN pin is L, count up. • When the value of the BIN pin detected at the falling edge of the AIN pin is H, count up. • When the value of the BIN pin detected at the falling edge of the AIN pin is L, count down. Figure 6.4-2 shows an overview of operation in phase difference counting mode (multiply-by-4). 179 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Figure 6.4-2 Overview of the Phase Difference Counting Mode (Four Multiplication) Operation AIN pin BIN pin Count value 0 +1 +1 +1 +1 +1 1 2 3 4 5 +1 +1 6 7 +1 +1 +1 -1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 8 9 10 9 10 9 8 7 6 5 4 3 2 1 For counting the encoder output, by inputting the A phase to the AIN pin, the B phase to the BIN pin, and the Z phase to the ZIN pin, a highly precise count of the rotation angle and number of rotations can be obtained and the rotation direction can be detected as well. When this counting mode is selected, the selection of the detection edge with CES1 and CES0 of CCRM are invalid. 180 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.5 Reload and Compare Functions The 8/16-bit up/down counter/timer have the reload and compare functions. These two functions can be combined for processing. ■ Reload and Compare Function Table 6.5-1 shows an example for the selection of the reload/compare function. Table 6.5-1 Example of Selection for Reload/Compare Function RLDE, UCRE Reload/compare function 00B Disables reload/compare (initial value). 01B Enables compare. 10B Enables reload. 11B Enables reload/compare. ■ When the Reload Function is Started When the reload function is started, the value of the RCR is transferred to the UDCR with the timing of the down count clock after an underflow. In this case, when UDFF is set, an interrupt request is generated. In a mode in which down counting is not performed, starting this function is invalid. Figure 6.5-1 shows an overview of reload function operation. Figure 6.5-1 Overview of the Operation for the Reload Function (0FFFFH) 0FFH Reload, interrupt occur. Reload, interrupt occur. RCR 00H Underflow Underflow 181 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER ■ When the Compare Function is Started The compare function can be used in all modes other than timer mode. When the compare function is started if the value of RCR and the value of UDCR match, CMPF is set and an interrupt request is generated. When the compare clear function is started, the UDCR is cleared with the timing of the next up count clock. In a mode in which up counting is not performed, starting this function is invalid. Figure 6.5-2 shows an overview of compare function operation. Figure 6.5-2 Overview of the Compare Function Operation (0FFFFH) 0FFH Compare match Compare match RCR 00H Counter is cleared, interrupt is generated. Counter is cleared, interrupt is generated. ■ When the Reload and Compare Functions are Started Simultaneously When the reload/compare function is started, counting up or down can be perform with an arbitrary width. The reload function is started at an underflow and transfers the value of the RCR to the UDCR. When the values of RCR and UDCR match, the compare function clears the UDCR. By using these functions, counting up or down is performed for values between 0000H and the value of the RCR. Figure 6.5-3 shows an overview of operation when the reload and compare functions are started simultaneously. 182 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER Figure 6.5-3 Overview of the Operation when the Reload and Compare Functions are Started at the Same Time 0FFH Compare match Compare match Reload Reload Reload Compare match Underflow Underflow Counter clear RCR 00H Counter clear Counter clear Underflow An interrupt to the CPU can be generated at a compare match or at reload (underflow). These interrupt outputs can be enabled separately. The timing for reloading and clearing the UDCR is different during counting and when counting is stopped. • During counting, if an event for reloading or clearing occurs, all the events are synchronized with the counter clock (the figure shows the status when 0080H is reloaded). UDCR 065H 066H Reload/clear event 080H 081H Synchronizes with this clock. Count clock • When an event for reloading and clearing occurs during counting, if counting is stopped in count clock synchronization wait state (state of waiting for the count input for synchronization), the reload and clear operations are performed when counting is stopped (the figure shows the state when 0080H is reloaded). UDCR 065H 066H 080H Reload/clear event Count clock Count enable Enable (counting permitted) Disable (counting prohibited) 183 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER • If an event for reloading or clearing occurs while the counter is stopped, reload and clear are performed when the event occurs (the figure shows the state when 0080H is reloaded). UDCR 065H 080H Reload/clear event Clear by compare is performed when the values of the UDCR and the RCR match and while counting up. If down counting is performed or counting is stopped, the clear operation is not performed even when the values of the UDCR and the RCR match. As for the timing of clearing and reloading, the clear operation follows the above timing for all events other than reset input, and reloading also uses the above timing for all events. When the events for clearing and reloading occur at the same time, the clear event takes priority. 184 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER 6.6 Writing Data to the Up/Down Count Register (UDCR) Data cannot be written to the up/down count register (UDCR) directly from the data bus. This section describes the procedure for writing, counter clearing, and flags of the device. ■ Writing Data to the Up/Down Count Register (UDCR) To write any data to the UDCR, follow the procedure below: 1. Write the data that is to be written to the UDCR first to the RCR (Note that this means that the original data in the RCR will be lost). 2. By setting the CTUT of the CCR to 1, data is transferred from the RCR to the UDCR. Perform the above operation while counting is stopped (when the CSTR bit of the CSR is 0). Besides the above procedure, the following procedure can also be applied to clear the counter. • Clearing by reset input (initialization). • Clearing by edge input through the ZIN pin. • Clearing by writing 0 to UDCC of the CCR. • Clearing by compare. The above can be performed regardless of the status for the counter (regardless of whether counting is performed or stopped). ■ Count Clear/Gate Function The ZIN pin can be used after selecting the count clear function or gate function based on the CGSC bit of the CCR register. When the count clear function is started, the ZIN pin clears the counter. The CGE1 and CGE0 bits of the CCRL register can control which edge input of the ZIN pin to use for clearing the counter. When the gate function is started, the ZIN pin enables or disables counting. The CGE1 and CGE0 bits of the CCR register can control which level input of the ZIN pin enables counting. This function is effective for all modes. Table 6.6-1 summarizes how the ZIN pin functions are selected. Table 6.6-1 Selecting the ZIN Pin Function When counter clear function is used When gate function is used CGSC ZIN pin function CGE1, CGE0 0 Counter clear function 00B Disables detection. Disables detection. 1 Gate function 01B Rising edge "L" level 10B Falling edge "H" level 185 CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER ■ Count Direction Flag The count direction flag (UDF1 and UDF0) indicates at the time of up/down counting whether the counting operation preceding the current operation was counting up or down. Based on the counter clock signal from the input of the AIN and BIN pins, this value of this flag changes for each count. By checking this flag, the current rotation angle can be determined such as the control of motor. Table 6.6-2 summarizes how the count direction flag works. Table 6.6-2 Count Direction Flag UDF1, UDF0 Count direction 01B Down count 10B Up count 11B Up/down occurs simultaneously (no counting operation is performed). ■ Count Direction Change Flag The CDCF is set when the counting direction changes between up and down. Simultaneously to setting this flag, an interrupt request to the CPU can be generated. By referring the interrupt and count direction flag, the direction to which counting is changed can be determined. However, note that when the period of direction change is short and multiple direction changes are performed in succession, the direction that the flag indicates after the direction change may return to the original direction so that it appears as if the counting direction has not changed at all in between. Table 6.6-3 summarizes how the count direction change flag works. Table 6.6-3 Count Direction Change Flag CDCF Count direction change detection 0 No direction change 1 Counting direction has changed (at least once). ■ Compare Detection Flag The CMPF is set when the values of UDCR and RCR match during counting. This flag is set for a match during counting up, match by occurrence of a reloading event, as well as when the values already match when counting started. However, a match during counting down (other than a match by compare during reload due to an underflow) is not regarded as a match, and this flag is not set. ■ Operations for 8 Bits x 2 Channels and 16 Bits x 1 Channel This module can be used as an 8-bit up/down counter for two channels or a 16-bit up/down counter for one channel. Setting the M16E bit of the CCRH0 register to 0 sets 8-bit mode for two channels. Setting the bit to 1 sets 16-bit mode for one channel. For operation in 16-bit mode for one channel, the registers CSR0, CCRL0, and CCRH0 are valid and the CSR1, CCRL1, and CCRH1 registers are invalid. In addition, the AIN0, BIN0, and ZIN0 pins are enabled as input pins, while the AIN1, BIN1, and ZIN1 pins are disabled. 186 CHAPTER 7 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of the timer registers, and the operations of the 16-bit reload timer. The chapter also provides a block diagram of the 16-bit reload timer. 7.1 Overview of 16-bit Reload Timer 7.2 Block diagram of a 16-bit reload timer 7.3 Registers of 16-bit Reload Timer 7.4 Internal Clock Operation 7.5 Underflow Operation 7.6 Counter Operation States 187 CHAPTER 7 16-BIT RELOAD TIMER 7.1 Overview of 16-bit Reload Timer The 16-bit reload timer consists of the following elements: • 16-bit down counter • 16-bit reload register • Internal count clock generation prescaler • Control register ■ Features of 16-bit Reload Timer 188 • The input clock can be selected from three internal clocks (1/2, 1/8, and 1/32 of the machine clock). • Interrupt-driven DMA transfer is supported. • This model contains four reload timer channels. • Output T0 of reload timer ch.2 is connected to the A/D converter in the LSI circuit. Therefore, A/D conversion can be started at the intervals specified in the reload register. CHAPTER 7 16-BIT RELOAD TIMER 7.2 Block diagram of a 16-bit reload timer Figure 7.2-1 shows a block diagram of the 16-bit reload timer. ■ Block Diagram of the 16-bit Reload Timer Figure 7.2-1 Block Diagram of the 16-bit Reload Timer 16-bit reload register 16 8 Reload RELD 16 16-bit down counter OUTE UF R-bus 2 OUTL OUT CTL. GATE 2 INTE CSL1 UF CSL0 CNTE IRQ Clock selector 2 TRG IN CTL. Retrigger 3 21 23 25 Prescaler clear MOD2 PWM (ch.0, ch.1) A/D (ch.2) MOD1 Internal clocks MOD0 3 189 CHAPTER 7 16-BIT RELOAD TIMER 7.3 Registers of 16-bit Reload Timer Figure 7.3-1 lists the registers of the 16-bit reload timer. ■ Register List of the 16-bit Reload Timer Figure 7.3-1 Register List of 16-bit Reload Timer bit 15 bit 14 bit 13 bit 12 bit 11 CSL1 bit 10 bit 9 bit 8 CSL0 MOD2 MOD1 Control status register (TMCSR0 to TMCSR3) bit 7 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 MOD0 OUTE OUTL RELD INTE UF CNTE TRG bit 15 bit 6 bit 0 16-bit timer register (TMR0 to TMR3) bit 15 bit 0 16-bit reload register (TMRLR0 to TMRLR3) 190 CHAPTER 7 16-BIT RELOAD TIMER 7.3.1 Control Status Register (TMCSR0 to TMCSR3) This register controls the operation mode and interrupts of the 16-bit timer. Bits other than UF, CNTE, and TRG can be rewritten only when CNTE = 0. Concurrent writing can be performed. ■ Control Status Register (TMCSR0 to TMCSR3) The register configuration of the control status register (TMCSR0 to TMCSR3) is shown below. bit 11 TMCSR bit 4 bit 3 bit 2 bit 1 bit 0 Initial value CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG -000H R/W R/W R/W R/W Address: 000032H R/W 00003AH 000042H 00004AH bit 10 R/W bit 9 R/W bit 8 R/W bit 7 R/W bit 6 R/W bit 5 R/W R/W [bit 11, bit 10] CSL1, CSL0 (Counter clock select) These are counter clock select bits. Table 7.3-1 lists the clock sources that can be selected. Table 7.3-1 Clock Sources and CSL Bits CSL1 CSL0 Clock source (φ: machine clock) 0 0 φ/21 0 1 φ/23 1 0 φ/25 1 1 Setting prohibited [bit 9, bit 8, bit 7] MOD2, MOD1, MOD0 (MODe) These bits set the operation mode. All bits must be set to 0. [bit 6] OUTE (OUTput Enable) This is an output enable bit. When this bit is set to 0, the TO pin becomes a general-purpose port and when it is set to 1, the TO pin becomes a timer output pin. The output waveform becomes toggled output at the reload mode and rectangular wave output at the one-shot mode. [bit 5] OUTL: This bit set the output level of the TO pin. The output level reverses in case of setting the bit to 0 or 1. 191 CHAPTER 7 16-BIT RELOAD TIMER [bit 4] RELD: This is a reload enable bit. When this bit is set to 1, the reload mode is entered, and if the counter value underflows from 0000H to FFFFH, the counter loads the reload register value and continues operating. When this bit is set to 0, if the counter value underflows from 0000H to FFFFH, the timer stops counting. Table 7.3-2 How to Set OUTE, OUTL and RELD OUTE OUTL RELD OUTPUT WAVEFORM 0 X X General-purpose port 1 0 0 Rectangular wave with "H" level in counting 1 1 0 Rectangular wave with "L" level in counting 1 0 1 Toggled output with "L" level at count start 1 1 1 Toggled output with "H" level at count start Note: "X" in the table means any value. [bit 3] INTE: This is an interrupt request enable bit. When this bit is set to 1, if the UF bit is set to 1, an interrupt request is generated. If the UF bit is 0, an interrupt request is not generated. [bit 2] UF: This is a timer interrupt request flag. When the counter value underflows (0000H --> FFFFH), this bit is set to 1. When this bit is set to 0, the interrupt request flag is cleared. Setting this bit to 1 has no effect. When this bit is read by read-modify-write instructions, 1 is returned. [bit 1] CNTE: This is a timer-count-enable bit. When this bit is set to 1, the activation trigger waiting state is entered. When this bit is set to 0, the timer stops counting. [bit 0] TRG: This is a software trigger bit. When this bit is set to 1, a software trigger is activated, the value in the reload register is loaded into the counter, and the timer starts counting. Setting this bit to 0 has no effect. When this bit is read, 0 is always returned. A trigger input to this register is valid only when CNTE = 1. When CNTE = 0, no operation is performed. 192 CHAPTER 7 16-BIT RELOAD TIMER 7.3.2 16-bit Timer Register (TMR0 to TMR3) and 16-bit Reload Register (TMRLR0 to TMRLR3) The 16-bit timer register (TMR0 to TMR3) reads the count value from the 16-bit timer. The initial value of this register is undefined. The 16-bit reload register (TMRLR0 to TMRLR3) retains the initial count value. The initial value of this register is undefined. ■ 16-bit Timer Register (TMR0 to TMR3) The register configuration of the 16-bit timer register is shown below. 15 bit 0 TMR Address: 00002EH 000036H 00003EH 000046H Initial value R R R R R R R R R x x x x x x x x x Note: Always use a 16-bit data transfer instruction to read data from this register. ■ 16-bit Reload Register (TMRLR0 to TMRLR3) The register configuration of the 16-bit reload register is shown below. bit 15 0 TMRLR Address: 00002CH 000034H 00003CH 000044H Initial value W W W W W W W W W x x x x x x x x x Note: Always use a 16-bit data transfer instruction to write data from this register. 193 CHAPTER 7 16-BIT RELOAD TIMER 7.4 Internal Clock Operation When the timer is driven by a divided-by internal clock, the clock source can be selected from 1/2, 1/8, and 1/32 of the machine clock. ■ Internal Clock Operation To start counting immediately after counting is enabled, set the CNTE and TRG bits of the control status register to 1. A trigger input to the TRG bit is always valid when the timer is in active state (CNTE = 1) regardless of the operation mode. Figure 7.4-1 shows the activation and operation of the counter. A time T (T: Peripheral clock machine cycle) elapses from when a trigger for starting the counter is inputted to when the data of the reload register is loaded into the counter Figure 7.4-1 Activation and Operations of a Counter Count clock Counter Reloaded data Data load CNTE (register) TRG (register) T 194 -1 -1 -1 CHAPTER 7 16-BIT RELOAD TIMER 7.5 Underflow Operation A transition of a counter value from 0000H to FFFFH is called "underflow". Therefore, an underflow occurs when the [set value in the reload register + 1] count is reached. ■ Underflow Operation When an underflow occurs, and the RELD bit in the control register is 1, the counter loads the value in the reload register and continues counting. If the RELD bit is 0, the counter stops at FFFFH. The UF bit of the control register is set by an underflow, and if the INTE bit is 1, an interrupt request is generated. Figure 7.5-1 shows underflow operation. Figure 7.5-1 Underflow Operation Count clock Counter 0000H Reloaded data -1 -1 -1 Data load Underflow set [RELD=1] Count clock Counter 0000H FFFFH Underflow set [RELD=0] 195 CHAPTER 7 16-BIT RELOAD TIMER ■ Function of Output Pin The TO0 to TO3 output pin operates as toggled output reversed by underflowing at the reload mode, and as pulse output meaning the counting operation at the one-shot mode. The output polarity can be set by the OUTL bit of the register. When the OUTL bit is set to 0, the TO0 to TO3 output pin outputs initial value 0 as toggled output, and value 1 as the one-shot pulse output during counting operation. When the OUTL bit is set to 1, the output waveform is reversed. Figure 7.5-2 and Figure 7.5-3 show the function of output pin. Figure 7.5-2 Function(1) of Output Pin of 16-bit Reload Timer Count start Underflow TO0 to TO3 Inverse at OUTL=1 General-purpose port CNTE Start up trigger [RELD=1, OUTL=0] Figure 7.5-3 Function(2) of Output Pin of 16-bit Reload Timer Count start Underflow TO0 to TO3 Inverse at OUTL=1 General-purpose port CNTE Start up trigger [RELD=0, OUTL=0] 196 Waiting state for start up trigger CHAPTER 7 16-BIT RELOAD TIMER 7.6 Counter Operation States The state of the counter depends on the CNTE bit of the control register and the WAIT signal generated internally. The states that can be set are the stop state (STOP state) for CNTE = 0 and WAIT = 1, the start trigger waiting state (WAIT state) for CNTE = 1 and WAIT = 1, and the operational state (RUN state) for CNTE = 1 and WAIT = 0. ■ Counter Operation States Figure 7.6-1 shows the transitions between these states. Figure 7.6-1 Counter State Transition State transition through hardware Reset State transition through register access STOP CNTE=0, WAIT=1 Counter retains value stored when it stops. Counter value after reset is undefined. CNTE=1 TRG=1 CNTE=1 TRG=0 WAIT CNTE=1,WAIT=1 Counter retains value stored when it stops. Counter value is undefined until loaded after reset. RUN CNTE=1,WAIT=0 Counter is operating. RELD UF TRG=1 TRG=1 RELD UF LOAD CNTE=1,WAIT=0 Value in reload register is loaded into counter Load completed 197 CHAPTER 7 16-BIT RELOAD TIMER 198 CHAPTER 8 PPG TIMER This chapter describes the PPG timer, register configurations and functions, and PPG timer operation. The chapter also provides a block diagram of the PPG timer. 8.1 Overview of PPG Timer 8.2 Block Diagram of PPG Timer 8.3 Registers of PPG Timer 8.4 PWM Operation 8.5 One-shot Operation 8.6 PWM Timer Interrupt Source and Timing Chart 8.7 Activating Multiple Channels by Using the General Control Register 199 CHAPTER 8 PPG TIMER 8.1 Overview of PPG Timer The PPG timer can generate PWM waveforms with high precision and efficiency. The MB91150 has six built-in channels for the PPG timers. Each channel consists of the following elements: • 16-bit down counter • 16-bit data register with cycle setting buffer • 16-bit compare register with duty setting buffer • Pin controller ■ Features of PPG Timer • • Internal clock: φ • Internal clock: φ/4 • Internal clock: φ/16 • Internal clock: φ/64 • The counter value can be initialized to FFFFH by using reset and counter borrows. • Each channel has a PWM output. • Register • • • 200 One of the following can be selected for the 16-bit down counter count clock: • Cycle set register: reload data register with buffer • Duty set register: compare register with buffer • Transfer from buffers is performed by using counter borrows. Pin control overview • When a duty match occurs, the counter value is set to 1. (Preferred) • When a counter borrow occurs, the counter value is reset to 0. • By using output value fix mode, all-low (or all-high) can be outputted easily. • In addition, the polarity can be specified. An interrupt request can be generated by the following combination. Interrupt requests can be used to start DMA transfer. • Start of PPG timer • Counter borrow (cycle match) • Duty match • Counter borrow (cycle match) or duty match Software or other interval timers can be used to specify that multiple channels are activated at the same time. In addition, restart during operation can be specified. CHAPTER 8 PPG TIMER 8.2 Block Diagram of PPG Timer Figure 8.2-1 shows the block diagram of an entire PPG timer. Figure 8.2-2 shows the block diagram of one channel of the PPG timer. ■ Block Diagram of the Entire PPG Timer Figure 8.2-1 Block Diagram of the Entire PPG Timer TRG input PWM timer ch.0 PWM0 TRG input PWM timer ch.1 PWM1 TRG input PWM timer ch.2 PWM2 TRG input PWM timer ch.3 PWM3 External TRG4 TRG input PWM timer ch.4 PWM4 External TRG5 TRG input PWM timer ch.5 PWM5 16-bit reload timer ch.0 16-bit reload timer ch.1 General control register 2 External TRG0 to TRG3 4 General control register 1 (Source selection) 4 201 CHAPTER 8 PPG TIMER ■ Block Diagram of One Channel for the PPG Timer Figure 8.2-2 Block Diagram of One Channel for the PPG Timer PCSR PDUT Prescaler 1/1 1/4 Clock Load CMP 1/16 1/64 16-bit down counter Start Borrow PPG mask Peripheral clock S Q PWM output R Reverse bit Enable TRG input Edge detection Software trigger 202 Interrupt selection IRQ CHAPTER 8 PPG TIMER 8.3 Registers of PPG Timer Figure 8.3-1 lists the registers of the PPG timer. ■ Register List of PPG Timer Figure 8.3-1 Register List of PPG Timer Address 15 General control register 1 0 00000094H R/W GCN1 General control register 2 00000097H GCN2 R/W PWM timer register (ch.0) 00000098H R PTMR0 PWM cycle set register (ch.0) 0000009AH W PCSR0 PWM duty set register (ch.0) 0000009CH W PDUT0 Control status register (ch.0) 0000009EH PCNH0 PCNL0 R/W PWM timer register (ch.1) 000000A0H R PTMR1 PWM cycle set register (ch.1) 000000A2H W PCSR1 PWM duty set register (ch.1) 000000A4H W PDUT1 Control status register (ch.1) 000000A6H PCNH1 PCNL1 R/W PWM timer register (ch.2) 000000A8H R PTMR2 PWM cycle set register (ch.2) 000000AAH W PCSR2 PWM duty set register (ch.2) 000000ACH W PDUT2 Control status register (ch.2) 000000AEH PCNH2 PCNL2 R/W (Continued) 203 CHAPTER 8 PPG TIMER (Continued) Address 15 0 000000B0H PTMR3 000000B2H PCSR3 000000B4H PDUT3 000000B6H PCNH3 PCNL3 00000 0B8H PTMR4 00000 0BA H PCSR4 00000 0BCH PDUT4 00000 0BEH PCNH4 PCNL4 00000 0C0H PTMR5 00000 0C2H PCSR5 00000 0C4H PDUT5 000000C6 H PCNH5 204 PCNL5 R PWM timer register (ch.3) W PWM cycle set register (ch.3) W PWM duty set register (ch.3) R/W Control status register (ch.3) R PWM timer register (ch.4) W PWM cycle set register (ch.4) W PWM duty set register (ch.4) R/W Control status register (ch.4) R PWM timer register (ch.5) W PWM cycle set register (ch.5) W PWM duty set register (ch.5) R/W Control status register (ch.5) CHAPTER 8 PPG TIMER 8.3.1 Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5) The control status register (PCNH0 to PCNH5, PCNL0 to PCNL5) controls the PWM timer and indicates the status of the timer. Note that some bits cannot be rewritten while the PWM timer is operating. ■ Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5) The register configuration of the control status registers is shown below. PCNH0 to PCNH5 Address: ch.0 00009E H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 CNTE STGR MDSE RTRG CKS1 CKS0 PGMS - R/W R/W R/W R/W R/W R/W R/W - Attribute 0 0 0 0 0 0 0 - Initial value - Rewriting during operation ch.1 0000A6 H ch.2 0000AE H ch.3 0000B6 H ch.4 0000BE H ch.5 0000C6 H PCNL0 to PCNL5 Address: ch.0 00009F H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EGS1 EGS0 IREN IRQF IRS1 IRS0 POEN OSEL R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 ch.1 0000A7 H ch.2 0000AF H ch.3 0000B7 H Attribute Initial value Rewriting during operation ch.4 0000BF H ch.5 0000C7 H [bit 15] CNTE: Timer enable bit This bit enables operation of the 16-bit down counter. 0 Stopped (initial value) 1 Enabled [bit 14] STGR: Software trigger bit When this bit is set to 1, a software trigger is activated. Whenever this bit is read, a value of 0 is returned. 205 CHAPTER 8 PPG TIMER [bit 13] MDSE: Mode selection bit This bit determines whether the PWM operation in which pulses are generated continuously or the one-shot operation in which only single pulses are generated is used. 0 PWM operation (initial value) 1 One-shot operation [bit 12] RTRG: Restart enable bit This bit determines whether restart through a software trigger or trigger input is allowed. 0 Restart disabled (initial value) 1 Restart enabled [bit 11, bit 10] CKS1, CKS0: Counter clock selection bit These bits select the count clock of the 16-bit down counter. CKS1 CKS0 Cycle 0 0 φ (initial value) 0 1 φ/4 1 0 φ/16 1 1 φ/64 φ: Peripheral machine clock [bit 9] PGMS: PWM output mask selection bit When this bit is set to 1, the PWM output can be masked to 0 or 1 regardless of the mode setting, cycle setting, or duty ratio setting. PWM output when PGMS is set to 1 Polarity PWM output Normal polarity "L" output Reverse polarity "H" output For output of all-high for normal polarity (or all-low for reverse polarity), write the same value to the cycle set register and the duty set register to obtain the reverse output of these mask values. [bit 8] Unused bit 206 CHAPTER 8 PPG TIMER [bit 7, bit 6] EGS1, EGS0: Trigger input edge selection bit These bits select the valid edge for the activation source selected by the general control register 1. When the software trigger bit is set to 1, a software trigger is enabled regardless of the mode selected. EGS1 EGS0 Edge selection 0 0 Disabled (initial value) 0 1 Rising edge 1 0 Falling edge 1 1 Both edges [bit 5] IREN: Interrupt request enable bit This bit specifies whether to enable interrupt requests. 0 Disabled (initial value) 1 Enabled [bit 4] IRQF: Interrupt request flag When bit 5 (IREN) is set to "Enabled", and the interrupt source specified by bit 3 and bit 2 (IRS1 and IRS2) occurs, this bit is set and an interrupt request is issued to the CPU. In addition, when activation of DMA transfer is specified, DMA transfer is started. This bit is cleared when a value of 0 is written and the clear signal is received from the DMAC. The value of this bit does not change even if there is an attempt to set it to 1 via a write operation. When this bit is read by read-modify-write instructions, 1 is returned regardless of the bit value. [bit 3, bit 2] IRS1, IRS0: Interrupt source selection bit These bits select the interrupt source that sets bit 4 (IRQF). IRS1 IRS0 Interrupt source 0 0 Software trigger or trigger input (initial value) 0 1 Counter borrow (cycle match) 1 0 Duty match 1 1 Counter borrow (cycle match) or duty match [bit 1] POEN: PWM output enable bit When this bit is set to 1, the PWM output is generated from the pin. 0 General-purpose port (initial value) 1 PWM output pin 207 CHAPTER 8 PPG TIMER [bit 0] OSEL: PWM output polarity specification bit This bit specifies the polarity of the PWM output. This bit and bit 9 are combined to select the type of PWM output. 208 PGMS OSEL PWM output 0 0 Normal polarity (initial value) 0 1 Reverse polarity 1 0 Fixed to "L" level 1 1 Fixed to "H" level Polarity After reset Normal polarity "L" output Reverse polarity "H" output Duty match Counter borrow CHAPTER 8 PPG TIMER 8.3.2 PWM Cycle Set Register (PCSR0 to PCSR5) The PCSR is a register for setting cycles. It has a buffer. Transfers from the buffer are performed through counter borrows. ■ PWM Cycle Set Register (PCSR0 to PCSR5) The register configuration of the PCSR is shown below. PCSR0 to PCSR5 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Address: ch.0 00009A H ch.1 0000A2 H ch.2 0000AA H bit 0 ch.3 0000B2 H ch.4 0000BA H ch.5 0000C2 H This register is write-only. Initial value is undefined. Note: • When initializing or rewriting the PCSR, be sure to write to the duty set register after writing of the PCSR. • This register must be accessed in 16-bit data. 209 CHAPTER 8 PPG TIMER 8.3.3 PWM Duty Set Register (PDUT0 to PDUT5) The PDUT is a register for setting duties. It has a buffer. Transfers from the buffer are performed through counter borrows. ■ PWM Duty Set Register (PDUT0 to PDUT5) The register configuration of the PDUT is shown below. PDUT0 to PDUT5 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Address: ch.0 00009CH ch.1 0000A4H ch.2 0000ACH bit 0 ch.3 0000B4H ch.4 0000BCH ch.5 0000C4H This register is write-only. Initial value is undefined. If the same value is written to the PCSR and PDUT, all-high is outputted for normal polarity and all-low is outputted for reverse polarity. Note: 210 • Do not set values so that the condition PCSR < PDUT would be met. Otherwise, the PWM output becomes undefined. • This register must be accessed in 16-bit data. CHAPTER 8 PPG TIMER 8.3.4 PWM Timer Register (PTMR0 to PTMR5) The PTMR can be used to read the 16-bit down counter. ■ PWM Timer Register (PTMR0 to PTMR5) The register configuration of the PTMR is shown below. PTMR0 to PTMR5 Address: ch.0 000098 H bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 ch.1 0000A0 H ch.2 0000A8 H bit 0 ch.3 0000B0 H ch.4 0000B8 H ch.5 0000C0 H This register is read-only. Initial value is FFFFH. Note: This register must be accessed in 16-bit data. 211 CHAPTER 8 PPG TIMER 8.3.5 General Control Register 1 (GCN1) The GCN1 selects the source of the PWM timer trigger input. ■ General Control Register 1 (GCN1) The register configuration of the GCN1 is shown below. bit 15 GCN1 bit 14 bit 13 bit 12 bit 11 TSEL33 to TSEL30 Address: 000094H bit 10 bit 9 bit 8 TSEL23 to TSEL20 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 1 0 0 1 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 TSEL13 to TSEL10 Attribute Initial value TSEL03 to TSEL00 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 1 0 0 0 0 Attribute Initial value [bit 15 to bit 12] TSEL33 to TSEL30: ch.3 trigger input selection bit TSEL33 to TSEL30 212 ch.3 trigger input 0 0 0 0 EN0 bit of GCN2 0 0 0 1 EN1 bit of GCN2 0 0 1 0 EN2 bit of GCN2 0 0 1 1 EN3 bit of GCN2 (initial value) 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 X Setting prohibited 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 X X Setting prohibited CHAPTER 8 PPG TIMER [bit 11 to bit 8] TSEL23 to TSEL20: ch.2 trigger input selection bit TSEL23 to TSEL20 ch.2 trigger input 0 0 0 0 EN0 bit of GCN2 0 0 0 1 EN1 bit of GCN2 0 0 1 0 EN2 bit of GCN2 (initial value) 0 0 1 1 EN3 bit of GCN2 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 X Setting prohibited 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 X X Setting prohibited [bit 7 to bit 4] TSEL13 to TSEL10: ch.1 trigger input selection bit TSEL13 to TSEL10 ch.1 trigger input 0 0 0 0 EN0 bit of GCN2 0 0 0 1 EN1 bit of GCN2 (initial value) 0 0 1 0 EN2 bit of GCN2 0 0 1 1 EN3 bit of GCN2 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 X Setting prohibited 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 X X Setting prohibited 213 CHAPTER 8 PPG TIMER [bit 3 to bit 0] TSEL03 to TSEL00: ch.0 trigger input selection bit TSEL03 to TSEL00 214 ch.0 trigger input 0 0 0 0 EN0 bit of GCN2 (initial value) 0 0 0 1 EN1 bit of GCN2 0 0 1 0 EN2 bit of GCN2 0 0 1 1 EN3 bit of GCN2 0 1 0 0 16-bit reload timer ch.0 0 1 0 1 16-bit reload timer ch.1 0 1 1 X Setting prohibited 1 0 0 0 External TRG0 1 0 0 1 External TRG1 1 0 1 0 External TRG2 1 0 1 1 External TRG3 1 1 X X Setting prohibited CHAPTER 8 PPG TIMER 8.3.6 General Control Register 2 (GCN2) The GCN2 activates a start trigger through software. ■ General Control Register 2 (GCN2) The register configuration of the GCN2 is shown below. bit 7 GCN2 bit 6 bit 5 bit 4 Address: 000097H bit 3 bit 2 bit 1 bit 0 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Attribute Initial value When one of the EN3 to EN0 bits for this register is selected by the GCN1 register, the register value is passed to the trigger input of the PWM timer. The PWM timers of multiple channels can be activated at the same time by generating the edge selected by the EGS1 and EGS0 bits of the control status register via software. Note: Bit 7 to bit 4 of this register must be set to 0. 215 CHAPTER 8 PPG TIMER 8.4 PWM Operation The PWM operation allows continuous pulses to be outputted after a start trigger is detected. The cycle and duty ratio of the output pulses can be controlled by changing the values of the PCSR and PDUT, respectively. ■ PWM Operation ❍ When restart is inhibited Figure 8.4-1 shows a timing chart of the PWM operation when trigger restart is inhibited. Figure 8.4-1 Timing Chart of PWM Operation (Trigger Restart Prohibited) Rising edge detected Trigger ignored Start trigger m n o PWM A B T: Count clock cycle m: PCSR value n: PDUT value 216 CHAPTER 8 PPG TIMER ❍ When restart is enabled Figure 8.4-2 shows the timing chart of the PWM operation when trigger restart is enabled. Figure 8.4-2 Timing Chart of PWM Operation (Trigger Restart Enabled) Rising edge detected Restarted by trigger Start trigger m n o PWM A B T: Count clock cycle m: PCSR value n: PDUT value Note: After data is written to PCSR, be sure to write to PDUT. 217 CHAPTER 8 PPG TIMER 8.5 One-shot Operation The one-shot operation allows output for a single pulse of any width through a trigger. If restart is enabled, the counter value is reloaded when the edge is detected during operation. ■ One-shot Operation ❍ When restart is inhibited Figure 8.5-1 shows the timing chart of a one-shot operation when a trigger restart is inhibited. Figure 8.5-1 Timing Chart of a One-shot Operation (Trigger Restart Prohibited) Rising edge detected Trigger ignored Start trigger m n o PWM A B T: Count clock cycle m: PCSR value n: PDUT value 218 CHAPTER 8 PPG TIMER ❍ When restart is enabled Figure 8.5-2 shows the timing chart of a one-shot operation when a trigger restart is enabled. Figure 8.5-2 Timing Chart of One-shot Operation (Trigger Restart Enabled) Rising edge detected Restarted by trigger Start trigger m n o PWM A B T: Count clock cycle m: PCSR value n: PDUT value 219 CHAPTER 8 PPG TIMER 8.6 PWM Timer Interrupt Source and Timing Chart This section describes interrupt sources and provides the related timing charts. ■ Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) Figure 8.6-1 shows the PWM timer interrupt sources and a timing chart. Note: A maximum time of 2.5 T (T: count clock cycle) is required from when a start trigger is activated to when the count value is loaded. Figure 8.6-1 PWM Timer Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) Start trigger Maximum of 2.5 T Load Clock Count value X 0003 0002 0001 0000 0003 PWM Clock Valid edge Duty match Counter borrow ■ Examples for Setting PWM Output to All-low or All-high ❍ Example of setting PWM output to all-low Figure 8.6-2 shows how to set the PWM output to all-low. Figure 8.6-2 Example of Setting PWM Output to All-low PWM Decrease the duty value in stages. 220 Set the PGMS (mask bit) to 1 by issuing a borrow interrupt. Setting the PGMS (mask bit) to 0 with borrow interrupt allows to output a PWM waveform without whisker. CHAPTER 8 PPG TIMER ❍ Example of setting PWM output to all-high level Figure 8.6-3 shows an example of setting PWM output to all-high level. Figure 8.6-3 Example of Setting PWM Output to All-high PWM Increase duty value in stages. Write the same value to duty set register as that set in cycle set register by compare match interrupt. 221 CHAPTER 8 PPG TIMER 8.7 Activating Multiple Channels by Using the General Control Register You can activate multiple channels at the same time by selecting the start trigger with the GCN1 register. This section shows an example of how GCN2 register is set to activate channels via software. ■ Activating Multiple Channels with the GCN [Setting procedure] 1) Set the cycle in the PCSR. 2) Set the duty in the PDUT. Note that the setting must follow the order of PCSR followed by PDUT. 3) Specify the trigger input source for the channel to be activated using GCN1 register. In this case, the initial setting is kept because GCN2 register is used. (ch.0 --> EN0, ch.1 --> EN1, ch.2 --> EN2, ch.3 --> EN3) 4) Set the control status register for the channel to be activated. - CNTE: 1 --> Enables timer operation. - STGR: 0 --> Since the channel is activated by GCN2, this bit is not set. - MDSE: 0 --> Selects PWM operation. - RTRG: 0 --> Inhibits restart. - CSK1, CSK0:00 --> Sets the count clock to φ. - PGMS: 0 --> Does not mask output. (bit 8:0 --> Any value can be set because these bits are unused.) - EGS1, EGS0:01 --> Activates channel at a rising edge - IREN: 1 --> Enables interrupt request. - IRQF: 0 --> Clears interrupt source. - IRS1, IRS0:01 --> Issues interrupt request when counter borrow occurs. - POEN: 1 --> Enables PWM output. - OSEL: 0 --> Sets normal polarity. 5) Activate a start trigger by writing data to GCN2. To activate ch.0 and ch.1 at the same time with the above settings, set the EN0 and EN1 bits of GCN2 to 1. A rising edge is generated and pulses are outputted from PWM0 and PWM1. 222 CHAPTER 8 PPG TIMER ■ When the 16-bit Reload Timer is Used for Activation Specify the 16-bit reload timer as a source in GCN1 register (see 3) above). Start the 16-bit reload timer instead of writing data to GCN2 as in 5) above. In addition, set the control status register as follows: • RTRG: 1 --> Enables restart. • EGS1, EGS0:11 --> Enables activation by both edges By setting 16-bit reload timer output to toggle output mode, the PPG timer can be restarted at fixed intervals. 223 CHAPTER 8 PPG TIMER 224 CHAPTER 9 MULTIFUNCTIONAL TIMER This chapter gives an overview of the multifunctional timer, the configuration and functions of its registers, and its operation. 9.1 Overview of Multifunctional Timer 9.2 Block Diagram of the Multifunctional Timer 9.3 Registers of Multifunctional Timer 9.4 Operations of Multifunctional Timer 225 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.1 Overview of Multifunctional Timer The multifunctional timer consists of the following elements: • 16-bit free-run timer, • Eight 16-bit output compares, • Four 16-bit input captures, • 16-bit PPG timer with 6 channels. This function enables output of waveforms based on the 16-bit free-run timer, as well as measuring the width of input pulses and the external clock cycle. ■ Configuration of the Multifunctional Timer ❍ 16-bit free-run timer (x1) The 16-bit free-run timer consists of a 16-bit up counter, control register, 16-bit compare clear register, and prescaler. The output values of this counter are used as a base timer for output compare and input capture operations. • The user can select a counter operating clock of eight clocks. Eight internal clocks (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, and φ/128) φ: Machine clock • An interrupt can be generated as result of an overflow or compare match with the compare clear register. (For the compare match, a mode must be set.) • The counter value can be initialized to 0000H by reset, software clear, and a compare match with the compare clear register. ❍ Output compare (x8) An output compare consists of eight 16-bit compare registers, a latch for compare output, and a control register. When a 16-bit free-run timer value matches a compare register value and the output level is reversed, interrupts can be generated at the same time. • Eight compare registers can be operated independently. The output compare has an output pin and interrupt flag for each of the compare registers. • Two compare registers can be paired to control output pins in the sense that two compare registers are used to reverse the output levels. • The user can set initial values for the output pins. • An interrupt can be generated by a compare match. ❍ Input capture (x4) An input capture consists of four independent external input pins, the corresponding capture register, and a control register. When any edge of a signal input from an external input pin is detected, a 16-bit free-run timer value can be stored in the capture register and an interrupt can be generated at the same time. • 226 The user can select the significant edges (rising edge, falling edge, and both edges) of external input signals. CHAPTER 9 MULTIFUNCTIONAL TIMER • Four input captures can operate independently. • Interrupts can be generated by the significant edge of an external input signal. ❍ 16-bit PPG timer (x6) See "CHAPTER 8 PPG TIMER". 227 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.2 Block Diagram of the Multifunctional Timer Figure 9.2-1 shows a block diagram of the multifunctional timer unit. ■ Block Diagram of Multifunctional Timer Figure 9.2-1 Block Diagram of Multifunctional Timer φ Interrupt IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 Divider Clock 16-bit free-run timer R-bus 16-bit compare clear register (Ch 6 compare register) Interrupt Compare circuit Compare register 0/2/4/6 CST0 Compare circuit Compare register 1/3/5/7 T Q OC0/2/4/6 T Q OC1/3/5/7 CMOD Select Compare circuit IOP1 IOP0 IOE1 IOE0 Interrupt Interrupt Detection of an edge Capture data register 0/2 EG11 EG10 EG01 Detection of an edge Capture data register 1/3 ICP0 ICP1 ICE0 IN 0/2 EG00 IN 1/3 ICE1 Interrupt Interrupt 228 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.3 Registers of Multifunctional Timer This section lists the registers of the multifunctional timer unit. ■ Registers of Multifunctional Timer See "APPENDIX A I/O Map", for a list of registers of the multifunctional timer unit. 229 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.3.1 Registers of 16-bit Free-run Timer The 16-bit free-run timer has the following three registers. • Data register (TCDT) • Compare clear register • Timer control status register (TCCS) ■ Data Register (TCDT) The register configuration of the data register (TCDT) is as follows: Upper 8 bits of timer data register bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Address: 00008CH T15 T14 T13 T12 T11 T10 T09 T08 R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) bit6 bit5 bit4 bit3 bit2 bit1 bit0 Lower 8 bits of timer data register bit7 Address: 00008CH T07 T06 T05 T04 T03 T02 T01 T00 R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) Attribute Initial value Attribute Initial value This register allows reading the counter value of the 16-bit free-run timer. The counter value is cleared to 0000H at reset. To set a timer value, write it to this register in the stop status (STOP = 1). Access this register in units of words. The 16-bit free-run timer is initialized by following one of the methods below. • Initialization by reset • Initialization by clearing the control status register (SCLR) • Initialization by matching a compare clear register (ch.6 compare register) value with a timer counter value (A mode must be set.) ■ Compare Clear Register This register is a 16-bit compare register for comparison with the 16-bit free-run timer. The ch.6 compare register of an output compare is used. When this register value matches the value of the 16-bit free-run timer, the 16-bit free-run timer value is initialized to 0000H and a compare clear interrupt flag is set. When interrupt operation is allowed, an interrupt request is issued to the CPU. 230 CHAPTER 9 MULTIFUNCTIONAL TIMER ■ Timer Control Status Register (TCCS) The register configuration of the timer control status register (TCCS) is as follows: Upper 8 bits of timer control status register bit15 bit14 Address: 00008EH bit13 bit12 bit11 bit10 bit9 bit8 ( ( ( ( ( ( ECLK R/W (0) ( ) Lower 8 bits of timer control status register bit7 bit6 ) bit5 ) bit4 ) ) ) ) bit3 bit2 bit1 bit0 IVF IVFE STOP MODE SCLR CLK2 CLK1 CLK0 R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) Address: 00008EH Attribute Initial value Attribute Initial value [bit 15]: ECLK This bit is always set to 0 by the write processing. 0 Internal clock source is selected (initial value). 1 Setting is prohibited. [bit 14 to bit 8]: Unused bits [bit 7]: IVF This bit is an interrupt request flag of the 16-bit free-run timer. When an overflow occurs in the 16-bit free-run timer, this bit is set to 1. If an interrupt request permission bit (bit 6: IVFE) is set, an interrupt occurs. This bit is cleared by setting it to 0. Writing 1 has no effect. The reading result of read modify write instructions is always 1. 0 No interrupt request (initial value) 1 Interrupt request [bit 6]: IVFE This bit is an interrupt permission bit for the 16-bit free-run timer. When this bit is 1 and the interrupt flag (bit 7: IVF) is set to 1, an interrupt occurs. 0 Prohibits an interrupt (initial value) 1 Allows an interrupt. [bit 5]: STOP This bit is used to stop the counting of the 16-bit free-run timer. When the bit is set to 1, the counting of the timer is stopped. When the bit is set to 0, the counting of the timer is started. 0 Allows counting (operation) (initial value) 1 Prohibits counting (stop) 231 CHAPTER 9 MULTIFUNCTIONAL TIMER Note: When the 16-bit free-run timer is stopped, output compare operation is stopped as well. [bit 4]: MODE This bit is used to set the initialization condition of the 16-bit free-run timer. When this bit is set to 0, the counter value can be initialized by reset or with the clear bit (bit 3: SCLR). When the bit is set to 1, the counter value can be initialized by reset, with the clear bit (bit 3: SCLR), or by a match with the value of compare register 6 during an output compare operation. 0 Initialization by reset or the clear bit (initial value) 1 Initialization by reset, clear bit, or output comparison with compare register 6 Note: The counter value is initialized when the counter value is changed. [bit 3]: SCLR This bit is used to initialize the value of the operating 16-bit free-run timer to 0000H. When this bit is set to 1, the counter is initialized to 0000H. Setting this bit to 0 has no effect. The returned value during the read operation is always 0. The counter value is initialized when the count value is changed. SCLR Meaning of flag 0 This value has no effect. (initial value) 1 The counter value is initialized to 0000H. Note: When initializing the counter value while the timer is stopped, set the data register to 0000H. [bit 2, bit 1, and bit 0]: CLK2, CLK1, and CLK0 These bits are used to select a count clock for the 16-bit free-run timer. Immediately after these bits are set to a new value, the clock is switched. Therefore, change these bits while the output compare and input capture are stopped. CLK2 CLK1 CLK0 Count clock φ=16MHz φ=8MHz φ=4MHz φ=1MHz 0 0 0 φ 62.5 ns 125 ns 0.25 µs 1 µs 0 0 1 φ/2 125 ns 0.25 µs 0.5 µs 2 µs 0 1 0 φ/4 0.25 µs 0.5 µs 1 µs 4 µs 0 1 1 φ/8 0.5 µs 1 µs 2 µs 8 µs 1 0 0 φ/16 1 µs 2 µs 4 µs 16 µs 1 0 1 φ/32 2 µs 4 µs 8 µs 32 µs 1 1 0 φ/64 4 µs 8 µs 16 µs 64 µs 1 1 1 φ/128 8 µs 16 µs 32 µs 128 µs φ: Machine clock 232 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.3.2 Registers of the Output Compare The output compare has the following two registers. • Compare register (OCCP0 to OCCP7) • Output control register (OCS0 to OCS7) ■ Compare Register (OCCP0 to OCCP7) The register configuration of the compare registers (OCCP0 to OCCP7) is as follows: Upper 8 bits of compare register bit15 Address: 000074H to 000080H bit14 bit13 bit12 bit11 bit10 bit9 OP15 OP14 OP13 OP12 OP11 OP10 OP09 OP08 R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) bit8 Attribute Initial value Lower 8 bits of compare register bit7 Address: 000074H to 000080H bit6 bit5 bit4 bit3 bit2 bit1 OP07 OP06 OP05 OP04 OP03 OP02 OP01 OP00 R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) R/W (X) bit0 Attribute Initial value This register is a 16-bit compare register for comparison with the 16-bit free-run timer. Since the initial value of this register is not fixed, allow activation only after a value has been set. Access this register in word units. When this register value matches a value of the 16-bit free-run timer, a compare signal is issued and an output-compare interrupt flag is set. When output permission is set, the output level corresponding to the compare register is reversed. Note: To rewriting the compare register, within the compare interrupt routine or compare operation is disabled. Be sure not to occur a compare match and writing the compare register simultaneously. ■ Output Control Register (OCS0 to OCS7) The register configuration of the output control registers (OCS0 to OCS7) is as follows: 233 CHAPTER 9 MULTIFUNCTIONAL TIMER Upper 8 bits of output control register bit15 Address: 000084H to 000088H R/W (X) R/W (X) Lower 8 bits of output control register bit7 Address: 000084H to 000088H bit14 bit13 R/W (X) bit6 bit12 bit11 bit10 bit9 CMOD OTE1 OTE0 OTD1 OTD0 R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) bit5 IOP1 IOP0 IOE1 IOE0 R/W (0) R/W (0) R/W (0) R/W (0) bit4 R/W (X) bit3 R/W (X) bit2 bit1 CST1 CST0 R/W (0) R/W (0) bit8 Attribute Initial value bit0 Attribute Initial value This section explains ch.0 and ch.1. The explanation of ch.0 also applies to ch.2, ch.4, and ch.6, while the explanation of ch.1 applies also to ch.3, ch.5, and ch.7. [bit 12]: CMOD If pin output is allowed (OTE1 = 0 or OTE0 = 1), the pin output level reverse operation mode is switched when a compare match is detected. • When CMOD = 0 (initial value), the output level of the pin corresponding to a compare register is reversed. OC0: The level is reversed due to a match with compare register 0. OC1: The level is reversed due to a match with compare register 1. • When CMOD = 1, the output level of compare register 0 is reversed in the same way as when CMOD = 0. However, the output level of the pin (OC1) corresponding to compare register 1 is reversed in case of a match with compare register 0 and a match of compare register 1. When the value of compare register 0 is the same as that of compare register 1, the operation is the same as when a single compare register was used. OC0: The level is reversed due to a match with compare register 0. OC1: The level is reversed due to matches with compare registers 0 and 1. [bit 11 and bit 10]: OTE1 and OTE0 These bits are used to enable pin output of the output compare. 0 Operate as general-purpose ports (PF0 to PF7). (initial value) 1 Output compare pin output is allowed. OTE1: Corresponds to output compare 1. OTE0: Corresponds to output compare 0. [bit 9 and bit 8]: OTD1 and OTD0 These bits are used to change the pin output level, if pin output of the output compare register is allowed. The initial value of the compare pin output is 0. To write a value, stop the compare operation. During a read operation, the output compare pin output value can be read. 234 0 Set the compare pin output to 0. (initial value) 1 Set the compare pin output to 1. CHAPTER 9 MULTIFUNCTIONAL TIMER OTD1: Corresponds to output compare 1. OTD0: Corresponds to output compare 0. [bit 7 and bit 6]: IOP1 and IOP0 These bits are used as interrupt flags of the output compare. When the value of the compare register matches the value of the 16-bit free-run timer, the bits are set to 1. If these bits are set to 1 when the interrupt request bits (IOE1 and IOE0) are enabled, an output-compare interrupt occurs. These bits are cleared by setting them to 0. Writing 1 has no effect. Reading these bits with read modify write instructions always returns 1. 0 No output compare match exists. (initial value) 1 An output compare match exists. IOP1: Corresponds to output compare 1. IOP0: Corresponds to output compare 0. [bit 5 and bit 4]: IOE1 and IOE0 These bits are used to allow an interrupt of the output compare. An output-compare interrupt occurs when these bits are set to 1 and the interrupt flags (IOP1 and IOP0) are also set to 1. 0 Prohibits output-compare interrupts. (initial value) 1 Allows an output-compare interrupt. IOE1: Corresponds to output compare 1. IOE0: Corresponds to output compare 0. [bit 3 and bit 2]: Unused bits [bit 1 and bit 0]: CST1 and CST0 These bits are used to allow a match operation with the 16-bit free-run timer. Before allowing a compare operation, be sure to set a compare register value and an output data register value. 0 Prohibits the compare operation. (initial value) 1 Allows the compare operation. CST1: Corresponds to output compare 1. CST0: Corresponds to output compare 0. Note: • The rewrite processing of the compare register should be performed in the interrupt routine for the comparison, or under the prohibition state of the compare operation so that both of the comparison agreement and the write processing do not occur at the same time. • The output compare is synchronized with the 16-bit free-run timer. Therefore, when the 16-bit free-run timer is stopped, the output compare operation is stopped as well. 235 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.3.3 Registers of Input Capture The input capture has the following two registers: • Input capture data register (IPCP0 to IPCP3) • Input capture control register (ICS01, ICS23) ■ Input Capture Data Register (IPCP0 to IPCP3) The register configuration of the input capture data registers (IPCP0 to IPCP3) is as follows: Upper 8 bits of input capture data register bit15 Address: 000068H, 00006AH 00006CH, 00006EH bit14 bit13 bit12 bit11 bit10 bit9 CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 R (X) R (X) R (X) R (X) R (X) R (X) R (X) R (X) bit8 Attribute Initial value Lower 8 bits of input capture data register bit7 Address: 000068H, 00006AH 00006CH, 00006EH bit6 bit5 bit4 bit3 bit2 bit1 CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 R (X) R (X) R (X) R (X) R (X) R (X) R (X) R (X) bit0 Attribute Initial value The input capture data registers (IPCP0 to IPCP3) are used to store the value of the 16-bit freerun timer when a significant edge of the corresponding external pin input waveform is detected. (Access this register in word units. The user cannot write any value to this register.) ■ Input Capture Control Register (ICS01, ICS23) The register configuration of the input capture control register (ICS01, ICS23) is as follows: Upper 8 bits of capturecontrol register (ICS23) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Address: 000071H ICP3 ICP2 ICE3 ICE2 EG31 EG30 EG21 EG20 R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) Upper 8 bits of capturecontrol register (ICS01) bit7 bit6 bit5 Address: 000073H 236 bit4 bit3 bit2 bit1 bit0 ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) Attribute Initial value Attribute Initial value CHAPTER 9 MULTIFUNCTIONAL TIMER [bit 7 and bit 6]: ICP3, ICP2, ICP1, and ICP0 These bits are used as input-capture interrupt flags. When a significant edge of an external input pin is detected, these bits are set to 1. When the interrupt permission bits (ICE3, ICE2, ICE1, and ICE0) are also set, an interrupt is generated as soon as the significant edge is detected. To clear these bits, set them to 0. Setting these bits to 1 has no effect. Read operations with read modify write instructions always return 1 for these bits. 0 No significant edge is detected. (initial value) 1 A significant edge is detected. ICPn: n corresponds to the channel number of the input capture. [bit 5 and bit 4]: ICE3, ICE2, ICE1, and ICE0 These bits are used as input-capture interrupt permission bits. When these bits are set to 1 and the interrupt flags (ICP3, ICP2, ICP1, and ICP0) are also 1, an input-capture interrupt occurs. 0 Prohibits interrupts. (initial value) 1 Allows an interrupt. ICEn: n corresponds to the channel number of the input capture. [bit 3 to bit 0]: EG31, EG30, EG21, EG20, EG11, EG10, EG01, and EG00 These bits are used to select the significant edge polarity of the external input. They are also used to enable input capture operations. EG31 EG30 Edge detection polarity 0 0 No edge is detected. (stop status) (initial value) 0 1 A rising edge is detected. ↑ 1 0 A falling edge is detected. ↓ 1 1 Both edges are detected. ↑ & ↓ EGn1 and EGn0: n corresponds to the channel number of the input capture. 237 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.4 Operations of Multifunctional Timer This section describes the operations of the multifunctional timer. ■ Explanation of Multifunctional Timer Operation ❍ 16-bit free-run timer The 16-bit free-run timer starts counting from the counter value 0000H after releasing reset. This counter value is the reference time for the 16-bit output compare and 16-bit input capture. ❍ 16-bit output compare The 16-bit output compare compares the set compare register value with the 16-bit free-run timer value. If these values match, an interrupt flag can be set and the output level can be reversed. ❍ 16-bit input capture The 16-bit input capture captures the 16-bit free-run timer value to the capture register to generate an interrupt when the set significant edge is detected. 238 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.4.1 Operation of 16-bit Free-run Timer The 16-bit free-run timer starts counting from the counter value 0000H after releasing reset. The counter value becomes the reference time of the 16-bit output compare and the 16-bit input capture. ■ Explanation of 16-bit Free-run Timer Operation The counter value is cleared under the following conditions. • When an overflow occurs • When the value compare-matches that of the compare clear register (compare register of output compare ch.6) (A mode must be set.) • When the SCLR bit in the TCCS register is set to 1 during operation • When 0000H is written to TCDT register while the timer is stopped An interrupt occurs when an overflow occurs and the counter is cleared because the counter value compare-matches that of the compare clear register. (For a compare match interrupt, a mode must be set.) Figure 9.4-1 shows an example of the output waveform when an overflow occurs and the counter is cleared. Figure 9.4-2 is an example of the output waveform when the counter value comparematches that of the compare clear register, and the counter is cleared. Figure 9.4-1 Clearing the Counter when an Overflow Occurs Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset Interrupt 239 CHAPTER 9 MULTIFUNCTIONAL TIMER Figure 9.4-2 Clearing the Counter when the Counter Value Compare-matches that of the Compare Clear Register Counter value FFFFH Match BFFFH Match 7FFFH 3FFFH Time 0000H Reset Compare register H Interrupt ■ Timing to Clear the 16-bit Free-run Timer The counter is cleared by reset, software, or when the counter value matches that of the compare clear register. When clearing the counter by way of reset or software, it is cleared immediately when a clear command is issued. However, when the counter is cleared because of a match with the value in the compare clear register, clearing is performed in synchronization with the count timing. Figure 9.4-3 shows the clear timing of the free-run timer. Figure 9.4-3 Clear Timing of the Free-run Timer N Compare clear register value Compare match N Counter value 0000 ■ Count Timing of the 16-bit Free-run Timer The counter of the 16-bit free-run timer is incremented by the input clock (internal or external clock). When an external clock is selected, the counter is incremented by a rising edge. Figure 9.4-4 shows the count timing of the 16-bit free-run timer. Figure 9.4-4 Count Timing of the 16-bit Free-run Timer External clock input Count clock Counter value 240 N N+1 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.4.2 Operation of 16-bit Output Compare The 16-bit output compare compares the set compare register value with the value of the 16-bit free-run timer. If the values match, the compare can set an interrupt flag and reverse the output level. ■ Explanation of 16-bit Output Compare Operation ❍ CMOD = 0 A compare operation can be performed independently with a single channel. (When CMOD = 0) Figure 9.4-5 shows an example of the output waveform when compare registers 0 and 1 are used (at the beginning of output, a value of "0" is assumed). Figure 9.4-5 Example of the Output Waveform when Compare Registers 0 and 1 are Used (At the Beginning of Output, 0 is Assumed.) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000 H Time Reset Compare register 0 BFFFH Compare register 1 7FFFH Output compare 0 Output compare 1 Compare 0 interrupt Compare 1 interrupt ❍ 1 when CMOD=1 The output level can be changed by using two pairs of compare registers. (1 when CMOD = 1) Figure 9.4-6 is an example of the output waveform when compare registers 0 and 1 are used (at the beginning of output, a value of "0" is assumed). 241 CHAPTER 9 MULTIFUNCTIONAL TIMER Figure 9.4-6 Example of the Output Waveform when Compare Registers 0 and 1 are Used (At the Beginning of Output, 0 is Assumed.) Counter value FFFFH BFFFH 7FFFH 3FFFH 0000h Time Reset Compare register 0 BFFFH Compare register 1 7FFFH Output compare 0 Output compare 1 Compare 0 interrupt Compare 1 interrupt ■ Timing of 16-bit Output Compare The output level can be changed by using two pairs of compare registers. (One when CMOD = 1) The output compare can generate a compare match signal to reverse output and also generate an interrupt when the value of the free-run timer matches that of the set compare register. The timing of output reverse at a compare match is synchronized with the count timing of the counter. Figure 9.4-7 is a timing chart of the 16-bit output compare. Figure 9.4-7 Timing Chart of 16-bit Output Compare N Counter value Value of compare clear register N+1 N Compare match Interrupt Counter value Value of compare clear register N N N+1 N+1 N Compare match Pin output Note: The rewrite processing of the compare register should be performed in the interrupt routine for the comparison, or under the prohibition state of the compare operation so that both of the comparison agreement and the write processing do not occur at the same time. 242 CHAPTER 9 MULTIFUNCTIONAL TIMER 9.4.3 Operation of 16-bit Input Capture When the set significant edge is detected, the 16-bit input capture can capture the 16-bit free-run timer value to the capture register to generate an interrupt. ■ Operation of 16-bit Input Capture Figure 9.4-8 shows an example of capture timing for the 16-bit input capture. Figure 9.4-8 Example of Capture Timing for the 16-bit Input Capture Counter value FFFFH BFFFH 7FFFH 3FFFH Time 0000H Reset IN0 IN1 IN example Data register 0 Not fixed 3FFFH Data register 1 Data register example BFFFH Not fixed Not fixed BFFFH 7FFFH Capture 0 interrupt Capture 1 interrupt Capture example interrupt Capture 0 = rising edge Capture 1 = falling edge Capture example = both edges (example) An interrupt occurs again because of a significant edge. Clearing an interrupt by use of software 243 CHAPTER 9 MULTIFUNCTIONAL TIMER ■ Input Timing of 16-bit Input Capture Figure 9.4-9 shows the input timing of the 16-bit input capture. Figure 9.4-9 Input Timing of 16-bit Input Capture Counter value N N+1 Input capture input Significant edge Capture signal Capture register value Interrupt 244 N+1 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK This chapter gives an overview of the external interrupt control block, the structure and functions of the registers, and the operation of the external interrupt control block. 10.1 Overview of External Interrupt Control Block 10.2 External Interrupt Control Block Registers 10.3 External Interrupt Control Block Operation 10.4 External Interrupt Request Level 245 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.1 Overview of External Interrupt Control Block The external interrupt control block is a block that controls external interrupt requests received through INT0 to INT15. You can select one of the following request levels to be detected: high, low, rising edge, or falling edge. ■ Block Diagram of the External Interrupt Control Block Figure 10.1-1 shows a block diagram of the external interrupt control block. Figure 10.1-1 Block Diagram of the External Interrupt Control Block R -b us 16 Interrupt request 16 16 32 246 Interrupt enable register Gate Source F/F Interrupt source register Request level set register Edge detection circuit 16 I NT 0 to I NT 15 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2 External Interrupt Control Block Registers Figure 10.2-1 lists the registers in the external interrupt control block. ■ List of External Interrupt Control Block Registers Figure 10.2-1 List of External Interrupt Control Block Registers External interrupt enable register (ENIR0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address: 0000C9H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 External interrupt enable register (ENIR1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 External interrupt source register (EIRR0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address: 0000C8H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 External interrupt source register (EIRR1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ER15 ER14 ER13 ER12 ER11 ER10 ER9 ER8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LB11 LA11 LB10 LA10 LB9 LA9 LB8 LA8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 Address: 0000CBH Address: 0000CAH Request level set register (ELVR0) Address: 0000CCH Request level set register (ELVR1) Address: 0000CEH Since two sets of these registers (eight channels) are included in this block, a total of 16 channels are provided. 247 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2.1 Interrupt Enable Register (ENIR0, ENIR1) The interrupt enable register (ENIR0, ENIR1) masks external interrupt request output. ■ Interrupt Enable Register (ENIR0, ENIR1: Interrupt ENable Register 0,1) The register configuration of the interrupt enable register (ENIR0, ENIR1) is shown below. ENIR 0 Address:0000C9H E N I R1 Address:0000CBH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EN7 EN6 EN5 EN4 E N3 EN2 EN1 EN0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value E N9 E N8 00000000B [R/W] E N1 5 E N1 4 E N1 3 E N1 2 E N1 1 E N1 0 Initial value 00000000B [R/W] The output of interrupt requests, corresponding to this register bit being set to 1, is enabled (INT0 is enabled by EN0), and the request is outputted to the interrupt controller. The pins for which the corresponding bit is set to 0 retain an interrupt source but do not issue an interrupt request to the interrupt controller. 248 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2.2 External Interrupt Request Register (EIRR0, EIRR1) During a read operation, the external interrupt request register (EIRR0, EIRR1) indicates whether a corresponding external interrupt request exists. A write operation clears the value in the flip-flop indicating the request. ■ External Interrupt Source Register (EIRR0, EIRR1: External Interrupt Request Register 0,1) The register configuration of the external interrupt source register (EIRR0, EIRR1) is shown below. E I R R0 Address:0000C8H E I R R1 A d d r e s s : 0 0 0 0 C AH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000B bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value E R1 2 E R1 1 E R1 0 E R9 E R8 00000000B E R1 5 E R1 4 E R1 3 [R/W] [R/W] When a bit of this register is 1, the pin corresponding to the bit has received an external interrupt request. When a bit of this register is set to 0, the value in the flip-flop corresponding to the bit, which indicates a request, is cleared. Writing 1 to this register is prohibited. When this register is read by read-modify-write instructions, 1 is returned. 249 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.2.3 External Interrupt Level Setting Register (ELVR0, ELVR1) The external level register (ELVR0, ELVR1) selects the level at which an interrupt request is detected. ■ External Level Register (ELVR0, ELVR1: External Level Register) The register configuration of the external level register (ELVR0, ELVR1) is shown below. ELVR 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value Address:0000CC H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000 B bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Initial value LB 7 LA 7 LB 6 LA 6 LB 5 LA 5 LB4 LA 4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value LB 11 LA 11 LB 1 0 LA 10 LB9 LA 9 LB8 LA8 00000000 B bit 15 bit 11 bit 10 bit 9 bit 8 Initial value ELVR 1 Address:0000CE H bit 14 bit 13 bit 12 LB 15 LA 15 LB 14 LA 14 LB13 LA 13 LB 12 LA 12 00000000 B 00000000 B [R/ W] [R/ W] [R/ W] [R/ W] INT0 to INT15 has two bits that specify the operations shown below. If you specify that the request be detected at a low or high level, even when each bit of the EIRR is cleared, the corresponding bits are set again when active-level input occurs. Table 10.2-1 is the external interrupt level setting. Table 10.2-1 External Interrupt Level Setting 250 LB15 to LB0 LA15 to LA0 Operation 0 0 "L" level request 0 1 "H" level request 1 0 Rising edge request 1 1 Falling edge request CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.3 External Interrupt Control Block Operation When the request specified by the ELVR register is inputted to the corresponding pin after the request level and enable register are set, this module issues an interrupt request signal to the interrupt controller. ■ External Interrupt Operation When the interrupt issued from this resource has the highest priority of all the interrupts issued concurrently in the interrupt controller, the appropriate interrupt is generated. Figure 10.3-1 shows the operation for an external interrupt. Figure 10.3-1 External Interrupt Operation External interrupt Interrupt controller CPU Resource request ELVR EIRR ENIR Interrupt Level I CR YY CMP I CR XX CMP I LM Interrupt source ■ Return from Stop State When the rising or falling edge request is selected, the return from the stop state of the clock stop mode is not performed. ■ Setting Procedure for an External Interrupt To set the registers in the external interrupt block, follow the steps below. 1. The general-purpose I/O port that is shared with the pin used as input of external interrupt is set to the input port 2. Disable the appropriate bits of the interrupt enable register. 3. Set the appropriate bits of the external level register. 4. Clear the appropriate bits of the external interrupt source register. 5. Enable the appropriate bits of the interrupt enable register. Steps 4 and 5 can be performed concurrently by writing 16-bit data. Before setting registers included in this module, be sure to disable the interrupt enable register. In addition, before enabling the interrupt enable register, be sure to clear the external interrupt source register. This prevents interrupt sources from being accidentally generated when the registers are set or interrupts are enabled. 251 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 10.4 External Interrupt Request Level When the request level is the edge request, a minimum of three machine cycles (peripheral clock machine cycles) are required for edge detection. When the request input level is in accordance with the level setting, even if the request input previously issued externally is canceled, the request to the interrupt controller remains active because the internal source-holding circuit retains it. To cancel the request to the interrupt controller, clear the external interrupt source register. ■ External Interrupt Request Level Figure 10.4-1 shows how the source holding circuit is cleared when the level is set. Figure 10.4-2 shows how interrupt sources are inputted when interrupt sources are enabled and how an interrupt request is issued to the interrupt controller. Figure 10.4-1 Clearing the Source-holding Circuit During Level Setting Interrupt input Level detection Enable gate Source F/F (Source-holding circuit) To interrupt controller Sources are retained until holding circuit is cleared. Figure 10.4-2 Interrupt-source Input with Interrupts Enabled and Interrupt Request to the Interrupt Controller Interrupt input "H" level Interrupt request to interrupt controller Inactivated by clearing source F/F ■ Notes on using External Interrupt to Return from STOP State where Clock Oscillation is Stopped In a STOP state where clock oscillation is stopped, the first external interrupt signal which is input to the INT pin can be input asynchronously to allow the device to return from the STOP state. Note, however, that in a period from when the STOP state is released to when the oscillation stabilization wait time elapses, there is a period in which the input of other external interrupt signals cannot be recognized (the period "b" + "c" in Figure 10.4-3). This is because the external input signal after the release of the STOP state is synchronized with the internal clock, and as a consequence, that interrupt source cannot be retained while the clock is unstable. Therefore, input an external interrupt signal after the oscillation stabilization wait time has elapsed, when inputting an external interrupt after the STOP state is released. 252 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK The following figure shows an example of when INT1 for level detection is input after INT0 for edge detection. The level input which is input during the oscillation stabilization wait time is not detected. Figure 10.4-3 Sequence of Return Operation from STOP State by External Interrupt INT1 INT0 Internal STOP Execution of instruction (run) Internal operation (RUN) X0 Internal Clock Clearing of interrupt flag Interrupt source bit ER0 Internal source bit ER1 (a)STOP (d) RUN (b) Oscillation time of oscillator (c) Oscillation stabilization time of oscillator ■ Return Operation from STOP State The STOP return operation of the current circuit using an external interrupt is performed as described below. ❍ Handling steps before device enters STOP state Setting external interrupt Set the corresponding external interrupt input pin to a port input as it is necessary to enable interrupt input pass in a STOP state before the device enters the STOP state. Inputting external interrupt The external interrupt signal is set to send the input signal asynchronously, when the device returns from the STOP state. As soon as this interrupt input is asserted, the internal STOP signal falls. At the same time, the external interrupt circuit is switched so as to synchronize other level interrupt input. ❍ Oscillation time of oscillator The clock starts oscillating upon the detection of an external interrupt. The oscillation time varies depending on the oscillator used. ❍ Oscillation stabilization wait time The oscillation stabilization wait time is taken within the device after the oscillation time of the oscillator. The oscillation stabilization wait time is specified by OS1 and OS0 bits in the standby control register. Upon the completion of the oscillation stabilization wait time, the internal clock is supplied, instruction operation is started by the external interrupt, and any external interrupt source other than the source for returning from the STOP state can be accepted. 253 CHAPTER 10 EXTERNAL INTERRUPT CONTROL BLOCK 254 CHAPTER 11 DELAYED INTERRUPT MODULE This chapter gives an overview of the delayed interrupt module, the structure and functions of the registers, and the operation of the delayed interrupt module. 11.1 Overview of Delayed Interrupt Module 11.2 Delayed Interrupt Control Register (DICR) 11.3 Operation of Delayed Interrupt Module 255 CHAPTER 11 DELAYED INTERRUPT MODULE 11.1 Overview of Delayed Interrupt Module The delayed interrupt module issues an interrupt for switching tasks. This module can be used to issue or cancel an interrupt request to the CPU via software. ■ Block Diagram of the Delayed Interrupt Module A block diagram of the delayed interrupt module is shown in Section "12.2 Block Diagram of the Interrupt Controller". ■ List of Delayed Interrupt Module Registers Figure 11.1-1 lists the delayed interrupt module registers. Figure 11.1-1 List of Delayed Interrupt Module Registers bit 7 Address: 000430H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DLYI R/W 256 DICR CHAPTER 11 DELAYED INTERRUPT MODULE 11.2 Delayed Interrupt Control Register (DICR) The delayed interrupt control register (DICR) controls delayed interrupts. ■ Delayed Interrupt Control Register (DICR) The register configuration of the delayed interrupt control register (DICR) is shown below. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Address: 000430H bit 0 DLYI -------0B (Initial value) R/W [bit0] DLYI This bit controls issuing and canceling of the appropriate interrupt sources. DLYI Description 0 Delayed interrupt source not canceled or requested (initial value) 1 Delayed interrupt source issued 257 CHAPTER 11 DELAYED INTERRUPT MODULE 11.3 Operation of Delayed Interrupt Module The delayed interrupt function issues interrupts for switching tasks. This function can be used to issue or cancel an interrupt request to the CPU via software. ■ Interrupt Number The delayed interrupt is assigned to the interrupt source corresponding to the maximum interrupt number. For the MB91150, the delayed interrupt is assigned to interrupt number 63 (3FH). ■ DLYI Bit of DICR To issue a delayed interrupt source, set this bit to 1. To cancel the delayed interrupt source, set this bit to 0. This bit is the same as that used as interrupt-source flag of general interrupts. Use the interrupt routine to clear this bit and switch tasks. 258 CHAPTER 12 INTERRUPT CONTROLLER This chapter provides an overview of the interrupt controller, its block diagram, the structure and functions of the registers, the operation of the interrupt controller. 12.1 Overview of Interrupt Controller 12.2 Block Diagram of the Interrupt Controller 12.3 List of Interrupt Control Registers 12.4 Priority Evaluation 12.5 Return from Standby (Stop or Sleep) Mode 12.6 Hold-Request Cancellation Request 12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR) 259 CHAPTER 12 INTERRUPT CONTROLLER 12.1 Overview of Interrupt Controller The interrupt controller accepts and arbitrates interrupts. ■ Hardware Configuration of Interrupt Controller This module consists of the following components. • Interrupt control register (ICR register: ICR00 to ICR47) • Interrupt priority evaluation circuit • Interrupt level and interrupt number (vector) generator • HOLD request cancellation request generator ■ Main Functions of the Interrupt Controller This module performs the following functions: 260 • Detecting an interrupt request. • Evaluating the interrupt priority (based on levels and numbers) • Forwarding the result of source-interrupt level evaluation (to the CPU) • Forwarding the result of source-interrupt number evaluation (to the CPU) • Indicating a recovery from the stop mode through interrupt generation • Issuing HOLD request cancellation requests to the bus master CHAPTER 12 INTERRUPT CONTROLLER 12.2 Block Diagram of the Interrupt Controller Figure 12.2-1 shows a block diagram of the interrupt controller. ■ Block Diagram of the Interrupt Controller Figure 12.2-1 Block Diagram of the Interrupt Controller *2 INT0 IM Priority evaluation OR 5 5 NMI handling NMI LEVEL4 to LEVEL0 4 Hold request Level evaluation ICR00 Resource interrupt RI00 Vector evaluation 6 Level and vector generation Cancellation request HLDCAN *3 6 VCT5 to VCT0 ICR47 RI47 *1 (DLYIRQ) *1 *2 *3 Note) DLYI DLYI in the figure represents the delayed interrupt block (see CHAPTER 11 "DELAYED INTERRUPT MODULE"). INT0 is the wake-up signal for a clock control block in sleep or stop state. HLDCAN is the bus-release request signal for a bus master other than the CPU. This device type does not have the NMI function. 261 CHAPTER 12 INTERRUPT CONTROLLER 12.3 List of Interrupt Control Registers Figure 12.3-1 lists the registers of the interrupt control. ■ List of Interrupt Control Registers Figure 12.3-1 List of Interrupt Control Registers bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address : 00000400H ICR3 ICR2 ICR1 ICR0 ICR00 Address : 00000401H ICR3 ICR2 ICR1 ICR0 ICR01 Address : 00000402H ICR3 ICR2 ICR1 ICR0 ICR02 Address : 00000403H ICR3 ICR2 ICR1 ICR0 ICR03 Address : 00000404H ICR3 ICR2 ICR1 ICR0 ICR04 Address : 00000405H ICR3 ICR2 ICR1 ICR0 ICR05 Address : 00000406H ICR3 ICR2 ICR1 ICR0 ICR06 Address : 00000407H ICR3 ICR2 ICR1 ICR0 ICR07 Address : 00000408H ICR3 ICR2 ICR1 ICR0 ICR08 Address : 00000409H ICR3 ICR2 ICR1 ICR0 ICR09 Address : 0000040AH ICR3 ICR2 ICR1 ICR0 ICR10 Address : 0000040BH ICR3 ICR2 ICR1 ICR0 ICR11 Address : 0000040CH ICR3 ICR2 ICR1 ICR0 ICR12 Address : 0000040DH ICR3 ICR2 ICR1 ICR0 ICR13 Address : 0000040EH ICR3 ICR2 ICR1 ICR0 ICR14 Address : 0000040FH ICR3 ICR2 ICR1 ICR0 ICR15 Address : 00000410H ICR3 ICR2 ICR1 ICR0 ICR16 Address : 00000411H ICR3 ICR2 ICR1 ICR0 ICR17 Address : 00000412H ICR3 ICR2 ICR1 ICR0 ICR18 Address : 00000413H ICR3 ICR2 ICR1 ICR0 ICR19 Address : 00000414H ICR3 ICR2 ICR1 ICR0 ICR20 Address : 00000415H ICR3 ICR2 ICR1 ICR0 ICR21 Address : 00000416H ICR3 ICR2 ICR1 ICR0 ICR22 Address : 00000417H ICR3 ICR2 ICR1 ICR0 ICR23 Address : 00000418H ICR3 ICR2 ICR1 ICR0 ICR24 Address : 00000419H ICR3 ICR2 ICR1 ICR0 ICR25 Address : 0000041AH ICR3 ICR2 ICR1 ICR0 ICR26 Address : 0000041BH ICR3 ICR2 ICR1 ICR0 ICR27 Address : 0000041CH ICR3 ICR2 ICR1 ICR0 ICR28 Address : 0000041DH ICR3 ICR2 ICR1 ICR0 ICR29 Address : 0000041EH ICR3 ICR2 ICR1 ICR0 ICR30 Address : 0000041FH ICR3 ICR2 ICR1 ICR0 ICR31 R/W R/W R/W R/W (Continued) 262 CHAPTER 12 INTERRUPT CONTROLLER (Continued) bit 7 bit 3 bit 2 bit 1 bit 0 Address : 00000420H ICR3 ICR2 ICR1 ICR0 ICR32 Address : 00000421H ICR3 ICR2 ICR1 ICR0 ICR33 Address : 00000422H ICR3 ICR2 ICR1 ICR0 ICR34 Address : 00000423H ICR3 ICR2 ICR1 ICR0 ICR35 Address : 00000424H ICR3 ICR2 ICR1 ICR0 ICR36 Address : 00000425H ICR3 ICR2 ICR1 ICR0 ICR37 Address : 00000426H ICR3 ICR2 ICR1 ICR0 ICR38 Address : 00000427H ICR3 ICR2 ICR1 ICR0 ICR39 Address : 00000428H ICR3 ICR2 ICR1 ICR0 ICR40 Address : 00000429H ICR3 ICR2 ICR1 ICR0 ICR41 Address : 0000042AH ICR3 ICR2 ICR1 ICR0 ICR42 Address : 0000042BH ICR3 ICR2 ICR1 ICR0 ICR43 Address : 0000042CH ICR3 ICR2 ICR1 ICR0 ICR44 Address : 0000042DH ICR3 ICR2 ICR1 ICR0 ICR45 Address : 0000042EH ICR3 ICR2 ICR1 ICR0 ICR46 Address : 0000042FH ICR3 ICR2 ICR1 ICR0 ICR47 R/W R/W R/W R/W LVL3 LVL2 LVL1 LVL0 R/W R/W R/W R/W Address : 00000431H bit 6 bit 5 bit 4 HRCL 263 CHAPTER 12 INTERRUPT CONTROLLER 12.3.1 Interrupt Control Register (ICR00 to ICR47) This register controls interrupts. One of these registers exists for each interrupt input and is used to set the interrupt level of the corresponding interrupt request. ■ Interrupt Control Register (ICR00 to ICR47) The register configuration of the interrupt control register (ICR00 to ICR47) is shown below. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ICR3 ICR2 ICR1 ICR0 R/W R/W R/W R/W ----1111B (Initial value) [bit 3 to 0] ICR3 to ICR0 These are interrupt-level setting bits and specify the interrupt level of the corresponding interrupt request. If the interrupt level specified in this register is equal to or greater than to the level mask value specified in the ILM register of the CPU, the interrupt request is masked by the CPU. These bits are initialized to 1111B at reset. The interrupt-level setting bits that can be set and the corresponding interrupt levels are shown in Table 12.3-1. 264 CHAPTER 12 INTERRUPT CONTROLLER Table 12.3-1 Interrupt-level Setting Bits and Corresponding Interrupt Levels ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level 0 0 0 0 0 0 0 1 1 1 0 14 0 1 1 1 1 15 (NMI) 1 0 0 0 0 16 1 0 0 0 1 17 Highest level that can be set (High) 1 0 0 1 0 18 1 0 0 1 1 19 1 0 1 0 0 20 1 0 1 0 1 21 1 0 1 1 0 22 1 0 1 1 1 23 1 1 0 0 0 24 1 1 0 0 1 25 1 1 0 1 0 26 1 1 0 1 1 27 1 1 1 0 0 28 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 Reserved by the system (Low) Interrupt disabled The ICR4 is fixed to 1. 265 CHAPTER 12 INTERRUPT CONTROLLER 12.3.2 Hold-Request Cancellation-Request Level-Set Register (HRCL) This register sets the level for issuing hold-request cancellation requests. ■ Hold-request Cancellation Request Level Set Register (HRCL) The register configuration of the hold-request cancellation-request level-set register (HRCL) is shown below. bit 7 bit 6 bit 5 Address :000431H bit 4 bit 3 bit 2 bit 1 bit 0 LVL3 LVL2 LVL1 LVL0 R/W R/W R/W R/W ----1111B (Initial value) [bits3 to 0] LVL3 to LVL0 These bits set the interrupt level for issuing hold-request cancellation requests. If an interrupt request with an interrupt level higher than that specified in this register is issued, a hold-request cancellation request is issued to the bus master. 266 CHAPTER 12 INTERRUPT CONTROLLER 12.4 Priority Evaluation This module selects the interrupt source with the highest priority, out of all interrupt sources that occur at the same time and outputs the interrupt level and interrupt number of the source to the CPU. ■ Priority Evaluation The criteria for evaluating the priority are shown below. 1. NMI 2. The interrupt source meets the following conditions: • The interrupt source has an interrupt level other than "31" (A value of "31" represents interrupt disable.) • The interrupt source has the lowest interrupt level • The interrupt source has the smallest interrupt number Table 12.4-1 shows the relationship among interrupt sources, interrupt numbers, and interrupt levels. Table 12.4-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1/2) Interrupt number Decimal Hexadecimal Interrupt level (NMI request) 15 0F 15(FH) fixed 3C0H 000FFFC0H External interrupt 0 16 10 ICR00 3BCH 000FFFBCH External interrupt 1 17 11 ICR01 3B8H 000FFFB8H External interrupt 2 18 12 ICR02 3B4H 000FFFB4H External interrupt 3 19 13 ICR03 3B0H 000FFFB0H External interrupt 4 20 14 ICR04 3ACH 000FFFACH External interrupt 5 21 15 ICR05 3A8H 000FFFA8H External interrupt 6 22 16 ICR06 3A4H 000FFFA4H External interrupt 7 23 17 ICR07 3A0H 000FFFA0H External interrupt 8 to 15 24 18 ICR08 39CH 000FFF9CH System-reserved 25 19 ICR09 398H 000FFF98H UART0 (Receiving completed) 26 1A ICR10 394H 000FFF94H UART1 (Receiving completed) 27 1B ICR11 390H 000FFF90H UART2 (Receiving completed) 28 1C ICR12 38CH 000FFF8CH UART3 (Receiving completed) 29 1D ICR13 388H 000FFF88H System-reserved 30 1E ICR14 384H 000FFF84H 31 1F ICR15 380H 000FFF80H Interrupt source UART0 (Sending completed) Offset TBR default address 267 CHAPTER 12 INTERRUPT CONTROLLER Table 12.4-1 Relationship Among Interrupt Sources, Interrupt Numbers, and Interrupt Levels (2/2) Interrupt number Decimal Hexadecimal Interrupt level Offset TBR default address UART1 (Sending completed) 32 20 ICR16 37CH 000FFF7CH UART2 (Sending completed) 33 21 ICR17 378H 000FFF78H UART3 (Sending completed) 34 22 ICR18 374H 000FFF74H I 2C 35 23 ICR19 370H 000FFF70H DMAC (Exit and error) 36 24 ICR20 36CH 000FFF6CH Reload timer 0 37 25 ICR21 368H 000FFF68H Reload timer 1 38 26 ICR22 364H 000FFF64H Reload timer 2 39 27 ICR23 360H 000FFF60H Reload timer 3 40 28 ICR24 35CH 000FFF5CH 41 29 IRC25 358H 000FFF58H A/D 42 2A ICR26 354H 000FFF54H PPG0 43 2B ICR27 350H 000FFF50H PPG1 44 2C ICR28 34CH 000FFF4CH PPG2 45 2D ICR29 348H 000FFF48H PPG3 46 2E ICR30 344H 000FFF44H PPG4 47 2F ICR31 340H 000FFF40H PPG5 48 30 ICR32 33CH 000FFF3CH U/D counter 0 49 31 ICR33 338H 000FFF38H U/D counter 1 50 32 ICR34 334H 000FFF34H ICU0 (Fetch) 51 33 ICR35 330H 000FFF30H ICU1 (Fetch) 52 34 ICR36 32CH 000FFF2CH ICU2 (Fetch) 53 35 ICR37 328H 000FFF28H ICU3 (Fetch) 54 36 ICR38 324H 000FFF24H OCU0 (Coincidence) 55 37 ICR39 320H 000FFF20H OCU1 (Coincidence) 56 38 ICR40 31CH 000FFF1CH OCU2 (Coincidence) 57 39 ICR41 318H 000FFF18H OCU3 (Coincidence) 58 3A ICR42 314H 000FFF14H OCU4/5 (Coincidence) 59 3B ICR43 310H 000FFF10H OCU6/7 (Coincidence) 60 3C ICR44 30CH 000FFF0CH System-reserved 61 3D ICR45 308H 000FFF08H 16-bit free running timer 62 3E ICR46 304H 000FFF04H Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H Interrupt source System-reserved 268 CHAPTER 12 INTERRUPT CONTROLLER ■ Releasing Interrupt Factors The interrupt routine has restrictions on the relationship between an instruction for releasing interrupt factors and the RETI instruction. For details, see "CHAPTER 3 MEMORY SPACE, CPU, AND CONTROL UNIT". 269 CHAPTER 12 INTERRUPT CONTROLLER 12.5 Return from Standby (Stop or Sleep) Mode This module implements the function that enables a return from the stop mode through interrupts. ■ Return from Standby (Stop or Sleep) Mode If at least one interrupt request is issued from a peripheral, the request for returning from the stop mode is sent to the clock control block. Since the priority evaluation block restarts operation after the clock signal is supplied upon return from stop mode, the CPU continues executing instructions until the result is outputted from the priority evaluation block. The same operation is performed when returning from the sleep state. The registers in this module are accessible in the sleep state. Note: For interrupt sources you do not want to use to return from the stop and sleep states, set the control register for the corresponding peripheral to prohibit the interrupt request output. Since the return request signal in the standby state is generated by simply logical sum of all interrupt sources, the contents of the interrupt level specified in ICR register are not applied. 270 CHAPTER 12 INTERRUPT CONTROLLER 12.6 Hold-Request Cancellation Request To handle an interrupt with a higher priority while the CPU is in hold status, the requester of the hold request must cancel that request. The interrupt level used to determine whether a hold-request cancellation request is issued needs to be set in the HRCL register. ■ Criteria for Determining whether a Hold-request Cancellation-request must be Issued If an interrupt source with an interrupt level higher than that specified in the HRCL register is issued, a hold-request cancellation request must be generated. • Interrupt level of HRCL register is greater than interrupt level after evaluating priority --> Cancellation request issued • Interrupt level of HRCL register is equal to or less than interrupt level after evaluating priority -> Cancellation request not issued Since this cancellation request is valid unless the interrupt source is cleared, DMA transfer does never start. Be sure to clear the corresponding interrupt source. ■ Levels that can be Set for Hold Request Cancellation Requests A number from 0000B to 1111B can be set in the HRCL register. When 1111B is set, the cancellation request is issued for all interrupt levels. When 0000B is set, the cancellation request is issued only for NMI. Table 12.6-1 lists the interrupt levels for which the hold-request cancellation request is issued. Table 12.6-1 Interrupt Levels for which the Hold-request Cancellation Request is Issued HRCL register Interrupt levels for which the hold-request cancellation request is issued 16 (Only NMI) 17 Interrupt level 16 18 Interrupt levels 16 and 17 : 31 : Interrupt levels 16 to 30 [initial value] Note: After a reset, DMA transfer is disabled for all interrupt levels. This means that DMA transfer is not performed when an interrupt has been issued. Therefore, set the HRCL register to the appropriate value. 271 CHAPTER 12 INTERRUPT CONTROLLER 12.7 Example of Using Hold-Request Cancellation-Request Function (HRCR) To let the CPU perform an operation with a higher priority during DMA transfer, the DMA must release the hold state by canceling the hold request. In this case, use an interrupt to cause the DMA to cancel the hold request. This allows the CPU to operate with a higher priority. ■ Control Register ❍ HRCL (Hold-request cancellation-level set register): this module When an interrupt with the priority level higher than that specified in this register occurs, the holdrequest cancellation-request is issued to the DMA. This register is used to set the base level. ❍ ICR: this module For the ICR register corresponding to the interrupt source used, set an interrupt level higher than that specified in the HRCL register. ❍ PDRR (DMA request disable register): clock control block This register temporarily disables a hold request from the DMA. It prevents the system from entering the hold state again by clearing the interrupt source. A hold request from the DMA is passed to the CPU only when this register is set to 0000B. The contents of this register must be incremented at the beginning of the interrupt routine and decremented at the end of the interrupt routine. ■ Hardware Configuration The signal flow of each signal is shown below. Figure 12.7-1 Sample Hardware Configuration for Using a Hold-request Cancellation-request This module IRQ DHRQ: HRQ: HACK: IRQ: HRCR: 272 (ICR) (HRCL) Clock control block (PDRR) HRQ DMA HRCR DHRQ DMA hold request Hold request Hold acknowledge Interrupt request Hold request cancellation request HACK CPU CHAPTER 12 INTERRUPT CONTROLLER ■ Hold-request Cancellation-request Sequence ❍ Example for the interrupt routine Figure 12.7-2 is a sample timing chart of the hold-request cancellation-request sequence (interrupt level HRCL > a). Figure 12.7-2 Sample Timing Chart of the Hold-request Cancellation-request Sequence (Interrupt Level is HRCL > a) RUN Bus hold CPU Interrupt handling (1)(2) (3) (4) Bus hold (DMA transfer) DHRQ HRQ HACK IRQ LEVEL a HRCR PDRR 0000 0001 0000 (1) PDRR incremented (2) Interrupt source cleared (3) PDRR decremented (4) RETI When an interrupt request is issued, the interrupt level is changed. If this level is higher than the level specified in the HRCL register, the HRCR is activated for the DMA. This causes the DMA to cancel the hold request. The CPU returns from the hold state and performs interrupt handling. The interrupt routine increments PDRR and clears the interrupt source. This causes the interrupt level to vary, inactivates the HRCR, and allows the DMA to issue a hold request again. However, because the PDRR is not 0, this hold request is blocked. To enable DMA transfer again, decrement the PDRR to pass the hold request to the CPU. 273 CHAPTER 12 INTERRUPT CONTROLLER ❍ Example for multiple interrupt routine Figure 12.7-3 is a sample timing chart for multiple interrupts. Figure 12.7-3 Sample Timing of the Hold-request Cancellation-request Sequence (HRCL > a > b) RUN Bus hold Interrupt I (1) CPU Interrupt handling II (5)(6) (7)(8) b a Interrupt handling I (2) Bus hold (3) (4) DHRQ HRQ HACK IRQ1 IRQ2 LEVEL a HRCR PDRR 0000 0001 0002 0001 0000 (1), (5) Increment PDRR. (2), (6) Clear the interrupt source. (3), (7) Decrement PDRR. (4), (8) RETI In this example, an interrupt with a higher priority occurs while interrupt routine is running. This example also prevents a hold request from being issued accidentally by incrementing the PDRR at the beginning of each interrupt routine and decrementing the PDRR at the end of the routine. Notes: 274 • Increment the PDRR at the beginning of the interrupt routine that is processed while DMA transfer is performed (the CPU is held), and decrement it at the end of the interrupt routine. Otherwise, DMA transfer is performed again while the interrupt routine is being executed. • In addition, do not increment and decrement the PDRR in a normal routine. This degrades performance because DMA transfer cannot be performed while the interrupt routine is being executed. • Exercise caution when setting interrupt levels in the HRCL register and in the ICR register. CHAPTER 13 8/10-BIT A/D CONVERTER This chapter provides an overview of the 8/10-bit A/D converter, its block diagram, configuration and functions of its registers, and operation of the 8/10-bit A/D converter. 13.1 Overview of the 8/10-bit A/D Converter 13.2 8/10-bit A/D Converter Block Diagram 13.3 8/10-bit A/D Converter Pins 13.4 8/10-bit A/D Converter Registers 13.5 8/10-bit A/D Converter Interrupt 13.6 Operation of the 8/10-bit A/D Converter 13.7 A/D Converted Data Preservation Function 13.8 Notes on Using the 8/10-bit A/D Converter 275 CHAPTER 13 8/10-BIT A/D CONVERTER 13.1 Overview of the 8/10-bit A/D Converter The 8/10-bit A/D converter converts an analog voltage (input voltage) that is inputted to an analog input pin into a digital value. ■ Features of the 8/10-bit A/D Converter The 8/10-bit A/D converter changes an analog input voltage into a 10-bit or 8-bit digital value based on the RC successive approximation conversion method. Signals are inputted through eight analog input channel pins, and software, internal clock, or external pin trigger can be selected as a cause of startup of conversion. The 8/10-bit A/D converter has the following features: • The minimum conversion time is 5.0 µs (including the sampling time, when the machine clock frequency is 33 MHz). • The RC successive approximation conversion method is applied using a sampling/holding circuit. • For the resolution, 10 bits or 8 bits can be selected. • Any of the eight channels can be selected for the analog input pins by a program. • An interrupt request can be generated at the end of A/D conversion. • When interrupts are enabled, no data is lost during continuous conversion due to the converted data-preservation function. • Software, 16-bit reload timer 2 (rising edge), or external pin trigger (falling edge) can be selected as a cause for starting conversion. ■ Conversion Modes of 8/10-bit A/D Converter The following three conversion modes are supported. Table 13.1-1 8/10-bit A/D Converter Conversion Modes Conversion mode Single conversion operation Scan conversion operation Singleconversion mode The converter converts a signal input from a specified channel (only one channel) and terminates. The converter simultaneously converts signal inputs from contiguous multiple channels (up to eight channels can be specified) and terminates. Continuousconversion mode The converter continuously converts signal inputs from a specified channel (only one channel). The converter continuously converts signal inputs from contiguous multiple channels (up to eight channels can be specified). Stop-conversion mode The converter converts a signal input from the specified channel (only one channel), then stops temporarily until it is started again. The converter continuously converts signal inputs from continuous multiple channels (up to eight channels can be specified). However, the converter temporarily stops after converting a signal input until it is started again. 276 CHAPTER 13 8/10-BIT A/D CONVERTER 13.2 8/10-bit A/D Converter Block Diagram Figure 13.2-1 is a block diagram of the 8/10-bit A/D converter. ■ 8/10-bit A/D Converter Block Diagram Figure 13.2-1 8/10-bit A/D Converter Block Diagram AVRH, AVSS AVRL AVSS MPX D/A converter Input circuit AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Successive appro -ximation register Comparator R-bus Sampling and holding circuit Decoder Data register ADCR A/D control register 1 A/D control register 2 16-bit reload timer 2 External pin trigger ADCS1, ADCS2 Operation clock Prescaler The function of each block is as follows. ❍ A/D control status registers (ADCS1, ADCS2) The A/D control status registers can be used for starting conversion via software, selecting a start trigger, selecting a conversion mode, selecting an A/D conversion channel, and enabling/ disabling interrupt requests. Moreover, they can be used for checking the state of interrupt requests, and indicating that the converter is temporarily stopped or converting signals. 277 CHAPTER 13 8/10-BIT A/D CONVERTER ❍ A/D data register (ADCR) Stores the result of A/D conversion. This register also selects the resolution of A/D conversion. ❍ Clock selector Selects an A/D conversion start clock. 16-bit reload timer ch.2 output or external pin trigger can be selected for the start clock. ❍ Decoder Selects the analog input pin to be used in accordance with the setting of the ANE0 to ANE2 bits and ANS0 to ANS2 bits for the A/D control status register (ADCS1). ❍ Analog channel selector Selects one of the eight analog input pins to be used. ❍ Sampling/holding circuit Maintains the input voltage from the pin selected by the analog channel selector. This circuit samples and holds the input voltage immediately after A/D conversion is started to allow conversion to be performed without being affected by fluctuations in the input voltage during A/D conversion (comparison). ❍ D/A converter Generates a reference voltage used for comparison with the input voltage that is sampled and held. ❍ Comparator Compares the input voltage that is sampled and held with the D/A converter output voltage to determine which is higher respectively lower. ❍ Control circuit Determines the A/D conversion value based on whether a high or low signal is sent from the comparator. After A/D conversion, the result of conversion is stored in the A/D data register (ADCR), after which an interrupt request is generated. 278 CHAPTER 13 8/10-BIT A/D CONVERTER 13.3 8/10-bit A/D Converter Pins This section provides the 8/10-bit A/D converter pins and the block diagram of the pins. ■ 8/10-bit A/D Converter Pins The 8/10-bit A/D converter pins are also used as general-purpose ports. Table 13.3-1 lists the functions, I/O formats of the pins, and settings when the 8/10-bit A/D converter is used. Table 13.3-1 8/10-bit A/D Converter Pins Function Pin name ch.0 PK0/AN0 ch.1 PK1/AN1 ch.2 PK2/AN2 ch.3 PK3/AN3 ch.4 PK4/AN4 ch.5 PK5/AN5 ch.6 PK6/AN6 ch.7 PK7/AN7 Pin function I/O format Port K I/O, analog input CMOS output, CMOS hysteresis input or analog input Pull-up setting None Standby control I/O port settings required for use of the pins None Port K is set for input. (DDRK: bit 0 to bit 7 = 0) Pins are set for analog input. (AICR bit 0 to bit 7 = 1) 279 CHAPTER 13 8/10-BIT A/D CONVERTER ■ 8/10-bit A/D Converter Pin Block Diagram Figure 13.3-1 is a block diagram of the 8/10-bit A/D converter pins. Figure 13.3-1 Block Diagram of the Pins PK0/AN0 to PK7/AN7 AICR Analog input Internal data bus PDR (port data register) PDR read Output latch PDR write Pin DDR (port direction register) Direction latch DDR write DDR read Standby control Notes: 280 • For the pins to be used as input ports, set the DDRK register bits corresponding to these pins to 0 and apply pull-up resistance to the external pin. Also, set the AICR register bits corresponding to the pins to 0. • For pins to be used as analog input pins, set the AICR register bits corresponding to these pins to 1 as well. The value that is read from the PDRK register at this time is 0. CHAPTER 13 8/10-BIT A/D CONVERTER 13.4 8/10-bit A/D Converter Registers Figure 13.4-1 provides a schema of the 8/10-bit A/D converter registers. ■ Schema of the 8/10-bit A/D Converter Registers Figure 13.4-1 Schema of the 8/10-bit A/D Converter Registers bit 15 14 13 12 11 10 9 8 7 0000EBH 0000E6H 0000E4H 6 5 4 3 2 1 0 AICR ADCS1 ADCS0 ADCR 281 CHAPTER 13 8/10-BIT A/D CONVERTER 13.4.1 A/D Control Status Register 1 (ADCS1) A/D control status register 1 (ADCS1) is used for starting conversion via software, selecting a start trigger, enabling/disabling interrupt requests, checking the state of interrupt requests, and indicating when the converter is temporarily stopped or converting signals. ■ A/D Control Status Register 1 (ADCS1) Figure 13.4-2 shows the configuration and provides a functional outline of the A/D control status register 1 (ADCS1). Figure 13.4-2 Configuration and Functional Outline of A/D Control Status Register 1 (ADCS1). bit15 0000E6H bit14 bit13 bit12 bit11 bit10 bit9 bit8 BUSY INT INTE PAUS STS1 STS0 STRT RESV R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) W (0) R/W (0) RESV bit0 bit7 (ADCS0) Reserved bit Be sure to set this bit to 0. STRT A/D conversion start bit (effective only when start via software is specified) 0 Do not start the A/D conversion function. 1 Starts the A/D conversion function. STS1 STS0 0 0 0 1 1 0 1 1 A/D start source selection bit Start via software Start via zero detection or start via software Start via 16-bit reload timer or start via software Start via zero detection, start via 16-bit reload timer, or start via software 0 Temporary stop flag bit A/D conversion operation is not temporarily stopped. 1 A/D conversion operation is temporarily stopped. PAUS INTE Interrupt request permission bit 0 Disables output of interrupt requests. 1 Enables output of interrupt requests. Interrupt request flag bit INT 0 1 BUSY During read A/D conversion has not ended. A/D conversion has ended. 0 1 282 No changes and no external effect Converting bits During read R/W: Read/Write enabled W: Write only 0, 1: Initial value During write This bit is cleared. A/D conversion is being stopped. A/D conversion is being performed. During write A/D conversion is forcibly stopped. No changes and no external effect CHAPTER 13 8/10-BIT A/D CONVERTER [bit 15] BUSY (Converting bit) • This is the bit for indicating that the A/D converter is currently performing a conversion. • When a read access shows that this bit is 0, the converter is not executing an A/D conversion. When the bit is 1, an A/D conversion is in progress. • Setting this bit to 0 in a write operation forcibly stops the A/D conversion. Setting this bit to 1 has no effect. (Note) Do not specify forcible stop and start via software (BUSY = 0 and STRT = 1) at the same time. [bit 14] INT (Interrupt request flag bit) • When data is stored in the A/D data register via A/D conversion, this bit is set to 1. • When both this bit and the interrupt request permission bit (ADCS: INTE) are set to 1, an interrupt request is generated. • This bit is cleared by setting it to 0 via a write operation. Setting this bit to 1 has no effect. (Note) Clear this bit by setting it to 0 in a write operation while the A/D converter is stopped. [bit 13] INTE (Interrupt request permission bit) • This bit enables/disables output of an interrupt to the CPU. • When both this bit and the interrupt request flag bit (ADCS: INT) are 1, an interrupt request is generated. [bit 12] PAUS (Temporary stop flag bit) • This bit becomes 1 when the A/D conversion operation is temporarily stopped. • This A/D converter has only one A/D data register. Thus, when continuous-conversion mode is used, and if the CPU has not read the result of a previous conversion, the result of the previous conversion is lost when the data in the register is overwritten with the result of the next conversion. Therefore, in continuous-conversion mode, it is normally required to ensure that the result of a conversion is transferred to memory whenever a conversion ends. However, there may be cases where a transfer of converted data is not completed by the time the next conversion starts due to multiple interrupts. This bit is used for addressing this problem. If this bit is set to 1, A/D conversion is stopped in the period from when a conversion ends to when the content in the data register is fully transferred so that the data register is not overwritten with the data from the next conversion. [bit 11, 10] STS1, STS0 (A/D start cause selection bits) • These bits select the cause for starting A/D conversion. • When multiple causes are specified as the start source, the start source that occurred first is used for start. (Note) The change in the start procedure becomes effective as soon as a new cause has been written. Therefore, if start causes are to be changed during A/D conversion, change the start causes in a period in which no new start causes need to be applied. 283 CHAPTER 13 8/10-BIT A/D CONVERTER [bit 9] STRT (A/D conversion start bit) • This bit is used for starting A/D conversion from software. • Setting this bit to 1 in a writing operation starts A/D conversion. • In stop-conversion mode, this bit cannot restart A/D conversion. (Note) Do not specify forcible stop and start via software (BUSY = 0 and STRT = 1) at the same time. [bit 8] RESV (Reserved bit) (Note) Be sure to set this bit to 0. 284 CHAPTER 13 8/10-BIT A/D CONVERTER 13.4.2 A/D Control Status Register 0 (ADCS0) A/D control status register 0 (ADCS0) is used for selecting a conversion mode and A/D conversion channel. ■ A/D Control Status Register 0 (ADCS0) Figure 13.4-3 shows the configuration and function outline of A/D control status register 0 (ADCS0). Figure 13.4-3 Configuration and Functional Outline of A/D Control Status Register 0 (ADCS0) bit15 0000E7H bit8 (ADCS1) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) R/W (0) ANE2 ANE1 0 0 ANE0 A/D conversion end channel selection bits 0 AN0 pin 0 0 1 AN1 pin 0 1 0 AN2 pin 0 1 1 AN3 pin 1 0 0 AN4 pin 1 0 1 AN5 pin 1 1 0 AN6 pin 1 1 1 AN7 pin ANS2 ANS1 ANS0 A/D conversion start channel selection bits At a stop R/W: Read/Write enabled 0, 1: Initial value Read operation during conversion Read operation at a stop in stopconversion mode Number of the channel for which a signal is being converted Number of the channel for which conversion has been performed immediately before 0 0 0 AN0 pin 0 0 1 AN1 pin 0 1 0 AN2 pin 0 1 1 AN3 pin 1 0 0 AN4 pin 1 0 1 AN5 pin 1 1 0 AN6 pin 1 1 1 AN7 pin MD1 MD0 A/D conversion mode selection bits 0 0 0 1 1 0 1 1 Single-conversion mode 1 (A converter operating in this mode can be restarted.) Single-conversion mode 2 (A converter operating in this mode cannot be restarted.) Continuous-conversion mode (A converter operating in this mode cannot be restarted.) Stop-conversion mode (A converter operating in this mode cannot be restarted.) 285 CHAPTER 13 8/10-BIT A/D CONVERTER [bit 7, 6] MD1, MD0 (A/D conversion mode selection bits) • These bits are used for selecting the A/D conversion mode. • Single-conversion mode 1, single-conversion mode 2, continuous-conversion mode, or stopconversion mode is selected in accordance with the values in the MD1 and MD0 bits. • The operation in each mode is as follows: • Single-conversion mode 1: Consecutively performs A/D conversion between the channel specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0 only once. The converter can be restarted. • Single-conversion mode 2: Consecutively performs A/D conversion between the channel specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0 only once. The converter cannot be restarted. • Continuous-conversion mode: Repeatedly performs A/D conversion between the channel specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0 until operation is forcibly stopped with the BUSY bit. The converter cannot be restarted. • Stop-conversion mode: Repeatedly performs A/D conversion between the channel specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0, temporarily stopping A/D conversion on a per-channel basis, until it is forcibly stopped by the BUSY bit. The converter cannot be restarted. A temporarily stopped A/D conversion is restarted in accordance with the start source selected with the STS1 and STS0 bits. Note: • When the converter cannot be restarted in single-, continuous-, or stop-conversion modes, the converter cannot be restarted by the timer, external trigger, or software. • Restart can be performed during A/D conversion when A/D conversion mode selection bits (MD1, MD0) are set to "00B". In this mode, only the software start-up option (STS1, STS0 = "00B") can be selected. Perform the restart in the following steps. (1) Clear the INT bit to 0. (2) Write "1" to the STRT bit at the same time as writing "0" to the INT bit. [bit 5, 4, 3] ANS2, ANS1, ANS0 (A/D conversion start channel selection bits) • These bits are used to specify the channel on which A/D conversion starts, and for checking the number of the channel on which conversion is being performed. • The converter starts A/D conversion from the channel specified by these bits. • The number of the channel on which conversion is being performed can be read during A/D conversion. While A/D conversion is being temporarily stopped in stop-conversion mode, the number of the channel for which conversion was previously performed can be read. [bit 2, 1, 0] ANE2, ANE1, ANE0(A/D conversion end channel selection bits) 286 • These bits specify the channel at which A/D conversion ends. • A/D conversion is performed up to the channel specified by these bits at the start of A/D conversion. • When the channel specified by ANS2 through ANS0 is specified by these bits, A/D conversion is performed only for this channel. CHAPTER 13 8/10-BIT A/D CONVERTER When continuous-conversion mode or stop-conversion mode is specified, A/D conversion control returns to the start channel specified by ANS2 to ANS0 after A/D conversion is performed for the channel specified by these bits. When the specified start channel number is larger than the specified end channel number, conversion is performed from the start channel to AN7, then from AN0 to the end channel in a cycle. Note: Please do not set the A/D conversion mode setting bit (MD1,MD0) and the A/D conversion end channel selection bit (ANE2, ANE1, ANE0) by the read-modify-write type instruction after setting the start channel to the A/D conversion start channel selection bit (ANS2, ANS1, ANS0). From ANS2, ANS1, and the ANS0 bit, the last conversion channel is read until starting the A/D conversion. Therefore, when MD1, the MD0 bit, ANE2, ANE1, and the ANE0 bit are set by the readmodify-write type instruction after setting the start channel to ANS2, ANS1, and the ANS0 bit, the value of ANE2, ANE1, and the ANE0 bit may be written. 287 CHAPTER 13 8/10-BIT A/D CONVERTER 13.4.3 A/D Data Register (ADCR) The A/D data register (ADCR) stores the result of A/D conversion. This register is also used for selecting the resolution of A/D conversion. ■ A/D Data Register (ADCR) The figure below shows the configuration and functional outline of the A/D data register (ADCR). Figure 13.4-4 Configuration and Functional Outline of A/D Data Register (ADCR) 0000E4H bit15 bit14 bit13 bit12 bit11 S10 ST1 ST0 CT1 CT0 bit9 bit8 D9 D8 W (0) W (0) W (1) W (0) W (1) (X) R (X) R (X) bit7 bit6 D7 D6 bit5 bit4 bit3 bit2 bit1 bit0 D5 D4 D3 D2 D1 R (X) R (X) D0 R (X) R (X) R (X) R (X) R (X) R (X) bit10 D0 to D9 A/D data bits Converted data CT1 288 Comparison time setting bits 0 0 34 machine cycles 0 1 67 machine cycles 1 0 100 machine cycles 1 1 122 machine cycles ST1 ST0 0 0 11 machine cycles 0 1 23 machine cycles 1 0 33 machine cycles 1 1 45 machine cycles S10 R: Read only W: Write only 0, 1: Initial value CT0 Sampling time setting bits A/D conversion resolution selecting bit 0 10-bit resolution mode (D9 to D0) 1 8-bit resolution mode (D7 to D0) CHAPTER 13 8/10-BIT A/D CONVERTER [bit 15] S10 (A/D conversion resolution selection bit) • This bit is used for selecting the resolution of A/D conversion. • Setting this bit to 0 in a writing operation selects a resolution of 10 bits. Setting this bit to 1 selects a resolution of 8 bits. Note: Which data bits are used depends on the resolution. [bit 14, 13] ST1, ST0 (Sampling time setting bits) • These bits are used for selecting the A/D conversion sampling time. • After A/D conversion is started, analog input is acquired for the time specified by these bits. Note: When 00 for 8 MHz is specified when 16-MHz operation is used, analog voltages may not be correctly acquired. [bit 12, 11] CT1, CT0 (Comparison time setting bit) • These bits are used to select the comparison time for A/D conversion. • After analog input is acquired (the sampling time elapses) and the time specified by these bits elapses, the converted data is fixed and stored in bit 9 to bit 0 of this register. Note: when 00 for 8 MHz is specified in cases where 16-MHz operation is used, the analog converted value may not be correctly obtained. [bit 10] Unused bit [bit 9 to bit 0] D9 to D0 • The result of A/D conversion is stored. The content of this register is rewritten every time conversion is completed. • Normally, the final value of conversion is stored. • The initial value of this register is undetermined. Note: The device has a function for saving converted data. Do not write these bits during A/D conversion. Notes: • Be sure to rewrite the S10 bit during a stop of the A/D conversion operation and before the conversion operation is restarted. When the S10 bit is rewritten after conversion, the content of the ADCR becomes unknown. • When the 10-bit mode is specified, be sure to use the word transfer command to read data from the ADCR register. 289 CHAPTER 13 8/10-BIT A/D CONVERTER 13.5 8/10-bit A/D Converter Interrupt The 8/10-bit A/D converter can generate an interrupt request when data is set in the A/D data register during A/D conversion. ■ 8/10-bit A/D Converter Interrupt Table 13.5-1 shows the 8/10-bit A/D converter interrupt control bits and the cause for an interrupt. Table 13.5-1 8/10-bit A/D Converter Interrupt Control Bits and Cause for an Interrupt 8/10-bit A/D converter Interrupt request flag bit ADCS1:INT Interrupt request permission bit ADCS1:INTE Cause of interrupt Writing the A/D conversion result to the A/D data register When the A/D conversion operation is started and the A/D conversion result is set to the A/D data register (ADCR), the INT bit of the A/D control status register 1 (ADCS1) is set to 1. If the interrupt request is enabled (ADCS1: INTE = 1), an interrupt request is then outputted to the interrupt controller. 290 CHAPTER 13 8/10-BIT A/D CONVERTER 13.6 Operation of the 8/10-bit A/D Converter The 8/10-bit A/D converter supports three modes: single-conversion mode, continuousconversion mode, or stop-conversion mode. This section describes the operation of the converter in each mode. ■ Operation in Single-conversion Mode In single-conversion mode, analog inputs from channels specified by the ANS bits and ANE bits are converted in sequence. After conversion is done for the end channel specified by the ANE bits, A/D conversion ends. When the start channel is the same as the end channel (ANS = ANE), conversion is performed only for the channel specified by the ANS bits. To operate the converter in single-conversion mode, the setting shown in Figure 13.6-1 is required. Figure 13.6-1 Single-conversion Mode Setting bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ADCS0, BUSY INT INTE PAUS STS1 STS0 STRT Re- MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 served ADCS1 0 ADCR S10 ST1 ST0 CT1 CT0 Stores converted data. : Used bit : Set the bit corresponding to the used pin to 1. 0 : Set 0. AICR Note: The following shows examples for the conversion sequences in single-conversion mode. ANS = 000B, ANE = 011B: AN0 --> AN1 --> AN2 --> AN3 --> End ANS = 110B, ANE = 010B: AN6 --> AN7 --> AN0 --> AN1 --> AN2 --> End ANS = 011B, ANE = 011B: AN3 --> End ■ Operation in Continuous-conversion Mode In the continuous-conversion mode, analog inputs from channels specified by the ANS bits and ANE bits are converted in sequence. After conversion is done for the end channel specified by the ANE bits, A/D conversion control returns to the analog input channel specified by the ANS bits, before A/D conversion for the channel continues. When the start channel is same as the end channel (ANS = ANE), conversion is repeatedly performed only for the channel specified by the ANS bits. To operate the converter in continuous-conversion mode, the setting shown in Figure 13.6-2 is required. 291 CHAPTER 13 8/10-BIT A/D CONVERTER Figure 13.6-2 Continuous-conversion Mode Setting bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ADCS0, BUSY INT INTE PAUS STS1 STS0 STRT Reserved MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 ADCS1 0 ADCR 1 0 Stores converted data. S10 ST1 ST0 CT1 CT0 : : 1 : 0 : AICR Used bit Set the bit corresponding to the used pin to 1. Set 1. Set 0. Note The following shows examples for the conversion sequences in continuous-conversion mode. ANS = 000B, ANE = 011B: AN0 --> AN1 --> AN2 --> AN3 --> AN0 --> Repeat ANS = 110B, ANE = 010B: AN6 --> AN7 --> AN0 --> AN1 -->AN2 --> AN6 --> Repeat ANS = 011B, ANE = 011B: AN3 --> AN3 --> Repeat ■ Operation in Stop-conversion Mode In stop-conversion mode, analog inputs from channels specified by the ANS bits and ANE bits are converted with a temporary stop of each of the channels. After conversion is performed for the end channel specified by the ANE bits, A/D conversion control returns to the analog input channel specified by the ANS bits, and A/D conversion continues from the channel that was temporarily stopped. When the start channel is the same as the end channel (ANS = ANE), conversion is repeatedly performed only for the channel specified by the ANS bits. To restart a conversion that was temporarily stopped, generate the start source specified by the STS1 and STS0 bits. To operate the converter in stop-conversion mode, the setting shown in Figure 13.6-3 is required. Figure 13.6-3 Stop-conversion Mode Setting bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ReADCS0, ADCS1 BUSY INT INTE PAUS STS1 STS0 STRT served MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 0 ADCR 1 S10 ST1 ST0 CT1 CT0 Stores converted data. : : 1: 0: AICR 0 Used bit Set the bit corresponding to the used pin to 1. Set 1. Set 0. Note: The following shows examples for the conversion sequences in stop-conversion mode. ANS = 000B, ANE = 011B: AN0 --> Temporary stop --> AN1 --> Temporary stop --> AN2 --> Temporary stop --> AN0 --> Repeat ANS = 110B, ANE = 001B: AN6 --> Temporary stop --> AN7 --> Temporary stop --> AN0 --> Temporary stop --> AN1 --> Temporary stop --> AN6 --> Repeat ANS = 011B, ANE = 011B: AN3 --> Temporary stop --> AN3 --> Temporary stop --> Repeat 292 CHAPTER 13 8/10-BIT A/D CONVERTER 13.7 A/D Converted Data Preservation Function The converted data preservation function is executed when A/D conversion is performed while interrupts are enabled. ■ A/D Converted Data Preservation Function A/D converter has only one data register for storing converted data. When A/D conversion is performed, data stored in the data register is rewritten at the end of conversion. Therefore, if the converted data is not fully transferred to memory before the converted data in the data register is rewritten, some of the data is lost. To cope with this problem, the data preservation function is executed when interrupts are enabled (INTE = 1) as described below. When converted data is stored in the A/D data register (ADCR), the INT bit of A/D control status register 1 (ADCS1) is set to 1. While this bit is 1, A/D conversion temporarily stops. When the INT bit is cleared after the data in the A/D data register (ADCR) is transferred to memory within the interrupt routine, the temporary stop is released. Notes: • The converted data preservation function operates only when interrupts are enabled (ADCS1: INTE = 1). • Restarting the converter while it is temporarily stopped might lead to corruption of the data on standby. 293 CHAPTER 13 8/10-BIT A/D CONVERTER 13.8 Notes on Using the 8/10-bit A/D Converter This section provides notes on using the 8/10-bit A/D converter. ■ Notes on Using the 8/10-bit A/D Converter ❍ Analog input pin The A/D input pins are also used as I/O pins for port K. The pins are switched using the port K direction register (DDRK) and analog input control register (AICR). For a pin to be used for analog input, set the DDRK bit corresponding to the pin to 0 to set the pin as the input port, then specify the analog input mode using the AICR register to fix the input gate for the port. While port input mode is set, the input leak current flows to the gate if an intermediate level signal is inputted. ❍ Note on using the A/D converter with the internal timer To start the A/D converter with the internal timer, specify the STS1 and STS0 bits of A/D control status register 1 (ADCS1) and also set the value for internal timer inputs to inactive (L for the internal timer). When it is set to active, the internal timer may start operating as soon as a write operation to the ADCS register is performed. ❍ Priorities of A/D converter power and analog input Be sure to apply the power to the A/D converter (AVCC, AVRH, AVRL) and analog input (AN0 to AN7) after or as soon as the digital power supply (VCC) is turned on. Also, be sure to turn off the digital power (VCC) after or as soon as the power to the A/D converter and analog input are cut off. ❍ Power supply voltage of the A/D converter To prevent a latch-up, set an A/D converter voltage (AVCC) that does not exceed the voltage of the digital power (VCC). ❍ Restart during A/D conversion Restart can be performed during A/D conversion when A/D conversion mode selection bits (MD1, MD0) are set to "00B". In this mode, only the software start-up option (STS1, STS0 = "00B") can be selected. Perform the restart in the following steps. (1) Clear the INT bit to 0. (2) Write "1" to the STRT bit at the same time as writing "0" to the INT bit. 294 CHAPTER 14 8-BIT D/A CONVERTER This chapter provides an overview of the 8-bit D/A converter, the block diagram, the configuration and functions of the registers, and the operation of the 8-bit D/A converter. 14.1 Overview of the 8-bit D/A Converter 14.2 8-bit D/A Converter Block Diagram 14.3 8-bit D/A Converter Registers 14.4 8-bit D/A Converter Operation 295 CHAPTER 14 8-BIT D/A CONVERTER 14.1 Overview of the 8-bit D/A Converter This 8-bit D/A converter supports a resolution of 8 bits and is an R-2R type D/A converter. ■ Features of the 8-bit D/A Converter The MB91150 contains a 3-channel D/A converter. The D/A control registers can control the output of the three channels separately. 296 CHAPTER 14 8-BIT D/A CONVERTER 14.2 8-bit D/A Converter Block Diagram The 8-bit D/A converter consists of the following three blocks: • 8-bit resistance ladder • Data registers • Control registers ■ 8-bit D/A Converter Block Diagram Figure 14.2-1 shows the 8-bit D/A converter block diagram. Figure 14.2-1 8-bit D/A Converter Block Diagram R-bus DAVC DA27 DA07 to DA00 DA17 to DA10 DA27 to DA20 DA20 DAVC DA17 DA10 DAVC DA07 DA00 DAE2 DAE1 DAE0 Standby control Standby control Standby control D/A output ch.2 D/A output ch.1 D/A output ch.0 ■ 8-bit D/A Converter Pins The 8-bit D/A converter pins are exclusively used for the D/A converter. 297 CHAPTER 14 8-BIT D/A CONVERTER 14.3 8-bit D/A Converter Registers Figure 14.3-1 lists the 8-bit D/A converter registers. ■ List of the 8-bit D/A Converter Registers Figure 14.3-1 List of the 8-bit D/A Converter Registers bit 7 DADR0 0000E3H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 D/A data register 0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 DADR1 0000E2H bit 0 bit 8 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 D/A data register 1 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 DADR2 0000E1H DACR0 0000DFH DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 D/A data register 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 - - - - - - - bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 DACR1 0000DEH - - - - - - - bit 0 DAE0 D/A control register 0 bit 8 DAE1 D/A control register 1 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 DACR2 0000DDH 298 - - - - - - - DAE2 D/A control register 2 CHAPTER 14 8-BIT D/A CONVERTER 14.3.1 D/A Control Registers (DACR0, DACR1, DACR2) The D/A control registers (DACR0, DACR1, and DACR2) enable or disable D/A converter output. ■ D/A Control Registers (DACR0, DACR1, DACR2) The figure below shows the configuration of the D/A control registers (DACR0, DACR1, DACR2). DACR0 0000DFH bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 - - - - - - - bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 DACR1 0000DEH - - - - - - - bit 0 DAE0 Initial value -------0B R/W bit 8 DAE1 Initial value -------0B R/W bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 DACR2 0000DDH - - - - - - - DAE2 Initial value -------0B R/W [bit 0] DAE2, DAE1, DAE0 • DAE2, DAE1, and DAE0 are used to control the output of ch.2, ch.1, and ch.0, respectively. • When bit 0 is set to 1, D/A output is enabled. When bit 0 is set to 0, D/A output is disabled. • A reset initializes these bits to 0. These bits can be both read and written. • When output is disabled, the D/A converter output pins are set to the output level of 0. 299 CHAPTER 14 8-BIT D/A CONVERTER 14.3.2 D/A Data Registers (DADR2, DADR1, DADR0) The D/A data registers (DADR2, DADR1, and DADR0) specify the D/A converter output voltage. ■ D/A Data Registers (DADR2, DADR1, DADR0) The figure below shows the configuration of the D/A data registers (DADR2, DADR1, DADR0). bit 7 DADR0 0000E3H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 DADR1 0000E2H bit 0 R/W bit 8 DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 DADR2 0000E1H DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W [bit 23 to bit 16] DA27 to DA20 • These bits are used to set the output voltage of D/A converter ch.2. • A reset does not initialize these bits. These bits can be both read and written. [bit 15 to bit 8] DA17 to DA10 • These bits are used to set the output voltage of D/A converter ch.1. • A reset does not initialize these bits. These bits can be both read and written. [bit 7 to bit 0] DA07 to DA00 300 • These bits are used to set the output voltage of D/A converter ch.0. • A reset does not initialize these bits. These bits can be both read and written. CHAPTER 14 8-BIT D/A CONVERTER 14.4 8-bit D/A Converter Operation D/A output starts by setting the desired D/A output value in the D/A data register (DADR) and setting the permission bit for the D/A output channel in the D/A control register (DACR) to 1. ■ Operation of the 8-bit D/A Converter When D/A output is disabled. The D/A converter is also internally cleared to an output state of 0, and the direct current routes are cut off. This operation is also performed in the stop mode. This D/A converter does not have a built-in buffer amplifier for its output. In addition, an analog switch (nearly equal to 100 Ω) is connected to its output in series. For external output load, always take the required settling time into consideration. The D/A converter output voltage ranges from 0 V to 255/256 x DAVC. External adjustments to the DAVC voltage change the output voltage range. Table 14.4-1 shows the logical values of the D/A converter output voltages. Table 14.4-1 Logical Values of the 8-bit D/A Converter Output Voltages Values specified in DA07 to DA00 DA17 to DA10 DA27 to DA20 8-bit D/A converter 00H 0/256 x DAVC (=0V) 01H 1/256 x DAVC 02H 2/256 x DAVC : : FDH 253/256 x DAVC FEH 254/256 x DAVC FFH 255/256 x DAVC 301 CHAPTER 14 8-BIT D/A CONVERTER 302 CHAPTER 15 UART This chapter describes the UART, the block diagram, pins, the configuration and functions of UART registers, and UART operations. 15.1 Overview of the UART 15.2 UART Block Diagram 15.3 UART Pins 15.4 UART Registers 15.5 UART Interrupts 15.6 Receive-Interrupt Generation and Flag Set Timing 15.7 Send-Interrupt Generation and Flag Set Timing 15.8 Baud Rate 15.9 UART Operations 15.10 Notes on Using UART 303 CHAPTER 15 UART 15.1 Overview of the UART The UART is a general-purpose serial data communication interface for synchronous or asynchronous communication (start-stop synchronization) with external devices. The UART has an ordinary bidirectional communication function (normal mode) and a master/slave-type communication function (multiprocessor mode: Only the master is supported). ■ UART Features The UART is a general-purpose serial data communication interface that sends serial data to and receives serial data from other CPUs and peripheral devices. The UART has the functions listed in Table 15.1-1. Table 15.1-1 UART Functions Function Data buffer Full-duplex double buffer Transfer mode • • Synchronous with the clock (without start/stop bits) Asynchronous with the clock (start-stop synchronization cycle) Baud rate • • • A dedicated baud-rate generator is provided. One of eight types can be selected. External clock input enabled Internal clock (An internal clock whose pulses are supplied from the 16-bit reload timer that corresponds to each channel can be used.) Data length • • 7 bits (only in asynchronous normal mode) 8 bits Signal method Non Return to Zero (NRZ) method Receive-error detection • • • Framing error Overrun error Parity error (disabled in multiprocessor mode) Interrupt request • Receive interrupt (receiving completed, receive-error detection) Send interrupt (sending completed) • Master/slave-type communication function (multiprocessor mode) Enables 1-to-n (master-to-slaves) communication. (Only the master is supported.) Note: The UART appends neither a start bit nor stop bit, and transfers only the data itself during clock synchronous transfer. 304 CHAPTER 15 UART Table 15.1-2 lists the UART operation modes. Table 15.1-2 UART Operation Modes Data length Operation mode Without parity With parity 7 bits or 8 bits Synchronization method Stop-bit length 0 Normal mode Asynchronous 1 Multiprocessor mode 2 Normal mode -: *1: *2: Setting is not allowed. +1 is the address/data selection bit (A/D) used for communication control. Only a single bit can be detected as stop bit during reception. 1 bit or 2 bits *2 8 + 1 *1 - Asynchronous 8 - Synchronous None 305 CHAPTER 15 UART 15.2 UART Block Diagram Figure 15.2-1 shows a block diagram of UART. ■ UART Block Diagram Figure 15.2-1 UART Block Diagram Control bus Receive-interrupt signal #26-29* Dedicated baud-rate generator 16-bit reload timer Send-interrupt signal #31-34* Send clock Clock selector Receive clock Pins Receivecontrol circuit Send-control circuit <SCK0 to SCK3> Start bit detection circuit Send-start circuit Receive-bit counter Send-bit counter Receive-parity counter Send-parity counter <SOT0 to SOT3> Pins <SIN0 to SIN3> Receive-shift register Pins Receive-status identification circuit SIDR0 to SIDR3 Send-shift register Receive end SODR0 to SODR3 Send start Receive error Generation signal (to CPU) Internal data bus SMR0 to SMR3 register MD1 MD0 CS2 CS1 CS0 SCKE SOE *: Interrupt number 306 SCR0 to SCR3 register PEN P SBL CL A/D REC RXE TXE SSR0 to SSR3 register PE ORE FRE RDRF TDRE BDS RIE TIE CHAPTER 15 UART The following describes the function of each block. ❍ Clock selector The clock selector selects the send and receive clocks from the dedicated baud-rate generator, external input clock, and internal clock (clock supplied from the 16-bit reload timer). ❍ Receive-control circuit The receive-control circuit consists of the receive-bit counter, start-bit detection circuit, and receive-parity counter. The receive-bit counter counts receive data and, after reception of one data unit is completed, generates a receive-interrupt request in accordance with the set-data length. The start-bit detection circuit detects a start bit in the serial-input signal and, if a start bit is detected, writes data to the SIDR0 to SIDR3 register while shifting in accordance with the specified transfer speed. The receive-parity counter calculates the parity of receive data. ❍ Send-control circuit The send-control circuit consists of the send-bit counter, send-start circuit, and send-parity counter. The send-bit counter counts send data and, when sending of one data unit is completed, generates a send-interrupt request in accordance with the set data length. The send-start circuit starts a send operation when SODR0 to SODR3 is written. The send-parity counter generates the parity of send data when parity is enabled. ❍ Receive-shift register The receive-shift register fetches the receive data, which is inputted from the SIN pins, while shifting the data in steps of one bit. When reception terminates, the receive data is transferred from the receive-shift register to the SIDR0 to SIDR3 register. ❍ Send-shift register The send-shift register transfers the data written in SODR0 to SODR3 to the send-shift register and outputs the data to the SOT pins while shifting the data in steps of one bit. ❍ Mode register 1 (SMR0 to SMR3) This register selects the operation mode, selects the clock-input source, sets the dedicated baudrate generator, and selects the clock rate (clock divide-by value) for using the dedicated baudrate generator. It also sets serial data output to pin enabled or disabled and sets clock output to pin enabled or disabled. ❍ Control register 1 (SCR0 to SCR3) This register sets parity to enabled or disabled, selects the parity, sets the stop-bit length, sets the data length, selects the frame data format in mode 1, and clears the flag. It also sets sending to enabled or disabled and sets receiving to enabled or disabled. ❍ Status register 1 (SSR0 to SSR3) This register checks the send, receive and error statuses and sets send- and receive-interrupt request enabled/disabled. ❍ Input-data register 1 (SIDR0 to SIDR3) This register retains the receive data. Serial input is converted and stored in this register. ❍ Output-data register 1 (SODR0 to SODR3) This register sets the send data. The data written in this register undergoes parallel-to-serial conversion and is outputted. 307 CHAPTER 15 UART 15.3 UART Pins This section describes the UART pins and provides pin block diagrams. ■ UART Pins UART pins can also be used as general-purpose ports. Table 15.3-1 shows the pin functions, input-output format, and settings for using the UART. Table 15.3-1 UART Pins (1/2) Pin name Pin function PH0/SIN0 Port H inputoutput/serial data input PH1/SOT0 Port H inputoutput/serial data output PH2/SCK0/ T00 Port H inputoutput/serial clock inputoutput PH3/SIN1 Port H inputoutput/serial data input PH4/SOT1 Port H inputoutput/serial data output PH5/SCK1/ T01 308 Port H inputoutput/serial clock inputoutput Inputoutput format Pull-up selection Standby control Opendrain control Settings necessary for using the pins Set to input port (DDRH: Bit 0 = 0) CMOS output/ CMOS hysteresis input Set to output enabled (SMR0: SOE = 1) Available Available Available Set to input port at clock input (DDRH: Bit 2 = 0) Set to output enabled at clock output (SMR0: SCKE = 1) Set to input port (DDRH: Bit 3 = 0) CMOS output/ CMOS hysteresis input Set to output enabled (SMR1: SOE = 1) Available Available Available Set to input port at clock input (DDRH: Bit 5 = 0) Set to output enabled at clock output (SMR1: SCKE = 1) CHAPTER 15 UART Table 15.3-1 UART Pins (2/2) Pin name Pin function PI0/SIN2 Port I inputoutput/serial data input PI1/SOT2 Port I inputoutput/serial data output PI2/SCK2/ T02 Port I inputoutput/serial clock inputoutput PI3/SIN3 Port I inputoutput/serial data input PI4/SOT3 Port I inputoutput/serial data output PI5/SCK3/ T03 Port I inputoutput/serial clock inputoutput Inputoutput format Pull-up selection Standby control Opendrain control Settings necessary for using the pins Set to input port (DDRI: Bit 0 = 0) CMOS output/ CMOS hysteresis input Set to output enabled (SMR2: SOE = 1) Available Available Available Set to input port at clock input (DDRI: Bit 2 = 0) Set to output enabled at clock output (SMR2: SCKE = 1) Set to input port (DDRI: Bit 3 = 0) CMOS output/ CMOS hysteresis input Set to output enabled (SMR3: SOE = 1) Available Available Available Set to input port at clock input (DDRI: Bit 5 = 0) Set to output enabled at clock output (SMR3: SCKE = 1) 309 CHAPTER 15 UART ■ UART Pin Block Diagram Figure 15.3-1 shows a block diagram of UART pins. Figure 15.3-1 UART Pin Block Diagram Data Bus Resource input 0 1 PDR read pin 0 PDR DDR Resource 1 output Resource output enabled ODCR PCR PDR : DDR : ODCR: PCR: 310 Port Data Register Data Direction Register Open Drain Control Register Pull-up Control Register CHAPTER 15 UART 15.4 UART Registers Figure 15.4-1 shows the configuration of the UART registers. ■ UART Registers Figure 15.4-1 UART Registers Address bit 15 ...................................... bit 8 bit 7 ........................................bit 0 ch.0:00001EH, 00001FH ch.1:000022H, 000023H ch.2:000026H, 000027H ch.3:00002AH, 00002BH SCR (control register) SMR (mode register) ch.0:00001CH, 00001DH ch.1:000020H, 000021H ch.2:000024H, 000025H ch.3:000028H, 000029H SSR (status register) SIDR/SODR (input-output data register) ch.0:00004EH ch.1:00004CH ch.2:000052H ch.3:000050H CDCR (communication prescaler control register) Unoccupied 311 CHAPTER 15 UART 15.4.1 Control Register (SCR0 to SCR3) The control register (SCR0 to SCR3) sets the parity, selects the stop-bit length and data length, selects the frame data format in mode 1, clears the receive-error flag, and sets send- and receive-operations to enabled or disabled. ■ Control Register (SCR0 to SCR3) The configuration and functional outline of the control register (SCR0 to SCR3) is shown below. Figure 15.4-2 Configuration and Functional Outline of Control Register (SCR0 to SCR3) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ch.0:0000_001EH ch.1:0000_0022H ch.2:0000_0026H ch.3:0000_002AH PEN P SBL CL A/D REC RXE TXE R/W R/W R/W R/W R/W W R/W R/W bit7 ............... bit0 (SMR) Initial value 00000100B R/W: Read/write enabled W: Write only TXE Send-operation enable bit CL 0 Send operation is disabled 0 7 bits 1 Send operation is enabled 1 8 bits RXE Receive-operation enable bit SBL 0 Receive operation is disabled 0 1-bit length 1 Receive operation is enabled 1 2-bit length REC Receive-error flag-clear bit 0 Clears the FRE, ORE, and PE flags 1 Does not change, does not affect other operations A/D 0 Data frame 1 Address frame Stop-bit length selection bit Parity selection bit P Only (PEN = 1) is valid when parity is enabled 0 Even-number parity 1 Odd-number parity Address/data selection bit 0 , 1 : The underline indicates an initial value. 312 Data-length selection bit PEN Send-enable bit 0 Without parity 1 With parity CHAPTER 15 UART [bit 15] PEN (Parity enable bit) This bit selects whether to add a parity bit to serial data (for sending). This bit selects whether to detect a parity bit (for receiving) within the serial data. (Note) When operation mode 1 or 2 is selected, parity cannot be used. Always set this bit to 0. [bit 14] P (Parity selection bit) This bit selects odd parity or even parity when parity is enabled (PEN = 1). [bit 13] SBL (Stop-bit-length selection bit) This bit selects the bit length of the stop bit, which is a frame-end mark for the send data in asynchronous transfer mode. (Note) Only one bit is detected as stop bit at reception. [bit 12] CL (Data-length selection bit) This bit specifies the data length of the send and receive data. (Note) Bit 7 can be selected only in operation mode 0 (asynchronous). Bit 8 (CL = 1) must be selected in operation mode 1 (multiprocessor mode) and operation mode 2 (synchronous). [bit 11] A/D (Address/data selection bit) • This bit specifies the data format of frames to be sent and received in multiprocessor mode (mode 1). • When this bit is 0, ordinary data is selected. When this bit is 1, address data is selected. [bit 10] REC (Receive-error flag-clear bit) • This bit clears the FRE, ORE, and PE flags of the status register (SSR). • When this bit is set to 0, the FRE, ORE, and PE flags are cleared. When this bit is set to 1, the flags do not change and other operations are not affected. (Note) Clear the REC bit only when the FRE, ORE, or PE flag is 1 in receive interrupt enabled status during UART operation. [bit 9] RXE (Receive-operation enable bit) • This bit controls the UART receive operation. • When this bit is 0, the receive operation is disabled. When this bit is 1, the receive operation is enabled. (Note) If the receive operation is disabled during reception, the receive operation stops when reception of the frame is completed and receive data is stored in the receive data buffer (SIDR0 to SIDR3). [bit 8] TXE (Send-operation enable bit) • This bit controls the UART send operation. • When this bit is 0, the send operation is disabled. When this bit is 1, the send operation is enabled. (Note) If the send operation is disabled during sending, the send operation stops after the send-data buffer (SODR0 to SODR3) runs out of data. When data is written to SODR0 to SODR3, wait a specified period of time before setting this bit to "0". In clock asynchronous transfer mode, this specified period of time is 1/16 of the baud rate; in clock synchronous transfer mode, it is the baud rate. 313 CHAPTER 15 UART 15.4.2 Mode Register (SMR0 to SMR3) The mode register (SMR0 to SMR3) selects the operation mode, selects the baud-rate clock, and sets serial data and clock output to pin enabled or disabled. ■ Mode Register (SMR0 to SMR3) The configuration and functional outline of the mode register (SMR0 to SMR3) is shown below. Figure 15.4-3 Configuration and Functional Outline of the Mode Register (SMR0 to SMR3) Address bit15 ............ bit8 ch.0:0000_001F H ch.1:0000_0023 H ch.2:0000_0027 H ch.3:0000_002B H (SCR) bit7 bit6 bit5 bit4 bit3 MD1 MD0 CS2 CS1 R/W R/W R/W R/W bit2 bit1 bit0 CS0 SCKE SOE R/W R/W R/W Initial value 00000-00B R/W: Read/write enabled SOE Serial data output-enable bit 0 Sets to general-purpose input-output port 1 Sets to UART serial data output pins SCKE Serial clock output-enable bit 0 Sets to general-purpose input-output port or UART clock-input pin 1 Sets to UART clock output pins CS2 to CS0 "000B" to "101B" Clock selection bit Baud rate based on the dedicated baud-rate generator "110B" Baud rate based on the internal timer (16-bit reload timer) "111B" Sets to UART clock output pins Operation mode selection bit MD1 MD0 Operation mode 0 0 0 Asynchronous (normal mode) 0 1 1 Asynchronous (multiprocessor mode) 1 0 2 Synchronous (normal mode) 1 1 Setting is prohibited 0 , 1 : The underline indicates an initial value. 314 CHAPTER 15 UART [bit 7, bit 6] MD1, MD0 (Operation mode selection bit) • These bits select the operation mode. (Notes) In operation mode 1 (multiprocessor mode), these bits can only be used at the side of the master in master-slave-type communication. These bits cannot be used in the slave unit because the UART does not have a function for distinguishing between the address and the data at reception. [bit 5 to bit3] CS2 to CS0 (Clock selection bit) • These bits select the baud-rate clock source. When the dedicated baud-rate generator is selected, the baud rate is determined simultaneously. • When the dedicated baud-rate generator is selected, one of a total of eight baud rates can be selected, five of them for asynchronous transfer mode and three types for synchronous transfer mode. • The clock input can be selected from the external clock (SCK0 to SCK3 pin), 16-bit reload timer, and dedicated baud-rate generator. [bit 2] Unused bit Unused [bit 1] SCKE (Serial clock output-enable bit) • This bit controls serial clock input and output. • When this bit is set to 0, the SCK0 to SCK3 pins become general-purpose input-output ports or serial clock input pins. When this bit is set to 1, the SCK0 to SCK3 pins become serial clock output pins. (Notes) 1. When using the SCK0 to SCK3 pins as serial clock input pins (SCKE=0), set the corresponding port to be an input port. Also, select the external clock by the clock selection bits (SMR0 to SMR3: CS2 to CS0 = 111B). 2. When using the SCK0 to SCK3 pins as serial clock output pins (SCKE=1), select a clock other than the external clock (SMR0 to SMR3: CS2 to CS0 = other than 111B). 3. The condition that serial clock output is enabled (SCKE=1) is permitted only by the synchronous transfer. When serial clock output is enabled (SCKE=1), the SCK0 to SCK3 pins function as serial clock output pins regardless of the general-purpose input-output port status. [bit 0] SOE (Serial data output-enable bit) • This bit enables or disables serial data output. • When this bit is set to 0, the SOT0 to SOT3 pins become general-purpose input-output ports. When this bit is set to 1, the SOTn pins become serial data output pins (SOT0 to SOT3). (Notes) When serial data output is enabled (SOE=1), the SOTn pins function as SOT0 to SOT3 pins regardless of the general-purpose input-output port status. 315 CHAPTER 15 UART 15.4.3 Status Register (SSR0 to SSR3) The status register (SSR0 to SSR3) is used to check the send, receive and error statuses and sets interrupt enabled or disabled. ■ Status Register (SSR0 to SSR3) The configuration and functional outline of the status register (SSR0 to SSR3) is shown below. Figure 15.4-4 Configuration and Functional Outline of the Status Register (SSR0 to SSR3) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 ............... bit0 ch.0:0000_001C H ch.1:0000_0020 H ch.2:0000_0024 H ch.3:0000_0028 H PE ORE FRE RDRF TDRE BDS RIE TIE (SIDR/SODR) R R R R R/W R/W R/W R Initial value 00001000B R/W: Read/write enabled R: Read only TIE Send-interrupt request enable bit RDRF Receive data full flag bit 0 Disables send-interrupt request output 0 Without receive data 1 Enables send-interrupt request output 1 With receive data RIE Receive-interrupt request enable bit FRE Framing error flag bit 0 Disables receive-interrupt request output 0 Without framing error 1 Enables receive-interrupt request output 1 With framing error BDS Transfer direction selection bit ORE Overrun error flag bit 0 LSB first (transfer begins from the least significant bit) 0 Without overrun error 1 MSB first (transfer begins from the most significant bit) 1 With overrun error PE Parity error flag bit TDRE Send data empty flag bit 0 With send data (disables send data to be written) 0 Without parity error 1 Without send data (enables send data to be written) 1 With parity error 0 , 1 : The underline indicates an initial value. [bit 15] PE (Parity error flag bit) 316 • If a parity error occurs at reception, this bit is set to 1. When the REC bit of the control register (SCR0 to SCR3) is set to 0, this bit is cleared. • When this bit and the RIE bit are 1, a receive-interrupt request is outputted. • When this flag is set, data in the input-data register (SIDR0 to SIDR3) is invalid. CHAPTER 15 UART [bit 14] ORE (Overrun error flag bit) • If an overrun occurs at reception, this bit is set to 1. When the REC bit of the control register (SCR0 to SCR3) is set to 0, this bit is cleared to 0. • When this bit and the RIE bit are 1, a receive-interrupt request is outputted. • When this flag is set, data in the input-data register (SIDR0 to SIDR3) is invalid. [bit 13] FRE (Framing error flag bit) • If a framing error occurs at reception, this bit is set to 1. When the REC bit of the control register (SCR0 to SCR3) is set to 0, this bit is cleared to 0. • When this bit and the RIE bit are 1, a receive-interrupt request is outputted. • When this flag is set, data in the input-data register (SIDR0 to SIDR3) is invalid. [bit 12] RDRF (Receive data full flag bit) • This bit indicates the status of the input-data register (SIDR0 to SIDR3). • When receive data is loaded into SIDR0 to SIDR3, this bit is set to 1. When the SIDR0 to SIDR3 is read, this bit is cleared to 0. • When this bit and the RIE bit are 1, a receive-interrupt request is outputted. [bit 11] TDRE (Send data empty flag bit) • This bit indicates the status of the output-data register (SODR0 to SODR3). • When send data is written into SODR0 to SODR3, this bit is cleared to 0. When data is loaded into the send-shift register and sending starts, this bit is set to 1. • When this bit and the TIE bit are 1, a send-interrupt request is outputted. (Note) In the initial status, this bit is set to 1 (SODR0 to SODR3 unoccupied). [bit 10] BDS (Transfer direction selection bit) • This bit selects whether to begin transferring serial data from the least significant bit (LSB first, BDS = 0) or from the most significant bit (MSB first, BDS = 1). (Note) If this bit is rewritten after data is written into the SIDR0 to SIDR3 register, the data becomes invalid. This is because the high-order bits and low-order bits of the data are swapped during read and write accesses to the serial data register. [bit 9] RIE (Receive-interrupt request enable bit) • This bit enables or disables output of receive-interrupt requests to the CPU. • When this bit and the receive data flag bit (RDRF) bit are 1 or when this bit and one or more of the error flag bits (PE, ORE, and FRE) are 1, a receive-interrupt request is outputted. [bit 8] TIE (Send-interrupt request enable bit) • This bit enables/disables send-interrupt requests to be outputted to the CPU. • When this bit and the TDRE bit are 1, a send-interrupt request is outputted. 317 CHAPTER 15 UART 15.4.4 Input-data Register (SIDR0 to SIDR3), Output-data Register (SODR0 to SODR3) The input-data register (SIDR0 to SIDR3) is for receiving serial data. The output-data register (SODR0 to SODR3) is for sending serial data. The SIDR0 to SIDR3 and SODR0 to SODR3 registers are located at the same address. ■ Input-data Register (SIDR0 to SIDR3) The configuration of the input-data register (SIDR0 to SIDR3) is shown below. Address ch.0:0000_001DH ch.1:0000_0021H ch.2:0000_0025H ch.3:0000_0029H bit15 ........... bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R Initial value XXXXXXXXB R: Read only X: Undetermined Received data is stored in this register. The shift register converts the serial data signal sent to the SIN0 to SIN3 pins. The converted data is stored in this register. When the data length is 7 bits, the high-order bit (D7) contains invalid data. When the receive data is stored in this register, the receive data full flag bit (SSR0 to SSR3: RDRF) is set to 1. If receive-interrupt request is enabled, a receive interrupt occurs. Read the SIDR0 to SIDR3 when the RDRF bit of the status register (SSR0 to SSR3) is 1. The RDRF bit is automatically cleared to 0 when the SIDR0 to SIDR3 is read. If a receive error occurs (SSR0 to SSR3: If PE, ORE, or FRE is 1), the SIDR0 to SIDR3 data becomes invalid. 318 CHAPTER 15 UART ■ Output-data Register (SODR0 to SODR3) The configuration of the output-data register (SODR0 to SODR3) is shown below. Address ch.0:0000_001DH ch.1:0000_0021H ch.2:0000_0025H ch.3:0000_0029H bit15 ................ bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 W W W W W W W W Initial value XXXXXXXXB W: Write only X: Undetermined When send data is written to this register in send-enabled status, the send data is transferred to the send-shift register, is converted into serial data, and is sent out from the serial data output pins (SOT0 to SOT3 pins). When the data length is 7 bits, the high-order bit (D7) contains invalid data. When the send data is written to this register, the send data empty flag (SSR0 to SSR3: TDRE) is cleared to 0. When the transfer to the send-shift register terminates, the flag is set to 1. When the TDRE bit is 1, the next send data can be written. If send-interrupt request output is enabled, a send interrupt occurs. The next send data should be written when a send interrupt occurs or when the TDRE bit is 1. Note: The SODR0 to SODR3 is a write-only register and the SIDR0 to SIDR3 is a read-only register. The write value and read value are different because these registers are located at the same address. Therefore, instructions that perform the read-modify-write (RMW) operation cannot be used. 319 CHAPTER 15 UART 15.4.5 Communication Prescaler Control Register (CDCR0 to CDCR3) The communication prescaler control register (CDCR) controls division of the machine clock. ■ Communication Prescaler Control Register (CDCR) The UART operation clock is obtained by dividing the machine clock. This communication prescaler is designed to obtain a fixed baud rate for machine cycles. The configuration of the communication prescaler control register (CDCR) is shown below. Address bit11 bit10 bit9 bit8 MD DIV3 DIV2 DIV1 DIV0 R/W R/W R/W R/W R/W bit15 ch.0:0000_004EH ch.1:0000_004CH ch.2:0000_0052H ch.3:0000_0050H bit14 bit13 bit12 Initial value 0---0000B R/W: Read/write enabled [bit 15] MD (Machine clock divide mode select) This is the communication prescaler operation enable bit. 0: The communication prescaler stops. 1: The communication prescaler operates. [bit 11 to bit 8] DIV3 to DIV0 (DIVide 3 to DIVide 0) The machine clock division ratio is determined in accordance with Table 15.4-1. Table 15.4-1 Communication Prescaler (1/2) 320 MD DIV3 DIV2 DIV1 DIV0 div 0 - - - - Stop 1 0 0 0 0 1 1 0 0 0 1 2 1 0 0 1 0 3 1 0 0 1 1 4 1 0 1 0 0 5 1 0 1 0 1 6 1 0 1 1 0 7 1 0 1 1 1 8 CHAPTER 15 UART Table 15.4-1 Communication Prescaler (2/2) MD DIV3 DIV2 DIV1 DIV0 div 1 1 0 0 0 9 1 1 0 0 1 10 1 1 0 1 0 11 1 1 0 1 1 12 1 1 1 0 0 13 1 1 1 0 1 14 1 1 1 1 0 15 1 1 1 1 1 16 Notes: • After the division ratio has been changed, wait two cycles for the clock to stabilize before performing communication. • When the dedicated baud rate generator is used at the synchronous transmission, the following settings are prohibited. - CS2 to CS0=000B - CS2 to CS0=001B and DIV3 to DIV0=0000B 321 CHAPTER 15 UART 15.5 UART Interrupts The UART has receive interrupts and send interrupts. Interrupt requests are generated in the following cases: • When receive data is set in the input-data register (SIDR0 to SIDR3) or when a receive error occurs • When send data is transferred from the output-data register (SODR0 to SODR3) to the send-shift register ■ UART Interrupts Table 15.5-1 shows the UART interrupt control bit and interrupt sources. Table 15.5-1 UART Interrupt Control Bit and Interrupt Sources Send or receive Receive Send Interrupt request flag bit Operation mode 0 1 2 RDRF o o o Receive data is loaded into the buffer (SIDR0 to SIDR3) ORE o o o An overrun error occurs FRE o o x A framing error occurs PE o x x A parity error occurs TDRE o o o Send buffer (SODR0 to SODR3) is empty Interrupt source Interrupt source enable bit Interrupt request flag clear Receive data is read SSR0 to SSR3:RIE The receiveerror flag-clear bit (SCR0 to SCR3: REC) is set to 0 SSR0 to SSR3:TIE Send data is written o: Used bit x: Unused bit ❍ Receive interrupt In receive mode, if data reception is completed (SSR0 to SSR3: RDRF), if an overrun error occurs (SSR0 to SSR3: ORE), if a framing error occurs (SSR0 to SSR3: FRE), or if a parity error occurs (SSR0 to SSR3: PE), the corresponding flag bit is set to 1. If the receive interrupt is enabled (SSR0 to SSR3: RIE = 1) when any of these flag bits is 1, a receive-interrupt request is outputted to the interrupt controller. The receive data full flag (SSR0 to SSR3: RDRF) is automatically cleared to 0 when the inputdata register (SIDR0 to SIDR3) is read. When the REC bit of the control register (SCR0 to SCR3) is set to 0, the receive-error flags (SSR0 to SSR3: PE, ORE, FRE) are cleared to 0. ❍ Send interrupt When send data is transferred from the output-data register (SODR0 to SODR3) to the transfer shift register, the TDRE bit of the status register (SSR0 to SSR3) is set to 1. If the send interrupt is enabled (SSR0 to SSR3: TIE = 1), a send-interrupt request is outputted to the interrupt controller. 322 CHAPTER 15 UART ■ UART-related Interrupts Table 15.5-2 lists the UART-related interrupts. Table 15.5-2 UART-related Interrupts Interrupt source Interrupt number Interrupt control register Vector table address Register name Address Offset TBR default address UART0 receive interrupt #26 (1AH) ICR10 00040AH 394H 000FFF94H UART1 receive interrupt #27 (1BH) ICR11 00040BH 390H 000FFF90H UART2 receive interrupt #28 (1CH) ICR12 00040CH 38CH 000FFF8CH UART3 receive interrupt #29 (1DH) ICR13 00040DH 388H 000FFF88H UART0 send interrupt #31 (1FH) ICR15 00040FH 380H 000FFF80H UART1 send interrupt #32 (20H) ICR16 000410H 37CH 000FFF7CH UART2 send interrupt #33 (21H) ICR17 000411H 378H 000FFF78H UART3 send interrupt #34 (22H) ICR18 000412H 374H 000FFF74H 323 CHAPTER 15 UART 15.6 Receive-Interrupt Generation and Flag Set Timing The receive interrupts are interrupts indicating receive completion (SSR0 to SSR3: RDRF) and receive-error generation (SSR0 to SSR3: PE, ORE, FRE). ■ Receive-interrupt Generation and Flag Set Timing When the stop bit is detected (in operation modes 0 to 4) or when the final bit (D7) of the data is detected (in operation mode 2) during reception, the receive data is stored in input-data register 1 (SIDR0 to SIDR3). In case of a receive error, the error flag (SSR0 to SSR3: PE, ORE, FRE) is set. After this, the receive data full flag (SSR0 to SSR3: RDRF) is set to 1. In each mode, the SIDR0 to SIDR3 value is invalid when the error flag is 1. ❍ Operation mode 0 (asynchronous, normal mode) When the stop bit is detected, the RDRF is set to 1. When a receive error occurs, the error flag (PE, ORE, FRE) is set. ❍ Operation mode 1 (asynchronous, multiprocessor mode) When the stop bit is detected, the RDRF is set to 1. When a receive error occurs, the error flag (ORE, FRE) is set. Parity errors cannot be detected. ❍ Operation mode 2 (synchronous, normal mode) When the final bit (D7) of receive data is detected, the RDRF is set to 1. If a receive error occurs, the error flag (ORE) is set. Parity errors and framing errors cannot be detected. Figure 15.6-1 shows the receive operation and flag set timing. Figure 15.6-1 Receive Operation and Flag Set Timing Receive data (Operation mode 0) ST D0 D1 D5 D6 D7/P SP Receive data (Operation mode 1) ST D0 D1 D6 D7 A/D SP D0 D1 D4 D5 D6 D7 Receive data (Operation mode 2) PE, ORE, FRE* RDRF *: The PE flag cannot be used in mode 1. The PE and FRE flags cannot be used in mode 2. ST: Start bit SP: Stop bit A/D: Mode 2 (multiprocessor mode) address/data selection bit 324 Receive-interrupt generation CHAPTER 15 UART ❍ Timing of receive-interrupt generation A receive-interrupt request is issued immediately after the RDRF, PE, ORE, or FRE flag is set to 1 while receive interrupts are enabled (SSR0 to SSR3: RIE = 1). 325 CHAPTER 15 UART 15.7 Send-Interrupt Generation and Flag Set Timing A send interrupt is generated when the output-data register (SODR0 to SODR3) enables the next unit of data to be written. ■ Send-interrupt Generation and Flag Set Timing When data from the output-data register (SODR0 to SODR3) is transferred to the send-shift register and writing of the next unit for data is enabled, the send data empty flag bit (SSR0 to SSR3: TDRE) is set to 1. When the send data is written to the SODR0 to SODR3, the TDRE is cleared to 0. Figure 15.7-1 shows the send operation and flag set timing. Figure 15.7-1 Send Operation and Flag Set Timing [Operation modes 0, 1] Send-interrupt generation Send-interrupt generation SODR write TDRE SOUT output ST [Operation mode 2] D0 D1 D2 D3 D4 Send-interrupt generation D5 D6 D7 SP SP A/D ST D0 D1 D2 D3 D3 D4 D5 D6 D7 Send-interrupt generation SODR write TDRE SOUT output D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 ST: Start bit D0 to D7: Data bits SP: Stop bit A/D: Address/data selection bit ❍ Timing of send-interrupt request generation A send-interrupt request is issued immediately after the TDRE flag is set to 1 while send interrupts are enabled (SSR0 to SSR3: TIE = 1). Note: A send completion interrupt is generated immediately when the send interrupt is enabled (TIE = 1) because the initial status of the TDRE bit is 1. The TDRE bit is read-only and can only be cleared when new data is written to the output-data register (SODR0 to SODR3). So, be careful with the timing for enabling send interrupts. 326 CHAPTER 15 UART 15.8 Baud Rate The UART send and receive clocks can be selected from any of the following. • Dedicated baud-rate generator • Internal clock (16-bit reload timer) • External clock (SCK pin input clock) ■ UART Baud-rate Selection The baud-rate selection circuit consists of the following. The baud rate to be selected can be one of three kinds. ❍ Baud-rate selection based on the dedicated baud-rate generator The UART internally contains a dedicated baud-rate generator. One of eight baud rates can be selected through the mode register (SMR0 to SMR3). Select an asynchronous or clocksynchronous baud rate through the machine clock frequency and CS2 to CS0 bits of the mode register (SMR0 to SMR3). ❍ Baud rate based on the internal timer The frequency of the internal clock supplied from 16-bit reload timer 0-3 is used as the baud rate as it is (in synchronous mode) or first divided by 16 and then used as the baud rate (in asynchronous mode). Any baud rate can be set through the reload value setting. ❍ Baud rate based on the external clock The clock frequency input from the UART clock-input pins is used as the baud rate as it is (in synchronous mode) or first divided by 16 and then used as the baud rate (in asynchronous mode). Any baud rate can be set externally. 327 CHAPTER 15 UART ■ UART Baud-Rate Selection Circuit Figure 15.8-1 shows a UART baud rate selection circuit. Figure 15.8-1 UART Baud-rate Selection Circuit SMR0 to SMR3:CS2/1/0 (Clock selection bit) Clock selector [Dedicated baud-rate generator] φ For 000B to 101B Divide-by circuit (Synchronous) Select 1/2, 1/4, or 1/8 division (Asynchronous) Select the internal fixed division ratio Prescaler [Internal timer] TMCSR0 to TMCSCR3:CSL1,CSL0 2 Clock selector φ φ/2 Down counter For 110B UF 1/1 (synchronous) 1/16 (asynchronous) φ/8 φ/32 Prescaler 16-bit reload timer 0-3 [External clock] SCK0 to SCK3 Pins For 111B 1/1 (synchronous) 1/16 (asynchronous) SMR0 to SMR3:MD1 (Clock synchronous/asynchronous selection) φ: Machine clock frequency 328 Baud rate CHAPTER 15 UART 15.8.1 Baud Rate Based on the Dedicated Baud-Rate Generator This section shows the baud rates that can be set when the output clock of the dedicated baud-rate generator is selected as the UART transfer clock. ■ Baud Rate Based on the Dedicated Baud-rate Generator When the dedicated baud-rate generator is used to generate the transfer clock, the machine clock prescaler is used to divide the machine clock rate by the transfer clock division ratio selected with the clock selector. The machine clock division ratio is common in asynchronous and synchronous modes, but the transfer clock division ratio differs in asynchronous and synchronous modes. The values internally set separately for asynchronous and synchronous modes are selected. Therefore, the actual baud rate can be expressed in the following equations. • Asynchronous baud rate = φ (prescaler division ratio) x (asynchronous transfer clock division ratio) • Synchronous baud rate = φ (prescaler division ratio) x (synchronous transfer clock division ratio) φ: Machine clock frequency ❍ Division ratio based on the prescaler (common for asynchronous and synchronous modes) The machine clock division ratio is determined in accordance with the DIV3 to DIV0 bits of the communication prescaler control register as shown in Table 15.8-1. Table 15.8-1 Selection of Division Ratio Based on the Machine Clock Prescaler (1/2) MD DIV3 DIV2 DIV1 DIV0 div 0 - - - - Stop 1 0 0 0 0 1 1 0 0 0 1 2 1 0 0 1 0 3 1 0 0 1 1 4 1 0 1 0 0 5 1 0 1 0 1 6 1 0 1 1 0 7 1 0 1 1 1 8 1 1 0 0 0 9 1 1 0 0 1 10 1 1 0 1 0 11 1 1 0 1 1 12 329 CHAPTER 15 UART Table 15.8-1 Selection of Division Ratio Based on the Machine Clock Prescaler (2/2) MD DIV3 DIV2 DIV1 DIV0 div 1 1 1 0 0 13 1 1 1 0 1 14 1 1 1 1 0 15 1 1 1 1 1 16 ❍ Synchronous transfer clock division ratio The synchronous baud-rate division ratio is specified in the CS2 to CS0 bits of the mode register (SMR0 to SMR3) as shown in Table 15.8-2. Table 15.8-2 Selection of Synchronous Baud-rate Division Ratio CS2 CS1 CS0 Synchronous with CLK (Hz) Equation for calculation 0 0 0 Disabled Disabled 0 0 1 - (φ/div)/2 0 1 0 - (φ/div)/4 0 1 1 4M (φ/div)/8 1 0 0 2M (φ/div)/16 1 0 1 1M (φ/div)/32 Note that the calculation is based on a machine cycle, φ, of 32.0 MHz, and div = 1. Note: When the dedicated baud rate generator is used at the synchronous transmission, the following settings are prohibited. - CS2 to CS0=000B - CS2 to CS0=001B and DIV3 to DIV0=0000B 330 CHAPTER 15 UART ❍ Asynchronous transfer clock division ratio The asynchronous baud-rate division ratio is specified in the CS2 to CS0 bits of the mode register (SMR0 to SMR3) as shown in Table 15.8-3. Table 15.8-3 Selection of Asynchronous Baud-rate Division Ratio CS2 CS1 CS0 Asynchronous (start-stop synchronization) (Hz) Equation for calculation 0 0 0 76.8K (φ/div)/(8x13x2) 0 0 1 38.4K (φ/div)/(8x13x4) 0 1 0 19.2K (φ/div)/(8x13x8) 0 1 1 9.6K (φ/div)/(8x13x16) 1 0 0 500K (φ/div)/(8x2x2) 1 0 1 250K (φ/div)/(8x2x4) Note that the calculation is based on a machine cycle, φ, of 31.9488 MHz, and div = 2. ❍ Internal timer The equations for calculating the baud rate with CS2 to CS0 set to 110 and the internal timer selected (example of using the reload timer) are shown below. • Asynchronous (start-stop synchronization) (φ/N)/(16x2x(n+1)) • Synchronous with CLK (φ/N)/(2x(n+1)) N: Timer count clock source n: Timer reload value ❍ External clock The baud rate for cases where CS2 to CS0 are set to 111 and the external clock has a frequency of f is shown below. Asynchronous (start-stop synchronization) f/16 Synchronous with CLK f’ The maximum of f is one-half (1/2) the machine clock frequency and the maximum of f’ is oneeighth (1/8) the machine clock frequency. 331 CHAPTER 15 UART 15.8.2 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) This section shows the settings and equations for calculating the baud rate when the internal clock from 16-bit reload timer 0 is selected as the UART transfer clock. ■ Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) When the bits CS2 to CS0 of the mode register (SMR0 to SMR3) are set to 110B, the baud rate is selected based on the internal timer. Any baud rate can be set through selection of the prescaler division ratio and reload value for the 16-bit reload timer 0. Figure 15.8-2 shows the baud-rate selection circuit based on the internal timer. Figure 15.8-2 Baud-rate Selection Circuit Based on the Internal Timer (16-bit Reload Timer 0) SMR0 to SMR3: CS2/1/0=110 B (Internal timer selection) Clock selector 1/1 (synchronous) 1/16 (asynchronous) 16-bit reload timer 0 output (frequency specified in accordance with the prescaler divide-by value and reload value) Baud rate SMR0 to SMR3: MD1 (Clock synchronous/asynchronous selection) ❍ Equation for baud-rate calculation Asynchronous baud rate = bps X (n+1) 2 X (n+1) 2 Synchronous baud rate = 332 16 bps CHAPTER 15 UART ❍ Example of reload-value setting (when the machine clock is 31.9488 MHz) Table 15.8-4 shows the baud rate and reload value. Table 15.8-4 Baud Rate and Reload Value Reload value Baud rate (bps) Asynchronous with the clock (start-stop synchronization) Synchronous with the clock X = 21 (Divide-by-two machine cycle) X = 23 (Divide-by-eight machine cycle) X = 21 (Divide-by-two machine cycle) X = 23 (Divide-by-eight machine cycle) 38400 12 - 207 51 19200 25 - 415 103 9600 51 12 831 207 4800 103 25 1663 415 2400 207 51 3327 831 1200 415 103 6655 1663 600 831 207 13311 3327 300 1663 415 26623 6655 X: Division ratio based on the prescaler of the 16-bit reload timer 0 -: Setting is not allowed. 333 CHAPTER 15 UART 15.8.3 Baud Rate Based on the External clock This section shows the settings and equations for calculating the baud rate when the external clock is selected as the UART transfer clock. ■ Baud Rate Based on the External Clock The following three settings are necessary for selecting the baud rate based on the external clock. • Set the SCKE bit of the mode register (SMR0 to SMR3) to 0. • Set the bits CS2 to CS0 of the mode register (SMR0 to SMR3) to 111B and select the baud rate based on the external clock. • The port for input the external clock is set to the input status. The baud rate is selected based on the external clock input from the SCK0 to SCK3 pins as shown in Figure 15.8-3. To change the baud rate, the cycle of the external input clock must be changed because the internal division ratio is fixed. Figure 15.8-3 Circuit for Baud Rate Selection Based on the External Clock SMR0 to SMR3: CS2/1/0=111 B (Internal clock selection) Clock selector SCK0 to SCK3 1/1 (synchronous) 1/16 (asynchronous) Pins Baud rate SMR0 to SMR3: MD1 (Clock synchronous/asynchronous selection) ❍ Equation for baud-rate calculation Asynchronous baud rate = f/16 Synchronous baud rate = f f: External clock frequency (The maximum of f is [frequency of peripheral operation clock]/8. With a frequency of the peripheral operation clock of 31.9488 MHz, the maximum of f is 3.9936 MHz.) 334 CHAPTER 15 UART 15.9 UART Operations The UART has an ordinary bidirectional serial communication function (operation modes 0 and 2) and master/slave-type connection communication function (operation mode 1). ■ UART Operations ❍ Operation mode The UART has three operation modes, mode 0 to mode 2. The inter-CPU connection method and data transfer method can be used to select the operation mode as shown in Table 15.9-1. Table 15.9-1 UART Operation Modes Data length Operation mode Without parity 0 Normal mode 1 Multiprocessor mode 2 Normal mode With parity 7 bits or 8 bits Synchronization method Stop-bit length Asynchronous 1 bit or 2 bits (*2) -: *1: *2: 8 + 1 (*1) - Asynchronous 8 - Synchronous None Setting is disabled. +1 is the address/data selection bit (A/D) used for communication control. Only one bit can be detected as stop bit at reception. Note: UART operation mode 1 is only used for the master unit in master/slave-type connection. ❍ Inter-CPU connection method One-to-one connection (normal mode) or master/slave-type connection (multiprocessor mode) can be selected. With either method, the data length, whether to use parity, and the synchronization method must be the same for all CPUs. The operation mode is selected as shown below. • In a one-to-one connection, the two CPUs must use the same operation mode (operation mode 0 or 2). For the asynchronous method, select operation mode 0. For the synchronous method, select operation mode 2. • In the master/slave-type connection, use operation mode 1. Select operation mode 1 and use the unit as the master. In this connection, select no parity. ❍ Synchronization method For the operation mode, the asynchronous method (start-stop synchronization) or clock synchronization method can be selected. 335 CHAPTER 15 UART ❍ Signal method The UART can handle data in the Non Return to Zero (NRZ) format only. ❍ Operation enable The UART has the TXE (sending) and RXE (receiving) operation enable bits separately for sending and receiving, which are used to control send and receive operations. If operation becomes disabled while the operation is in progress, the following occurs. 336 • If the receive operation is disabled during reception (while data is being inputted into the receive-shift register), the receive operation stops when reception of the frame is completed and receive data is stored in the input-data register (SIDR0 to SIDR3). • If the send operation is disabled during sending (while data is being outputted from the sendshift register), the send operation stops after the output-data register (SODR0 to SODR3) runs out of data. CHAPTER 15 UART 15.9.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) When the UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the transfer becomes asynchronous. ■ Operation in Asynchronous Mode (Operation Modes 0 and 1) ❍ Transfer-data format Transfer data always starts from the start bit (L level), is transferred LSB first with the specified data bit length, and ends with the stop bit (H level). • In a normal mode of operation mode 0, the data length can be set to 7 bits or 8 bits. • In operation mode 1, data has a fixed length of eight bits without parity, but an address/data selection bit (A/D) is added instead of the parity bit. Figure 15.9-1 shows the data format in asynchronous mode. Figure 15.9-1 Transfer-data Format (Operation Modes 0 and 1) [Operation mode 0] [Operation mode 1] ST D0 D1 D2 D3 D4 D5 D6 * D7/P SP ST D0 D1 D2 D3 D4 D5 D6 D7 A/D SP : D7 (bit 7): Without parity P (parity): With parity ST : Start bit SP : Stop bit A/D : Operation mode 1 (multiprocessor mode) address/data selection bit * ❍ Send operation When the send data empty flag bit (SSR0 to SSR3: TDRE) is 1, send data is written to the outputdata register (SODR0 to SODR3). If sending is enabled (SCR0 to SCR3: TXE = 1), the data is sent. The send data is transferred to the send-shift register. When sending begins, the TDRE flag is set to 1 again and setting of the next unit of send data is enabled. If send-interrupt requests are enabled (SSR0 to SSR3: TIE = 1), a send-interrupt request that requests the send data to be set in SODR0 to SODR3 is outputted. As soon as the send data is written to SODR0 to SODR3, the TDRE flag is cleared to 0. 337 CHAPTER 15 UART ❍ Receive operation If receiving is enabled (SCR0 to SCR3: RXE = 1), receive operations are consistently performed. When the start bit is detected, data of one frame is received in accordance with the data format determined by the control register (SCR0 to SCR3). After reception of the data of one frame, if an error has occurred, the error flag is set and the receive data full flag bit (SSR0 to SSR3: RDRF) is set to 1. If receive-interrupt requests are enabled (SSR0 to SSR3: RIE = 1), a receive-interrupt request is outputted. Check each flag of the status register (SSR0 to SSR3). If reception is normal, read the input-data register (SIDR0 to SIDR3). If an error has occurred, perform the required processing to handle the error. As soon as the receive data is read from SIDR0 to SIDR3, the RDRF flag is cleared to 0. ❍ Detecting the start bit Implement the following settings to detect the start bit: • Set the communication line level to H (attach the mark level) before the communication period. • Specify reception permission (RXE = H) while the communication line level is H (mark level). • Do not specify reception permission (RXE = H) for periods other than the communication period (without mark level). Otherwise, data is not received correctly. • After the stop bit is detected (the RDRF flag is set to 1), specify reception inhibition (RXE = L) while the communication line level is H (mark level). Figure 15.9-2 Normal Operation Communication period Non-communication period Mark level Start bit SIN ST Non-communication period Stop bit Data D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 SP (Sending 01010101B) RXE Receive clock Sampling clock Receive clock (8 pulse) Recognition by the microcontroller ST Generating sampling clocks by dividing the receive clock by 16 D2 D3 D4 D5 D6 D7 SP (Receiving 01010101B) Note that specifying reception permission at the timing shown below obstructs the correct recognition of the input data (SIN) by the microcontroller. • Example of operation if reception permission (RXE = H) is specified while the communication line level is L. Figure 15.9-3 Abnormal Operation Communication period Non-communication period Mark level Start bit SIN (Sending 01010101B) RXE Non-communication period Stop bit Data ST D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SP SP Receive clock Sampling clock Recognition by the microcontroller ST recognition (Receiving 10101010B) PE,ORE,FRE Occurrence of a reception error 338 CHAPTER 15 UART ❍ Stop bit For sending, 1 bit or 2 bits can be selected. However, the receiving side always detects only the first 1 bit. ❍ Error detection • In mode 0, parity errors, overrun errors, and frame errors can be detected. • In mode 1, overrun errors and frame errors can be detected, but parity errors cannot be detected. ❍ Parity 0 Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to use parity is specified in the PEN bit of the control register (SCR0 to SCR3). Whether to use even-number parity or odd-number parity is specified in the P bit. In operation mode 1 (asynchronous, multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity cannot be used. Figure 15.9-4 shows the send and receive data operations with parity set to valid. Figure 15.9-4 Send Data Operation with Parity Set to Valid SIN0 to SIN3 ST 1 SOT0 to SOT3 1 1 0 0 0 1 1 0 0 0 1 1 0 0 Sending of even-number parity (SCR0 to SCR3: P=0) SP Sending of odd-number parity (SCR0 to SCR3: P=1) 1 ST 1 SP 0 ST 1 SOT0 to SOT3 0 SP Parity error occurred during reception with even-number parity (SCR0 to SCR3: P=0) 0 Data Parity ST: Start bit SP: Stop bit Note: In operation modes 1 and 2, parity cannot be used. 339 CHAPTER 15 UART 15.9.2 Operation in Synchronous Mode (Operation Mode 2) When the UART is used in operation mode 2 (normal mode), the transfer mode becomes clock synchronization. ■ Operation in Synchronous Mode (Operation Mode 2) ❍ Transfer-data format In synchronous mode, data is transferred in units of eight bits LSB first without the start bit and stop bit appended. Figure 15.9-5 shows the data format in clock synchronization mode. Figure 15.9-5 Transfer-data Format (Operation Mode 2) Send-data write Send and receive clock Mark level RXE, TXE Send and receive data 1 LSB 0 1 1 Data 0 0 1 0 MSB ❍ Clock supply In clock synchronization mode, a number of clock pulses equal to the number of send and receive bits must be supplied. • With the internal clock (dedicated baud-rate generator or internal timer) is selected, the synchronization clock for data reception is automatically generated when data is sent. • When the external clock is selected, ensure that the output-data register (SODR0 to SODR3) on the sending-side UART has data (SSR0 to SSR3: TDRE = 0). Then, clock pulses matching a length of exactly one byte must be supplied externally. Before sending begins and after sending, the mark level (H) must always be set. ❍ Error detection Overrun errors can be detected, but parity errors and frame errors cannot be detected. 340 CHAPTER 15 UART ❍ Initialization The setting values of each control register in synchronous mode are shown below. [Mode register (SMR0 to SMR3)] - MD1, MD0: 10B - CS2, CS1, CS0: Specify the clock selector clock input. - SCKE: 1 for the dedicated baud-rate generator or internal timer, and 0 for the clock output and external clock (clock input) - SOE: 1 for sending and 0 for receive-only [Control register (SCR0 to SCR3)] - PEN: 0 - P, SBL, and A/D: These bits have no effect. - CL: 1 (8-bit data) - REC: 0 (To initialize, the error flag is cleared.) - RXE, TXE: At least one of these must be 1. [Status register (SSR0 to SSR3)] - RIE: 1 for using interrupts and 0 for not using interrupts - TIE: 0 ❍ Start of communication Communication starts by writing to the output-data register (SODR0 to SODR3). Note that this applies even to communication for receiving: In this case, dummy data must be written to SODR0 to SODR3. ❍ End of communication When sending or receiving of the data for one frame terminates, the RDRF flag of the status register (SSR0 to SSR3) is set to 1. For receiving, check the overrun error flag bit (SSR0 to SSR3: ORE) and determine whether communication was performed normally. 341 CHAPTER 15 UART 15.9.3 Bidirectional Communication Function (Normal Mode) In operation modes 0 and 2, ordinary serial bidirectional communication can be performed in a one-to-one connection. The synchronization method is asynchronous in operation mode 0 and synchronous in operation mode 2. ■ Bidirectional Communication Function To operate the UART in normal mode (operation modes 0 and 2), the settings shown in Figure 15.9-6 are necessary. Figure 15.9-6 Settings for UART Operation Mode 0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 SCR1, SMR1 PEN P SBL CL AD bit8 bit7 bit6 bit5 bit4 bit3 bit2 REC RXE TXE MD1 MD0 CS2 CS1 CS0 bit1 SCKE SOE Mode 0 0 Mode 2 SSR1, SIDR1/SODR1 PE 1 0 ORE FRE RDRF TDRE 1 RIE TIE 0 Send data is set (for writing)/receive data is retained (for reading) Mode 0 Mode 2 : Used bit : Unused bit 1: Set to 1 0: Set to 0 ❍ Inter-CPU connection Connect the two CPUs to each other as shown in Figure 15.9-7. Figure 15.9-7 Example of Connection for UART Bidirectional Communication SOT1 SOT1 SIN1 SIN1 Output SCK1 CPU-1 342 Input SCK1 CPU-2 bit0 CHAPTER 15 UART ❍ Communication procedure Communication can start at any timing from the sending side when send data is ready. The receiving side receives send data and periodically returns ANS (in this example for each byte). Figure 15.9-8 shows an example of the bidirectional communication flow. Figure 15.9-8 Example of Bidirectional Communication Flow (Sending side) (Receiving side) Start Start Set operation mode ("0" or "2") Set operation mode (that matches the sending side) Set one-byte data in SODR and perform communication Send data Does receive data exist? NO YES NO Read and process receive data Does receive data exist? YES Read and process receive data Send data (ANS) Send one-byte data 343 CHAPTER 15 UART 15.9.4 Master/Slave-type Communication Function (Multiprocessor Mode) The UART can communicate with multiple CPUs in a master/slave-type connection in operation mode 1. However, the UART can only be used as the master CPU. ■ Master/Slave-type Communication Function To operate the UART in multiprocessor mode (operation mode 1), the settings shown in Figure 15.9-9 are necessary. Figure 15.9-9 Settings for UART Operation Mode 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 SCR1, SMR1 PEN P SBL 0 SSR1, SIDR1/SODR1 PE CL AD 1 bit8 bit7 bit6 bit5 bit4 bit3 REC RXE TXE MD1 MD0 CS2 CS1 CS0 0 ORE FRE RDRF TDRE 0 RIE TIE 1 bit2 bit1 bit0 SCKE SOE 0 Send data is set (for writing)/receive data is retained (for reading) : Used bit : Unused bit 1: Set to 1 0: Set to 0 ❍ Inter-CPU connection Connect one master CPU and multiple slave CPUs to two common communication lines and configure the communication system as shown in Figure 15.9-10. UART can only be used as the master CPU. Figure 15.9-10 Example of Connection for UART Master/Slave-type Communication SOT1 SIN1 Master CPU SOT SIN Slave CPU #0 344 SOT SIN Slave CPU #1 CHAPTER 15 UART ❍ Function selection For master/slave-type communication, select the operation mode and data transfer method as shown in Table 15.9-2. Table 15.9-2 Selection of Master/Slave-type Communication Functions Operation mode Data Master CPU Parity Synchronization method Stop bit None Asynchronous 1 bit or 2 bits Slave CPU A/D=1 + 8-bit address Address send and receive Mode 1 - Data send and receive A/D=0 + 8-bit data ❍ Communication procedure Communication starts when the master CPU sends address data. Address data is indicated by the fact that the A/D bit set to 1. It selects the slave CPU to communicate with. Each slave CPU determines the address data via the program. If the address data matches the allocated address, the slave CPU communicates (ordinary data) with the master CPU. Figure 15.9-11 shows a flowchart of the master-slave-type communication (in multiprocessor mode). 345 CHAPTER 15 UART Figure 15.9-11 Flowchart of Master/Slave-type Communication (Master CPU) START Set to operation mode 1 Set the SIN pins to serial-data input Set 1-byte data (address data) that selects the slave CPU in D0 to D7 and send (A/D = 1) Set A/D to 0 Enable receive operation Communicate with slave CPU Communication terminated? NO YES Communicate with another slave CPU YES Enable receive operation 346 NO END CHAPTER 15 UART 15.10 Notes on Using UART This section provides notes on using the UART. ■ Notes on Using the UART ❍ Operation enabled The UART has the TXE (sending) and RXE (receiving) operation enable bits in the control register (SCR0 to SCR3) separately for sending and receiving. Since both sending and receiving are disabled in the default state (initial value), these operations must be enabled before performing the transfer. The operations can be disabled to stop transfer as necessary. ❍ Communication mode setting Set the communication mode while the UART is stopped. If the mode is set during a sending or receiving operation, the integrity of the sent or received data cannot be guaranteed. ❍ Synchronization mode The UART clock synchronization mode (operation mode 2) employs the clock control (I/O extend serial) method and does not append the start bit and stop bit to data. ❍ Timing of enabling send interrupts A send-interrupt request occurs immediately after the send-interrupt request is enabled (SSR0 to SSR3: TIE = 1) because the default (initial value) of the send data empty flag bit (SSR0 to SSR3: TDRE) is 1 (no send data, send-data write enabled). The send data must be ready before the TIE flag is set to 1. 347 CHAPTER 15 UART 348 CHAPTER 16 I2C INTERFACE This chapter gives an overview of the I2C interface, the configuration and functions of registers, and the operation of the I2C interface. It also provides the related block diagrams. 16.1 Overview of I2C Interface 16.2 Block Diagram of I2C Interface 16.3 Registers of I2C Interface 16.4 Operation of I2C Interface 349 CHAPTER 16 I2C INTERFACE 16.1 Overview of I2C Interface The I2C interface is a serial I/O port that supports inter-IC buses. The I2C interfaces operate as master/slave devices on the I2C bus. ■ Features of I2C Interface In the MB91150, the I2C interface has one built-in channel. The following shows the features of I2C interface. 350 • Transmission to and reception from master/slave unit • Arbitration function • Clock synchronization function • Slave address/general call address detection function • Transfer direction detection function • Repeated generation of start condition and detection function • Bus error detection function CHAPTER 16 I2C INTERFACE 16.2 Block Diagram of I2C Interface Figure 16.2-1 is a block diagram of the I2C interface. ■ Block Diagram of I2C Interface Figure 16.2-1 Block Diagram of I2C Interface ICCR I 2C enable EN Peripheral clock Clock division 1 5 6 7 8 ICCR Clock selection 1 CS4 CS3 Clock division 2 CS2 2 4 8 16 32 64 128 256 Sync CS1 R-bus CS0 Clock selection 2 IBSR Shift clock Edge change timing Bus busy BB RSC Repeat start LRB Last bit TRX Shift clock generation Start-stop condition detection Error Send/receive FBT First byte AL Arbitration lost detection IBCR SCL BER SDA BEIE Interrupt request IRQ INTE INT IBCR SCC MSS ACK GCAA End Start Master ACK enable Start-stop condition detection GC-ACK enable IDAR IBSR AAS GCA Slave Global call Slave address comparison IADR 351 CHAPTER 16 I2C INTERFACE 16.3 Registers of I2C Interface Figure 16.3-1 lists the registers of the I2C interface. ■ Registers of the I2C Interface Figure 16.3-1 Registers of I2C Interface Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00000120H BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W R/W: Can be read and written R/W R/W R/W R/W R/W Address 00000121H R/W Initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 BB RSC AL LRB TRX AAS GCA FBT R R R R R R R R bit14 bit13 bit12 bit11 bit10 bit9 bit8 A6 A5 A4 A3 A2 A1 A0 R/W R/W: Can be read and written R/W R/W R/W R/W R/W R/W Address bit5 bit4 bit3 bit2 bit1 bit0 EN CS4 CS3 CS2 CS1 CS0 R/W R/W R/W R/W R/W bit15 00000122H bit7 bit6 00000123H 00000125H R/W Address register (IADR) Clock control register (ICCR) Initial value --0XXXXXB bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Can be read and written 352 Bus status register (IBSR) Initial value -XXXXXXXB R/W: Can be read and written Address 00000000B Initial value 00000000B R: Read only Address Bus control register (IBCR) Data register (IDAR) Initial value XXXXXXXXB CHAPTER 16 I2C INTERFACE 16.3.1 Bus Control Register (IBCR) The bus control register (IBCR) has the following functions. • Interrupt request/interrupt enable • Start condition generation • Master/slave selection • Acknowledge enable ■ Bus Control Register (IBCR) The bus control register (IBCR) has the following bit configuration. Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00000120H BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W R/W: Can be read and written R/W R/W R/W R/W R/W R/W Initial value 00000000B [bit 15] BER (Bus Error) This bit is a bus error interrupt request flag bit. (During writing) 0 Clears the bus error interrupt request flag. 1 Inapplicable (During reading) 0 Bus error is not detected. 1 Invalid start or stop condition is detected during data transfer. When this bit is set, the EN bit of the CCR register is cleared, the I2C interface is stopped, and data transfer is suspended. [bit 14] BEIE (Bus Error Interrupt Enable) This bit is a bus error interrupt enable bit. 0 Disables bus error interrupt. 1 Enables bus error interrupt. If the BER bit is 1 when this bit is 1, an interrupt is generated. 353 CHAPTER 16 I2C INTERFACE [bit 13] SCC (Start Condition Continue) This bit is a start condition generation bit. (During writing) 0 Inapplicable 1 Generates another start condition during transfer to or from the master. The read value of this bit is always 0. [bit 12] MSS (Master Slave Select) This bit is a master/slave selection bit. 354 0 A stop condition is generated, and slave mode is selected after the transfer ends. 1 Master mode is selected to generate a start condition and start transfer. CHAPTER 16 I2C INTERFACE When arbitration lost occurs during transfer to or from the master, this bit is cleared and slave mode is selected. Note: When other LSI that becomes a master mode besides this LSI exists on the bus, this LSI cannot be used in the master mode. • Construction example that can be used I2C bus MB91150 Series Master Slave A Slave B I2C bus MB91150 Series Slave A Master A Slave • Construction example that can not be used I2C bus MB91150 Series Slave A Master A Master [bit 11] ACK (ACKnowledge) This bit is an acknowledge enable bit when the data is received. 0 Acknowledge is not generated. 1 Acknowledge is generated. This bit becomes invalid during address data reception in slave mode. 355 CHAPTER 16 I2C INTERFACE [bit 10] GCAA (General Call Address Acknowledge) This bit is an acknowledge enable bit when a general call address is received. 0 Acknowledge is not generated. 1 Acknowledge is generated. [bit 9] INTE (INTerrupt Enable) This bit is an interrupt enable bit. 0 Interrupts disabled 1 Interrupts enabled If the INT bit is 1 when this bit is 1, interrupts are enabled. [bit 8] INT (INTerrupt) This bit is a transfer-end interrupt-request flag bit. (During writing) 0 Clears the transfer-end interrupt-request flag. 1 Inapplicable (During reading) 0 Transfer has not completed. 1 When the transfer of 1 byte, including the acknowledge bit, ends, and one of the following conditions is met, this bit is set. • Bus master is selected. • The slave is addressed. • General call address is received. • Arbitration lost occurred. • When another system is using the bus, an attempt is made to generate a start condition. When this bit is 1, the SCL line is kept at "L" level. When this bit is cleared by writing 0, the SCL line is released, and transfer of the next byte is performed. When a start or stop condition is generated in master mode, this bit is reset to 0. 356 CHAPTER 16 I2C INTERFACE Note: If the instruction that generates the start condition is executed on the timing in Figure 16.3-2 and Figure 16.3-3 ("1" is set to the MMS bit), the interrupt (INT bit = 1) by the arbitration lost detection (AL bit = 1) is not generated. • Condition 1 that interrupt (INT bit = 1) by AL bit = 1 detection is not generated Condition that the instruction fort generating the start condition is executed ("1" is set to the MSS bit of the IBCR register), when the SDA pin level or the SCL pin level is "L" at the undetected status for start condition (BB bit = 0). Figure 16.3-2 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur SCL pin or SDA pin at "L" level SCL pin "L" SDA pin "L" I2C operation enable status (EN bit = 1) Master mode setting (MSS bit = 1) "1" Arbitration lost detection (AL bit) Bus busy (BB bit) "0" Interrupt (INT bit) "0" 357 CHAPTER 16 I2C INTERFACE • Condition 2 in which an interrupt (INT bit=1) upon detection of "AL bit=1" does not occur When an instruction which generates a start condition by enabling I2C operation (EN bit=1) is executed (set "1" to MSS bit in IBCR register) with the I2C bus occupied by another master. This is because, as shown in Figure 16.3-3, when the other master on the I2C bus starts communication with I2C disabled (EN bit=0), the I2C bus enters the occupied state with no start condition detected (BB bit =0). Figure 16.3-3 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" does not Occur Start Condition The INT bit interrupt does not occur in the ninth clock cycle. Stop Condition SCL pin SDA pin SLAVE ADDRESS ACK DAT ACK EN bit MSS bit AL bit BB bit INT bit "0" "0" If a symptom as described above can occur, follow the procedure below for software processing. 1. Execute the instruction that generates a start condition (set the MSS bit to "1"). 2. Use, for example, the timer function to wait for the time for three-bit data transmission at the I2C transfer frequency set in the ICCR register.* Example:Time for three-bit data transmission at an I2C transfer frequency of 100 kHz = {1/(100x103)}x30=30 µs 3. Check the AL and BB bits in the IBSR register and, if the AL and BB bits are "1" and "0", respectively, set the EN bit in the ICCR register to "0" to initialize I2C. When the AL and BB bits are not so, perform normal processing. 358 CHAPTER 16 I2C INTERFACE A sample flow is given below. Master mode setting Set MSS bit in bus control register (IBCR) to "1". Wait for the time for three-bit data transmission at the I2C transfer frequency set in the clock control register (ICCR)* NO BB bit=0 and AL bit=1 YES Setting EN bit to "0" and initializing of I2C To normal process *: When the arbitration lost is detected, the MSS bit is set to "1" and then the AL bit is set to "1" without fail after the time for three-bit data transmission at the I2C transfer frequency. • Example of occurrence for an interrupt (INT bit=1) upon detection of "AL bit=1" When an instruction which generates a start condition is executed (setting the MSS bit to "1") with "bus busy" detected (BB bit=1) and arbitration is lost, the INT bit interrupt occurs upon detection of "AL bit=1". Figure 16.3-4 Diagram of Timing at which an Interrupt upon Detection of "AL bit=1" Occurs Start Condition Interrupt in the ninth clock cycle SCL pin SDA pin SLAVE ADDRESS ACK DAT EN bit MSS bit AL bit Clearing the AL bit by software BB bit INT bit Releasing the SCL by clearing the INT bit by software 359 CHAPTER 16 I2C INTERFACE ■ Contention Among SCC, MSS, and INT Bits In simultaneous write operations of the SCC, MSS, and INT bits, transfer of the next byte, startcondition generation, and stop-condition generation compete with each other. In this case, the priority order becomes as follows: 1. Transfer of the next byte and stop-condition generation • When an attempt is made to set the INT bit and the MSS bit to 0 by writing, the writing of the MSS bit is given priority, and a stop condition is generated. 2. Transfer of the next byte and start-condition generation • When an attempt is made to set the INT to 0 and the SCC bit to 1, writing the SCC bit is given priority, and a start condition is generated. 3. Start-condition and stop-condition generation • 360 Do not simultaneously set the SCC bit to 1 and the MSS bit to 0. CHAPTER 16 I2C INTERFACE 16.3.2 Bus Status Register (IBSR) The bus status register (IBSR) has the following functions: • Detection of repeated start conditions • Detection of arbitration lost • Acknowledge storage • Data transfer • Addressing detection • Detection of general call address • Detection of the first byte ■ Bus Status Register (IBSR) The bus status register (IBSR) has the following bit configuration: Address 00000121H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 BB RSC AL LRB TRX AAS GCA FBT R R R R R R R R Initial value 00000000B R: Read only [bit 7] BB (Bus Busy) This bit indicates the I2C bus status. 0 Stop condition is detected. 1 Start condition is detected (the bus is used). [bit 6] RSC (Repeated Start Condition) This bit is used to detect repeated start conditions. 0 Repeated start conditions are not detected. 1 Another start condition is detected while the bus is used. If this bit is not addressed, the INT bit is set to 0, or in slave mode, it is cleared by detection of a start or stop condition when the bus is inactive. 361 CHAPTER 16 I2C INTERFACE [bit 5] AL (Arbitration Lost) This bit is used to detect arbitration lost. 0 Arbitration lost is not detected. 1 Arbitration lost occurred during transmission to or from the master, or the MSS bit was set to 1 while another system is using the bus. This bit is cleared by setting the INT bit to 0 in a write operation. [bit 4] LRB (Last Received Bit) This bit stores acknowledge. This bit stores an acknowledge sent from the receiving side. 0 Sleep acknowledge is detected. 1 Sleep acknowledge is not detected. This bit is cleared when a start or stop condition is detected. [bit 3] TRX (Transfer/Receive) This bit indicates whether data transfer is a transmission or reception. 0 Reception status 1 Transmission status [bit 2] AAS (Addressed As Slave) This bit is used to detect the addressing status. 0 Addressing is not made in slave mode. 1 Addressing is made in slave mode. This bit is cleared by detecting a start or stop condition. [bit 1] GCA (General Call Address) This bit is used to detect a general call address (00H). 0 General call address is not received in slave mode. 1 General call address is received in slave mode. This bit is cleared by detecting a start or stop condition. 362 CHAPTER 16 I2C INTERFACE [bit 0] FBT (First Byte Transfer) This bit is used to detect the first byte. 0 The received item of data is not the first byte. 1 The received item of data is the first byte (address data). Even if this bit is set to 1 by detecting a start condition, this bit will be cleared if the INT bit is set to 0 by writing, or if addressing is omitted in slave mode. 363 CHAPTER 16 I2C INTERFACE 16.3.3 Address Register (IADR)/Data Register (IDAR) The address register (IADR) is used to specify a slave address. The data register (IDAR) is used to perform serial transfer. ■ Address Register (IADR) The address register (IADR) has the following bit configuration: Address 00000122H bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 − A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W − R/W R/W: Can be read and written Initial value -XXXXXXXB [bit 14 to bit 8] A6 to A0 (Slave address bit) This register specifies a slave address. After address data is received in slave mode, it is compared with that of the IDAR register. If both values match, acknowledge is transmitted to the master. ■ Data Register (IDAR) The data register (IDAR) has the following bit configuration: Address 00000125H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W: Can be read and written Initial value XXXXXXXXB [bit 7 to bit 0] D7 to D0 (Data bit) This data register is used to perform serial transfer, during which data is transferred starting from the MSB. At the time of data reception (TRX=1), the output data value becomes 1. This register has a double buffer on the writing side. When the bus is in use (BB=1), data to be written is loaded into the serial transfer register at each byte transfer. Because the data of the serial transfer register is directly read during data reading, received data is valid only when the INT bit is set. 364 CHAPTER 16 I2C INTERFACE 16.3.4 Clock Control Register (ICCR) The clock control register (ICCR) has the following functions: • Enabling the I2C interface • Setting of serial clock frequency ■ Clock Control Register (ICCR) The clock control register (ICCR) has the following bit configuration: Address 00000123H bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 − − EN CS4 CS3 CS2 CS1 CS0 − − R/W R/W R/W R/W R/W R/W Initial value --0XXXXXB R/W: Can be read and written [bit 7, bit 6] Unused bits [bit 5] EN (ENable) This bit enables or disables the I2C interface. 0 Disable operation 1 Enable operation When this bit is 0, the IBSR and IBCR registers (excluding the BER and BEIE bits) are cleared. When the BER bit is set, this bit is cleared. [bit 4 to bit 0] CS4 to CS0 (Clock Period Select 4 to 0) These bits set a serial clock frequency. The shift clock frequency fsck is set according to the following formula: Fsck = φ m×n+4 φ : Machine clock frequency Note: The cycle of + 4 is the minimum overhead required to check whether the output level of the SCL pin varies. When the rise-time response to delay at the SCL pin is large or the clocks are extended to the slave device, this value becomes larger. 365 CHAPTER 16 I2C INTERFACE Table 16.3-1 lists the m and n values for CS4-CS0. Table 16.3-1 Setting of Serial Clock Frequency 366 m CS4 CS3 n CS2 CS1 CS0 5 0 0 4 0 0 0 6 0 1 8 0 0 1 7 1 0 16 0 1 0 8 1 1 32 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 CHAPTER 16 I2C INTERFACE 16.4 Operation of I2C Interface The I2C bus establishes communication via two bidirectional bus lines, one serial data line (SDA) and one serial clock line (SCL). The I2C interface has two open-drain input pins (SDA and SCL) to make the wiring logic possible. ■ I2C Interface Operation ❍ Start conditions When the MSS bit is set to 1 while the bus is opened (BB=0, MSS=0), the I2C interface is put in master mode and generates a start condition at the same time. Even if the bus is being used (BB=1) in master mode, another start condition can be generated by setting the SCC bit to 1. Start conditions can be generated in the following two ways. • Setting the MSS bit to 1 by writing when the bus is not used (MSS=0, BB=0, INT=0, AL=0). • Write 1 to the SCC bit in interrupt state when the bus is in master mode (MSS=1, BB=1, INT=1, AL=0). If the MSS bit is set to 1 by writing when another system (idling) is using the bus, the AL bit is set to 1. Any attempt other than as described above to set the MSS and SCC bits to 1 is not effective. ❍ Stop conditions If the MSS bit is set to 0 by writing in master mode (MSS=1), a stop condition is generated and the I2C interface is put into slave mode. Stop conditions are generated under the following conditions: • Setting the MSS bit to 0 by writing interrupt state when the bus is in master mode (MSS=1,BB=1,INT=1,AL=0). • Any attempt other than as described above to set the MSS bit to 0 is ignored. ❍ Addressing In master mode, after a start condition is generated, the I2C interface is set to BB=1 and TRX=1, and the contents of the IDAR register are outputted, starting from the MSB. If acknowledge is received from the slave after address data is transmitted, bit 0 of the transmitted data (bit 0 of the posttransmission IDAR register) is inverted, which is stored in the TRX bit. In slave mode, after a start condition is generated, the I2C interface is set to BB=1 and TRX=0, and the data transmitted from the master is received by the IDAR register. After the address data is received, the contents of the IDAR register are compared with those of the IADR register. If both values match, AAS=1 is set and acknowledge is transmitted to the master. Then, the value of bit 0 of the received data (bit 0 of the postreception IDAR register) is stored in the TRX bit. 367 CHAPTER 16 I2C INTERFACE ❍ Arbitration When more than one master transmits data at the same time, arbitration starts. When the data to be transmitted is 1, and the data on the SDA line is at the "L" level, the master sets AL=1, assuming that it has lost the arbitration. If an attempt is made to generate a start condition when the bus is used as described above, AL=1 is set. When AL=1 is set, MSS=0 and TRX=0 are set and slave receive mode is entered. ❍ Acknowledge Acknowledge is transmitted from the receiving unit to the transmitting unit. At the time of data reception, reception with or without acknowledge can be selected by the ACK bit. At the time of data transmission, an acknowledge from the receiving side is stored in the LRB bit. When the receiving master does not receive acknowledge during transmission from the slave, TRX=0 is set and the slave is put in receive mode. This allows the master to generate a stop condition when the slave releases the SCL line. ❍ Bus error When one of the following conditions is met, a bus error is assumed and the I2C interface is stopped. 368 • Detection of violation for basic rules on the I2C bus during data transfer (including the ACK bit) • Detection of stop conditions in master mode • Detection of violation for basic rules on the I2C bus in bus idle state CHAPTER 17 DMA CONTROLLER (DMAC) This chapter describes an overview of the DMA controller, the block diagram, the configuration and function of its registers, and its operations. 17.1 Overview of the DMA Controller 17.2 Block Diagram of the DMA Controller 17.3 Registers of the DMA Controller 17.4 Transfer Modes Supported by the DMA Controller 17.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output 17.6 Notes on the DMA Controller 17.7 Timing Charts for the DMA Controller 369 CHAPTER 17 DMA CONTROLLER (DMAC) 17.1 Overview of the DMA Controller The DMA controller is a module built in the MB91150 that performs DMA (Direct Memory Access) transfers. ■ Features of the DMA Controller 370 • Eight channels • The 3 transfer modes below are available • Single/block transfer • Burst transfer • Continuous transfer • Transfers between the entire address areas • Up to 65536 transfers • Interrupt at end of transfer • Software selection available for increasing or decreasing the number of transfer addresses • The following pins are available (3 of each kind): • Input pin for external transfer request • Output pin for reception of external transfer request • Output pin for end of external transfer CHAPTER 17 DMA CONTROLLER (DMAC) 17.2 Block Diagram of the DMA Controller Figure 17.2-1 shows a block diagram of the DMA controller. ■ Block Diagram of the DMA Controller Figure 17.2-1 Block Diagram of the DMA Controller DREQ0 to DREQ2 Internal resource transfer request 3 Edge/level detector circuit 3 3 3 Sequencer 5 Data buffer 8 DACK0 to DACK2 DEOP0 to DEOP2 Interrupt request Switcher DPDP Data bus DACSR DATCR Mode BLK DEC BLK DMACT INC/DEC SADR DADR 371 CHAPTER 17 DMA CONTROLLER (DMAC) 17.3 Registers of the DMA Controller Figure 17.3-1 lists the registers of the DMA controller. ■ Registers of the DMA Controller Figure 17.3-1 Registers for the DMA Controller [Internal registers in the DMAC] 31 0 000200H DPDP 000204H DACSR 000208H DATCR [DMA descriptors in RAM] 31 0 DPDP + 0H DMA ch.0 Descriptor DMA ch.1 Descriptor DPDP + 0CH : : DPDP + 54H 372 DMA ch.7 Descriptor CHAPTER 17 DMA CONTROLLER (DMAC) 17.3.1 DMAC Parameter Descriptor Pointer (DPDP) This pointer is the internal register of DMAC and stores the start address in the descriptor table for the DMAC in RAM. Bit 0 to bit 6 are always set to 0. The start address of the descriptor can be set in units of 128 bytes. ■ DMAC Parameter Descriptor Pointer (DPDP) The register configuration of the DMAC parameter descriptor pointer (DPDP) is given below. 31 7 000200H 6 0 0000000 Initial value: 0000000B Initial value: Undefined • Upon reset, the pointer is not initialized. • The pointer value can be read and written. • Use a 32-bit transfer instruction to access this register. The descriptor used to specify the operating mode for each channel is placed at an address set by the DPDP, as covered in Table 17.3-1. Table 17.3-1 Descriptor address for Each Channel DMA channel Descriptor address DMA channel Descriptor address 0 DPDP + 0 (00H) 4 DPDP + 48 (30H) 1 DPDP + 12 (0CH) 5 DPDP + 60 (3CH) 2 DPDP + 24 (18H) 6 DPDP + 72 (48H) 3 DPDP + 36 (24H) 7 DPDP + 84 (54H) 373 CHAPTER 17 DMA CONTROLLER (DMAC) 17.3.2 DMAC Control Status Register (DACSR) The DMAC control status register (DACSR) is an internal register in the DMAC that controls the entire DMAC and indicates its status. ■ DMAC Control Status Register (DACSR) The register configuration of the DMAC control status register (DACSR) is given below. 000204H bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 DER7 DED7 DIE7 DOE7 DER6 DED6 DIE6 DOE6 R/W R/W R/W R/W R/W R/W R/W R/W bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 DER5 DED5 DIE5 DOE5 DER4 DED4 DIE4 DOE4 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 DER3 DED3 DIE3 DOE3 DER2 DED2 DIE2 DOE2 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DER1 DED1 DIE1 DOE1 DER0 DED0 DIE0 DOE0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: 00000000H [bit 31, bit 27, bit 23, bit 19, bit 15, bit 11, bit 7, and bit 3] DER7 to DER0 (DMA error) Indicates that an error has occurred at the DMA request source of ch.n and that DMA transfer processing has been terminated. 0: No error has occurred. 1: An error has occurred. Whether an error is detected depends on the DMA request source. Some DMA request sources have no error detection. - Upon a reset, the bits in the register are initialized to 0. - Although these bits can be read and written, they can be set only to 0. - Read/modify/write instructions always return a reading value of 1. 374 CHAPTER 17 DMA CONTROLLER (DMAC) [bit 30, bit 26, bit 22, bit 18, bit 14, bit 10, bit 06, and bit 02] DED7 to DED0 (DMA end) Indicates that DMA transfer over ch.n has ended. 0: DMA transfer operation has not ended. 1: The counter has been reset to 0, or an error occurred at the transfer request source. - Upon a reset, the bits in the register are initialized to 0. - Although these bits can be read and written, these bits can only be set to 0. - Read/modify/write instructions always return a reading value of 1. [bit 29, bit 25, bit 21, bit 17, bit 13, bit 9, bit 5, and bit 1] DIE7 to DIE0 (DMA interrupt enable) Specify whether to generate an interrupt at the end of DMA transfer over ch.n (when DED7 to DED0 is set to 1). 0: Disables interrupts. 1: Enables interrupts. - Upon reset, the bits in the register are initialized to 0. - These bits can be read and written. [bit 28, bit 24, bit 20, bit 16, bit 12, bit 8, bit 4, and bit 0] DOE7 to DOE0 (DMA operation enable) Enables DMA transfer operation over ch.n. 0: Disables operation. 1: Enables operation. - Upon completion of DMA transfer over the appropriate channel (when DED7 to DED0 is set to 1), DOE7 to DOE0 is reset to 0. - If a clearing operation following completion of transfer and a setting operation by loading from a bus are performed concurrently, the setting operation has priority. - Upon reset, the bits in the register are initialized to 0. - These bits can be read and written. 375 CHAPTER 17 DMA CONTROLLER (DMAC) 17.3.3 DMAC Pin Control Register (DATCR) The DMAC pin control register (DATCR) in the DMAC controls an external transfer request input pin, an external transfer-request-acceptance output pin, and an external transfer-end output pin. ■ DMAC Pin Control Register (DATCR) The register configuration of the DMAC pin control register (DATCR) is given below. bit 31 bit 24 000208H bit 23 bit 15 bit 7 bit 22 bit 14 bit 6 bit 21 bit 20 bit 19 bit 18 bit 17 LS21 LS20 AKSE2 R/W R/W R/W R/W R/W R/W bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 LS11 LS10 AKSE1 AKDE1 EPSE1 EPDE1 R/W R/W R/W R/W R/W R/W bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 LS01 LS00 AKSE0 AKDE0 EPSE0 EPDE0 R/W R/W R/W R/W R/W R/W AKDE2 EPSE2 bit 16 EPDE2 Initial value: XXX0X0X0H [bit 21, bit 20, bit 13, bit 12, bit 5, and bit 4] LS21, LS20, LS11, LS10, LS01 and LS00 for transfer request input detection level selection These bits select a detection level for an external transfer request input pin DREQ2 to DREQ0 as shown below. LS21, LS11, LS01 LS20, LS10, LS00 0 0 Detects a leading edge. 0 1 Detects a trailing edge. 1 0 Detects the H level. 1 1 Detects the L level. • • • 376 Description Upon reset, register operation is undefined. These bits can be read and written. To use continuous transfer mode, set H level detection or L level detection. CHAPTER 17 DMA CONTROLLER (DMAC) [bit 19, bit 11, and bit 3] AKSE2, AKSE1, AKSE0 [bit 18, bit 10, and bit 2] AKDE2, AKDE1, AKDE0 Specify the timing at which to generate a transfer-request-acceptance output signal. Also, specify whether to enable or disable the function for output of transfer-request-acceptance output signals from a pin. • • AKSE2, AKSE1, AKSE0 AKDE2, AKDE1, AKDE0 0 0 Disables transfer-acceptance output. 0 1 Enables transfer-acceptance output during access to transfer destination data. 1 0 Enables transfer-acceptance output during access to transfer source data. 1 1 Enables transfer-acceptance output during access to transfer destination data. Description Upon a reset, the bits in the register are initialized to 00B. These bits can be read and written. [bit 17, bit 9, and bit 1] EPSE2, EPSE1, EPSE0 [bit 16, bit 8, and bit 0] EPDE2, EPDE1, EPDE0 Specify the timing at which to generate a transfer-end output signal. Also, specify whether to enable or disable the function for outputting a transfer-end output signal from a pin. • • EPSE2, EPSE1, EPSE0 EPDE2, EPDE1, EPDE0 0 0 Disables transfer-end output. 0 1 Enables transfer-end output during access to transfer destination data. 1 0 Enables transfer-end output during access to transfer source data. 1 1 Enables transfer-end output during access to transfer source and transfer destination data. Description Upon reset, the bits in the register are initialized to 00B. These bits can be read and written. 377 CHAPTER 17 DMA CONTROLLER (DMAC) 17.3.4 Register of the Descriptor in RAM This register stores information for each channel for DMA transfer. This register has a size of 12 bytes per channel and uses the memory space at the address allocated by the DPDP. For details on the start address of the descriptor for each channel, see Table 17.3-1. ■ Descriptor Start Word The register configuration of the descriptor start word is given below. bit 31 bit 16 DMACT R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 BLK R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SCS1 SCS0 DCS1 DCS0 WS1 WS0 MOD1 MOD0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value: Undefined [bit 31 to bit 16] DMACT transfer count Specify the number of times the DMA is to be transferred. With 0000H set, the DMA is transferred 65536 times. The value is decremented by one for each transfer. [bit 15 to bit 12] Empty [bit 11 to bit 8] BLK block size Specify the size of a block to be transferred in single/block transfer mode. If you specify 0, a block size of 16 is set. For single transfer, specify 1. [bit 7 and bit 6] SCS1 and SCS0 transfer source address update mode [bit 5 and bit 4] DCS1 and DCS0 transfer destination address update mode Specify the mode for updating the transfer source and destination addresses for each transfer. You can specify the combinations listed in the following table. 378 CHAPTER 17 DMA CONTROLLER (DMAC) SCS1 SCS0 DCS1 DCS0 Transfer source address Transfer destination address 0 0 0 0 Address incremented Address incremented 0 0 0 1 Address incremented Address decremented 0 0 1 0 Address incremented Address fixed 0 1 0 0 Address decremented Address incremented 0 1 0 1 Address decremented Address decremented 0 1 1 0 Address decremented Address fixed 1 0 0 0 Address fixed Address incremented 1 0 0 1 Address fixed Address decremented 1 0 1 0 Address fixed Address fixed Others Setting disabled In address update mode, the units of increment or decrement are as follows, depending on the length of data to be transferred. Length of data transferred Unit of address increment or decrement Byte (8 bits) Plus or minus 1 byte Half word (16 bits) Plus or minus 2 bytes Word (32 bits) Plus or minus 4 bytes [bit 3 and bit 2] WS1 and WS0 Specify the length of data to be transferred. WS1 WS0 Length of data to be transferred 0 0 Byte 0 1 Half word 1 0 Word 1 1 Setting disabled 379 CHAPTER 17 DMA CONTROLLER (DMAC) [bit 1 and bit 0] MOD1 and MOD0 transfer mode Specify transfer mode. MOD1 MOD0 Operating mode 0 0 Single/block mode 0 1 Burst mode 1 0 Continuous transfer mode 1 1 Setting disabled Only ch.0 to ch.2 can use in continuous transfer mode. ■ Second Word in the Descriptor 31 0 SADR R/W Stores a transfer source address. The value is updated in accordance with a transfer operation based on the specified address update mode (SCS1 and SCS0 bits). Specify a multiple of 2 as the address if the data to be transferred is half word length, and a multiple of 4 as the address if the data is of word length. ■ Third Word in the Descriptor 31 0 DADR R/W Stores a transfer destination address. The value is updated in accordance with transfer operation based on the specified address update mode (DCS1 and DCS0 bits). Specify a multiple of 2 as the address if the data to be transferred is half word length, and a multiple of 4 as the address if the data is of word length. 380 CHAPTER 17 DMA CONTROLLER (DMAC) 17.4 Transfer Modes Supported by the DMA Controller The DMA controller supports the following three transfer modes. • Single/block transfer mode • Continuous transfer mode • Burst transfer mode ■ Single/Block Transfer Mode 1. Use an initialization routine to set the descriptor. 2. Use the appropriate program to initialize the DMA transfer request source. If this source is an internal peripheral circuit, enable interrupt requests. Disable interrupt requests for interrupt controller ICR register at the same time. 3. Use a program to set the DOE7 to DOE0 bit in the desired DACSR to 1. This completes the DMA setup. 4. When the DMAC detects DMA transfer request input, it requests the CPU to acquire the bus right. 5. When the CPU assigns the bus right, the DMAC accesses three-word information stored in the descriptor via the bus. 6. DMACT subtraction is performed, and data is transferred in accordance with information in the descriptor by the number of times set in BLK or until the DMACT becomes 0. During data transfer, the transfer-request-acceptance output signal is outputted (if external transfer request input is used). If the DMACT subject to subtraction becomes 0, the transfer-end output signal is outputted during data transfer. 7. The transfer request input is cleared. 8. SADR or DADR addition or subtraction is performed, and a new value is written back to the descriptor together with the DMACT value. 9. The bus right is returned to the CPU. 10.If the DMACT value is 0, DACSR DED7 to DED0 is set to 1, and a CPU interrupt is generated if interrupts are enabled. If the descriptor is stored in the internal RAM, and data of byte length is transferred between external buses, the required minimum cycle count per transfer is as described below, under the conditions indicated: • When both the transfer source and destination addresses are fixed: (6 + 5 x BLK) cycles • When only one of the transfer source and destination addresses is fixed: (7 + 5 x BLK) cycles • When both the transfer source and destination addresses are incremented or decremented: (8 + 5 x BLK) cycles 381 CHAPTER 17 DMA CONTROLLER (DMAC) ■ Continuous Transfer Mode 1. Use an initialization routine to set the descriptor. 2. Use the appropriate program to initialize the DMA transfer request source. Set the external transfer request input pin to H or L level detection. 3. Use the program to set the DOE7 to DOE0 bit in the desired DACSR to 1. This completes the DMA setup. 4. When the DMAC detects DMA transfer request input, its requests the CPU to acquire the bus right. 5. When the CPU assigns the bus right, the DMAC accesses three-word information in the descriptor via the bus. 6. DMACT subtraction is performed, and data is transferred once in accordance with the information in the descriptor. During data transfer, the transfer-request-acceptance output signal is outputted. When the DMACT subject to the subtraction becomes 0, the transfer-end output signal is outputted during data transfer. 7. If the DMACT value is not 0 and a peripheral DMA request still exists, step 6) is repeated. (Step 8) is used depending on the bus status.) 8. If the DMACT value is 0 or if a peripheral DMA request is cleared, SADR or DADR addition or subtraction is performed, and a new value is written back to the descriptor together with the DMACT value. 9. The bus right is returned to the CPU. 10.If the counter value is 0, DACSR DED7 to DED0 is set to 1, and a CPU interrupt is generated if interrupts are enabled. If the descriptor is stored in the internal RAM, and data of byte length is transferred between external buses, the required minimum cycle count per transfer is as described below, under the conditions indicated: • When both the transfer source and destination addresses are fixed: (6 + 5 x n) cycles • When only one of the transfer source and destination addresses is fixed: (7 + 5 x n) cycles • When both the transfer source and destination addresses are incremented or decremented: (8 + 5 x n) cycles ■ Burst Transfer Mode 1. Use an initialization routine to set the descriptor. 2. Use the appropriate program to initialize the DMA transfer request source. If the internal peripheral circuit is the transfer request source, enable interrupt requests. At the same time, disable interrupt for interrupt controller ICR register. 3. Use the program to set the DOE7 to DOE0 bit in the desired DACSR to 1. This completes the DMA setup. 4. When the DMAC detects DMA transfer request input, it requests the CPU to acquire the bus right. 5. When the CPU assigns the bus right, the DMAC accesses three-word information in the descriptor via the bus. 6. Data is transferred in accordance with the descriptor information by the number of times set in the DMACT during DMACT subtraction. The transfer-request-acceptance output signal is outputted during data transfer. (If external transfer request input is used,) the transfer-end output signal is outputted during data transfer when the DMACT becomes 0. 382 CHAPTER 17 DMA CONTROLLER (DMAC) 7. SADR or DADR addition or subtraction is performed, and a new value is written back to the descriptor together with the DMACT value. 8. The bus right is returned to the CPU. 9. DACSR DED7 to DED0 is set to 1, and a CPU interrupt is generated if interrupts are enabled. If the descriptor is stored in the internal RAM, and data of byte length is transferred between external buses, the required minimum cycle count per transfer is as described below, under the conditions indicated: • When both the transfer source and destination addresses are fixed: (6 + 5 x n) cycles • When only one of the transfer source and destination addresses is fixed: (7 + 5 x n) cycles • When both the transfer source and destination addresses are incremented or decremented: (8 + 5 x n) cycles ■ Combinations of Request Sense Modes and Transfer Modes Figure 17.4-1 shows the available combinations of request sense modes and transfer modes. Figure 17.4-1 Combinations of Request Sense Modes and Transfer Modes Request sense Transfer mode Transfer unit Edge sense Step operation mode Single transfer Level sense Burst transfer mode Block transfer Continuous transfer mode ■ DREC Signal Sense Modes ❍ Edge sense This mode can be used in step transfer (single/block) and burst transfer modes. DMA requests are detected at an "active" edge. Because the input of an external DREQ is masked during DMAC transfer, note that the active edge for the next transfer must be after that of the transfer destination DACK in the previous DMA transfer. Note that step transfer is used. ❍ Level sense This mode can be used in step transfer (single/block) and continuous and burst transfer modes. DMA requests are detected at an "active" level. Note: min 2tCYC [ns] applies as the electrical characteristic of DACK signals for both level and edge sense. In the case of edge sense, min 2tCYC [ns] is also required as DACK negation interval. 383 CHAPTER 17 DMA CONTROLLER (DMAC) 17.4.1 Step Transfer (Single/Block Transfer) The step transfer (single/block transfer) performs one DMA transfer per transfer request. Edge or level can be selected for the DREQ input. ■ Step Transfer (Single/Block Transfer) In step transfer mode, the bus access right is transferred to the CPU for each DMA transfer. The unit of transfer is determined based on the block size. As the block size increases, the DMAC transfer rate increases, but the CPU throughput decreases. Figure 17.4-2 shows a sample timing of step transfer the case a CLK doubler, internal descriptors, and a block size of 1 are used. Figure 17.4-2 Sample Timing of Step Transfer Step transfer [use of CLK doubler, internal descriptors, and block size = 1] CLK DREQ DACK Descriptor access Internal D-Abus Interval during which the CPU can use the DATA bus External Abus Transfer Transfer destination destination 384 Transfer Transfer destination destination CHAPTER 17 DMA CONTROLLER (DMAC) 17.4.2 Continuous Transfer In continuous transfer, DMA transfer is performed while a transfer request (DREQ) retains the active level. For the DREQ input, only level sense mode is possible. ■ Continuous Transfer In continuous transfer mode, the bus access right is transferred to the CPU when the transfer count register is reset to 0 or the DREQ input is negated. Figure 17.4-3 shows an example for continuous transfer timing when a CLK doubler and internal descriptors are used. Figure 17.4-3 Sample Timing of Continuous Transfer Continuous transfer [use of CLK doubler and internal descriptors] CLK Descriptor access DREQ DACK Internal D-Abus External Abus Interval during which the CPU can use the DATA bus Transfer destination Transfer Transfer destination destination Transfer destination 385 CHAPTER 17 DMA CONTROLLER (DMAC) 17.4.3 Burst Transfer In burst transfer, DMA transfer is performed as many times as specified in a transfer request (DREQ). Level or edge sense mode can be selected for the DREQ input. ■ Burst Transfer In burst transfer mode, DMA transfer is finished when the transfer count register becomes 0, and bus access right is transferred to the CPU. Figure 17.4-4 shows an example of burst transfer timing when a CLK doubler and internal descriptors are used. Figure 17.4-4 Sample Timing of Burst Transfer Burst transfer [use of CLK doubler and internal descriptors] CLK DREQ Descriptor access DACK Internal D-Abus External Abus Interval during which the CPU can use the DATA bus Transfer destination Transfer Transfer Transfer destination destination destination DEOP2 to DEOP0 DMACT=1 386 DMACT=0 CHAPTER 17 DMA CONTROLLER (DMAC) 17.4.4 Differences Because of DREQ Sense Mode The DREQ sense modes include level and edge modes. This section provides notes on each mode. ■ Notes on Level Mode In level sense mode, be careful that overrun occurs during DMAC transfer. Negate DREQ until the rising DACK edge during transfer destination access. Figure 17.4-5 shows the level-mode timing. Figure 17.4-5 Level-mode Timing Up to 1 tCYC CLK DREQ DREQ DACK DREQ(NG) Transfer is performed twice per transfer request. Source reading Writing to destination Internal D-A Descriptor writing Descriptor reading External A bus Transfer destination Transfer destination A B A: Request flag clearance point Sensing start point for the next DREQ in edge sense mode Sensing start point for the next DREQ in continuous transfer mode B: Sensing start point for the next DREQ during single and block transfer in level sense mode Note: The timing from DREQ to DMA start reflects the case where this is performed close to top speed. 387 CHAPTER 17 DMA CONTROLLER (DMAC) ■ Notes on Edge Mode In edge sense mode, the next DREQ edge must be inputted after the clearance point of the DMAC request flag. Note that any edge input before that point is ignored. To ensure the edge is recognized, a negation interval of min 2tCYC [ns] is required. Input the DREQ, as shown in Figure 17.4-6, after the falling DACK edge during transfer destination access. Figure 17.4-6 shows the timing in edge-mode. Figure 17.4-6 Edge-mode Timing CLK DREQ DACK DREQ(NG) Active edge is too early. DREQ(NG) DREQ(NG) Writing to destination The time is greater than "Min 2tCYC [ns]" Internal D-Abus Descriptor writing External A bus Transfer destination Transfer destination A A: B Request flag clearance point Sensing start point for the next DREQ in edge sense mode Sensing start point for the next DREQ in continuous transfer mode B: Sensing start point for the next DREQ during single and block transfer in level sense mode Note: The timing from DREQ to DMA start reflects the case where this is performed close to top speed. 388 CHAPTER 17 DMA CONTROLLER (DMAC) 17.5 Transfer-Acceptance Signal Output and Transfer-End Signal Output Channels 0, 1 and 2 support a function for outputting the transfer-request-acceptance signal and transfer-end signal output from a pin. For the transfer-acceptance signal output, when accepting transfer request input from a pin for DMA transfer, the DMAC outputs the transfer-request-acceptance signal. For the transfer-end signal output accepting transfer request input from a pin for DMA transfer and ending the transfer with the DMACT counter set to 0, the DMAC outputs the transfer-end signal. ■ Transfer-acceptance Signal Output The transfer-request-acceptance signal is outputted as active-low pulses when transfer data is accessed. Using the AKSE2 to AKSE0 and AKDE2 to AKDE0 bits in DATCR, you can set whether to output that signal synchronously with transfer source access, transfer destination access, or both of transfer source access and transfer destination access. ■ Transfer-end Signal Output The transfer-end signal is outputted as active-low pulses when the final transfer data is accessed. Using the EPSE2 to EPSE0 and EPDE2 to EPDE0 bits in DATCR, you can set whether to output that signal synchronously with transfer source access, transfer destination access, or both of transfer source access and transfer destination access. 389 CHAPTER 17 DMA CONTROLLER (DMAC) 17.6 Notes on the DMA Controller This section provides notes on using the DMA controller. ■ Priority of Channels Once the DMAC is activated by a DMA transfer request over a channel, a DMA transfer request over another channel is not accepted and is held until the end of the current transfer. If requests over multiple channels are simultaneously active at detection of a DMA transfer request by the DMAC, which channel is to be accepted depends on the priority given below. (High) ch.0 --> ch.1 --> ch.2 --> ch.3 --> ch.4 --> ch.5 --> ch.6 --> ch.7 (Low) If requests over multiple channels are generated concurrently, the DMA transfer over one channel is executed, then bus control is returned to the CPU before performing DMA transfer over the next channel. ■ Notes on Using a Resource Interrupt Request as a DMA Transfer Request For DMA controller transfer, you must disable the interrupt levels via the appropriate interrupt controller. In contrast, for interrupt generation, you must disable the DMA controller operation enable bit in the DMA controller and set the interrupt level to a proper value. ■ Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt The FR family supports a function for terminating DMA transfer originating in a DMA transfer request when a higher-priority interrupt occurs. ❍ HRCL register You can terminate DMA transfer operation upon occurrence of an interrupt request by operating the HRCL register (hold request cancel level register) in the interrupt controller. If the interrupt level set in an interrupt request generated from a peripheral circuit is higher than that set in the HRCL register, DMAC DMA transfer operation is suppressed. With DMA transfer operation executed, the transfer operation is suspended at a breakpoint, and the bus right is given to the CPU. If the system is currently waiting for the generation of a DMA transfer request, a DMA transfer request is held when it is generated. After reset, the HRCL register is set to the lowest level (31). The DMA transfer operation is, therefore, suppressed against all interrupt requests. To operate DMA transfer even with an interrupt request generated, set the HRCL register to the required value. 390 CHAPTER 17 DMA CONTROLLER (DMAC) ❍ PDRR register The function for suppressing DMA transfer operation by setting the HRCL register is enabled only when an interrupt request of a higher priority is active. For example, when an interrupt request is cleared in the interrupt handler program, the suppression of DMA transfer by the HRCL register may be released, with the CPU losing the bus right. The clock control section supports a PDRR register to clear an interrupt request so that other interrupt requests may be accepted and to suppress DMA transfer operation. If you use the interrupt handler to load the PDRR with a value other than 0, DMA transfer operation is suppressed. To release the suppression of DMA transfer operation, load the PDRR with 0. ■ DMA Transfer Operation in Sleep Mode DMA transfer operation can not use during sleep mode. Before the CPU changes to sleep mode, the state of DMA transfer operation must be set to prohibition state. ■ Transfer Operation to DMAC Internal Register Do not specify a DMAC internal register as a transfer destination address. Table 17.6-1 lists the DMA transfer request sources. Table 17.6-1 Source for DMA Transfer Requests Channel number Description 0 External transfer request input pin DREQ0 1 External transfer request input pin DREQ1 2 External transfer request input pin DREQ2 3 PPG ch.0 4 Received over UART ch.0 5 Sent over UART ch.0 6 16-bit reload timer ch.0 7 A/D converter ❍ Error status in the DMAC transfer request source Only ch.4 can report the occurrence of an error in the DMA request source, by using the DER7 to DER0 bit in the DACSR. When a UART ch.0 reception interrupt is used as the DMA transfer request, the DER4 bit is set to 1 if any of the errors given below occurs. • Parity error • Overrun error • Framing error 391 CHAPTER 17 DMA CONTROLLER (DMAC) 17.7 Timing Charts for the DMA Controller This section covers timing charts for DMA controller operation. • Timing chart for the descriptor access section • Timing chart for the data transfer section • Timing chart for transfer termination in continuous transfer mode • Timing chart for transfer-end operation ■ Symbols Used in the Timing Charts Table 17.7-1 shows the symbols used in the timing charts. Table 17.7-1 Symbols Used in the Timing Charts Symbol #0 Descriptor No. 0 #0H Bit 31 to bit 16 in descriptor No. 0 #0L Bit 15 to bit 0 in descriptor No. 0 #1 Descriptor No. 1 #1H Bit 31 to bit 16 in descriptor No. 1 #1L Bit 15 to bit 0 in descriptor No. 1 #2 Descriptor No. 2 #2H Bit 31 to bit 16 in descriptor No. 2 #2L Bit 15 to bit 0 in descriptor No. 2 #1/2 Descriptor No. 1 or No. 2 (Depending on SCS1 and SCS0, and DCS1 and DCS0) #1/2H Bit 31 to bit 16 in descriptor No. 1 or No. 2 #1/2L Bit 15 to bit 0 in descriptor No. 1 or No. 2 S 392 Description Transfer source SH Bit 31 to bit 16 of the transfer source SL Bit 15 to bit 0 of the transfer source D Transfer destination DH Bit 31 to bit 16 of the transfer destination DL Bit 15 to bit 0 of the transfer destination CHAPTER 17 DMA CONTROLLER (DMAC) 17.7.1 Timing Charts for the Descriptor Access Section This section covers the timing charts for the descriptor access section. ■ Descriptor Access Section ❍ Request pin input mode: Level, Descriptor address: External (A) CLK DREQ2 to DREQ0 Addr pin Data pin #0H #0L #1H #0L #0H #1H #1L #1L #2H #2H #2L #2L S S RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 ❍ Request pin input mode: Level, Descriptor address: Internal (A) Internal KB CLK DREQ2 to DREQ0 Addr pin Data pin S S RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 393 CHAPTER 17 DMA CONTROLLER (DMAC) ❍ Request pin input mode: Edge, Descriptor address: External (A) CLK DREQ2 to DREQ0 Addr pin #0H Data pin #0L #0H #1H #0L #1H #1L #1L #2H #2H #2L #2L S S RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 ❍ Request pin input mode: Edge, Descriptor address: Internal (A) CLK DREQ2 to DREQ0 Addr pin S Data pin S RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 Note: For the part from DREQn generation to the start of DMAC operation, only the conditions for the fastest case are covered. The actual start of the DMAC operation may be delayed owing to bus contention originating in CPU instruction fetching and data access. 394 CHAPTER 17 DMA CONTROLLER (DMAC) 17.7.2 Timing Charts for the Data Transfer Section This section covers timing charts for the data transfer section. ■ Data Transfer Section, 16/8-bit Data ❍ Transfer source area: External, Transfer destination area: External (A) CLK DREQ2 to DREQ0 Addr pin #2 Data pin S #2 D S S D D S S D D S S D D S D RD WR0, WR1 W W W DACK2 to DACK0 DEOP2 to DEOP0 ❍ Transfer source area: External, Transfer destination area: Internal RAM (A) CLK DREQ2 to DREQ0 Addr pin #2 Data pin S #2 S S S S S S S RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 ❍ Transfer source area: Internal RAM, Transfer destination area: External (A) CLK DREQ2 to DREQ0 Addr pin Data pin #2 #2 D D D D D D D D W W W W RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 395 CHAPTER 17 DMA CONTROLLER (DMAC) 17.7.3 Timing Charts for Transfer Termination in Continuous Transfer Mode This section covers timing charts for transfer termination in continuous transfer mode. ■ Transfer Termination in Continuous Transfer Mode (When Either address is Fixed), 16/8-bit Data ❍ Transfer source area: External, Transfer destination area: External CLK DREQ2 to DREQ0 Addr pin D Data pin D S S D #0H #1/2H #1/2L D #0H #1/2H #1/2L W W W W RD WR0, WR1 W DACK2 to DACK0 DEOP2 to DEOP0 ❍ Transfer source area: External, Transfer destination area: Internal RAM CLK DREQ2 to DREQ0 Addr pin S Data pin S S S #0H #1/2H #1/2L #0H #1/2H #1/2L W W W RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 ❍ Transfer source area: Internal RAM, Transfer destination area: External CLK DREQ2 to DREQ0 Addr pin D D D #0H #1/2H #1/2L Data pin D D D #0H #1/2H #1/2L W W W W W W RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 396 CHAPTER 17 DMA CONTROLLER (DMAC) ■ Transfer Termination in Continuous Transfer Mode (When both Addresses are Changed), 16/8-bit Data ❍ Transfer source area: External, Transfer destination area: External CLK DREQ2 to DREQ0 Addr pin D Data pin S D #0H #1H #1L #2H #2L D #0H #1H #1L #2H #2L W W W W W W D S RD WR0, WR1 W DACK2 to DACK0 DEOP2 to DEOP0 ❍ Transfer source area: External, Transfer destination area: Internal RAM CLK DREQ2 to DREQ0 Addr pin S Data pin S S S #0H #1H #1L #2H #2L #0H #1H #1L #2H #2L W W W W W RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 ❍ Transfer source area: Internal RAM, Transfer destination area: External CLK DREQ2 to DREQ0 Addr pin D D D #0H #1H #1L #2H #2L Data pin D D D #0H #1H #1L #2H #2L W W W W W W W W RD WR0, WR1 DACK2 to DACK0 DEOP2 to DEOP0 397 CHAPTER 17 DMA CONTROLLER (DMAC) 17.7.4 Timing Charts for the Transfer Termination Operation This section covers timing charts for the transfer termination operation. ■ Transfer Termination Operation (When Either address is Fixed) ❍ Bus width: 16 bits, Data length: 8/16 bits CLK Addr pin D Data pin D S S D S S D D #0H #1/2H #1/2L D #0H #1/2H #1/2L W W W W RD W WR0, WR1 W AKSE2 to AKSE0 = 1 DACK AKDE2 to AKDE0 = 1 Both = 1 EPSE2 to AKDE0 = 1 DEOP EPDE2 to AKDE0 = 1 Both = 1 ❍ Bus width: 16 bits, Data length: 32 bits CLK Addr pin SH Data pin SH SL SL D DL D DL W W SH SH SL SL D DL #0H #1/2H #1/2L D DL #0H #1/2H #1/2L W W W W W RD WR0, WR1 AKSE1 to AKSE2 = 1 DACK AKDE1 to AKDE2 = 1 Both = 1 EPSE1 to EPSE2 = 1 DEOP EPDE1 to EPDE2 = 1 Both = 1 398 CHAPTER 17 DMA CONTROLLER (DMAC) ■ Transfer Termination Operation (When both Addresses are Changed) ❍ Bus width: 16 bits, Data length: 8/16 bits CLK Addr pin D Data pin D D S S D S S D #0H #1H #1L #2H #2L D #0H #1H #1L #2H #2L W W W W W W RD WR0, WR1 W W AKSE1 to AKSE2 = 1 DACK AKDE1 to AKDE2 = 1 Both = 1 EPSE1 to EPSE2 = 1 DEOP EPDE1 to EPDE2 = 1 Both = 1 ❍ Bus width: 16 bits, Data length: 32 bits CLK Addr pin SH Data pin SL SH SL D DL D DL W W SH SH SL SL D DL #0H #1H #1L D DL #0H #1H #1L W W W W W RD WR0, WR1 AKSE1 to AKSE2 = 1 DACK AKDE1 to AKDE2 = 1 Both = 1 EPSE1 to EPSE2 = 1 DEOP EPDE1 to EPDE2 = 1 Both = 1 CLK Addr pin #2H #2L Data pin #2H #2L W W RD WR0, WR1 399 CHAPTER 17 DMA CONTROLLER (DMAC) 400 CHAPTER 18 BIT-SEARCH MODULE This chapter describes the bit-search module, the register configuration and functions, and the operation of the bit-search module. 18.1 Overview of the Bit-Search Module 18.2 Registers of the Bit-Search Module 18.3 Operation of the Bit-Search Module and Save/Return Processing 401 CHAPTER 18 BIT-SEARCH MODULE 18.1 Overview of the Bit-Search Module This module searches for 0 or 1, or for changes in bit values in response to data loaded into the input register and returns the bit position at which the respective behavior was detected. ■ Block Diagram of the Bit-search Module Figure 18.1-1 shows a block diagram of the bit-search module. Figure 18.1-1 Block Diagram of the Bit-search Module D-bus Input latch Address decoder Detection mode 1 detection register Bit-search circuit Result of search ■ Registers of the Bit-search Module Figure 18.1-2 shows the bit search module registers. Figure 18.1-2 Registers of the Bit-search Module 31 0 Address: 0003F0H BSD0 0 detection data register Address: 0003F4H BSD1 1 detection data register Address: 0003F8H BSDC Change point detection data register Address: 0003FCH BSRR Detection result register 402 CHAPTER 18 BIT-SEARCH MODULE 18.2 Registers of the Bit-Search Module The bit-search module registers include the following four: • 0-detection data register (BSD0) • 1-detection data register (BSD1) • Change point detection data register (BSDC) • Detection result register (BSRR) ■ 0 Detection Data Register (BSD0) The register configuration of the 0 detection data register (BSD0) is given below. 31 0 0003F0H Read/write Initial value Write only Undefined 0 detection is performed for a written value. The initial value of this register upon reset is undefined. The read value is undefined. Use the 32-bit data transfer instruction to transfer data. (Do not use the 8-bit and 16-bit data transfer instructions.) ■ 1 Detection Data Register (BSD1) The register configuration of the 1 detection data register (BSD1) is given below. 31 0 0003F4H Read/write Initial value Can be read and written Undefined Use the 32-bit data transfer instruction to transfer data. (Do not use the 8-bit or 16-bit data transfer instructions.) 403 CHAPTER 18 BIT-SEARCH MODULE ❍ Writing 1 detection is performed for a written value. ❍ Reading Data for saving the internal status of the bit-search module is read. This function is used to save and return the original status when e.g. the interrupt handler uses the bit-search module. The original status can be saved and returned based on the 1 detection data register even if data has been loaded into the 0 detection or change point detection data register. The initial value of this register upon reset is undefined. ■ Value Change Detection Data Register (BSDC) The register configuration of the change point detection data register (BSDC) is given below. 31 0 0003F8H Read/write Initial value Write only Undefined Change point detection is performed for a written value. The initial value of this register upon reset is undefined. The read value is undefined. Use the 32-bit data transfer instruction to transfer data. (Do not use the 8-bit and 16-bit data transfer instructions.) ■ Detection Result Register (BSRR) The register configuration of the detection result register (BSRR) is given below. 31 0003FCH Read/write Initial value Read only Undefined This register reads the result of 0, 1 or change point detection. What detection result is read depends on the data register last loaded. 404 0 CHAPTER 18 BIT-SEARCH MODULE 18.3 Operation of the Bit-Search Module and Save/Return Processing This section explains the operation of 0 detection, 1 detection, and change point detection for bit search module and the save/return processing. ■ 0 Detection Data loaded in the 0 detection data register is scanned from the MSB to the LSB, and the position at which the first 0 is detected is returned. The result of detection is obtained by unloading the detection result register. Table 18.3-1 shows the relationship between detected positions and return values. If the data contains no 0 (i.e., the value is FFFFFFFFH), a value of 32 is returned as the search result. [Example of execution] Written data 11111111111111111111000000000000B 11111000010010011110000010101010B 10000000000000101010101010101010B 11111111111111111111111111111111B Read value (In decimal notation) (FFFFF000H) (F849E0AAH) (8002AAAAH) (FFFFFFFFH) 20 5 1 32 ■ 1 Detection Data written in the 1 detection data register is scanned from the MSB to the LSB, and the position at which first 1 is detected is returned. The result of detection is obtained by unloading the detection result register. Table 18.3-1 shows the relationship between detected positions and return values. If the data contains no 1 (i.e., the value is 00000000H), a value of 32 is returned as the search result. [Example of execution] Written data 00100000000000000000000000000000B 00000001001000110100010101100111B 00000000000000111111111111111111B 00000000000000000000000000000001B 00000000000000000000000000000000B Read value (In decimal notation) (20000000H) (01234567H) (0003FFFFH) (00000001H) (00000000H) 2 7 14 31 32 405 CHAPTER 18 BIT-SEARCH MODULE ■ Change Point Detection Data loaded into the change point detection data register is scanned from bit 30 to the LSB for comparison against the MSB value. The position at which a value different from the MSB is detected first is returned. The result of detection is obtained by unloading the detection result register. Table 18.3-1 shows the positions of detection and their corresponding return values. If no change point occurred, a value of 32 is returned. During change point detection, the value 0 is not returned as result. [Example of execution] Written data Read value (In decimal notation) 00100000000000000000000000000000B 00000001001000110100010101100111B 00000000000000111111111111111111B 00000000000000000000000000000001B 00000000000000000000000000000000B 11111111111111111111000000000000B 11111000010010011110000010101010B 10000000000000101010101010101010B 11111111111111111111111111111111B (20000000H) (01234567H) (0003FFFFH) (00000001H) (00000000H) (FFFFF000H) (F849E0AAH) (8002AAAAH) (FFFFFFFFH) 2 7 14 31 32 20 5 1 32 Table 18.3-1 Bit Positions and Return Values (Decimal) Detected bit position Return value Detected bit position Return value Detected bit position Return value Detected bit position Return value 31 0 23 8 15 16 7 24 30 1 22 9 14 17 6 25 29 2 21 10 13 18 5 26 28 3 20 11 12 19 4 27 27 4 19 12 11 20 3 28 26 5 18 13 10 21 2 29 25 6 17 14 9 22 1 30 24 7 16 15 8 23 0 31 Non existent 32 406 CHAPTER 18 BIT-SEARCH MODULE ■ Processing for Saving and Restoring If you must save and restore the internal status of the bit-search module owing to use of the bitsearch module in the interrupt handler, follow the procedure below. 1. Unload the detection data register, and save the read contents. (Save) 2. Use the bit-search module. 3. Load the 1 detection data register with the data saved in step 1. (Restore) The value obtained by the above operations when the detection result register is unloaded next depends on the contents written to the bit-search module before step "1". Even if the data register for which the last load operation is performed was the one for which zero or a change point was detected, the above procedure provides the correct return. 407 CHAPTER 18 BIT-SEARCH MODULE 408 CHAPTER 19 PERIPHERAL STOP CONTROL This chapter provides an overview of peripheral stop control and explains the configuration and the function of registers. 19.1 Overview of Peripheral Stop Control 19.2 Peripheral Stop Control Registers 409 CHAPTER 19 PERIPHERAL STOP CONTROL 19.1 Overview of Peripheral Stop Control The peripheral stop control stops the clocks for unused resources, which reduces power consumption. ■ Peripheral Stop Control Registers Figure 19.1-1 lists the peripheral stop control registers. Figure 19.1-1 Peripheral Stop Control Registers Address bit7……………………… bit0 000090H STPR0 000091H STPR1 000092H STPR2 ■ Operation of Peripheral Stop Control and Applicable Notes The clock for the resource corresponding to each bit can be stopped. Operation of a resource whose clock is stopped cannot be started. Do not access the register for a resource whose operation has been stopped. Do not use this function to stop the operation of a resource that is currently in use. 410 CHAPTER 19 PERIPHERAL STOP CONTROL 19.2 Peripheral Stop Control Registers The peripheral stop control registers include the following three: • Stop control register 0 (STPR0) • Stop control register 1 (STPR1) • Stop control register 2 (STPR2) ■ Stop Control Register 0 (STPR0) Stop control register 0 (STPR0) has the following bit configuration: Address bit7 bit6 bit5 bit4 000090H ST07 ST06 ST05 ST04 bit3 bit2 bit1 bit0 Initial value 0000----B (R/W) [bit 7] ST07 0 Enables UART0 operation. 1 Disables UART0 operation. [bit 6] ST06 0 Enables UART1 operation. 1 Disables UART1 operation. [bit 5] ST05 0 Enables UART2 operation. 1 Disables UART2 operation. [bit 4] ST04 0 Enables UART3 operation. 1 Disables UART3 operation. 411 CHAPTER 19 PERIPHERAL STOP CONTROL ■ Stop Control Register 1 (STPR1) Stop control register 1 (STPR1) has the following bit configuration: Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000091H ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 [bit 7] ST17 0 Enables reload timer 0 operation. 1 Disables reload timer 0 operation. [bit 6] ST16 0 Enables reload timer 1 operation. 1 Disables reload timer 1 operation. [bit 5] ST15 0 Enables reload timer 2 operation. 1 Disables reload timer 2 operation. [bit 4] ST14 0 Enables reload timer 3 operation. 1 Disables reload timer 3 operation. [bit 3] ST13 0 Enables the free-run timer operation. 1 Disables the free-run timer operation. [bit 2] ST12 0 Enables I2C operation. 1 Disables I2C operation. [bit 1] ST11 0 Enables up/down counter operation. 1 Disables up/down counter operation. [bit 0] ST10 412 0 Enables A/D converter operation. 1 Disables A/D converter operation. Initial value 00000000B (R/W) CHAPTER 19 PERIPHERAL STOP CONTROL ■ Stop Control Register 2 (STPR2) Stop control register 2 (STPR2) has the following bit configuration: Address bit7 bit6 bit5 bit4 bit3 bit2 000092H ST27 ST26 ST25 ST24 ST23 ST22 bit1 bit0 Initial value 000000- -B (R/W) [bit 7] ST27 0 Enables PPG0 operation. 1 Disables PPG0 operation. [bit 6] ST26 0 Enables PPG1 operation. 1 Disables PPG1 operation. [bit 5] ST25 0 Enables PPG2 operation. 1 Disables PPG2 operation. [bit 4] ST24 0 Enables PPG3 operation. 1 Disables PPG3 operation. [bit 3] ST23 0 Enables PPG4 operation. 1 Disables PPG4 operation. [bit 2] ST22 0 Enables PPG5 operation. 1 Disables PPG5 operation. 413 CHAPTER 19 PERIPHERAL STOP CONTROL 414 CHAPTER 20 CALENDAR MACROS This chapter provides an overview of the calendar macros and explains the configuration and functions of registers and the operation of calendar macros. 20.1 Overview of Calendar Macros 20.2 Registers of Calendar Macros 20.3 Operation of Calendar Macros 415 CHAPTER 20 CALENDAR MACROS 20.1 Overview of Calendar Macros The calendar macros use a basic clock frequency of 32.768 kHz. These macros have clock functions for years, months, days, hours, minutes, seconds, days of the week, and leap years. For the year, the lower 2 digits of the year, 0 to 99, are counted. ■ Block Diagram of Calendar Macros Figure 20.1-1 is a block diagram that applies to each calendar macro. Figure 20.1-1 Block Diagram of Calendar Macros Oscillator Calendar circuit Bus control D-bus 32kHz ■ Registers of Calendar Macros Figure 20.1-2 lists the calendar macro registers. Figure 20.1-2 Calendar Macro Registers 416 Address 000210H RST - - - - - MD1 MD0 CAC register Address 000211H - - S5 S4 S3 S2 S1 S0 CA1 register Address 000212H - - M5 M4 M3 M2 M1 M0 CA2 register Address 000213H - - - H4 H3 H2 H1 H0 CA3 register Address 000214H - - - DA4 DA3 DA2 DA1 DA0 CA4 register Address 000215H - - - - - W2 W1 W0 CA5 register Address 000216H - - - - MN3 MN2 MN1 MN0 CA6 register Address 000217H - Y6 Y5 Y4 Y3 Y2 Y1 Y0 CA7 register Address 00021FH TST - - - - - TST CAS register CHAPTER 20 CALENDAR MACROS 20.2 Registers of Calendar Macros The calendar macro registers include the following nine: • Calendar block read/write control register (CAC) • Second data register (CA1) • Minute data register (CA2) • Hour data register (CA3) • Day data register (CA4) • Day-of-the-week data register (CA5) • Month data register (CA6) • Year data register (CA7) • Calendar test register (CAS) ■ Calendar Block Read/Write Control Register (CAC) The calendar block read/write control register (CAC) has the following bit configuration: CAC 7 bit RST 6 bit - 5 bit - 4 bit - 3 bit - 2 bit - 1 bit MD1 0 bit MD0 Initial value 00000000B [R/W] [bit 7] RST This bit initializes the calendar control circuit. The calendar control circuit is initialized by writing 1. CA1-7 and the counter are not initialized. [bit 6 to bit 2] Reserved These bits are a reserved bit that must be set to 0. [bit 1, bit 0] MD1 and MD0 mode setting bits MD1 MD0 Mode 0 0 Normal count operation 0 1 Read mode 1 0 Write mode 1 1 Prohibited 417 CHAPTER 20 CALENDAR MACROS ■ Second Data Register (CA1) The second data register (CA1) has the following bit configuration: CA1 7 bit - 6 bit - 5 bit S5 4 bit S4 3 bit S3 2 bit S2 1 bit S1 0 bit S0 Initial value --XXXXXXB [R/W] [bit 7, bit 6] Reserved These bits are reserved. Writing to these bits is ignored. [bit 5 to bit 0] S5 to S0 These bits indicate second data. They indicate a binary value from 0 to 59. ■ Minute Data Register (CA2) The minute data register (CA2) has the following bit configuration: CA2 7 bit - 6 bit - 5 bit M5 4 bit M4 3 bit M3 2 bit M2 1 bit M1 0 bit M0 Initial value --XXXXXXB [R/W] [bit 7, bit 6] Reserved These bits are reserved. Writing to these bits is ignored. [bit 5 to bit 0] M5 to M0 These bits indicate minute data. They indicate a binary value from 0 to 59. ■ Hour Data Register (CA3) The hour data register (CA3) has the following bit configuration: CA3 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit - - - H4 H3 H2 H1 H0 Initial value ---XXXXXB [bit 7 to bit 5] Reserved These bits are reserved. Writing to these bits is ignored. [bit 4 to bit 0] H4 to H0 These bits indicate hour data. They indicate a binary value from 0 to 23. 418 [R/W] CHAPTER 20 CALENDAR MACROS ■ Day Data Register (CA4) The day data register (CA4) has the following bit configuration: CA4 7 bit - 6 bit - 5 bit - 4 bit DA4 3 bit DA3 2 bit DA2 1 bit DA1 0 bit DA0 Initial value ---XXXXXB [R/W] [bit 7 to bit 5] Reserved These bits are reserved. Writing to these bits is ignored. [bit 4 to bit 0] DA4 to DA0 These bits indicate day data. They indicate a binary value from 0 to 31. ■ Day-of-the-week Data Register (CA5) The day-of-the-week data register (CA5) has the following bit configuration: CA5 7 bit - 6 bit - 5 bit - 4 bit - 3 bit - 2 bit W2 1 bit W1 0 bit W0 Initial value -----XXXB [R/W] [bit 7 to bit 3] Reserved These bits are reserved. Writing to these bits is ignored. [bit 2 to bit 0] W2 to W0 These bits indicate day-of-the week data. They indicate a binary value from 0 to 6. ■ Month Data Register (CA6) The month data register (CA6) has the following bit configuration: CA6 7 bit - 6 bit - 5 bit - 4 bit - 3 bit MN3 2 bit MN2 1 bit MN1 0 bit MN0 Initial value ----XXXXB [R/W] [bit 7 to bit 4] Reserved These bits are reserved. Writing to these bits is ignored. [bit 3 to bit 0] MN3 to MN0 These bits indicate month data. They indicate a binary value from 1 to 12. 419 CHAPTER 20 CALENDAR MACROS ■ Year Data Register (CA7) The year data register (CA7) has the following bit configuration: CA7 7 bit - 6 bit Y6 5 bit Y5 4 bit Y4 3 bit Y3 2 bit Y2 1 bit Y1 0 bit Y0 Initial value -XXXXXXXB [R/W] [bit 7] Reserved This bit is reserved. Writing to this bit is ignored. [bit 6 to bit 0] Y6 to Y0 These bits indicate year data. They indicate a binary value from 0 to 99. ■ Calendar Test Register (CAS) The calendar test register (CAS) has the following bit configuration: CAS 7 bit TST 6 bit - 5 bit - 4 bit - 3 bit - 2 bit - 1 bit - 0 bit TST [bit 7, bit 0] TST This bit is a TST bit. Be sure to set this bit to 0. [bit 6 to bit 1] Reserved These bits are a reserved bit. Writing to these bits is ignored. 420 Initial value 0------0B [R/W] CHAPTER 20 CALENDAR MACROS 20.3 Operation of Calendar Macros This section describes the reset of calendar macros for initialization and explains how to set and read calendar values. ■ Initialization Reset Only the CAC and CAS registers can be initialized by a normal reset (CPU reset signal, such as reset by RST pin). To initialize the calendar circuit, the control system must be reset by setting the CAC register to 80H in a writing operation. CA1-7 and the counter are not reset in this case. ■ Setting Calendar Values Before setting a calendar value, Write mode (CAC register MD1 = 1, CAC register MD0 = 0) must be selected. Because the counter continues to run in Write mode, the contents of the counter cannot be written directly. After setting the contents of the registers (CA1-7), control returns to normal mode (CAC register D2 = 0). In this case, the register value for a normal return is loaded into the counter, which continues to run. Notes: • The counter continues to run during Write operation. Counting stops only when data is written to the CA1 register. When data is written to CA1, the counter starts from 0 when control returns to normal mode. • When the power fails in Write mode or during the four CPU cycles after Write mode ends, the data may become invalid. • A wait period of one CPU cycle is required to enter Write mode again after Write mode has been released. • Do not write values into the registers CA1 to CA7 that would exceed the respective maximum count value. ■ Reading Calendar Values Before reading any calendar value, select Read mode (CAC register MD1 = 0, CAC register MD0 = 1). When Read mode is selected, the current counter value is loaded into the respective internal register (CA1 to CA7) and remains fixed. Because the contents of the internal registers will be read back later on, the counter continues to run. 421 CHAPTER 20 CALENDAR MACROS Note: Unless a time of at least 35 µs is provided from when Read mode ends until Read mode is entered the next time, the values to be read might not have changed. 422 CHAPTER 21 FLASH MEMORY This chapter describes the flash memory of this device, its operation, as well as the configuration and functions of the flash memory registers. 21.1 Overview of Flash Memory 21.2 Flash Memory Registers 21.3 Flash Memory Operation 21.4 Automatic Algorithm of Flash Memory 21.5 Checking the Automatic Algorithm Execution Status 21.6 Writing and Erasing Flash Memory 423 CHAPTER 21 FLASH MEMORY 21.1 Overview of Flash Memory MB91FV150 and MB91F155A have a 510 Kbyte memory(4Mbit). These use a flash memory that supports to batch-erase all sectors with the 3-V single power supply, erase in units of sectors and write in half word (16 bits) units with the FR-CPU. ■ Overview of Flash Memory The flash memory in this device is a internal flash memory operating on 3 V. This flash memory is the same as the Fujitsu 2 megabit (512 Kbyte x 8 / 256 Kbyte x 16) flash memory MBM29LV400C except for a slight difference in the sector configuration. Writing to this flash memory from an external device with a ROM writer is also supported. In addition to the functions that are equivalent to those of the MBM29LV400C, when this flash memory is used as the internal ROM of the FR-CPU, data and instructions can also be read in word (32 bits) units. This enables high-speed device operation. Also see the MBM29LV400C Data Sheet supplied with this manual. In the MB91FV150 and MB91F155A, the following functions are implemented by combining flash memory macros with FR-CPU interface circuits: • • CPU program/data storage memory function • When this flash memory is used as ROM, 32-bit access is supported. • Read, write, and erase (automatic program algorithm(*)) via the CPU are supported. Functions equivalent to those of the MBM29LV400C (single flash memory product) • Read, write, and erase (automatic program algorithm(*)) via ROM writer are supported. This section describes how to use this flash memory from the FR-CPU. For details on how to use this flash memory from the ROM writer, see the separate ROM Writer User’s Guide. *: Automatic program algorithm = Embedded AlgorithmTM Embedded AlgorithmTM is a trademark of Advanced Micro Devices Corporation. 424 CHAPTER 21 FLASH MEMORY ■ Block Diagram of the Flash Memory Figure 21.1-1 is a block diagram of the flash memory. Figure 21.1-1 Block Diagram of the Flash Memory Rising edge detection Control signal generation RDY/BUSY RESET BYTE OE Flash memory INTE RDYINT RDY WE Bus control signal Interrupt request WE CE FA18-0 DI15-0 Address buffer DO31-0 Data buffer CA18-0 CD31-0 FR-C bus (instructions/data) ■ Memory Map Flash memory address mapping depends on whether flash memory mode or CPU mode is used. The memory map in each mode is shown below. ❍ Memory map in flash memory mode for MB91FV150 and MB91F155A Figure 21.1-2 shows the memory map in flash memory mode for MB91FV150 and MB91F155A. Figure 21.1-2 Memory Map in Flash Memory Mode for MB91FV150 and MB91F155A 0FFFFFH SA13 SA12 FLASH memory image SA11 SA10 SA9 SA8 07FFFFH SA7 SA6 SA5 SA4 SA3 010000H SA2 SA1 SA0 000000H (SAn: sector address n) FLASH memory mode 425 CHAPTER 21 FLASH MEMORY ❍ Memory map in CPU mode for MB91FV150 and MB91F155A Figure 21.1-3 shows the memory map in CPU mode for MB91FV150 and MB91F155A. Figure 21.1-3 Memory Map in CPU Mode for MB91FV150 and MB91F155A 0FFFFFH 0FFFFFH SA6 SA13 SA5 SA12 SA4 SA11 SA3 SA10 SA2 SA9 SA1 SA8 SA0 SA7 0F8000H 0F4000H FLASH memory area 0F0000H 0E0000H 080800H RAM area 2 KB 0C0000H 080000H 0A0000H 0007C0H Status register 080800H 000000H 080000H (SAn : sector address n) CPU mode ■ Sector Address Table Table 21.1-1 lists the sector addresses of the flash memory. Table 21.1-1 Sector address Table of the Flash Memory Sector address 426 Address range Corresponding bit position Sector capacity SA7 080802,3H to 09FFFE,FH (16 bits from the LSB side) Bit 15 to bit 0 64K byte SA8 0A0002,3H to 0BFFFE,FH (16 bits from the LSB side) Bit 15 to bit 0 64K byte SA9 0C0002,3H to 0DFFFE,FH (16 bits from the LSB side) Bit 15 to bit 0 64K byte SA10 0E0002,3H to 0EFFFE,FH (16 bits from the LSB side) Bit 15 to bit 0 32K byte SA11 0F0002,3H to 0F3FFE,FH (16 bits from the LSB side) Bit 15 to bit 0 8K byte SA12 0F4002,3H to 0F7FFE,FH (16 bits from the LSB side) Bit 15 to bit 0 8K byte SA13 0F8002,3H to 0FFFFE,FH (16 bits from the LSB side) Bit 15 to bit 0 16K byte SA0 080800,1H to 09FFFC,DH (16 bits from the MSB side) Bit 31 to s16 64K byte SA1 0A0000,1H to 0BFFFC,DH (16 bits from the MSB side) Bit 31 to s16 64K byte SA2 0C0000,1H to 0DFFFC,DH (16 bits from the MSB side) Bit 31 to s16 64K byte SA3 0E0000,1H to 0EFFFC,DH (16 bits from the MSB side) Bit 31 to s16 32K byte SA4 0F0000,1H to 0F3FFC,DH (16 bits from the MSB side) Bit 31 to s16 8K byte SA5 0F4000,1H to 0F7FFC,DH (16 bits from the MSB side) Bit 31 to s16 8K byte SA6 0F8000,1H to 0FFFFC,DH (16 bits from the MSB side) Bit 31 to s16 16K byte CHAPTER 21 FLASH MEMORY 21.2 Flash Memory Registers Flash memory has a status register (FLCR) and a wait register (FWTC). ■ Status Register (FLCR) (CPU Mode) Register indicating the operating status of the flash memory. The FLCR controls CPU interrupts and writing to the flash memory. The FLCR can be accessed only in CPU mode. Do not access the FLCR with a read modify write instruction. The structure of the FLCR (CPU mode) is as follows: 0007C0H bit 7 bit 6 bit 5 bit 4 INTE RDYINT WE RDY R/W (0) R/W (0) R (X) R/W (0) bit 3 bit 2 bit 1 bit 0 LPM (X) (X) (X) R/W (0) [bit 7]: INTE (INTerrupt Enable) Bit 7 is used to control the automatic algorithm (e.g., write and erase) termination interrupt output of the flash memory. 0 Disables automatic algorithm termination interrupt output. 1 Enables automatic algorithm termination interrupt output. • At reset, this bit is initialized to 0. • This bit can both be read and written. [bit 6]: RDYINT (Ready interrupt) Bit 6 is set to 1 when the automatic algorithm (e.g., write and erase) of the flash memory terminates. If this bit is set to 1 when bit 7 (INTE) is 1, an automatic algorithm termination interrupt request is issued 0 Automatic algorithm termination was not detected. 1 Automatic algorithm termination was detected. • At reset, this bit is initialized to 0. • This bit can both be read and written. However, it can only be set to 0. The value of this bit remains unchanged even there is an attempt to set it to 1. 427 CHAPTER 21 FLASH MEMORY Note: FLCR and the 16-bit free-run timer share the interrupt sources shown in the table below. Interrupt No. Interrupt source In decimal notation In hexadecimal notation 62 3E 16-bit free-run timer/ flash Interrupt level Offset TBR default address ICR46 304H 000FFF04H [bit 5]: WE (Write enable) Bit 5 is used to control writing of data or commands to the flash memory in CPU mode. When this bit is 0, all data/command writing to the flash memory is disabled and the speed at which data is read from the flash memory is doubled (32-bit access) compared to when this bit is 1. When this bit is 1, writing of data/commands to flash memory is enabled, making it possible to start automatic algorithm. However, the speed at which data is read from the flash memory is slower (16-bit access) compared to when this bit is 0. Be sure to verify that the automatic algorithm (e.g., write and erase) is stopped in accordance with the RDY bit before rewriting the value of this bit. When the RDY bit is 0, the value of this bit cannot be rewritten. In flash memory mode, writing is enabled regardless of the status for this bit. 0 Writing to flash memory is disabled and the speed at which data is read from the flash memory is twice that as when this bit is 1. 1 Writing the flash memory is enabled and the speed at which data is read from the flash memory is slower than when this bit is 0. • At reset, this bit is initialized to 0. • This bit can both be read and written. [bit 4]: RDY (Ready) Bit 4 is used to indicate the operating status of the automatic algorithm (e.g., write and erase). When this bit is 0, new data cannot be written and the erase command is not accepted because data is being written or erased by the automatic algorithm. Also, data cannot be read from the flash memory addresses. The read data indicates the flash memory status. 428 0 Data cannot be read and write and erase commands are not accepted while data is being written or erased. 1 Data can be read and write and erase commands can be accepted. • At reset, this bit is not initialized (processing of this bit conforms to the status of the flash memory at that point of time). • This is a read-only bit. Write operations do not affect the value of this bit. CHAPTER 21 FLASH MEMORY [bit 3, bit 2, and bit 1]: Reserved bits In write operations, be sure to set these bits to 0. [bit 0]: LPM (Low power mode) Bit 0 is used to enable the function for decreasing power consumption other than flash access during low-speed operation. Setting this bit to 1 prevents the flash memory circuit from being started when the address is changed. Use the function of this bit only when the CPU operating frequency is less than or equal to 10 MHz. 0 Normal status. CE output becomes L regardless of whether flash memory is accessed. [Initial value] 1 CE output becomes L only when flash memory is accessed. • At reset, this bit is initialized to 0. • This bit can both be read and written. Wait register (FWTC) FWTC controls flash memory wait in CPU mode. It also controls high-speed read (33 MHz operation) access of flash memory. The configuration of the FWTC is as follows: bit 7 bit 6 bit 5 bit 4 bit 3 0007C4H ( ) ( ) ( ) ( ) ( ) bit 2 bit 1 bit 0 FACH WTC1 WTC0 W (0) R/W (0) R/W (0) [bit 1 and bit 0]: WTC1 and WTC0 Bit 1 and bit 0 are used to control flash memory wait. - 00: +0 wait, 2 cycles [initial value] - 01: Cannot be used. - 10: Cannot be used. - 11: Cannot be used. [bit 2]: FACH Bit 2 is used to control the flash macro read speed. - 0: Reads flash macro at normal speed. - 1: Reads flash macros at high speed (used in 33-MHz operation). 429 CHAPTER 21 FLASH MEMORY 21.3 Flash Memory Operation MB91150 provides the following two modes for accessing flash memory via the FRCPU: • FR-CPU ROM mode In this mode, word data (32 bits) can be collectively read but cannot be written. • FR-CPU programming mode In this mode, access to word data (32 bits) is inhibited but half word data (16 bits) can be written. ■ FR-CPU ROM Mode (32 Bits, Read Only) In this mode, the flash memory functions as the internal ROM of the FR-CPU. In this mode, word data (32 bits) can be collectively read, but data cannot be written to flash memory and automatic algorithms cannot be activated. ❍ Mode specification method • When the WE bit of the flash memory status register (FLCR) is set to 0, the MB91150 enters FR-CPU ROM mode. • When the CPU is in operation, MB91150 always enters FR-CPU ROM mode after reset has been released. • When the CPU is not in operation, MB91150 cannot enter FR-CPU ROM mode. ❍ Description of operation • When the flash memory area is read, word data (32 bits) is collectively read from the memory. • The number of cycles required to read data is 2 cycles per word (1 wait). This enables instructions to be supplied to the FR-CPU without wait. ❍ Restrictions 430 • The addressing method and endian mode used when the ROM writer writes data to flash memory differ from those used in FR-CPU ROM mode. • In FR-CPU ROM mode, commands and data cannot be written to flash memory. CHAPTER 21 FLASH MEMORY ■ FR-CPU Programming Mode (16 Bits, Read/Write) In this mode, data can be erased and written. Word data (32 bits) cannot be collectively accessed; when the MB91150 is operating in this mode, programs in flash memory cannot be executed. ❍ Mode specification method • When the WE bit of the flash memory status register (FLCR) is set to 1, the MB91150 enters FR-CPU programming mode. • When the CPU is in operation, the WE bit is kept at 0 after reset has been released. To set FR-CPU programming mode, set the WE bit to 1. When the WE bit is again set to 0 or when the WE bit is set to 0 because of a reset, the FR-CPU programming mode switches to FRCPU ROM mode. • When the RDY bit of the FLCR is 0, the value of the WE bit cannot be rewritten. Rewrite the value of the WE bit after verifying that the RDY bit is 1. ❍ Description of operation • When reading the flash memory area, half word data (16 bits) is collectively read from memory. The number of cycles required to read data is 2 cycles per half word (1 wait). • Automatic algorithms can be activated by writing commands to the flash memory. This activation enables data to be erased from and written to flash memory. For details on the automatic algorithm, see the section that describes the automatic algorithm. ❍ Restrictions • The addressing method and endian mode used when the ROM writer writes data to flash memory differ from those used in FR-CPU programming mode. • In FR-CPU programming mode, word data (32 bits) cannot be read. ■ Execution Status of Automatic Algorithm When an automatic algorithm is activated in FR-CPU programming mode, the operating status of the automatic algorithm can be identified by the internal ready/busy signal (RDY/BUSYX). The level of this ready/busy signal can be determined from the RDY bit of the FLCR. When the RDY bit is 0, new write and erase commands cannot be accepted because data is being written or erased by the automatic algorithm. Also, data cannot be read from the flash memory addresses. The data read when the RDY bit is 0 is used as the hardware sequence flag indicating the status of the flash memory. 431 CHAPTER 21 FLASH MEMORY ■ Interrupt Control An interrupt request can be issued to the CPU by terminating the automatic algorithm sequence. This enables the user to immediately detect when an automatic algorithm sequence that runs over several hours has terminated. The automatic algorithm termination interrupt is controlled in accordance with the RDYINT and INTE bits of the FLCR. The RDYINT bit is the automatic algorithm termination interrupt flag. If the RDYINT bit is set while the internal ready/busy signal is 1, an interrupt request is issued to the CPU. To cancel the interrupt request, set the RDYINT or INTE bit to 0. FLCR and the 16-bit free-run timer share the interrupt sources shown in the table below. Interrupt No. Interrupt source 16-bit free-run timer/ flash 432 In decimal notation In hexadecimal notation 62 3E Interrupt level Offset TBR default address ICR46 304H 000FFF04H CHAPTER 21 FLASH MEMORY 21.4 Automatic Algorithm of Flash Memory Commands for activating the automatic algorithms of the flash memory can be divided into four types: Read/Reset, Write, Chip Erase, and Sector Erase. ■ Command Sequence To activate the automatic algorithm, write half word data (16 bits) to the flash memory continuously one to six times. This is called a command. If incorrect addresses and data are written or if addresses and data are written in incorrect order, the flash memory is reset to read mode. Table 21.4-1 lists the commands used when data is written to or erased from the flash memory. (The item "Address" in this table means a CPU address.) Table 21.4-1 Command Sequence Command sequence Bus write cycle 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus read/ write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read/Reset 1 XXXXXH F0H - - - - - - - - - - Read/Reset 4 D5555H AAH CAAABH 55H D5555H F0H (RA) (RD) - - - - Write 4 D5555H AAH CAAABH 55H D5555H A0H (PA) (PD) - - - - Chip Erase 6 D5555H AAH CAAABH 55H D5555H 80H D5555H AAH CAAABH 55H D5555H 10H Sector Erase 6 D5555H AAH CAAABH 55H D5555H 80H D5555H AAH CAAABH 55H (SA) 30H Auto Select 3 D5555H AAH CAAABH 55H D5555H 90H - - - - - - Continuation Mode 3 D5555H AAH CAAABH 55H D5555H 20H - - - - - - Continuous Write 2 XXXXXH A0H (PA) (PD) - - - - - - - - Continuous Mode Reset 2 XXXXXH 90H XXXXXH F0H or 00H - - - - - - - - The commands used in word mode are the same as those in byte mode. Bits not listed in this table can have any value. All addresses and data are represented in hexadecimal numbers. (RA): Read address (PA): Write address (SA): Sector address (specification of any address in the sector) (RD): Read data (PD): Write data Both reset commands can reset the flash memory to read mode. 433 CHAPTER 21 FLASH MEMORY ❍ Read/Reset command The read/reset command sets the flash memory to read/reset mode. The flash memory maintains the read status until another command is entered. When the power supply is turned on, the flash memory is automatically set to read/reset mode. In this case, the data read command is unnecessary. To return the flash memory from timing limit excess to read mode, issue the read/reset command sequence. The read/reset command reads data from the flash memory during the read cycle. ❍ Program (Write) command In FR-CPU programming mode, writing is executed in half word units. Writing requires four bus cycles. The command sequence begins with two unlock cycles that are followed by a Write setup command and a write data cycle. Writing to memory starts in the last write cycle. After the sequence of the write command in the automatic algorithm has been executed, flash memory no longer requires control from external devices. Flash memory automatically generates the internal write pulse and verifies the margin for the written cell. The automatic write operation is terminated by the data polling function when the value of bit 7 matches the value of this bit (see "■ Hardware sequence flags" in Section "21.5 Checking the Automatic Algorithm Execution Status"). At the same time, the flash memory returns to read mode and no longer accepts write addresses. As a result, the flash memory requests the next effective address at this point in time. In this way, data polling indicates that data is being written to memory. All commands written to flash memory are ignored during the write operation. If a hardware reset is activated during the write operation, the integrity of the written address data cannot be guaranteed. Data can be written in any address order. Data can also be written beyond a sector boundary. However, a data unit 0 cannot be set back to a data unit 1 by writing. If data unit 1 is written in data unit "0", the data polling algorithm determines that the data element is faulty or it only appears as if data unit 1 was written. If data is read in reset/read mode, a data unit 0 remains as it is. Only in an erase operation can be changed data unit 0 to data unit 1. ❍ Chip Erase command Chip erase (batch erase of all sectors) requires six access cycles. First, two unlock cycles are performed, then, the setup command is written. Two more unlock cycles are performed before finally the chip erase command itself is performed. During a chip erase operation, the user does not need to write data to the flash memory prior to erasing. During execution of the automatic erase algorithm, a pattern of zeroes is automatically written to flash memory for verification before all cells are erased (pre-program). During the chip erase operation, the flash memory does not require control from external devices. Automatic erase is started in the write cycle of the command sequence. When bit 7 is set to 1, the automatic erase operation terminates and the flash memory returns to read mode. The time for chip erase can be expressed as "sector erase time x total number of sectors + chip write time (pre-program)". 434 CHAPTER 21 FLASH MEMORY ❍ Sector Erase command Sector erase requires six access cycles. First, two unlock cycles are performed, then, the setup command is written. This is followed by two unlock cycles. Finally, sector erase is started by entering the sector erase command in the 6th cycle. The next sector erase command can be accepted in the period from writing of the last sector erase command to the 50µs timeout. Multiple sector erase commands can be accepted simultaneously after the first six bus cycles have been written. This sequence is executed by continuously writing the sector erase command (30H) for the addresses of all sectors to be erased. The sector erase operation itself is performed in the time after writing the last sector erase command to when the 50µs timeout time has elapsed. Consequently, to erase several sectors at the same time, each of the sectors to be erased must be specified within 50µs. If a sector is not specified within this time, the corresponding sector erase command may not be accepted. Bit 3 can be used to verify whether the subsequent sector erase commands are valid (see "■ Hardware sequence flags" in Section "21.5 Checking the Automatic Algorithm Execution Status"). A sector erase command in timeout status or commands other than the erase temporary stop command are reset to read and the immediately preceding command sequence is ignored. In this case, erase is completed by re-erasing the sector. Sector address input to the sector erase buffer can be executed for any combination of sectors and numbers (0 to 6). In sector erase, the user does not need to write data to the flash memory prior to erase. Data is written automatically to all cells of the flash memory in the sector to be erased (pre-program). When a sector is being erased, the sectors not to be erased are not affected at all. In this case, the flash memory does not require any control from external devices. Automatic sector erase is performed in the time from writing of the last sector erase command to when the 50µs timeout time has elapsed. When bit 7 is set to 1, automatic sector erase processing terminates and flash memory returns to read mode. Other commands are ignored. Data polling is effective for any address in the erased sector. The time for multiple sector erase can be expressed as "(sector erase time + sector write time (pre-program)) x number of erased sectors". 435 CHAPTER 21 FLASH MEMORY 21.5 Checking the Automatic Algorithm Execution Status The flash memory uses hardware for notifying the user for the internal operation status of flash memory and operation completion so as to perform the operation sequence for write/erase via the automatic algorithm. This automatic algorithm can use the following hardware sequence flags to check the operation status of flash memory: ■ Ready/Busy Signal (RDY/BUSYX) Besides the hardware sequence flags, the flash memory has the ready/busy signal as a means of notifying the user whether the automatic algorithm is being executed or has terminated. This ready/busy signal is connected to the flash memory interface circuit and can be read as the RDY bit of the flash memory status register (FLCR). At the rising edge of this signal, an interrupt request can also be issued to the CPU. When the read value of the RDY bit is 0, data is being written to or erased from the flash memory. At this time, flash memory does not accept write and erase commands. When the read value of the RDY bit is 1, the flash memory is in read/write status or in erase operation wait status. ■ Hardware Sequence Flags At halfword read 15 (Undefined) 8 At byte read (odd address only) 7 Hardware sequence flag 0 7 Hardware sequence flag 0 Note: Word read is inhibited (use only the FR-CPU programming mode). The value of the hardware sequence flag can be obtained as a data item by reading the respective flash memory address (an odd address during byte access) during execution of the automatic algorithm. In this data item, five bits are effective, each is used to indicate the status of the automatic algorithm. bit (At halfword or byte access) 7 DPOLL 6 5 4 3 TLOVER (Undefined) SETIMR 2 1 0 (Undefined) (Undefined) These flags are meaningless in FR-CPU ROM mode. Be sure to execute half word or byte read only in FR-CPU programming mode. 436 CHAPTER 21 FLASH MEMORY Table 21.5-1 lists the hardware sequence flag status. Table 21.5-1 Hardware Sequence Flag Status Status Being executed Time limit excess DPOLL TLOVER SETIMR Automatic write operation Reverse data 0 0 Automatic erase operation 0 0 1 Automatic write operation Reverse data 1 0 Automatic erase operation 0 1 1 The bits in the above table have the following meanings: [bit 7]: DPOLL (data polling) [bit 5]: TLOVER (timer limit excess) [bit 3]: SETIMR (sector erase timer) Each of these bits is simply explained below. [bit 7]: DPOLL (data polling flag) The data polling flag is used to notify the user with the data polling function that the automatic algorithm is being executed or has terminated. ❍ During write operation If read access is attempted when the automatic-write algorithm is being executed, flash memory outputs the inverse value of bit 7 in the last written data item, independently of the indicated address. If read access is attempted when the automatic-write algorithm terminates, flash memory outputs bit 7 of the read value at the indicated address. ❍ In chip/sector erase operation If read access is attempted when the chip erase/sector erase algorithm is being executed, flash memory outputs 0 from the currently erased sector (valid at sector erase) or without reference to the indicated address (valid at chip erase). When the chip erase/sector erase algorithm terminates, flash memory outputs 1. Note: When automatic algorithm is activated, read access to the specified address is ignored. For data read, output of other bits is enabled when termination is indicated with the data polling flag. For this reason, execute data read after automatic algorithm termination following the read access for which data polling termination was checked. [bit 5]: TLOVER (timing limit excess flag) The timing limit excess flag notifies the user that automatic algorithm execution exceeded the time (internal pulse count) defined in the flash memory. 437 CHAPTER 21 FLASH MEMORY ❍ At write/chip sector erase If the defined time (time required for write/erase) is not exceeded when read access is attempted after the automatic algorithm for write or chip sector erase has been activated, the timing limit excess flag becomes 0. If the defined time is exceeded, this flag becomes 1. This flag value has no relationship to whether the automatic algorithm is being executed or has terminated; however, it allows to determine whether write/erase has been successful or unsuccessful. That is, if the automatic algorithm is still being executed by the data polling function when this flag becomes 1, writing was obviously unsuccessful. For example, if an attempt is made to write 1 at a flash memory address where 0 was already written, a failure occurs. In this case, the flash memory becomes locked and the automatic algorithm does not terminate. For this reason, the data polling flag is not valid. This status indicates that the flash memory was not used correctly; it does not indicate that the flash memory is faulty. If this status occurs, execute the reset command. [bit 3]: SETIMR (sector erase timer flag) The sector erase timer flag notifies the user whether the sector erase wait period has been exceeded after the sector erase command has been activated. ❍ During sector erase operation If the sector erase wait period is not exceeded when read access is attempted after the sector erase command has been activated, the flash memory outputs 0. If the sector erase wait period has been exceeded, the flash memory outputs 1. This output, however, does not depend on the address of the sector for which the command was issued. If this flag is 1 when the erase algorithm is being executed by the data polling function, the erase processing to be controlled internally has already started. Commands other than the writing of subsequent sector erase codes are ignored until erase is terminated. If this flag is 0, the flash memory accepts writing commands for additional sector erase codes. To check this, the status of this flag should be checked before writing the subsequent sector erase codes. If this flag is set to 1 as a result of the second status check, additional sector erase codes may have not been accepted. ❍ When a sector erase operation If the indicated address belongs to the sector being erased when read access is attempted during a sector erase temporary stop, the flash memory outputs 1. If the indicated address does not belong to the sector being erased, the flash memory outputs bit 3 (DATA: 3) of the read value at the indicated address. 438 CHAPTER 21 FLASH MEMORY 21.6 Writing and Erasing Flash Memory This section describes how to issue the command that activates the automatic algorithm and how to perform read/reset, write, chip erase, and sector erase operations for the flash memory. ■ Overview of Writing and Erasing Flash Memory Executing the write cycle for each command sequence bus during read/reset, write, chip erase, or sector erase operation enables the flash memory to execute the automatic algorithm. The write cycle for each command sequence bus must always be executed continuously. The flash memory can also determine whether the automatic algorithm terminated by using the data polling function. It returns to the read/reset status after normal termination. 439 CHAPTER 21 FLASH MEMORY 21.6.1 Putting Flash Memory into Read/Reset Status This section describes how to place the flash memory in the read/reset status by issuing the read/reset command. ■ Placing the Flash Memory in Read/Reset Status The flash memory can be placed in the read/reset status by continuously transmitting the read/ reset command from the command sequence Table 21.4-1 to target sectors in the flash memory. The read/reset command provides two command sequences. One uses one bus cycle, the other uses three bus cycles. Other than that, there is no essential difference between these two sequences. The read/reset status is the initial status of the flash memory. If a command terminates normally when the power supply is on, the flash memory always enters the read/reset status. The read/ reset status means that the flash memory is waiting for the input of other commands. When in read/reset status, the flash memory can read data during normal read access. As with mask ROM, the flash memory supports program access from the CPU. Normal data read does not require this read/reset command. This command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally for some reason. 440 CHAPTER 21 FLASH MEMORY 21.6.2 Writing Data to Flash Memory This section describes how to write data to the flash memory by issuing the write command. ■ Writing Data to the Flash Memory The automatic algorithm for writing flash memory data can be activated by continuously sending the write command (see Table 21.4-1) to target sectors in the flash memory. When data writing at the target address of the 4th cycle terminates, the automatic algorithm is activated and then automatic writing starts. ■ Address Specification Method Only an even address can be specified in a data write cycle as a write address. Specifying an odd address does not assure correct data writing. That is, data writing at even addresses in half word data units becomes necessary. Data can be written in any order of address as well as beyond a sector boundary. However, only one half word data item can be written per write command. ■ Note on Writing Data to the Flash Memory Data unit 0 cannot be returned to data unit 1 by a write operation. If data unit 1 is written in data unit 0, the flash memory element is determined to be faulty because the data polling algorithm or toggle operation does not terminate and the timing limit excess flag is determined to be abnormal because the defined time for the write operation is exceeded. Alternatively, it may only appear as if data unit 1 has been written. If data is read in the reset/read status, however, data unit 0 remains as it is. Only in an erase operation can be changed data unit 0 to data unit 1. All other commands are ignored during execution of the automatic write operation. Note that if hardware reset is activated during the write operation, the integrity of written address data cannot be guaranteed. ■ Procedure for Flash Memory Write Figure 21.6-1 shows an example for the procedure of flash memory write. Using hardware sequence flags enables to determine the automatic algorithm status in flash memory. Here, the data polling flag (DPOLL) is used to check for the end of writing. Data for the flag check is read from the last written address. The data polling flag (DPOLL) changes simultaneously when the timing limit excess flag (TLOVER) changes. For this reason, even if timing limit excess flag (TLOVER) is 1, the data polling flag bit (DPOLL) must be rechecked. 441 CHAPTER 21 FLASH MEMORY Figure 21.6-1 Example of Flash Memory Write Procedure Start of write FLCR: WE(bit5) Enable flash memory write Write command sequence D5555H AAH CAAABH 55H D5555H A0H Write address write data Read internal address Data polling (DPOLL) Next address Data Data 0 Timing limit (TLOVER) 1 Read internal address Data Data polling (DPOLL) Data Write error Last address? No Yes FLCR: WE(bit5) Disable flash memory write Check by hardware sequence flags Completion of write 442 CHAPTER 21 FLASH MEMORY 21.6.3 Erasing Data There are two methods for erasing data in this device. One is chip erase and the other is sector erase. Chip erase is used to erase the data of the whole chip and sector erase is used to erase data in units of sectors. ■ Chip Erase All data can be erased from the flash memory by continuously transmitting the chip erase command from the command sequence Table 21.4-1 to target sectors in the flash memory. Chip erase command requires six bus cycles. The chip erase operation starts after writing in the 6th cycle is completed. With chip erase, the user need not write data to the flash memory prior to erase. During execution of the automatic erase algorithm, the flash memory automatically writes 0 for verification before erasing all cells. ■ Sector Erase Sector erase can erase data in units of sectors. The user can specify several sectors at the same time. Target sectors in flash memory can be erased by continuously transmitting the sector erase command from the command sequence table (Table 21.4-1) to those sectors. ❍ Sector specification method Sector erase command requires six bus cycles. 50µs sector erase wait is started by writing the sector erase code (30H) at any even address that can be accessed in a target sector in the 6th cycle. Multiple sector erase is enabled by writing the sector erase code (30H) at an address in the target sector to be erased after the above processing is finished. ❍ Note on specifying multiple sectors Erase is started after the period from writing of the last sector erase code to when the 50µs sector erase wait time elapsed. That is, to erase multiple sectors at the same time, it is necessary to enter the next erase sector address and an erase code (in the 6th cycle of the command sequence) within 50µs. Erase sector addresses and erase codes entered after the 50µs have elapsed may not be accepted. The sector erase timer (hardware sequence flag SETIMR) can be used to check whether writing of the subsequent sector erase codes was effective. In this case, however, the address from which the sector erase timer is read must indicate the sector to be erased. ❍ Sector erase procedure Using hardware sequence flags enables to determine the status of the automatic algorithm in the flash memory. Figure 21.6-2 is an example of the flash memory sector erase procedure. Note that data for flag check is read from the sector to be erased. The data polling flag (DPOLL) changes simultaneously with changes in the timing limit excess flag (TLOVER). For this reason, the data polling flag bit (DPOLL) must be rechecked. 443 CHAPTER 21 FLASH MEMORY Figure 21.6-2 Example of the Procedure for Flash Memory Sector Erase Start of erase FLCR: WE(bit5) Enable flash memory erase Sector erase timer (SETIMR) 1 Erase command sequence D5555H AAH CAAABH 55H D5555H 80H D5555H AAH CAAABH 55H 0 Enter erase sector code (30H) Yes Are there any other erase sectors? No Internal address read Internal address read Data polling (DPOLL) Next sector 1 0 Check by hardware sequence flags 0 Timing limit (TLOVER) 1 Internal address read 0 Data polling (DPOLL) 1 Erase error Last sector? Yes FLCR: WE(bit5) Disable flash memory erase Completion of erase 444 No CHAPTER 22 EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/ AF210/AD120/AF110 flash microcontroller programmer by Yokogawa Digital Computer Corporation. 22.1 Basic Configuration 22.2 Examples of Serial Programming Connection 445 CHAPTER 22 EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION 22.1 Basic Configuration The MB91F155A supports serial onboard writing (Fujitsu standard) of the flash ROM. This section provides the related specifications. ■ Basic Configuration of MB91F155A Serial Onboard Writing Fujitsu standard serial onboard writing uses the AF220/AF210/AD120/AF110 flash microcontroller programmer by Yokogawa Digital Computer Corporation. In the serial write mode of the flash product, the option of the single chip mode or the internal ROM external bus mode can be selected. Figure 22.1-1 shows the basic configuration of the MB91F155A serial programming connection. Figure 22.1-1 Basic Configuration of Example for Serial Programming Connection Common general-purpose cable (AZ210) Host interface cable RS232C AF220/AF210 /AD120/AF110 Flash Microcontroller Programmer + memory card CLK synchronous serial connection MB91F155A User system Operable in stand-alone mode For information on the functions of and operational procedures related to the flash microcontroller programmer (AF210), the general-purpose common cable (AZ210) for connection, and the connector, contact Yokogawa Digital Computer Corporation. 446 CHAPTER 22 EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION ■ Pins Used for Fujitsu Standard Serial Onboard Writing Table 22.1-1 shows the functions of the related pins. Table 22.1-1 Function of Pins Pin Function Description MD2, MD1, MD0 Mode pin Control to programming mode. Setting MD2=1, MD1=1, and MD0=0 to enter the Flash serial programming mode. Ref. : Setting MD2=0, MD1=1, and MD0=1 to enter the singlechip mode. PG3, PG4, PG5 Programming program start pin Setting PG5=1, PG4=0, and PG3=1 to rewrite the Flash serial. RST Reset pin SIN1 Serial data input pin SOT1 Serial data output pin SCK1 Serial clock input pin VCC Power voltage supply pin Supply the power voltage (VCC = 3.15V to 3.6V) from the user system. VSS GND pin Must be shared with GND of the flash microcontroller programmer. - Use resource for ch.1 of UART for CLK sync mode. 1. Similarly to PG3, PG4, and PG5, using the SIN1, SOT1, and SCK1 pins in the user system requires a control circuit as shown in Figure 22.1-2 (the user circuit is disconnected in serial programming mode by the flash microcontroller programmer’s "/TICS" signal). 2. Connect to AF200 when the power of the user system is turned off. Figure 22.1-2 Pin Control Circuit AF220/AF210 /AD120/AF110 Write control pin MB91F155A Write control pin 10k AF220/AF210 /AF120/AF110 /TICS pin User 447 CHAPTER 22 EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION ■ Example of Serial Programming Connection Refer to the connection example. • Internal vector mode (single-chip mode): example of standard connection • Internal vector mode (single-chip mode): example of minimum connection with AF200 ■ System Configuration of AF200 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation. Product name Main Unit Function AF220/AC4P Model with Ethernet Interface /100V to 220V Power supply adapter AF210/AC4P Standard Model /100V to 220V Power supply adapter AD120/AC4P Single Key Model with Ethernet Interface /100V to 220V Power supply adapter AF110/AC4P Single Key Model /100V to 220V Power supply adapter AZ221 Writer exclusive use. RS232C cable for PC/AT AZ210 Standard Target Probe (a): 1m FF205 Control modules for FR family FLASH microcontroller made by Fujitsu. AZ290 Remote Controller /P2 2M bytes PC Card (Option) up to FLASH Memory Capacity 128K bytes /P4 4M bytes PC Card (Option) up to FLASH Memory Capacity 512K bytes /P8 8M bytes PC Card (Option) up to FLASH Memory Capacity 1M bytes Inquiries: Yokogawa Digital Computer Corporation Telephone number: (81)-42-333-6224 ■ Oscillation Clock Frequency The oscillation clock frequency that can be used for Flash memory programming are from 2MHz to 16.5 MHz. ■ Other Note The port status at FLASH memory writing by the serial writer is equal to reset status without the pin for writing. 448 CHAPTER 22 EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION 22.2 Examples of Serial Programming Connection This section shows examples of serial programming connections when the power supply voltage of microcontroller is supplied by user power supply. For the mode pins, MD2 and MD0, MD2=1 and MD0=0 is inputted by TAUX3 and TMODE of AF200. Flash serial rewriting mode is MD2, MD1, and MD0=1, 1, 0. ■ Internal Vector Mode (Single-chip Mode): Example of Standard Connection Figure 22.2-1 Example of MB91F155A Serial Programming Connection AF200 Flash Micro-Controller Programmer TAUX3 User system Connector DX10-28S (19) MB91F155A at serial rewiting 1 MD2 52 MD1 53 MD0 54 PG5 96 PG4 95 10k 10k at serial rewiting 1 10k at serial rewiting 0 TMODE (12) 10k at serial rewiting 1 User circuit 10k TAUX WDT /TICS (23) at serial rewiting 0 10k (18) at serial rewiting 1 (10) PG3 94 RST 55 User circuit 10k /TRES (5) TTXD TRXD TCK (13) (27) (6) TVcc (2) GND SIN1 110 SOT1 109 SCK1 108 Vcc (14,15, Power supplied from user (3.3V) Vss 1,28) Pin 14 (27,56,68,77, 97,122,140) (9,26,44,59, 98,101,144) Pin 1 DX10-28S Pins 3,4,9,11,16,17,18, 20,24,25,26 are opened. Pin 28 Pin 15 Pin assignments of connector (Hirose Electric) DX10-28S : write angle type 10k pull-up 449 CHAPTER 22 EXAMPLES OF MB91F155A SERIAL PROGRAMMING CONNECTION ■ Internal Vector Mode (Single-chip Mode): Example of Minimum Connection with AF200 Example of minimum connection is shown when the power supply voltage of microcontroller is supplied by the user power supply. Flash serial rewriting mode is MD2, MD1, and MD0=1, 1, 0. Figure 22.2-2 Example of MB91F155A Serial Programming Connection AF200 Flash Micro-Controller Programmer TAUX3 User system Connector DX10-28S 10k (19) MB91F155A 10k at serial rewriting 1 MD2 52 MD1 53 MD0 54 PG5 96 PG4 95 10k at serial rewriting 1 10k at serial rewriting 0 TMODE (12) at serial rewriting 1 (23) WDT (18) /TICS (10) 10k User circuit 10k TAUX 10k at serial rewriting 0 at serial rewriting 1 10k PG3 94 RST 55 User circuit 10k /TRES TTXD TRXD TCK TVcc GND (5) (13) (27) SIN1 110 SOT1 109 (6) SCK1 108 (2) (14,15, Power supplied from user (3.3V) Vcc (27,56,68,77, 97,122,140) Vss (9,26,44,59, 98,101,144 ) 1,28) Pin 1 Pin 14 DX10-28S Pins 3,4,9,11,16,17,18, 20,24,25,26 are opened. Pin 28 Pin 15 Pin assignments of connector (Hirose Electric) DX10-28S : write angle type 450 10k pull-up APPENDIX These appendixes provide the I/O map, notes on using the little-endian area, and instruction lists. They also explain interrupt vectors and the pin status in each CPU state. APPENDIX A I/O Map APPENDIX B Interrupt Vectors APPENDIX C Pin Status in Each CPU State APPENDIX D Notes on Using the Little-Endian Area APPENDIX E Instruction Lists 451 APPENDIX A I/O Map APPENDIX A I/O Map Figure A-1 shows how to use the I/O map, and Table A-1 shows the I/O map itself (which indicates the correspondence between the memory space area and peripheral resources for each register). ■ How to Use the I/O Map Figure A-1 Address 000000 H How to Use the I/O Map Register +0 +1 PDR3 [R/W] PDR2 [R/W] +2 ________ +3 ________ Block Port Data Register XXXXXXXX XXXXXXXX Read/write attribute Initial register value after reset Register name (the register in column 1 has a number of the type 4n address, the register in column 2 has a number of the type 4n+2 address, etc.) Leftmost register address. (The register in column 1 becomes the MSB side of data in word access.) Notes: The bit values of a register have the following initial values: 1: Initial value 1 0: Initial value 0 X: Initial value X -: No register exists physically at this position. 452 APPENDIX A I/O Map ■ I/O Map Table A-1 I/O Map (1/7) Address Register +0 +1 000000H PDR3 [R/W] XXXXXXXX PDR2 [R/W] XXXXXXXX 000004H - PDR6 [R/W] XXXXXXXX +2 PDR5 [R/W] XXXXXXXX PDR4 [R/W] XXXXXXXX PDR8 [R/W] -XXXXXXX Port data register - 00000CH 000010H PDRF [R/W] ---XXXXX PDRE [R/W] XXXXXXXX PDRD [R/W] XXXXXXXX PDRC [R/W] XXXXXXXX 000014H PDRJ [R/W] ------11 PDRI [R/W] --XXXXXX PDRH [R/W] --XXXXXX PDRG [R/W] --XXXXXX PDRL [R/W] XXXXXXXX PDRK [R/W] XXXXXXXX - 000018H Block - - 000008H +3 00001CH SSR0 [R/W, R] 00001000 SIDR0 [R], SODR0 [W] XXXXXXXX SCR0 [R/W, W] 00000100 SMR0 [R/W] 00000-00 UART0 000020H SSR1 [R/W, R] 00001000 SIDR1 [R], SODR1 [W] XXXXXXXX SCR1 [R/W, W] 00000100 SMR1 [R/W] 00000-00 UART1 000024H SSR2 [R/W, R] 00001000 SIDR2 [R], SODR2 [W] XXXXXXXX SCR2 [R/W, W] 00000100 SMR2 [R/W] 00000-00 UART2 000028H SSR3 [R/W, R] 00001000 SIDR3 [R], SODR3 [W] XXXXXXXX SCR3 [R/W, W] 00000100 SMR3 [R/W] 00000-00 UART3 TMRLR0 [W] XXXXXXXX XXXXXXXX TMR0 [R] XXXXXXXX XXXXXXXX 000030H - TMCSR0 [R/W] ----0000 00000000 000034H TMRLR1 [W] XXXXXXXX XXXXXXXX TMR1 [R] XXXXXXXX XXXXXXXX 000038H - TMCSR1 [R/W] ----0000 00000000 00003CH TMRLR2 [W] XXXXXXXX XXXXXXXX TMR2 [R] XXXXXXXX XXXXXXXX - TMCSR2 [R/W] ----0000 00000000 00002CH 000040H Reload timer 0 Reload timer 1 Reload timer 2 453 APPENDIX A I/O Map Table A-1 I/O Map (2/7) Address 000044H Register +0 +1 +2 +3 TMRLR3 [W] XXXXXXXX XXXXXXXX TMR3 [R] XXXXXXXX XXXXXXXX - TMCSR3 [R/W] ----0000 00000000 000048H 00004CH CDCR1 [R/W] 0---0000 - CDCR0 [R/W] 0---0000 - 000050H CDCR3 [R/W] 0---0000 - CDCR2 [R/W] 0---0000 - 000054H to 000058H RCR1 [W] 00000000 RCR0 [W] 00000000 UDCR1 [R] 00000000 UDCR0 [R] 00000000 000060H CCRH0 [R/W] 00000000 CCRL0 [R/W, W] -000X000 - CSR0 [R/W, R] 00000000 000064H CCRH1 [R/W] -0000000 CCRL1 [R/W, W] -000X000 - CSR1 [R/W, R] 00000000 000068H IPCP1 [R] XXXXXXXX XXXXXXXX IPCP0 [R] XXXXXXXX XXXXXXXX 00006CH IPCP3 [R] XXXXXXXX XXXXXXXX IPCP2 [R] XXXXXXXX XXXXXXXX 000070H - 000074H OCCP1 [R/W] XXXXXXXX XXXXXXXX OCCP0 [R/W] XXXXXXXX XXXXXXXX 000078H OCCP3 [R/W] XXXXXXXX XXXXXXXX OCCP2 [R/W] XXXXXXXX XXXXXXXX 00007CH OCCP5 [R/W] XXXXXXXX XXXXXXXX OCCP4 [R/W] XXXXXXXX XXXXXXXX 000080H OCCP7 [R/W] XXXXXXXX XXXXXXXX OCCP6 [R/W] XXXXXXXX XXXXXXXX 000084H OCS2,3 [R/W] XXX00000 0000XX00 OCS0, 1 [R/W] XXX00000 0000XX00 000088H OCS6, 7 [R/W] XXX00000 0000XX00 OCS4, 5 [R/W] XXX00000 0000XX00 00008CH TCDT [R/W] 00000000 00000000 TCCS [R/W] 0------- 00000000 000090H 000094H 454 STPR0 [R/W] 0000---- STPR1 [R/W] 00000000 GCN1 [R/W] 00110010 00010000 Reload timer 3 Communication prescaler 1 Reserved 00005CH ICS23 [R/W] 00000000 Block - 8/16-bit up/ down counter/ timer 16-bit input capture unit ICS01 [R/W] 00000000 16-bit output compare unit 16-bit free-run timer STPR2 [R/W] 000000-- - Stop registers 0, 1 and 2 - GCN2 [R/W] 00000000 PPG control APPENDIX A I/O Map Table A-1 I/O Map (3/7) Address Register +0 +1 000098H PTMR0 [R] 11111111 11111111 00009CH PDUT0 [W] XXXXXXXX XXXXXXXX 0000A0H PTMR1 [R] 11111111 11111111 0000A4H PDUT1 [W] XXXXXXXX XXXXXXXX 0000A8H PTMR2 [R] 11111111 11111111 0000ACH PDUT2 [W] XXXXXXXX XXXXXXXX 0000B0H PTMR3 [R] 11111111 11111111 0000B4H PDUT3 [W] XXXXXXXX XXXXXXXX 0000B8H PTMR4 [R] 11111111 11111111 0000BCH PDUT4 [W] XXXXXXXX XXXXXXXX 0000C0H PTMR5 [R] 11111111 11111111 0000C4H PDUT5 [W] XXXXXXXX XXXXXXXX 0000C8H EIRR0 [R/W] 00000000 +2 PCSR0 [W] XXXXXXXX XXXXXXXX PCNH0 [R/W] 0000000- PCNH1 [R/W] 0000000- PCNL1 [R/W] 00000000 PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2 [R/W] 0000000- PCNL2 [R/W] 00000000 PCSR3 [W] XXXXXXXX XXXXXXXX PCNH3 [R/W] 0000000- PCNL3 [R/W] 00000000 PCSR4 [W] XXXXXXXX XXXXXXXX PCNH4 [R/W] 0000000- PCNL4 [R/W] 00000000 PCSR5 [W] XXXXXXXX XXXXXXXX ENIR0 [R/W] 00000000 0000D0H to 0000D8H PCNL0 [R/W] 00000000 PCSR1 [W] XXXXXXXX XXXXXXXX ELVR0 [R/W] 00000000 00000000 0000CCH +3 PCNH5 [R/W] 0000000- PCNL5 [R/W] 00000000 EIRR1 [R/W] 00000000 ENIR1 [R/W] 00000000 ELVR1 [R/W] 00000000 00000000 - Block PPG0 PPG1 PPG2 PPG3 PPG4 PPG5 Externalinterrupt Reserved - DACR2 [R/W] -------0 DACR1 [R/W] -------0 DACR0 [R/W] -------0 0000E0H - DADR2 [R/W] XXXXXXXX DADR1 [R/W] XXXXXXXX DADR0 [R/W] XXXXXXXX 0000E4H ADCR [R, W] 00101-XX XXXXXXXX ADCS1 [R/W, W] 00000000 ADCS0 [R/W] 00000000 A/D converter AICR [R/W] 00000000 Analog input control 0000DCH 0000E8H - D/A converter 455 APPENDIX A I/O Map Table A-1 I/O Map (4/7) Address Register +0 +1 0000ECH to 0000F0H +2 +3 - Reserved 0000F4H PCRH [R/W] --000000 PCRI [R/W] --000000 0000F8H OCRH [R/W] --000000 OCRI [R/W] --000000 0000FCH DDRF [R/W] ---00000 DDRE [R/W] 00000000 DDRD [R/W] 00000000 DDRC [R/W] 00000000 000100H - DDRI [R/W] -0000000 DDRH [R/W] --000000 DDRG [R/W] --000000 DDRL [R/W] 00000000 DDRK [R/W] 00000000 000108H to 00011CH 000120H 000124H PCRD [R/W] 00000000 PCRC [R/W] 00000000 IBCR [R/W] 00000000 IBSR [R] 00000000 - IDAR [R/W] XXXXXXXX IADR [R/W] -XXXXXXX ICCR [R/W] --0XXXXX 000200H DPDP [R/W] -------- -------- -------- -0000000 000204H DACSR [R/W] 00000000 00000000 00000000 00000000 000208H DATCR [R/W] XXXXXXXX XXXX0000 XXXX0000 XXXX0000 00020CH - Reserved DMAC Reserved 000210H CAC [R/W] 00000000 CA1 [R/W] --XXXXXX CA2 [R/W] --XXXXXX CA3 [R/W] ---XXXXX 000214H CA4 [R/W] ---XXXXX CA5 [R/W] -----XXX CA6 [R/W] ----XXXX CA7 [R/W] -XXXXXXX 000220H to 0003ECH 456 I2C interface - - 00021CH Data direction register Reserved 000128H to 0001FCH 000218H Pull-up control Open-drain control - - 000104H Block - Reserved CAS [R/W] 0------0 - - Calendar Calendar Reserved APPENDIX A I/O Map Table A-1 I/O Map (5/7) Address Register +0 +1 +2 +3 0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Bit search module 000400H ICR00 [R/W] ----1111 ICR01 [R/W] ----1111 ICR02 [R/W] ----1111 ICR03 [R/W] ----1111 000404H ICR04 [R/W] ----1111 ICR05 [R/W] ----1111 ICR06 [R/W] ----1111 ICR07 [R/W] ----1111 000408H ICR08 [R/W] ----1111 ICR09[R/W] ----1111 ICR10 [R/W] ----1111 ICR11 [R/W] ----1111 00040CH ICR12 [R/W] ----1111 ICR13 [R/W] ----1111 ICR14 [R/W] ----1111 ICR15 [R/W] ----1111 000410H ICR16 [R/W] ----1111 ICR17 [R/W] ----1111 ICR18 [R/W] ----1111 ICR19 [R/W] ----1111 000414H ICR20 [R/W] ----1111 ICR21 [R/W] ----1111 ICR22 [R/W] ----1111 ICR23 [R/W] ----1111 000418H ICR24 [R/W] ----1111 ICR25 [R/W] ----1111 ICR26 [R/W] ----1111 ICR27 [R/W] ----1111 00041CH ICR28 [R/W] ----1111 ICR29 [R/W] ----1111 ICR30 [R/W] ----1111 ICR31 [R/W] ----1111 000420H ICR32 [R/W] ----1111 ICR33 [R/W] ----1111 ICR34 [R/W] ----1111 ICR35 [R/W] ----1111 000424H ICR36 [R/W] ----1111 ICR37 [R/W] ----1111 ICR38 [R/W] ----1111 ICR39 [R/W] ----1111 000428H ICR40 [R/W] ----1111 ICR41 [R/W] ----1111 ICR42 [R/W] ----1111 ICR43 [R/W] ----1111 00042CH ICR44 [R/W] ----1111 ICR45 [R/W] ----1111 ICR46 [R/W] ----1111 ICR47 [R/W] ----1111 000430H DICR [R/W] -------0 HRCL [R/W] ----1111 000434H to 00047CH RSRR/WTCR [R, W] 1-XXX-00 STCR [R/W, W] 000111-- 000484H GCR [R/W, R] 110011-1 WPR [W] XXXXXXXX Interrupt control unit Delayed interrupt - 000480H Block Reserved PDRR [R/W] ----0000 CTBR [W] XXXXXXXX - Clock control unit 457 APPENDIX A I/O Map Table A-1 I/O Map (6/7) Address Register +0 +1 +2 +3 Block 000488H PCTR [R/W] 00XX0XXX - 00048CH to 0005FCH - Reserved 000600H DDR3 [W] 00000000 DDR2 [W] 00000000 - - 000604H - DDR6 [W] 00000000 DDR5 [W] 00000000 DDR4 [W] 00000000 DDR8 [W] -0000000 000608H - 00060CH ASR1 [W] 00000000 00000001 AMR1 [W] 00000000 00000000 000610H ASR2 [W] 00000000 00000010 AMR2 [W] 00000000 00000000 000614H ASR3 [W] 00000000 00000011 AMR3 [W] 00000000 00000000 000618H ASR4 [W] 00000000 00000100 AMR4 [W] 00000000 00000000 00061CH ASR5 [W] 00000000 00000101 AMR5 [W] 00000000 00000000 000620H AMD0 [R/W] ---00111 000624H AMD5 [R/W] 0--00000 AMD1 [R/W] 0--00000 000634H to 0007BCH EPCR1 [W] -------- 11111111 Reserved PCR6 [R/W] 00000000 - FLCR [R/W, R] 000XXXX0 - 0007C4H FWTC [R/W, W] -----000 - 458 Pull-up control Reserved 0007C0H 0007C8H to 0007F8H AMD4 [R/W] 0--00000 - T-unit - 00062CH 000630H AMD32 [R/W] 00000000 EPCR0 [W] ----1100 -1111111 000628H Data direction register FLASH control - Reserved APPENDIX A I/O Map Table A-1 I/O Map (7/7) Address Register +0 +1 - 0007FCH +2 +3 LER [W] -----000 MODR [W] XXXXXXXX Block Little endian register mode register Notes: 1. Do not execute a read-modify-write (RMW) instruction for a register with a write-only bit. 2. Read-modify-write (RMW) instructions: AND Rj, @Ri ANDH Rj, @Ri ANDB Rj, @Ri BANDL #u4, @Ri BANDH #u4, @Ri OR Rj, @Ri ORH Rj, @Ri ORB Rj, @Ri BORL #u4, @Ri BORH #u4, @Ri EOR Rj, @Ri EORH Rj, @Ri EORB Rj, @Ri BEORL #u4, @Ri BEORH #u4, @Ri 3. Reserved or data in (-) areas is undefined. 459 APPENDIX B Interrupt Vectors APPENDIX B Interrupt Vectors Table B-1 is the interrupt vector table. This table lists the MB91150 interrupt sources and assignment of interrupt vectors/interrupt control registers. ■ Interrupt Vectors • ICR00 to ICR47: Register located in the interrupt controller. This register sets an interrupt level for each interrupt request. An ICR is prepared for each interrupt request. • TBR: Register that indicates the first address of the EIT vector table. The address obtained by adding the contents of the TBR and the offset value determined for each EIT interrupt source is a vector address. The 1-Kbyte area starting from the address indicated by the TBR is the EIT vector area. Each vector has a size of four bytes, and the relationship between vector numbers and vector addresses is as follows: vctadr = TBR + vctofs = TBR + (3FCH - 4 x vct) vctadr: Vector address vctofs: Vector offset vct: Vector number Table B-1 Interrupt Vectors (1/4) Interrupt number Interrupt level Offset TBR default address 00 - 3FCH 000FFFFCH 1 01 - 3F8H 000FFFF8H System-reserved 2 02 - 3F4H 000FFFF4H System-reserved 3 03 - 3F0H 000FFFF0H System-reserved 4 04 - 3ECH 000FFFECH System-reserved 5 05 - 3E8H 000FFFE8H System-reserved 6 06 - 3E4H 000FFFE4H System-reserved 7 07 - 3E0H 000FFFE0H System-reserved 8 08 - 3DCH 000FFFDCH System-reserved 9 09 - 3D8H 000FFFD8H System-reserved 10 0A - 3D4H 000FFFD4H System-reserved 11 0B - 3D0H 000FFFD0H Interrupt source Decimal notation Hexadecimal notation Reset 0 System-reserved 460 APPENDIX B Interrupt Vectors Table B-1 Interrupt Vectors (2/4) Interrupt number Interrupt level Offset TBR default address 0C - 3CCH 000FFFCCH 13 0D - 3C8H 000FFFC8H Undefined instruction exception 14 0E - 3C4H 000FFFC4H System-reserved 15 0F - 3C0H 000FFFC0H External interrupt 0 16 10 ICR00 3BCH 000FFFBCH External interrupt 1 17 11 ICR01 3B8H 000FFFB8H External interrupt 2 18 12 ICR02 3B4H 000FFFB4H External interrupt 3 19 13 ICR03 3B0H 000FFFB0H External interrupt 4 20 14 ICR04 3ACH 000FFFACH External interrupt 5 21 15 ICR05 3A8H 000FFFA8H External interrupt 6 22 16 ICR06 3A4H 000FFFA4H External interrupt 7 23 17 ICR07 3A0H 000FFFA0H External interrupts 8 to 15 24 18 ICR08 39CH 000FFF9CH System-reserved 25 19 ICR09 398H 000FFF98H UART0 (reception completed) 26 1A ICR10 394H 000FFF94H UART1 (reception completed) 27 1B ICR11 390H 000FFF90H UART2 (reception completed) 28 1C ICR12 38CH 000FFF8CH UART3 (reception completed) 29 1D ICR13 388H 000FFF88H System-reserved 30 1E ICR14 384H 000FFF84H UART0 (transmission completed) 31 1F ICR15 380H 000FFF80H UART1 (transmission completed) 32 20 ICR16 37CH 000FFF7CH UART2 (transmission completed) 33 21 ICR17 378H 000FFF78H UART3 (transmission completed) 34 22 ICR18 374H 000FFF74H I2C 35 23 ICR19 370H 000FFF70H DMAC (ended with error) 36 24 ICR20 36CH 000FFF6CH Reload timer 0 37 25 ICR21 368H 000FFF68H Reload timer 1 38 26 ICR22 364H 000FFF64H Reload timer 2 39 27 ICR23 360H 000FFF60H Reload timer 3 40 28 ICR24 35CH 000FFF5CH Interrupt source Decimal notation Hexadecimal notation System-reserved 12 System-reserved 461 APPENDIX B Interrupt Vectors Table B-1 Interrupt Vectors (3/4) Interrupt number Interrupt level Offset TBR default address 29 ICR25 358H 000FFF58H 42 2A ICR26 354H 000FFF54H PPG0 43 2B ICR27 350H 000FFF50H PPG1 44 2C ICR28 34CH 000FFF4CH PPG2 45 2D ICR29 348H 000FFF48H PPG3 46 2E ICR30 344H 000FFF44H PPG4 47 2F ICR31 340H 000FFF40H PPG5 48 30 ICR32 33CH 000FFF3CH U/D counter 0 (compare/underflow, overflow, up/down inversion) 49 31 ICR33 338H 000FFF38H U/D counter 1 (compare/underflow, overflow, up/down inversion) 50 32 ICR34 334H 000FFF34H ICU0 (fetch) 51 33 ICR35 330H 000FFF30H ICU1 (fetch) 52 34 ICR36 32CH 000FFF2CH ICU2 (fetch) 53 35 ICR37 328H 000FFF28H ICU3 (fetch) 54 36 ICR38 324H 000FFF24H OCU0 (match) 55 37 ICR39 320H 000FFF20H OCU1 (match) 56 38 ICR40 31CH 000FFF1CH OCU2 (match) 57 39 ICR41 318H 000FFF18H OCU3 (match) 58 3A ICR42 314H 000FFF14H OCU4/5 (match) 59 3B ICR43 310H 000FFF10H OCU6/7 (match) 60 3C ICR44 30CH 000FFF0CH System-reserved 61 3D ICR45 308H 000FFF08H 16-bit free-run timer 62 3E ICR46 304H 000FFF04H Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H System-reserved (used by REALOS*) 64 40 - 2FCH 000FFEFCH System-reserved (used by REALOS*) 65 41 - 2F8H 000FFEF8H System-reserved 66 42 - 2F4H 000FFEF4H System-reserved 67 43 - 2F0H 000FFEF0H Interrupt source Decimal notation Hexadecimal notation System-reserved 41 A/D 462 APPENDIX B Interrupt Vectors Table B-1 Interrupt Vectors (4/4) Interrupt number Interrupt level Offset TBR default address 44 - 2ECH 000FFEECH 69 45 - 2E8H 000FFEE8H System-reserved 70 46 - 2E4H 000FFEE4H System-reserved 71 47 - 2E0H 000FFEE0H System-reserved 72 48 - 2DCH 000FFEDCH System-reserved 73 49 - 2D8H 000FFED8H System-reserved 74 4A - 2D4H 000FFED4H System-reserved 75 4B - 2D0H 000FFED0H System-reserved 76 4C - 2CCH 000FFECCH System-reserved 77 4D - 2C8H 000FFEC8H System-reserved 78 4E - 2C4H 000FFEC4H System-reserved 79 4F - 2C0H 000FFEC0H 80 | 255 50 | FF - Used by INT instruction 2BCH | 000H 00FFEBCH | 00FFC00H Interrupt source Decimal notation Hexadecimal notation System-reserved 68 System-reserved *: REALOS/FR uses 0x40 and 0x41 interrupts for system codes. 463 APPENDIX C Pin Status in Each CPU State APPENDIX C Pin Status in Each CPU State Table C-1 explains the terms related to pin status, and Table C-2 to Table C-4 list the pin status in each CPU state. ■ Terms Related to Pin Status Table C-1 lists the meanings of the terms related to pin status. Table C-1 Terms Related to Pin Status Term Meaning Input enabled This means that the input function can be used. Keep the input at 0 An external input is shut off at the input gate that is nearest to the pin and 0 is internally transferred. Output Hi-Z This means that the pin drive transistor enters the drive-disabled state and that the pin is set to high impedance (Hi-Z). Output retained This means that the output immediately before this mode continues to be outputted. In other words, if built-in peripheral circuit with an output is in operation, output is performed in accordance with that built-in peripheral circuit and retained for port output. Retaining the last status This means that the output status immediately before this mode was entered continues. If input was performed immediately before this mode was entered, this term indicates that input will continue to be enabled. 464 APPENDIX C Pin Status in Each CPU State ■ Pin Status in Each CPU State Table C-2 Pin Status in 16-bit Mode of the External Bus (1/2) Pin name In stop mode Function At reset HIZX=0 P20-7 D16-23 P30-7 D24-31 P40-7 A00-07 P50-7 A08-15 Bus release In sleep mode Output retained or Hi-Z Output retained or Hi-Z HIZX=1 Output Hi-Z or Output Hi-Z keep the input at 0 P60-7 A16-23 P: Last status retained F: Address output P80 RDY P: Last status retained F: RDY input Last status retained or keep the input at 0 BGRNT P: Last status retained F: H output L output P81 BRQ P: Last status retained F: BRQ input BRQ input P82 P83 RD Output Hi-Z P84 WR0 Last status retained P86 WRI P: Last status retained F: H output CLK P: Last status retained F: CLK output PC0-3 INT0-3 Last status retained Output Hi-Z or enable all-pin input FFH output Output retained Output retained (Address output) (Address output) P: Last status retained F: Address output P85 P: Last status retained F: RDY input Output Hi-Z or enable all-pin input H output - Input enabled CLK output CLK output Input enabled Last status retained Output Hi-Z or enable all-pin input PC4 INT4/CS0 P: Last status retained PC5-7 INT5-7/CS1-3 F: CS output Output Hi-Z or Input enabled Last status retained Hi-Z for CS output CS output PD0 AIN0/INT8 Input enabled PD1 BIN0/INT9 Last status retained Output Hi-Z or enable all-pin input PD2 AIN1/INT10 PD3 BIN1/INT11 PD4 ZIN0/INT12 PD5 ZIN1/INT13 PD6 DEOP2/INT14 PD7 ATG/INT15 Last status retained Remarks (BGRNT) 465 APPENDIX C Pin Status in Each CPU State Table C-2 Pin Status in 16-bit Mode of the External Bus (2/2) Pin name In stop mode Function Bus release In sleep mode HIZX=0 HIZX=1 At reset Remarks Output Hi-Z or enable all-pin input - (BGRNT) PE0-7 OC0-7 PF0-3 IN0-3 PF4 Port PG0-5 PPG0-5 PJ0 SCL PJ1 SDA PI0 SIN2 PI1 SOT2 PI2 SCK2/TO2 PI3 SIN3 PI4 SOT3 PI5 SCK3/TO3 PH0 SIN0 PH1 SOT0 PH2 SCK0/TO0 PH3 SIN1 PH4 SOT1 PH5 SCK1/TO1 Last status retained PK0-7 AN0-7 PL0 DREQ0 PL1 DACK0 PL2 DEOP0 PL3 DREQ1 PL4 DACK1 PL5 DEOP1 PL6 DREQ2 PL7 DACK2 P: At selection of general-purpose port F: At selection of specified function 466 Last status Output Hi-Z or Last status retained or keep keep the input at retained the input at 0 0 APPENDIX C Pin Status in Each CPU State Table C-3 Pin Status in External Bus 8-bit Mode (1/2) Pin name In stop mode Function At reset HIZX=0 P20-7 Port Last status retained Last status retained P30-7 D24-31 Output retained or Hi-Z Output retained or Hi-Z P40-7 A00-07 P50-7 A08-15 HIZX=1 P60-7 A16-23 P: Last status retained F: Address output P80 RDY P: Last status retained F: RDY input P81 BGRNT P: Last status retained F: H output Last status retained or keep the input at 0 P82 BRQ P: Last status retained F: BRQ input P83 RD P84 WR0 P85 Port P86 CLK Output Hi-Z or Last status keep the input at retained 0 Output Hi-Z Output Hi-Z or enable all-pin input FFH output P: Last status retained F: RDY input Output Hi-Z or enable all-pin input L output BRQ input Output Hi-Z H output Last status retained Output Hi-Z or enable all-pin input CLK output CLK output Input enabled Last status retained Output Hi-Z or enable all-pin input Last status retained P: Last status retained F: CLK output Last status retained Input enabled PC4 INT4/CS0 P: Last status retained PC5-7 INT5-7/CS1-3 F: CS output Output Hi-Z or input enabled Last status retained/ Hi-Z for CS output CS output PD0 AIN0/INT8 Input enabled PD1 BIN0/INT9 Last status retained Output Hi-Z or enable all-pin input PD2 AIN1/INT10 PD3 BIN1/INT11 PD4 ZIN0/INT12 PD5 ZIN1/INT13 PD6 DEOP2/INT14 PD7 ATG/INT15 Last status retained Remarks (BGRNT) Output retained Output retained (Address output) (Address output) P: Last status retained F: Address output PC0-3 INT0-3 Bus release In sleep mode 467 APPENDIX C Pin Status in Each CPU State Table C-3 Pin Status in External Bus 8-bit Mode (2/2) Pin name In stop mode Function Bus release In sleep mode HIZX=0 HIZX=1 At reset Remarks Output Hi-Z or enable all-pin input - (BGRNT) PE0-7 OC0-7 PF0-3 IN0-3 PF4 Port PG0-5 PPG0-5 PJ0 SCL PJ1 SDA PI0 SIN2 PI1 SOT2 PI2 SCK2/TO2 PI3 SIN3 PI4 SOT3 PI5 SCK3/TO3 PH0 SIN0 PH1 SOY0 PH2 SCK0/TO0 PH3 SIN1 PH4 SOT1 PH5 SCK1/TO1 Last status retained PK0-7 AN0-7 PL0 DREQ0 PL1 DACK0 PL2 DEOP0 PL3 DREQ1 PL4 DACK1 PL5 DEOP1 PL6 DREQ2 PL7 DACK2 P: At selection of general-purpose port F: At selection of specified function 468 Last status Output Hi-Z or Last status retained or keep keep the input at retained the input at 0 0 APPENDIX C Pin Status in Each CPU State Table C-4 Pin Status in Single-chip Mode (1/2) Pin name In stop mode Function In sleep mode HIZX=0 P20-7 Port P30-7 Last status retained - At reset Remarks - Output Hi-Z or enable all-pin input - HIZX=1 Last status Output Hi-Z or retained or keep keep the input at the input at 0 0 P40-7 P50-7 P60-7 P80 P81 P82 P83 P84 P85 P86 CLK PC0-7 INT0-7 PD0 AIN0/INT8 PD1 BIN0/INT9 PD2 AIN1/INT10 PD3 BIN1/INT11 PD4 ZIN0/INT12 PD5 ZIN1/INT13 PD6 DEOP2/INT14 PD7 ATG/INT15 PE0-7 OC0-7 PF0-3 IN0-3 PF4 Input enabled Input enabled Last status Output Hi-Z or retained or keep keep the input at the input at 0 0 Port PG0-5 PPG0-5 PJ0 SCL PJ1 SDA PI0 SIN2 PI1 SOT2 PI2 SCK2/TO2 PI3 SIN3 PI4 SOT3 PI5 SCK3/TO3 PH0 SIN0 PH1 SOT0 PH2 SCK0/TO0 469 APPENDIX C Pin Status in Each CPU State Table C-4 Pin Status in Single-chip Mode (2/2) Pin name In stop mode Function In sleep mode HIZX=0 PH3 SIN1 PH4 SOT1 PH5 SCK1/TO1 Last status retained PK0-7 AN0-7 PL0 DREQ0 PL1 DACK0 PL2 DEOP0 PL3 DREQ1 PL4 DACK1 PL5 DEOP1 PL6 DREQ2 PL7 DACK2 P: At selection of general-purpose port F: At selection of specified function 470 - At reset Remarks - Output Hi-Z or enable all-pin input - HIZX=1 Last status Output Hi-Z or retained or keep keep the input at the input at 0 0 APPENDIX D Notes on Using the Little-Endian Area APPENDIX D Notes on Using the Little-Endian Area This appendix provides notes on using the little-endian area for each of the following items: D.1 C Compiler (fcc911) D.2 Assembler (fasm911) D.3 Linker (flnk911) D.4 Debuggers (sim911, eml911, and mon911) 471 APPENDIX D Notes on Using the Little-Endian Area D.1 C Compiler (fcc911) When programming in C, note that the operation result is unpredictable if the following operations are performed for the little-endian area: • Allocation of variables having initial values • Structure insertion • Manipulation of a non-character type array by using a character-string handling function • Specification of the -K lib option during use of a character-string handling function • Using the double type and long-double type • Allocating stacks in the little-endian area ■ Allocation of Variables Having Initial Values A variable having an initial value cannot be allocated in the little-endian area. The compiler has no function for generating initial values in the little-endian area. The compiler can allocate variables in the little-endian area; however, it cannot set initial values in this area. Perform the processing for setting the initial value at the beginning of the program. [Example] Setting of an initial value for the variable little_data in the little-endian area extern int little_data; void little_init(void) { little_data = initial-value; } void main(void) { little_init(); ... } ■ Structure Insertion For insertion between structures, the compiler selects the optimum transfer method to perform transfer byte-by-byte, half word-by-half word, or word-by-word. If structure insertion is performed between structure variables allocated in an ordinary area and those allocated in the little-endian area, the obtained results will not be correct. Insert structure members, respectively. [Example] Structure insertion in the structure variable little_st of the little-endian area struct tag { char c; int i;} normal_st; extern struct tag little_st; #define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i; void main(void) { STRMOVE(little_st,normal_st); } 472 APPENDIX D Notes on Using the Little-Endian Area The location of the structure member differs for each compiler. So, the member location may differ from that of a structure generated by another compiler. If this occurs, the method previously explained will not produce correct results. If structure member locations do not match, do not allocate structure variables in the little-endian area. ■ Manipulation of a Non-character Type Array by Using a Character-string Handling Function The character-string handling functions provided in the standard library perform processing in units of bytes. They will therefore not produce correct results if processing is performed by using a character-string handling function for an area with a type other than char, unsigned char, and signed char allocated in the little-endian area. Do not attempt to perform such processing. [Erroneous example] Transfer of word data with memcpy int big = 0x01020304; /* extern int little; /* memcpy(&little,&big,4); /* Big-endian area Little-endian area Transfer with memcpy */ */ */} The execution result of the above example is shown below. It is wrong as result of a word-data transfer. (Big-endian area) 01 02 03 (Little-endian area) 04 memcpy 01 02 03 04 (Correct result) 04 03 02 01 ■ Specification of the -K lib Option During Use of a Character-string Handling Function When the -K lib option is specified, the compiler performs inline expansion for some characterstring handling functions. To optimize processing, the compiler may change the processing to half word-level or word-level processing. This type of processing does therefore not lead to the correct results for a little-endian area. When processing is performed for the little-endian area by using character-string-handling functions, do not specify the -K lib option. Do not specify the -04 option, which contains the -K lib option, or the -K speed option. 473 APPENDIX D Notes on Using the Little-Endian Area ■ Using Double Type and Long-double Type During access to data of double or long-double type, a word in either the higher bits or the lower bits of the data is accessed. Access to double type and long-double type variables allocated in the little-endian area does therefore not produce correct results. Variables of the same type allocated in the little-endian area can be replaced by each other. However, as a result of optimization, these insertions may be performed as constant insertions. Do not allocate variables of double type and long-double type in the little-endian area. [Erroneous example] Transfer of double-type data double big = 1.0; /* extern int little; /* little = big; /* Big-endian area Little-endian area Transfer of double-type data */ */ */ The execution result of the above example is shown below. It is not correct as result of a doubletype data transfer. (Big-endian area) 3f f0 00 00 00 00 (Little-endian area) 00 00 (Correct result) 00 00 f0 3f 00 00 00 00 00 00 00 00 00 00 f0 3f ■ Allocation of Stacks in the Little-endian area Integrity of operation results cannot be assured if all or some stacks are allocated in the littleendian area. 474 APPENDIX D Notes on Using the Little-Endian Area D.2 Assembler (fasm911) When programming in the assembler language for the FR family, note the following for the little-endian area with respect to the items below: • Sections • Data access ■ Sections The little-endian area is used mainly for data exchange with CPUs employing the little-endian system. Define this area as a data section without initial values. If a code, stack, or data section with initial values is specified in the little-endian area, the integrity of access operations of the MB91150 cannot be assured. [Example] /* Correct section definition for the little-endian area */ .SECTION Little_Area, DATA, ALIGN=4 Little_Word: .RES.W 1 Little_Half:' .RES.H 1 Little_Byte: .RES.B 1 ■ Data Access To execute a data access to the little-endian area, the data value can be coded without considering that the value is allocated in the endian area. However, be sure to use a data access matching the data length in the little-endian area. [Example] LDI #0x01020304, r0 LDI #Little_Word, r1 LDI #0x0102, r2 LDI #Little_Half, r3 LDI #0x01, r4 LDI #Little_Byte, r5 */ 32-bit data is accessed with the ST (or LD) instruction. */ ST r0, @r1 */ 16-bit data is accessed with the STH (or LDH) instruction. */ STH r2, @r3 */ 8-bit data is accessed with the STB (or LDB) instruction. */ STB r4, @r5 In the MB91150, if a data access operation that does not match the data length in the little-endian area, the integrity of the results cannot be assured. For example, if two consecutive 16-bit data items are accessed at the same time with a 32-bit access instruction, the integrity of the data values cannot be assured. 475 APPENDIX D Notes on Using the Little-Endian Area D.3 Linker (flnk911) This section provides notes related to the following topics for the section placement at linkage when a program that uses the little-endian area is to be created: • Restriction on section types • Failure to detect errors ■ Restriction on Section Types Only data sections without initial values can be allocated in the little-endian area. Assume that a data section, stack section, and code section having initial values is placed in the little-endian area. Because the linker internally performs such arithmetic operations as resolving addresses in big-endian mode, the correctness of program operation cannot be assured. ■ Failure to Detect Errors The linker is not aware of the little-endian area. Because of this, no error message is posted if an allocation in violation of the above restriction is made. Use the linker after thoroughly confirming the contents of the section allocated in the little-endian area. 476 APPENDIX D Notes on Using the Little-Endian Area D.4 Debuggers (sim911, eml911, and mon911) This section provides notes on using the simulator debugger, emulator debugger, and monitor debugger. ■ Simulator Debugger There is no memory space specification command that explicitly indicates the little-endian area. Therefore, memory operation commands and memory operation instructions are handled in bigendian mode. ■ Emulator Debugger and Monitor Debugger Note that, if the following commands are used to access the little-endian area, data values are handled as incorrect: ❍ set memory, show memory, enter, examine, and set watch commands If floating-point (single or double) data is handled, the specified value cannot be set or displayed. ❍ search memory command Half word or word data is not searched with the specified value. ❍ Line or reverse assembling (this includes reverse assembling of the contents in the sourcecode window) Normal instruction code cannot be set or displayed. (Do not set any instruction code in the littleendian area.) ❍ call and show call commands If the stack area is allocated in the little-endian area, operation is not performed normally. (Do not allocate the stack area in the little-endian area.) 477 APPENDIX E Instruction Lists APPENDIX E Instruction Lists This appendix lists the FR family instructions. For facilitating understanding the instruction list, notes on the following items are provided: • How to read the instruction lists • Addressing mode symbols • Instruction format ■ How to Read the Instruction Lists Mnemonic Type OP CYCLE NZVC Operation Remarks ADD Rj, Rj *ADD #s5, Rj , , A C , , AG A4 , , 1 1 , , CCCC CCCC , , Ri + Rj --> Rj Ri + s5 --> Ri , , - 3) 4) 5) 6) 7) 1) 2) 1) Indicates an instruction name. • An asterisk (*) indicates an extended instruction which is not listed in the CPU specifications and which was obtained by extending or adding an instruction with the assembler. 2) Indicates the addressing mode specifiable in an operand, with its symbol. • For the meaning of the symbols, see the sub-section on "■Addressing mode symbols". 3) Indicates the instruction format. 4) Indicates an instruction code in hexadecimal notation. 5) Indicates the number of machine cycles for the instruction. • a: Memory access cycle. It may be extended by the Ready function. • b: Memory access cycle. It may be extended by the Ready function. However, when the succeeding instruction references the register subject to LD operation, an interlock occurs and the number of execution cycles is incremented by one. • c: When the succeeding instruction performs reading or writing for R15, SSP, or USP, or it has instruction format A, an interlock occurs, and the number of execution cycles is incremented by one and becomes 2. • d: When the succeeding instruction references MDH or MDL, an interlock occurs and the number of execution cycles increments and becomes 2. • The minimum number of cycles is 1 for a, b, c, and d. 478 APPENDIX E Instruction Lists 6) Indicates flag changes. Flag change C: Change -: No change 0: Clear 1: Set Flag meaning N: Negative flag Z: Zero flag V: Overflow flag C: Carry flag 7) Indicates the operation of the instruction. ■ Addressing Mode Symbols Table E-1 Explanations of the addressing Mode Symbols (1/2) Symbol Meaning Ri Register direct (R0 to R15, AC, FP, and SP) Rj Register direct (R0 to R15, AC, FP, and SP) R13 Register direct (R13 and AC) Ps Register direct (program status register) Rs Register direct (TBR, RP, SSP, USP, MDH, and MDL) CRi Register direct (CR0 to CR15) CRj Register direct (CR0 to CR15) #i8 Unsigned 8-bit immediate value (-128 to 255) Note: -128 to -1 are handled as 128 to 255. #i20 Unsigned 20-bit immediate value (-0x80000 to 0xFFFFF) Note: -0x7FFFF to -1 are handled as 0x7FFFF to 0xFFFFF. #i32 Unsigned 32-bit immediate value (-0x80000000 to 0xFFFFFFFF) Note: -0x80000000 to -1 are handled as 0x80000000 to 0xFFFFFFFF. #s5 Signed 5-bit immediate value (-16 to 15) #s10 Signed 10-bit immediate value (-512 to 508, only multiples of 4) #u4 Unsigned 4-bit immediate value (0 to 15) #u5 Unsigned 5-bit immediate value (0 to 31) #u8 Unsigned 8-bit immediate value (0 to 255) #u10 Unsigned 10-bit immediate value (0 to 1020, only multiples of 4) @dir8 Unsigned 8-bit direct address (0 to 0xFF) @dir9 Unsigned 9-bit direct address (0 to 0x1FE, only multiples of 2) @dir10 Unsigned 10-bit direct address (0 to 0x3FC, only multiples of 4) label9 Signed 9-bit branch address (-0x100 to 0xFC, only multiples of 2) 479 APPENDIX E Instruction Lists Table E-1 Explanations of the addressing Mode Symbols (2/2) Symbol 480 Meaning label12 Signed 12-bit branch address (-0x800 to 0x7FC, only multiples of 2) label20 Signed 20-bit branch address (-0x80000 to 0x7FFFF) label32 Signed 20-bit branch address (-0x80000 to 0x7FFFF) @Ri Signed 32-bit branch address (-0x80000000 to 0x7FFFFFFF) @Rj Register indirect (R0 to R15, AC, FP, and SP) @(R13,Rj) Register relative indirect (Rj: R0 to R15, AC, FP, and SP) @(R14,disp10) Register relative indirect (disp10: -0x200 to 0x1FC, only multiples of 4) @(R14,disp9) Register relative indirect (disp9: -0x100 to 0xFE, only multiples of 2) @(R14,disp8) Register relative indirect (disp8: -0x80 to 0x7F) @(R15,udisp6) Register relative indirect (udisp6: 0 to 60, only multiples of 4) @Ri+ Register indirect with post-increment (R0 to R15, AC, FP, and SP) @R13+ Register indirect with post-increment (R13 and AC) @SP+ Stack pop @-SP Stack push (reglist) Register list APPENDIX E Instruction Lists ■ Instruction Format Table E-2 Instruction Format Type Instruction format A MSB LSB 16 bit OP Rj Ri 8 4 4 B OP i8/o8 Ri 8 4 4 C OP u4/m4 Ri 8 4 4 C’ Only for ADD, ADDN, CMP, LSL, LSR, and ASR instructions OP s5/u5 Ri 7 5 4 OP u8/re18/dir/ reglist 8 8 D E OP SUB-OP Ri 8 4 4 F OP re111 5 11 481 APPENDIX E Instruction Lists E.1 FR Family Instruction Lists This section provides lists of the FR family instructions in the following order. ■ FR Family Instruction Lists 482 • Table E.1-1 "Addition and subtraction instructions" • Table E.1-2 "Comparison operation instructions" • Table E.1-3 "Logical operation instructions" • Table E.1-4 "Bit manipulation instructions" • Table E.1-5 "Multiplication and division instructions" • Table E.1-6 "Shift instructions" • Table E.1-7 "Immediate value set, 16-bit immediate value, and 32-bit immediate value transfer instructions" • Table E.1-8 "Memory load instructions" • Table E.1-9 "Memory store instructions" • Table E.1-10 "Register-to-register transfer instructions" • Table E.1-11 "Ordinary branch (no delay) instructions" • Table E.1-12 "Delayed branch instructions" • Table E.1-13 "Other instructions" • Table E.1-14 "20-bit ordinary branch macroinstructions" • Table E.1-15 "20-bit delayed branch macroinstructions" • Table E.1-16 "32-bit ordinary branch macroinstructions" • Table E.1-17 "32-bit delayed branch macroinstructions" • Table E.1-18 "Direct addressing instructions" • Table E.1-19 "Resource instructions" • Table E.1-20 "Coprocessor control instructions" APPENDIX E Instruction Lists ■ Addition and Subtraction Instructions Table E.1-1 Addition and Subtraction Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks ADD Rj, Ri A A6 1 CCCC Ri+Rj --> Ri *ADD #s5, Ri C’ A4 1 CCCC Ri+s5 --> Ri The assembler assumes the higher one bit to be a symbol. ADD #u4, Ri C A4 1 CCCC Ri+extu(i4) --> Ri Zero extension ADD2 #u4, Ri C A5 1 CCCC Ri+extu(i4) --> Ri Minus extension ADDC Rj, Ri A A7 1 CCCC Ri+Rj + c --> Ri Addition with carries ADDN Rj, Ri A A2 1 ---- Ri+Rj --> Ri *ADDN #s5, Ri C’ A0 1 ---- Ri+s5 --> Ri The assembler assumes the higher one bit to be a symbol. ADDN #u4, Ri C A0 1 ---- Ri+extu(i4) --> Ri Zero extension ADDN2 #u4, Ri C A1 1 ---- Ri+extu(i4) --> Ri Minus extension SUB Rj, Ri A AC 1 CCCC Ri - Rj --> Ri SUBC Rj, Ri A AD 1 CCCC Ri - Rj - c --> Ri SUBN Rj, Ri A AE 1 ---- Subtraction with carries Ri - Rj --> Ri - ■ Comparison Operation Instruction Table E.1-2 Comparison Operation Instruction Mnemonic Type OP CYCLE NZVC Operation Remarks CMP Rj, Ri A AA 1 CCCC Ri - Rj *CMP #s5, Ri C’ A8 1 CCCC Ri - s5 The assembler assumes the higher one bit to be a symbol. CMP #u4, Ri C A8 1 CCCC Ri - extu(i4) Zero extension CMP2 #u4, Ri C A9 1 CCCC Ri - extu(i4) Minus extension 483 APPENDIX E Instruction Lists ■ Logical Operation Instructions Table E.1-3 Logical Operation Instructions Mnemonic Type OP CYCLE NZVC AND Rj, Ri A 82 1 CC-- Ri &= Rj - Word AND Rj, @Ri A 84 1+2a CC-- (Ri) &= Rj ❍ Word ANDH Rj, @Ri A 85 1+2a CC-- (Ri) &= Rj ❍ Half word ANDB Rj, @Ri A 86 1+2a CC-- (Ri) &= Rj ❍ Byte OR Rj, Ri A 92 1 CC-- Ri |= Rj - Word OR Rj, @Ri A 94 1+2a CC-- (Ri) |= Rj ❍ Word ORH Rj, @Ri A 95 1+2a CC-- (Ri) |= Rj ❍ Half word ORB Rj, @Ri A 96 1+2a CC-- (Ri) |= Rj ❍ Byte EOR Rj, Ri A 9A 1 CC-- Ri ^= Rj - Word EOR Rj, @Ri A 9C 1+2a CC-- (Ri) ^= Rj ❍ Word EORH Rj, @Ri A 9D 1+2a CC-- (Ri) ^= Rj ❍ Half word EORB Rj, @Ri A 9E 1+2a CC-- (Ri) ^= Rj ❍ Byte 484 Operation RMW Remarks APPENDIX E Instruction Lists ■ Bit Manipulation Instructions Table E.1-4 Bit Manipulation Instructions Mnemonic RMW Remarks (Ri) &=(0xF0+u4) ❍ Manipulation of the lower four bits ---- (Ri) &=((u4<<4)+0x0F) ❍ Manipulation of the higher four bits ---- (Ri) &=u8 - Type OP CYCLE NZVC BANDL #u4, @Ri C 80 1+2a ---- BANDH #u4, @Ri C 81 1+2a *BAND #u8, @Ri*1 Operation BORL #u4, @Ri C 90 1+2a ---- (Ri) |= u4 ❍ Manipulation of the lower four bits BORH #u4, @Ri C 91 1+2a ---- (Ri) |= (u4<<4) ❍ Manipulation of the higher four bits ---- (Ri) |= u8 - *BOR #u8, @Ri*2 BEORL #u4, @Ri C 98 1+2a ---- (Ri) ^= u4 ❍ Manipulation of the lower four bits BEORH #u4, @Ri C 99 1+2a ---- (Ri) ^= (u4<<4) ❍ Manipulation of the higher four bits ---- (Ri) ^= u8 - *BEOR #u8, @Ri*3 BTSTL #u4, @Ri C 88 2+a 0C-- (Ri) & u4 - Manipulation of the lower four bits BTSTH #u4, @Ri C 89 2+a CC-- (Ri) & (u4<<4) - Manipulation of the higher four bits *1: If the bit is set for u8&0x0F, the assembler generates BANDL. If the bit is set for u8&0xF0, the assembler generates BANDH. The assembler may generate both BANDL and BANDH. *2: If the bit is set for u8&0x0F, the assembler generates BORL. If the bit is set for u8&0xF0, the assembler generates BORH. The assembler may generate both BORL and BORH. *3: If the bit is set for u8&0x0F, the assembler generates BEORL. If the bit is set for u8&0xF0, the assembler generates BEORH. The assembler may generate both BEORL and BEORH. 485 APPENDIX E Instruction Lists ■ Multiplication and Division Instructions Table E.1-5 Multiplication and Division Instructions Mnemonic Type OP CYCLE NZVC MUL Rj,Ri A AF 5 CCC- Ri × Rj --> MDH,MDL 32bit×32bit=64bit MULU Rj,Ri A AB 5 CCC- Ri × Rj --> MDH,MDL Unsigned MULH Rj,Ri A BF 3 CC-- Ri × Rj --> MDL 16bit×16bit=32bit MULUH Rj,Ri A BB 3 CC-- Ri × Rj --> MDL Unsigned DIV0S Ri E 97-4 1 ---- Step operation DIV0U Ri E 97-5 1 ---- 32bit/32bit=32bit DIV1 Ri E 97-6 d -C-C E 97-7 1 -C-C DIV3 E 9F-6 1 ---- DIV4S E 9F-7 1 ---- *DIV Ri*1 36 -C-C MDL / Ri --> MDL, MDL % Ri--> MDH *DIVU Ri*2 33 -C-C MDL / Ri --> MDL, MDL % Ri--> MDH DIV2 Ri *3 Operation Remarks *1: Generates DIVOS, DIV1 x 32, DIV2, DIV3, and DIV4S. The instruction code length is 72 bytes. *2: Generates DIVOU and DIV1 x 32. The instruction code length is 66 bytes. *3: Be sure to place the DIV3 instruction after the DIV2 instruction. 486 APPENDIX E Instruction Lists ■ Shift Instructions Table E.1-6 Shift Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks LSL Rj, Ri A B6 1 CC-C Ri << Rj --> Ri *LSL # u5, Ri (u5:0 to 31) C’ B4 1 CC-C Ri << u5 --> Ri LSL #u4, Ri C B4 1 CC-C Ri << u4 --> Ri LSL2 #u4, Ri C B5 1 CC-C Ri <<(u4+16) --> Ri LSR Rj, Ri A B2 1 CC-C Ri << Rj --> Ri *LSR # u5, Ri (u5:0 to 31) C’ B0 1 CC-C Ri << u5 --> Ri LSR #u4, Ri C B0 1 CC-C Ri << u4 --> Ri LSR2 #u4, Ri C B1 1 CC-C Ri <<(u4+16) --> Ri ASR Rj, Ri A BA 1 CC-C Ri << Rj --> Ri *ASR # u5, Ri (u5:0 to 31) C’ B8 1 CC-C Ri << u5 --> Ri ASR #u4, Ri C B8 1 CC-C Ri << u4 --> Ri ASR2 #u4, Ri C B9 1 CC-C Ri <<(u4+16) --> Ri Logical shift Logical shift Arithmetic shift ■ Immediate Value Set, 16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions Table E.1-7 Immediate Value Set, 16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions Mnemonic Type OP CYCLE NZVC LDI:32 #i32, Ri E 9F-8 3 ---- i32 --> Ri LDI:20 #i20, Ri C 9B 2 ---- i20 --> Ri The higher 12 bits are zero-extended. LDI:8 #i8, Ri B C0 1 ---- i8 --> Ri The higher 24 bits are zero-extended. *LDI # {i8|i20|i32}, Ri* Operation Remarks {i8|i20|i32} --> Ri *: If an immediate value is an absolute value, the assembler automatically selects i8, i20, or i32. If the immediate value contains a relative value or external reference symbol, i32 is selected. 487 APPENDIX E Instruction Lists ■ Memory Load Instructions Table E.1-8 Memory Load Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks LD @Rj, Ri A 04 b ---- (Rj) --> Ri LD @(R13,Rj), Ri A 00 b ---- (R13+Rj) --> Ri LD @(R14,disp10), Ri B 20 b ---- (R14+disp10) --> Ri LD @(R15,udisp6), Ri C 03 b ---- (R15+udisp6) --> Ri LD @R15+, Ri E 07-0 b ---- (R15) --> Ri,R15+=4 LD @R15+, Rs E 07-8 b ---- (R15) --> Rs, R15+=4 LD @R15+, PS E 07-9 1+a+b CCCC (R15) --> PS, R15+=4 LDUH @Rj, Ri A 05 b ---- (Rj) --> Ri Zero extension LDUH @(R13,Rj), Ri A 01 b ---- (R13+Rj) --> Ri Zero extension LDUH @(R14,disp9), Ri B 40 b ---- (R14+disp9) --> Ri Zero extension LDUB @Rj, Ri A 06 b ---- (Rj) --> Ri Zero extension LDUB @(R13,Rj), Ri A 02 b ---- (R13+Rj) --> Ri Zero extension LDUB @(R14,disp8), Ri B 60 b ---- (R14+disp8) --> Ri Zero extension Rs: Special registers* * : Special registers Rs: TBR, RP, USP, SSP, MDH, and MDL Note: The assembler performs calculations as shown below and sets values in the o8 and o4 fields of the hardware specifications: disp10/4 --> o8, disp9/2 --> o8, and disp8 --> o8. disp10, disp9, and disp8 are signed operands. udisp6/4 --> o4. udisp6 is an unsigned operand. 488 APPENDIX E Instruction Lists ■ Memory Store Instructions Table E.1-9 Memory Store Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks ST Ri, @ Rj A 14 a ---- Ri --> (Rj) Word ST Ri, @ (R13,Rj) A 10 a ---- Ri --> (R13+Rj) Word ST Ri, @ (R14,disp10) B 30 a ---- Ri --> (R14+disp10) Word ST Ri, @ (R15,udisp6) C 13 a ---- Ri --> (R15+udisp6) ST Ri, @ -R15 E 17-0 a ---- R15-=4,Ri --> (R15) ST Rs, @ -R15 E 17-8 a ---- R15-=4, Rs --> (R15) ST PS, @ -R15 E 17-9 a ---- R15-=4, PS --> (R15) STH Ri, @ Rj A 15 a ---- Ri --> (Rj) Half word STH Ri, @ (R13,Rj) A 11 a ---- Ri --> (R13+Rj) Half word STH Ri, @ (R14,disp9) B 50 a ---- Ri --> (R14+disp9) Half word STB Ri, @ Rj A 16 a ---- Ri --> (Rj) Byte STB Ri, @ (R13,Rj) A 12 a ---- Ri --> (R13+Rj) Byte STB Ri, @ (R14,disp8) B 70 a ---- Ri --> (R14+disp8) Byte Rs: Special registers* * : Special registers Rs: TBR, RP, USP, SSP, MDH, and MDL Note: The assembler performs calculations as shown below and sets values in the o8 and o4 fields within the hardware specifications: disp10/4 --> o8, disp9/2 --> o8, and disp8 --> o8. disp10 disp9, and disp8 are signed operands. udisp6/4 --> o4. udisp6 is an unsigned operand. ■ Register-to-register Transfer Instructions Table E.1-10 Register-to-register Transfer Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks MOV Rj, Ri A 8B 1 ---- Rj --> Ri Transfer between generalpurpose registers MOV Rs, Ri A B7 1 ---- Rs --> Ri Rs: Special registers* MOV Ri, Rs A B3 1 ---- Ri --> Rs Rs: Special registers* MOV PS, Ri E 17-1 1 ---- PS --> Ri MOV Ri, PS E 07-1 c CCCC Ri --> PS * : Special registers Rs: TBR, RP, USP, SSP, MDH, and MDL 489 APPENDIX E Instruction Lists ■ Ordinary Branch (No Delay) Instructions Table E.1-11 Ordinary Branch (No Delay) Instructions Mnemonic Type OP CYCLE NZVC Operation JMP @Ri E 97-0 2 ---- Rj --> PC - CALL label12 F D0 2 ---- PC+2 --> RP, PC+2+(label12-PC-2) --> PC - CALL @Ri E 97-1 2 ---- PC+2 --> RP ,Ri --> PC RET E 97-2 2 ---- RP --> PC D 1F 3+3a ---- SSP-=4,PS --> (SSP), SSP-=4,PC+2 --> (SSP), 0 --> I flag, 0 --> S flag (TBR+0x3FC-u8 x 4) --> PC INTE E 9F-3 3+3a ---- SSP-=4,PS --> (SSP), SSP-=4,PC+2 --> (SSP), 0 --> S flag (TBR+0x3D8) --> PC RET1 E 97-3 2+2a CCCC INT #u8 (R15) --> PC,R15-=4, (R15) --> PS,R15-=4 BRA label9 D E0 2 ---- PC+2+(label9-PC-2) --> PC BNO label9 D E1 1 ---- No branch BEQ label9 D E2 2/1 ---- if(Z==1) then PC+2+(label9-PC-2) --> PC BNE label9 D E3 2/1 ---- s/Z==0 BC label9 D E4 2/1 ---- s/C==1 BNC label9 D E5 2/1 ---- s/C==0 BN label9 D E6 2/1 ---- s/N==1 BP label9 D E7 2/1 ---- s/N==0 BV label9 D E8 2/1 ---- s/V==1 BNV label9 D E9 2/1 ---- s/V==0 BLT label9 D EA 2/1 ---- s/V xor N==1 BGE label9 D EB 2/1 ---- s/V xor N==0 BLE label9 D EC 2/1 ---- s/(V xor N) or Z==1 BGT label9 D ED 2/1 ---- s/(V xor N) or Z==0 BLS label9 D EE 2/1 ---- s/C or Z==1 BHI label9 D EF 2/1 ---- s/C or Z==0 Remarks Return For the emulator - - Notes: • 2/1 in the number of CYCLEs indicates 2 for a branch and 1 for no branch. • The assembler performs calculations as shown below and sets values in the rel11 and rel8 fields of the hardware specifications: (label12-PC-2)/2 --> rel11 and (label9-PC-2)/2 --> rel8. label12 and label9 are signed operands. • To execute the RETI instruction, the S flag must be 0. 490 APPENDIX E Instruction Lists ■ Delayed Branch Instructions Table E.1-12 Delayed Branch Instructions Mnemonic Type OP CYCLE NZVC Operation JMP:D @Ri E 9F-0 1 ---- Ri --> PC - CALL:D label12 F D8 1 ---- PC+4 --> RP , PC+2+(label12-PC-2) --> PC - CALL:D @Ri E 9F-1 1 ---- PC+4 --> RP ,Ri --> PC RET:D E 9F-2 1 ---- RP --> PC BRA:D label9 D F0 1 ---- PC+2+(label9-PC-2) --> PC BNO:D label9 D F1 1 ---- No branch BEQ:D label9 D F2 1 ---- if(Z==1) then PC+2+(label9-PC-2) --> PC BNE:D label9 D F3 1 ---- s/Z==0 BC:D label9 D F4 1 ---- s/C==1 BNC:D label9 D F5 1 ---- s/C==0 BN:D label9 D F6 1 ---- s/N==1 BP:D label9 D F7 1 ---- s/N==0 BV:D label9 D F8 1 ---- s/V==1 BNV:D label9 D F9 1 ---- s/V==0 BLT:D label9 D FA 1 ---- s/V xor N==1 BGE:D label9 D FB 1 ---- s/V xor N==0 BLE:D label9 D FC 1 ---- s/(V xor N) or Z==1 BGT:D label9 D FD 1 ---- s/(V xor N) or Z==0 BLS:D label9 D FE 1 ---- s/C or Z==1 BHI:D label9 D FF 1 ---- s/C or Z==0 Remarks Return - Notes: • The assembler performs calculations as shown below and sets values in the rel11 and rel8 fields of the hardware specifications: (label12-PC-2)/2 --> rel11 and (label9-PC-2)/2 --> rel8. label12 and label9 are signed labels. • In a delayed branch, a branch will occur after the next instruction (delayed slot) is executed. • The instructions that can be placed in delayed slots are all one-cycle, a-cycle, b-cycle, c-cycle, and d-cycle instructions. Multiple-cycle instructions cannot be placed in delayed slots. 491 APPENDIX E Instruction Lists ■ Other Instructions Table E.1-13 Other Instructions RMW Remarks No change - - CCCC CCR and u8 --> CCR - c CCCC CCR or u8 --> CCR - 87 1 ---- i8 --> ILM - ILM immediate value set D A3 1 ---- R15 += s10 - ADD SP instruction EXTSB Ri E 97-8 1 ---- Sign extension 8 --> 32bit - EXTUB Ri E 97-9 1 ---- Zero extension 8 --> 32bit - EXTSH Ri E 97-A 1 ---- Sign extension 16 --> 32bit - EXTUH Ri E 97-B 1 ---- Zero extension 16 --> 32bit - LDM0 (reglist) D 8C - ---- (R15) --> reglist, R15 increment - Load multiple R0 to R7 LDM1 (reglist) D 8D ---- (R15) --> reglist, R15 increment - Load multiple R8 to R15 (R15) --> reglist, R15 increment - Load multiple R0 to R15 ---- R15 decrement reglist --> (R15) - Store multiple R0 to R7 ---- R15 decrement reglist --> (R15) - Store multiple R8 to R15 R15 decrement reglist --> (R15) - Store multiple R0 to R15 Mnemonic Type OP CYCLE NZVC NOP E 9F-A 1 ---- ANDCCR #u8 D 93 c ORCCR #u8 D 83 STILM #u8 D ADDSP #s10*1 *LDM (reglist)*2 STM0 (reglist) D 8E STM1 (reglist) D 8F - *STM (reglist)*3 Operation - - ENTER #u10*4 D 0F 1+a ---- R14 --> (R15 - 4), R15 - 4 --> R14, R15 - u10 --> R15 - Entry processing of a function LEAVE E 9F-9 b ---- R14 + 4 --> R15, (R15 - 4) --> R14 - Exit processing of a function A 8A 2a ---- Ri --> TEMP (Rj) --> Ri TEMP --> (Rj) ❍ For semaphore control Byte data XCHB @Rj, Ri *1: The assembler changes s10 to s8 by calculating s10/4 and sets a value. s10 is a signed value. *2: If reglist specifies any of R0 to R7, the assembler generates LDM0. If reglist specifies any of R8 to R15, the assembler generates LDM1. The assembler may generate both LDM0 and LDM1. *3: If reglist specifies any of R0 to R7, the assembler generates STM0. If reglist specifies any of R8 to R15, the assembler generates STM1. The assembler may generate both STM1 and STM0. *4: The assembler changes u10 to u8 by calculating u10/4 and sets a value. u10 is an unsigned value. Notes: • The number of execution cycles of LDM0 (reglist) and LDM1 (reglist) is a×(n-1)+b+1 cycles when the specified number of registers is n. • The number of execution cycles of STM0 (reglist) and STM1 (reglist) is a×n+1 cycles when the specified number of registers is n. 492 APPENDIX E Instruction Lists ■ 20-bit Ordinary Branch Macroinstructions Table E.1-14 20-bit Ordinary Branch Macroinstructions Mnemonic Operation Remarks *CALL20 label20,Ri Address of the next instruction --> RP label20 --> PC Ri: Temporary register (See Reference 1.) *BRA20 label20,Ri label20 --> PC Ri: Temporary register (See Reference 2.) *BEQ20 label20,Ri if(Z==1) then label20 -->PC Ri: Temporary register (See Reference 3.) *BNE20 label20,Ri s/Z==0 *BC20 label20,Ri s/C==1 *BNC20 label20,Ri s/C==0 *BN20 label20,Ri s/N==1 *BP20 label20,Ri s/N==0 *BV20 label20,Ri s/V==1 *BNV20 label20,Ri s/V==0 *BLT20 label20,Ri s/V xor N==1 *BGE20 label20,Ri s/V xor N==0 *BLE20 label20,Ri s/(V xor N) or Z==1 *BGT20 label20,Ri s/(V xor N) or Z==0 *BLS20 label20,Ri s/C or Z==1 *BHI20 label20,Ri s/C or Z==0 [Reference 1] CALL20 1) When label20-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows: CALL label12 2) When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:20 #label20,Ri CALL @Ri [Reference 2] BRA20 1) When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: BRA label9 2) When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:20 #label20,Ri JMP @Ri [Reference 3] Bcc20 1) When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: Bcc label9 2) When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: Bxcc false xcc is a condition against cc. LDI:20 #label20,Ri JMP @Ri false: 493 APPENDIX E Instruction Lists ■ 20-bit Delayed Branch Macroinstructions Table E.1-15 20-bit Delayed Branch Macroinstructions Mnemonic Operation Remarks *CALL20:D label20,Ri Address of the next instruction + 2 --> RP label20 --> PC Ri: Temporary register (See Reference 1.) *BRA20:D label20,Ri label20 --> PC Ri: Temporary register (See Reference 2.) *BEQ20:D label20,Ri if(Z==1) then label20 -->PC Ri: Temporary register (See Reference 3.) *BNE20:D label20,Ri s/Z==0 *BC20:D label20,Ri s/C==1 *BNC20:D label20,Ri s/C==0 *BN20:D label20,Ri s/N==1 *BP20:D label20,Ri s/N==0 *BV20:D label20,Ri s/V==1 *BNV20:D label20,Ri s/V==0 *BLT20:D label20,Ri s/V xor N==1 *BGE20:D label20,Ri s/V xor N==0 *BLE20:D label20,Ri s/(V xor N) or Z==1 *BGT20:D label20,Ri s/(V xor N) or Z==0 *BLS20:D label20,Ri s/C or Z==1 *BHI20:D label20,Ri s/C or Z==0 [Reference 1] CALL20:D 1) When label20-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows: CALL:D label12 2) When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:20 #label20,Ri CALL:D @Ri [Reference 2] BRA20:D 1) When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: BRA:D label9 2) When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:20 #label20,Ri JMP:D @Ri [Reference 3] Bcc20:D 1) When label20-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: Bcc:D label9 2) When label20-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: Bxcc false xcc is a condition against cc. LDI:20 #label20,Ri JMP:D @Ri false: 494 APPENDIX E Instruction Lists ■ 32-bit Ordinary Branch Macroinstructions Table E.1-16 32-bit Ordinary Branch Macroinstructions Mnemonic Operation Remarks *CALL32 label32,Ri Address of the next instruction --> RP label32 --> PC Ri: Temporary register (See Reference 1.) *BRA32 label32,Ri label32 --> PC Ri: Temporary register (See Reference 2.) *BEQ32 label32,Ri if(Z==1) then label32 -->PC Ri: Temporary register (See Reference 3.) *BNE32 label32,Ri s/Z==0 *BC32 label32,Ri s/C==1 *BNC32 label32,Ri s/C==0 *BN32 label32,Ri s/N==1 *BP32 label32,Ri s/N==0 *BV32 label32,Ri s/V==1 *BNV32 label32,Ri s/V==0 *BLT32 label32,Ri s/V xor N==1 *BGE32 label32,Ri s/V xor N==0 *BLE32 label32,Ri s/(V xor N) or Z==1 *BGT32 label32,Ri s/(V xor N) or Z==0 *BLS32 label32,Ri s/C or Z==1 *BHI32 label32,Ri s/C or Z==0 [Reference 1] CALL32 1) When label32-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows: CALL label12 2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:32 #label32,Ri CALL @Ri [Reference 2] BRA32 1) When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: BRA label9 2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:32 #label32,Ri JMP @Ri [Reference 3] Bcc32 1) When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: Bcc label9 2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: Bxcc false xcc is a condition against cc. LDI:32 #label32,Ri JMP @Ri false: 495 APPENDIX E Instruction Lists ■ 32-bit Delayed Branch Macroinstructions Table E.1-17 32-bit Delayed Branch Macroinstructions .Mnemonic Operation Remarks *CALL32:D label32,Ri Address of the next instruction + 2 --> RP label32 --> PC Ri: Temporary register (See Reference 1.) *BRA32:D label32,Ri label32 --> PC Ri: Temporary register (See Reference 2.) *BEQ32:D label32,Ri if(Z==1) then label32 -->PC Ri: Temporary register (See Reference 3.) *BNE32:D label32,Ri s/Z==0 *BC32:D label32,Ri s/C==1 *BNC32:D label32,Ri s/C==0 *BN32:D label32,Ri s/N==1 *BP32:D label32,Ri s/N==0 *BV32:D label32,Ri s/V==1 *BNV32:D label32,Ri s/V==0 *BLT32:D label32,Ri s/V xor N==1 *BGE32:D label32,Ri s/V xor N==0 *BLE32:D label32,Ri s/(V xor N) or Z==1 *BGT32:D label32,Ri s/(V xor N) or Z==0 *BLS32:D label32,Ri s/C or Z==1 *BHI32:D label32,Ri s/C or Z==0 [Reference 1] CALL32:D 1) When label32-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows: CALL:D label12 2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:32 #label32,Ri CALL:D @Ri [Reference 2] BRA32:D 1) When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: BRA:D label9 2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: LDI:32 #label32,Ri JMP:D @Ri [Reference 3] Bcc32:D 1) When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows: Bcc:D label9 2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the instruction is generated as follows: Bxcc false xcc is a condition against cc. LDI:32 #label32,Ri JMP:D @Ri false: 496 APPENDIX E Instruction Lists ■ Direct addressing Instructions Table E.1-18 Direct addressing Instructions Mnemonic Type OP CYCLE NZVC DMOV @dir10, R13 D 08 b ---- (dir10) --> R13 Word DMOV R13, D 18 a ---- R13 --> (dir10) Word DMOV @dir10, @R13+ D 0C 2a ---- (dir10) --> (R13),R13+=4 Word DMOV @R13+, @dir10* D 1C 2a ---- (R13) --> (dir10),R13+=4 Word DMOV @dir10, @-R15 D 0B 2a ---- R15-=4,(R15) --> (dir10) Word DMOV @R15+, @dir10 D 1B 2a ---- (R15) --> (dir10),R15+=4 Word DMOVH @dir9, R13 D 09 b ---- (dir9) --> R13 Half word DMOVH R13, D 19 a ---- R13 --> (dir9) Half word DMOVH @dir9, @R13+ D 0D 2a ---- (dir9) --> (R13),R13+=2 Half word DMOVH @R13+, @dir9* D 1D 2a ---- (R13) --> (dir9),R13+=2 Half word DMOVB @dir8, R13 D 0A b ---- (dir8) --> R13 Byte DMOVB R13, D 1A a ---- R13 --> (dir8) Byte DMOVB @dir8, @R13+ D 0E 2a ---- (dir8) --> (R13),R13++ Byte DMOVB @R13+, @dir8 D 1E 2a ---- (R13) --> (dir8),R13++ Byte @dir10 @dir9 @dir8 Operation Remarks * : Be sure to put one NOP after the DMOV instruction that uses R13+ as the transfer source. Note: The assembler performs calculations as shown below and sets values in the dir8, dir9, and dir10 fields: dir8 --> dir, dir9/2 --> dir, and dir10/4 --> dir. dir8, dir9, and dir10 are unsigned values. ■ Resource Instructions Table E.1-19 Resource Instructions Mnemonic Type OP CYCLE NZVC Operation Remarks LDRES @Ri+, #u4 C BC a ---- (Ri) --> u4 resource Ri+=4 u4: Channel number STRES #u4, @Ri+ C BD a ---- u4 resource --> (Ri) Ri+=4 u4: Channel number 497 APPENDIX E Instruction Lists ■ Coprocessor Control Instructions Table E.1-20 Coprocessor Control Instructions Mnemonic Type OP CYCLE NZVC Operation COPOP #u4, #u8, CRj, CRi E 9F-C 2+a ---- Arithmetic operation indication COPLD #u4, #u8, Rj, CRi E 9F-D 1+2a ---- Rj --> CRi COPST #u4, #u8, CRj, Ri E 9F-E 1+2a ---- CRj --> Ri COPSV #u4, #u8, CRj, Ri E 9F-F 1+2a ---- CRj --> Ri Remarks No error trap Notes: • {CRi|CRj}:= CR0|CR1|CR2|CR3|CR4|CR5|CR6|CR7|CR8|CR9|CR10|CR11|CR12|CR13|CR14|CR15 • u4: Channel specification • u8: Command specification • This model cannot use these instructions because it has no coprocessor. 498 INDEX The index follows on the next page. This is listed in alphabetic order. 499 Index Numerics 0 Detection 0 Detection ...................................................... 405 0 Detection Data Register (BSD0) ..................... 403 0 Detection Data Register 0 Detection Data Register (BSD0) ..................... 403 1 Detection 1 Detection ...................................................... 405 1 Detection Data Register (BSD1) ..................... 403 1 Detection Data Register 1 Detection Data Register (BSD1) ..................... 403 16 Bits,Read/Write FR-CPU Programming Mode (16 Bits,Read/Write)............................ 431 16/8-bit Data Data Transfer Section,16/8-bit Data ................... 395 Transfer Termination in Continuous Transfer Mode (When both Addresses are Changed), 16/8-bit Data....................................... 397 Transfer Termination in Continuous Transfer Mode (When Either address is Fixed), 16/8-bit Data....................................... 396 16-bit Free-run Timer Count Timing of the 16-bit Free-run Timer ......... 240 Explanation of 16-bit Free-run Timer Operation ........................................... 239 Timing to Clear the 16-bit Free-run Timer .......... 240 16-bit Immediate Value Immediate Value Set,16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions ......................................... 487 16-bit Input Capture Input Timing of 16-bit Input Capture.................. 244 Operation of 16-bit Input Capture ...................... 243 16-bit Output Compare Explanation of 16-bit Output Compare Operation ........................................... 241 Timing of 16-bit Output Compare ...................... 242 16-bit Reload Register 16-bit Reload Register (TMRLR0 to TMRLR3) ...................... 193 16-bit Reload Timer Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) ....................... 332 Block Diagram of the 16-bit Reload Timer ......... 189 Features of 16-bit Reload Timer ........................ 188 Register List of the 16-bit Reload Timer ............. 190 When the 16-bit Reload Timer is Used for Activation...................................... 223 500 16-bit Timer Register 16-bit Timer Register (TMR0 to TMR3) ............ 193 20-bit Delayed Branch 20-bit Delayed Branch Macroinstructions........... 494 20-bit Ordinary Branch 20-bit Ordinary Branch Macroinstructions.......... 493 32 Bits,Read Only FR-CPU ROM Mode (32 Bits,Read Only) ......... 430 32-bit Delayed Branch 32-bit Delayed Branch Macroinstructions........... 496 32-bit Immediate Value Immediate Value Set,16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions ........................................ 487 32-bit Ordinary Branch 32-bit Ordinary Branch Macroinstructions.......... 495 8 Bits x 2 Channels and 16 Bits x 1 Channel Operations for 8 Bits x 2 Channels and 16 Bits x 1 Channel....................... 186 8/10-bit A/D Converter 8/10-bit A/D Converter Block Diagram.............. 277 8/10-bit A/D Converter Interrupt ....................... 290 8/10-bit A/D Converter Pin Block Diagram ........ 280 8/10-bit A/D Converter Pins.............................. 279 Conversion Modes of 8/10-bit A/D Converter .................................... 276 Features of the 8/10-bit A/D Converter .............. 276 Notes on Using the 8/10-bit A/D Converter ........ 294 8/10-bit A/D Converter Registers Schema of the 8/10-bit A/D Converter Registers ............................................ 281 8/16-bit Up/Down Counter/Timer Block Diagram of the 8/16-bit Up/Down Counter/Timer .................................... 166 Characteristics of the 8/16-bit Up/Down Counter/Timer .................................... 164 List of Registers for the 8/16-bit Up/Down Counter/Timer .................................... 168 8-bit D/A Converter 8-bit D/A Converter Block Diagram .................. 297 8-bit D/A Converter Pins .................................. 297 Features of the 8-bit D/A Converter ................... 296 Operation of the 8-bit D/A Converter................. 301 8-bit D/A Converter Registers List of the 8-bit D/A Converter Registers ........... 298 A A/D Control Status Register A/D Control Status Register 0 (ADCS0) ............ 285 A/D Control Status Register 1 (ADCS1) ............ 282 A/D Converted Data Preservation Function A/D Converted Data Preservation Function ........ 293 A/D Converter 8/10-bit A/D Converter Block Diagram.............. 277 8/10-bit A/D Converter Interrupt ....................... 290 8/10-bit A/D Converter Pin Block Diagram ........ 280 8/10-bit A/D Converter Pins.............................. 279 Conversion Modes of 8/10-bit A/D Converter .................................... 276 Features of the 8/10-bit A/D Converter .............. 276 Notes on Using the 8/10-bit A/D Converter ........ 294 Schema of the 8/10-bit A/D Converter Registers ............................................ 281 A/D Data Register A/D Data Register (ADCR) .............................. 288 Access Big-endian Bus Access ..................................... 117 Byte Access..................................................... 131 Comparison of External Access in Big-endian and Little-endian Mode.............................. 117 Data Access............................................... 46, 475 Descriptor Access Section................................. 393 Differences and Similarities of Access in Little-endian and in Big-endian Mode ...................... 124 External Bus Access......................................... 121 Half Word Access ............................................ 129 Little-endian Bus Access .................................. 117 Normal Bus Access .......................................... 133 Program Access ................................................. 46 Word Access ................................................... 128 Acquisition Bus Right Acquisition ...................................... 145 Activating Activating the Watchdog Timer........................... 80 Activating Multiple Channels Activating Multiple Channels with the GCN....... 222 ADCR A/D Data Register (ADCR) .............................. 288 ADCS A/D Control Status Register 0 (ADCS0) ............ 285 A/D Control Status Register 1 (ADCS1) ............ 282 Addition Addition and Subtraction Instructions ................ 483 Address Register Address Register (IADR).................................. 364 Address Specification Method Address Specification Method........................... 441 Addressing Addressing Mode Symbols ............................... 479 Direct Addressing Area ...................................... 32 Direct Addressing Instructions .......................... 497 Addressing Mode Addressing Mode Symbols ............................... 479 AF200 Internal Vector Mode (Single-chip Mode): Example of Minimum Connection with AF200 ........450 System Configuration of AF200 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation...............448 AICR Analog Input Control Register (AICR) ...............162 All-low or All-high Examples for Setting PWM Output to All-low or All-high ..............................................220 Allocation Allocation of Stacks in the Little-endian area ....................................................474 Allocation of Variables Having Initial Values ................................................472 AMD Area Mode Register 0 (AMD0)..........................106 Area Mode Register 1 (AMD1)..........................108 Area Mode Register 32 (AMD32) ......................109 Area Mode Register 4 (AMD4)..........................110 Area Mode Register 5 (AMD5)..........................111 AMR Area Select Registers (ASR) and Area Mask Registers (AMR)................................................104 Analog Input Control Register Analog Input Control Register (AICR) ...............162 Applicable Notes Operation of Peripheral Stop Control and Applicable Notes..................................................410 Area Mask Registers Area Select Registers (ASR) and Area Mask Registers (AMR)................................................104 Area Mode Register Area Mode Register 0 (AMD0)..........................106 Area Mode Register 1 (AMD1)..........................108 Area Mode Register 32 (AMD32) ......................109 Area Mode Register 4 (AMD4)..........................110 Area Mode Register 5 (AMD5)..........................111 Area Select Registers Area Select Registers (ASR) and Area Mask Registers (AMR)................................................104 ASR Area Select Registers (ASR) and Area Mask Registers (AMR)................................................104 Assembler Source Code Example of the Related Assembler Source Code (Example of Switching to the PLL System) ................................................88 Asynchronous Operation in Asynchronous Mode (Operation Modes 0 and 1) ...................337 501 Asynchronous Mode Operation in Asynchronous Mode (Operation Modes 0 and 1) ................... 337 Automatic Algorithm Execution Status of Automatic Algorithm........... 431 Automatic Wait Cycle Automatic Wait Cycle Timing Chart .................. 143 B Basic Configuration Basic Configuration of MB91F155A Serial Onboard Writing............................................... 446 Basic I/O Port Block Diagram of Basic I/O Port ....................... 153 Basic Programming Model Basic Programming Model.................................. 38 Basic Read Cycle Timing Basic Read Cycle Timing Chart......................... 134 Basic Write Cycle Timing Basic Write Cycle Timing Chart ........................ 136 Baud Rate Baud Rate Based on the Dedicated Baud-Rate Generator ........................................... 329 Baud Rate Based on the External Clock.............. 334 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) ....................... 332 UART Baud-rate Selection................................ 327 UART Baud-Rate Selection Circuit.................... 328 Bidirectional Communication Bidirectional Communication Function .............. 342 Big-endian Big-endian Bus Access ..................................... 117 Comparison of External Access in Big-endian and Little-endian Mode .............................. 117 Differences and Similarities of Access in Little-endian and in Big-endian Mode....................... 124 Bit Manipulation Instructions Bit Manipulation Instructions ............................ 485 Bit Ordering Bit Ordering....................................................... 45 Bit-search Module Block Diagram of the Bit-search Module............ 402 Registers of the Bit-search Module .................... 402 Block Diagram 8/10-bit A/D Converter Block Diagram .............. 277 8/10-bit A/D Converter Pin Block Diagram ........ 280 8-bit D/A Converter Block Diagram................... 297 Block Diagram for MB91154 ................................ 6 Block Diagram for MB91FV150,MB91F155A and MB91155 ............................................... 5 Block Diagram of Basic I/O Port ....................... 153 Block Diagram of Calendar Macros ................... 416 Block Diagram of I/O Port with a Pull-up Resistor .............................................. 154 502 Block Diagram of I/O Port with Open-drain Output Function............................................. 157 Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor .............. 155 Block Diagram of I2C Interface......................... 351 Block Diagram of Multifunctional Timer ........... 228 Block Diagram of One Channel for the PPG Timer................................................. 202 Block Diagram of the 16-bit Reload Timer ......... 189 Block Diagram of the 8/16-bit Up/Down Counter/Timer .................................... 166 Block Diagram of the Bit-search Module ........... 402 Block Diagram of the Clock Generator ................ 70 Block Diagram of the Delayed Interrupt Module .............................................. 256 Block Diagram of the DMA Controller .............. 371 Block Diagram of the Entire PPG Timer ............ 201 Block Diagram of the External Interrupt Control Block ................................................. 246 Block Diagram of the Flash Memory ................. 425 Block Diagram of the Gear Control Block ............ 82 Block Diagram of the Interrupt Controller .......... 261 Block Diagram of the Reset Source Retention Circuit ................................................. 84 Block Diagram of the Sleep Control Block ........... 94 Block Diagram of the Stop Control Block ............ 91 Block Diagram of the Watchdog Control Block ................................................... 80 Bus Interface Block Diagram ............................ 102 I/O Port Block Diagrams .................................. 152 UART Block Diagram...................................... 306 UART Pin Block Diagram ................................ 310 Branch 20-bit Delayed Branch Macroinstructions........... 494 20-bit Ordinary Branch Macroinstructions.......... 493 32-bit Delayed Branch Macroinstructions........... 496 32-bit Ordinary Branch Macroinstructions.......... 495 Branch Instructions with Delay Slots ................... 50 Branch Instructions without a Delay Slot.............. 53 Delayed Branch Instructions ............................. 491 Explanation of Operation for Branch Instructions without a Delay Slot.............................. 53 Explanation of the Operation for Branch Instructions with Delay Slots ................................... 50 Ordinary Branch (No Delay) Instructions ........... 490 Restrictions on Branch Instructions with Delay Slots .................................................... 52 BSD 0 Detection Data Register (BSD0) ..................... 403 1 Detection Data Register (BSD1) ..................... 403 BSDC Value Change Detection Data Register (BSDC).............................................. 404 BSRR Detection Result Register (BSRR) ..................... 404 Burst Transfer Burst Transfer.................................................. 386 Burst Transfer Mode ........................................ 382 Bus Access Big-endian Bus Access ..................................... 117 External Bus Access......................................... 121 Little-endian Bus Access .................................. 117 Bus Control Register Bus Control Register (IBCR) ............................ 353 Bus Interface Bus Interface ................................................... 101 Bus Interface Block Diagram ............................ 102 Bus Interface Features ...................................... 100 Registers of the Bus Interface............................ 103 Bus Operation Program Example for External Bus Operation ........................................... 149 Specification Example of a Program for External Bus Operation ........................................... 148 Bus Right Bus Right Acquisition ...................................... 145 Releasing Bus Right ......................................... 145 Bus Status Register Bus Status Register (IBSR) ............................... 361 BUSYX Ready/Busy Signal (RDY/BUSYX)................... 436 Byte Access Byte Access..................................................... 131 Byte Ordering Byte Ordering .................................................... 45 C CA Day Data Register (CA4) .................................. 419 Day-of-the-week Data Register (CA5) ............... 419 Hour Data Register (CA3) ................................ 418 Minute Data Register (CA2) ............................. 418 Month Data Register (CA6) .............................. 419 Second Data Register (CA1) ............................. 418 Year Data Register (CA7) ................................. 420 CAC Calendar Block Read/Write Control Register (CAC)................................................ 417 Calendar Block Read/Write Control Register Calendar Block Read/Write Control Register (CAC)................................................ 417 Calendar Macro Block Diagram of Calendar Macros ................... 416 Registers of Calendar Macros............................ 416 When the Clock Function (Calendar Macro) is not Used .................................................... 30 Calendar Test Register Calendar Test Register (CAS) ........................... 420 Calendar Values Reading Calendar Values ..................................421 Setting Calendar Values ....................................421 CAS Calendar Test Register (CAS) ............................420 Causes Causes of Reset Delays Other than Programs ........81 CCRH Counter Control Register H/L ch.0 (CCRH0, CCRL0) ...............................169 Counter Control Register H/L ch.1 (CCRH1, CCRL1) ...............................173 CCRL Counter Control Register H/L ch.0 (CCRH0, CCRL0) ...............................169 Counter Control Register H/L ch.1 (CCRH1, CCRL1) ...............................173 CDCR Communication Prescaler Control Register (CDCR) ..............................................320 Change Point Detection Change Point Detection.....................................406 Channels Activating Multiple Channels with the GCN .......222 Operations for 8 Bits x 2 Channels and 16 Bits x 1 Channel........................186 Priority of Channels ..........................................390 Characteristics Characteristics of the 8/16-bit Up/Down Counter/Timer.....................................164 Character-string Manipulation of a Non-character Type Array by Using a Character-string Handling Function .............................................473 Specification of the -K lib Option During Use of a Character-string Handling Function .............................................473 Chip Erase Chip Erase .......................................................443 Chip Select Area Chip Select Area...............................................100 Circuit Handling Circuit Handling .................................................27 Clear Timing to Clear the 16-bit Free-run Timer ..........240 Clock Control Register Clock Control Register (ICCR) ..........................365 Clock Function When the Clock Function (Calendar Macro) is not Used.....................................................30 Clock Generator Block Diagram of the Clock Generator .................70 Register Configuration of Clock Generator ...........69 503 Clock Selection Clock Selection Method.................................... 146 Clock System Reference Chart for the Clock System .................. 87 Combinations Combinations of Request Sense Modes and Transfer Modes ................................................ 383 Command Sequence Command Sequence ......................................... 433 Communication Prescaler Control Register Communication Prescaler Control Register (CDCR).............................................. 320 Compare Compare Clear Register .................................... 230 Compare Register (OCCP0 to OCCP7) .............. 233 Explanation of 16-bit Output Compare Operation ........................................... 241 Reload and Compare Function........................... 181 Reload/Compare Register 0/1 (RCR 0, RCR 1) .................................. 177 Timing of 16-bit Output Compare ...................... 242 When the Compare Function is Started............... 182 When the Reload and Compare Functions are Started Simultaneously ................................... 182 Compare Clear Register Compare Clear Register .................................... 230 Compare Detection Compare Detection Flag ................................... 186 Compare Register Compare Register (OCCP0 to OCCP7) .............. 233 Comparison Comparison of External Access in Big-endian and Little-endian Mode .............................. 117 Comparison Operation Instruction Comparison Operation Instruction ..................... 483 Configuration Basic Configuration of MB91F155A Serial Onboard Writing............................................... 446 Configuration of the Multifunctional Timer ........ 226 Hardware Configuration.................................... 272 Hardware Configuration of Interrupt Controller ........................................... 260 Register Configuration of Clock Generator ........... 69 System Configuration of AF200 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation .............. 448 Connection with External Devices Example of Connection with External Devices .............................................. 123 Examples of Connection with External Devices .............................................. 127 Contention Contention Among SCC,MSS,and INT Bits........ 360 504 Continuous Transfer Continuous Transfer......................................... 385 Continuous Transfer Mode Continuous Transfer Mode ............................... 382 Transfer Termination in Continuous Transfer Mode (When both Addresses are Changed), 16/8-bit Data ...................................... 397 Transfer Termination in Continuous Transfer Mode (When Either address is Fixed), 16/8-bit Data ...................................... 396 Continuous-conversion Mode Operation in Continuous-conversion Mode......... 291 Control Register Control Register............................................... 272 Control Register (SCR0 to SCR3) ..................... 312 Pull-up Resistor Control Register (PCR6 to PCRI) .................................. 160 Control Signals Relationship Between Data Bus Width and Control Signals ....................................... 117, 118 Control Status Register Control Status Register (TMCSR0 to TMCSR3) ...................... 191 Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5).............................. 205 Conversion Modes Conversion Modes of 8/10-bit A/D Converter .................................... 276 Coprocessor Absence Trap Coprocessor Absence Trap ................................. 64 Coprocessor Control Coprocessor Control Instructions....................... 497 Coprocessor Error Trap Coprocessor Error Trap ...................................... 65 Count Clear Count Clear/Gate Function ............................... 185 Count Direction Count Direction Change Flag ............................ 186 Count Direction Flag ........................................ 186 Count Timing Count Timing of the 16-bit Free-run Timer ........ 240 Counter Control Register Counter Control Register H/L ch.0 (CCRH0, CCRL0) .............................. 169 Counter Control Register H/L ch.1 (CCRH1, CCRL1) .............................. 173 Counter Operation Counter Operation States .................................. 197 Counter Status Register Counter Status Register 0/1 (CSR0,CSR1) ......... 174 CPU FR-CPU Programming Mode (16 Bits,Read/Write) ........................... 431 FR-CPU ROM Mode (32 Bits,Read Only) ......... 430 Pin Status in Each CPU State ............................ 465 Status Register (FLCR) (CPU Mode) ................. 427 Criteria for Determining Criteria for Determining whether a Hold-request Cancellation-request must be Issued...... 271 CSR Counter Status Register 0/1 (CSR0,CSR1) ......... 174 CTBR Timebase Timer Clear Register (CTBR)............... 74 D D/A Control Registers D/A Control Registers (DACR0, DACR1, DACR2) ................ 299 D/A Converter 8-bit D/A Converter Block Diagram .................. 297 8-bit D/A Converter Pins .................................. 297 Features of the 8-bit D/A Converter ................... 296 List of the 8-bit D/A Converter Registers ........... 298 Operation of the 8-bit D/A Converter ................. 301 D/A Data Registers D/A Data Registers (DADR2, DADR1, DADR0)................ 300 DACR D/A Control Registers (DACR0, DACR1, DACR2) ................ 299 DACSR DMAC Control Status Register (DACSR) .......... 374 DADR D/A Data Registers (DADR2, DADR1, DADR0)................ 300 Data Access Data Access............................................... 46, 475 Data Bus Width Data Bus Width ....................................... 120, 126 Relationship Between Data Bus Width and Control Signals ....................................... 117, 118 Data Direction Register Data Direction Register (DDR) ......................... 159 Data Format Data Format ............................................ 119, 125 Data Register Data Register (IDAR)....................................... 364 Data Register (TCDT) ...................................... 230 Data Transfer Section Data Transfer Section,16/8-bit Data ................... 395 DATCR DMAC Pin Control Register (DATCR).............. 376 Day Data Register Day Data Register (CA4) .................................. 419 Day-of-the-week Data Register Day-of-the-week Data Register (CA5) ............... 419 DDR Data Direction Register (DDR) ..........................159 Debugger Emulator Debugger and Monitor Debugger.........477 Simulator Debugger ..........................................477 Dedicated Baud-Rate Generator Baud Rate Based on the Dedicated Baud-Rate Generator............................................329 Delay Branch Instructions with Delay Slots ....................50 Branch Instructions without a Delay Slot ..............53 Causes of Reset Delays Other than Programs ........81 Explanation of Operation for Branch Instructions without a Delay Slot...............................53 Explanation of the Operation for Branch Instructions with Delay Slots ....................................50 Ordinary Branch (No Delay) Instructions............490 Restrictions on Branch Instructions with Delay Slots .....................................................52 Watchdog Reset Generation Delay Register (WPR) ..................................................77 Delayed Branch 20-bit Delayed Branch Macroinstructions ...........494 32-bit Delayed Branch Macroinstructions ...........496 Delayed Branch Instructions ..............................491 Delayed Interrupt Block Diagram of the Delayed Interrupt Module ...............................................256 Delayed Interrupt Control Register (DICR) .........257 List of Delayed Interrupt Module Registers .........256 Delayed Interrupt Control Register Delayed Interrupt Control Register (DICR) .........257 Delayed Interrupt Module Registers List of Delayed Interrupt Module Registers .........256 Delaying Reset Generation Delaying Reset Generation ..................................81 Descriptor Descriptor Start Word .......................................378 Second Word in the Descriptor ..........................380 Third Word in the Descriptor .............................380 Descriptor Access Descriptor Access Section .................................393 Detect Errors Failure to Detect Errors .....................................476 Detection Result Register Detection Result Register (BSRR)......................404 DICR Delayed Interrupt Control Register (DICR) .........257 DLYI Bit of DICR ............................................258 Differences and Similarities of Access Differences and Similarities of Access in Little-endian and in Big-endian Mode .......................124 Direct Addressing Direct Addressing Area .......................................32 505 Direct Addressing Instructions........................... 497 Division Multiplication and Division Instructions ............. 486 Multiplication and Division Result Registers (MDH and MDL) .................................. 44 DLYI DLYI Bit of DICR............................................ 258 DMA Block Diagram of the DMA Controller............... 371 DMA Request Suppression Register (PDRR) ........ 78 DMA Transfer Operation in Sleep Mode ............ 391 Features of the DMA Controller ........................ 370 Notes on Using a Resource Interrupt Request as a DMA Transfer Request ........................ 390 Registers of the DMA Controller ....................... 372 Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt ...................... 390 DMA Request Suppression Register DMA Request Suppression Register (PDRR) ........ 78 DMA Transfer DMA Transfer Operation in Sleep Mode ............ 391 Notes on Using a Resource Interrupt Request as a DMA Transfer Request ........................ 390 Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt ...................... 390 DMAC DMAC Control Status Register (DACSR) .......... 374 DMAC Parameter Descriptor Pointer (DPDP) .......................................................... 373 DMAC Pin Control Register (DATCR) .............. 376 Transfer Operation to DMAC Internal Register .............................................. 391 DMAC Control Status Register DMAC Control Status Register (DACSR) .......... 374 DMAC Internal Register Transfer Operation to DMAC Internal Register .............................................. 391 DMAC Parameter Descriptor Pointer DMAC Parameter Descriptor Pointer (DPDP) .......................................................... 373 DMAC Pin Control Register DMAC Pin Control Register (DATCR) .............. 376 Double Type Using Double Type and Long-double Type......... 474 Down Count Timer Mode [Down Count] ............................... 178 DPDP DMAC Parameter Descriptor Pointer (DPDP) .......................................................... 373 DREC DREC Signal Sense Modes ............................... 383 DREC Signal Sense Modes DREC Signal Sense Modes ............................... 383 506 E Edge Mode Notes on Edge Mode ........................................ 388 EIRR External Interrupt Source Register (EIRR0, EIRR1: External Interrupt Request Register 0,1) ....................................... 249 EIT EIT................................................................... 54 EIT Source Acceptance Priority .......................... 59 EIT Sources....................................................... 54 Notes on EIT ..................................................... 54 Return from EIT ................................................ 54 ELVR External Level Register (ELVR0,ELVR1: External Level Register) ................................... 250 Emulator Emulator Debugger and Monitor Debugger ........ 477 ENIR Interrupt Enable Register (ENIR0,ENIR1: Interrupt ENable Register 0,1) ........................... 248 EPCR External Pin Control Register 0 (EPCR0) ........... 112 External Pin Control Register 1 (EPCR1) ........... 115 Error Coprocessor Error Trap ...................................... 65 Failure to Detect Errors .................................... 476 Example Example of Connection with External Devices .............................................. 123 Example of Serial Programming Connection ...... 448 Example of Setting the PLL Clock....................... 86 Example of the Related Assembler Source Code (Example of Switching to the PLL System)................................................ 88 Examples for Setting PWM Output to All-low or All-high ............................................. 220 Examples of Connection with External Devices .............................................. 127 Internal Vector Mode (Single-chip Mode): Example of Minimum Connection with AF200 ....... 450 Internal Vector Mode (Single-chip Mode): Example of Standard Connection ........................... 449 Program Example for External Bus Operation ........................................... 149 Specification Example of a Program for External Bus Operation ........................................... 148 Execution Status Execution Status of Automatic Algorithm .......... 431 Explanation Explanation of 16-bit Free-run Timer Operation ........................................... 239 Explanation of 16-bit Output Compare Operation ........................................... 241 Explanation of Multifunctional Timer Operation ........................................... 238 Explanation of Operation for Branch Instructions without a Delay Slot .............................. 53 Explanation of the Operation for Branch Instructions with Delay Slots.................................... 50 External Access Comparison of External Access in Big-endian and Little-endian Mode.............................. 117 External Bus Access External Bus Access......................................... 121 External Bus Operation Program Example for External Bus Operation ........................................... 149 Specification Example of a Program for External Bus Operation ........................................... 148 External Bus Request External Bus Request ....................................... 133 External Clock Baud Rate Based on the External Clock ............. 334 External Clock................................................... 28 External Devices Example of Connection with External Devices .............................................. 123 Examples of Connection with External Devices .............................................. 127 External Interrupt External Interrupt Operation.............................. 251 External Interrupt Request Level ....................... 252 External Interrupt Source Register (EIRR0, EIRR1: External Interrupt Request Register 0,1) ....................................... 249 Notes on using External Interrupt to Return from STOP State where Clock Oscillation is Stopped.............................................. 252 Setting Procedure for an External Interrupt ......... 251 External Interrupt Control Block Diagram of the External Interrupt Control Block ................................................. 246 External Interrupt Control Block Registers List of External Interrupt Control Block Registers ............................................ 247 External Interrupt Request Register External Interrupt Source Register (EIRR0, EIRR1: External Interrupt Request Register 0,1) ....................................... 249 External Interrupt Source Register External Interrupt Source Register (EIRR0, EIRR1: External Interrupt Request Register 0,1) ....................................... 249 External Level Register External Level Register (ELVR0,ELVR1: External Level Register) ................................... 250 External Pin Control Register External Pin Control Register 0 (EPCR0) ........... 112 External Pin Control Register 1 (EPCR1)............115 External Reset External Reset Input............................................28 External Wait Cycle Timing Chart of External Wait Cycle .................144 F Failure Failure to Detect Errors .....................................476 Features Bus Interface Features.......................................100 Features .............................................................35 Features of 16-bit Reload Timer.........................188 Features of I2C Interface ...................................350 Features of PPG Timer ......................................200 Features of the 8/10-bit A/D Converter ...............276 Features of the 8-bit D/A Converter....................296 Features of the DMA Controller.........................370 MB91150 Features ...............................................2 UART Features ................................................304 Flag Compare Detection Flag....................................186 Count Direction Change Flag.............................186 Count Direction Flag.........................................186 Hardware Sequence Flags..................................436 Receive-interrupt Generation and Flag Set Timing................................................324 Send-interrupt Generation and Flag Set Timing................................................326 Flash Memory Block Diagram of the Flash Memory ..................425 Note on Writing Data to the Flash Memory .........441 Overview of Flash Memory ...............................424 Overview of Writing and Erasing Flash Memory .....................................439 Placing the Flash Memory in Read/Reset Status .................................................440 Procedure for Flash Memory Write ....................441 Writing Data to the Flash Memory .....................441 Flash Microcontroller Programmer System Configuration of AF200 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation...............448 FLCR Status Register (FLCR) (CPU Mode)..................427 Format Data Format .............................................119, 125 Instruction Format ............................................481 FPT-144P-M01 Package Dimensions of FPT-144P-M01 .................9 Pin Assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) ...............12 507 FPT-144P-M08 Package Dimensions of FPT-144P-M08 ................. 8 Pin Assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01)............... 12 FR Family FR Family Instruction Lists ............................... 482 FR-CPU FR-CPU Programming Mode (16 Bits,Read/Write)............................ 431 FR-CPU ROM Mode (32 Bits,Read Only).......... 430 Free-run Timer Count Timing of the 16-bit Free-run Timer ......... 240 Explanation of 16-bit Free-run Timer Operation ........................................... 239 Timing to Clear the 16-bit Free-run Timer .......... 240 Function A/D Converted Data Preservation Function ........ 293 Bidirectional Communication Function .............. 342 Block Diagram of I/O Port with Open-drain Output Function ............................................. 157 Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor............... 155 Count Clear/Gate Function ................................ 185 Function of Output Pin...................................... 196 Functions of the MB91150 Pins........................... 13 Main Functions of the Interrupt Controller.......... 260 Manipulation of a Non-character Type Array by Using a Character-string Handling Function ............................................. 473 Master/Slave-type Communication Function....... 344 Reload and Compare Function........................... 181 Settings of the Gear Function .............................. 83 Specification of the -K lib Option During Use of a Character-string Handling Function ............................................. 473 Watchdog Timer Function................................... 28 When the Clock Function (Calendar Macro) is not Used .................................................... 30 When the Compare Function is Started............... 182 When the Reload and Compare Functions are Started Simultaneously ................................... 182 When the Reload Function is Started.................. 181 G Gate Count Clear/Gate Function ................................ 185 GCN Activating Multiple Channels with the GCN ....... 222 General Control Register 1 (GCN1) ................... 212 General Control Register 2 (GCN2) ................... 215 GCR Gear Control Register (GCR) .............................. 75 Gear Block Diagram of the Gear Control Block ............ 82 508 Gear Control Register (GCR) .............................. 75 Settings of the Gear Function .............................. 83 Gear Control Register Gear Control Register (GCR) .............................. 75 General Control Register General Control Register 1 (GCN1) ................... 212 General Control Register 2 (GCN2) ................... 215 General-purpose Registers General-purpose Registers .................................. 39 H Half Word Access Half Word Access............................................ 129 Handling Circuit Handling ................................................ 27 Manipulation of a Non-character Type Array by Using a Character-string Handling Function............................................. 473 Specification of the -K lib Option During Use of a Character-string Handling Function............................................. 473 Hardware Configuration Hardware Configuration ................................... 272 Hardware Configuration of Interrupt Controller........................................... 260 Hardware Sequence Hardware Sequence Flags ................................. 436 Hardware Sequence Flags Hardware Sequence Flags ................................. 436 Higher-priority Interrupt Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt ...................... 390 Hold Request Cancellation Requests Levels that can be Set for Hold Request Cancellation Requests ............................................ 271 Hold-request Cancellation Request Level Set Register Hold-request Cancellation Request Level Set Register (HRCL) ............................................. 266 Hold Request Cancellation Requests Criteria for Determining whether a Hold Request Cancellation Request must be Issued ......................................................... 271 Hold-request Cancellation-request Hold-request Cancellation-request Sequence ...... 273 Hour Data Register Hour Data Register (CA3) ................................ 418 How to Read How to Read the Instruction Lists...................... 478 How to Use How to Use the I/O Map................................... 452 HRCL Hold-request Cancellation Request Level Set Register (HRCL).............................................. 266 I I/O Block Diagram of Basic I/O Port ....................... 153 Block Diagram of I/O Port with a Pull-up Resistor.............................................. 154 Block Diagram of I/O Port with Open-drain Output Function............................................. 157 Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor .............. 155 How to Use the I/O Map ................................... 452 I/O Circuit Types ............................................... 21 I/O Map .......................................................... 453 I/O Port Block Diagrams .................................. 152 I/O Port Registers............................................. 152 I/O Circuit I/O Circuit Types ............................................... 21 I/O Map How to Use the I/O Map ................................... 452 I/O Map .......................................................... 453 I/O Port Block Diagram of Basic I/O Port ....................... 153 Block Diagram of I/O Port with a Pull-up Resistor.............................................. 154 Block Diagram of I/O Port with Open-drain Output Function............................................. 157 Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor .............. 155 I/O Port Block Diagrams .................................. 152 I/O Port Registers............................................. 152 I/O Port Registers I/O Port Registers............................................. 152 2 I C Block Diagram of I2C Interface ......................... 351 Features of I2C Interface................................... 350 I2C Interface Operation..................................... 367 Registers of the I2C Interface ............................ 352 IADR Address Register (IADR).................................. 364 IBCR Bus Control Register (IBCR) ............................ 353 IBSR Bus Status Register (IBSR) ............................... 361 ICCR Clock Control Register (ICCR) ......................... 365 ICR Interrupt Control Register (ICR00 to ICR47) ...... 264 ICS Input Capture Control Register (ICS01, ICS23) ................................... 236 IDAR Data Register (IDAR) .......................................364 Immediate Value Set Immediate Value Set,16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions .........................................487 Initial Values Allocation of Variables Having Initial Values ................................................472 Initialization Initialization by Reset .........................................66 Initialization Reset ............................................421 Input Capture Input Timing of 16-bit Input Capture ..................244 Operation of 16-bit Input Capture.......................243 Input Capture Control Register Input Capture Control Register (ICS01, ICS23)....................................236 Input Capture Data Register Input Capture Data Register (IPCP0 to IPCP3) ................................236 Input Timing Input Timing of 16-bit Input Capture ..................244 Input-data Register Input-data Register (SIDR0 to SIDR3)................318 Instruction Addition and Subtraction Instructions .................483 Bit Manipulation Instructions.............................485 Branch Instructions with Delay Slots ....................50 Branch Instructions without a Delay Slot ..............53 Comparison Operation Instruction......................483 Coprocessor Control Instructions .......................498 Delayed Branch Instructions ..............................491 Direct Addressing Instructions ...........................497 Explanation of Operation for Branch Instructions without a Delay Slot...............................53 Explanation of the Operation for Branch Instructions with Delay Slots ....................................50 FR Family Instruction Lists ...............................482 How to Read the Instruction Lists ......................478 Immediate Value Set,16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions .........................................487 Instruction Format ............................................481 Logical Operation Instructions ...........................484 Memory Load Instructions.................................488 Memory Store Instructions ................................489 Multiplication and Division Instructions .............486 Operation for an Undefined Instruction Exception..............................................64 Operation for INT Instruction ..............................62 Operation for INTE Instruction ............................63 Operation for RETI Instruction ............................65 Ordinary Branch (No Delay) Instructions............490 Other Instructions .............................................492 509 Overview of Instructions..................................... 48 Register-to-register Transfer Instructions............ 489 Resource Instructions........................................ 497 Restrictions on Branch Instructions with Delay Slots..................................................... 52 Shift Instructions .............................................. 487 INT Contention Among SCC,MSS,and INT Bits........ 360 Operation for INT Instruction .............................. 62 INTE Operation for INTE Instruction............................ 63 Interface Block Diagram of I2C Interface ......................... 351 Bus Interface.................................................... 101 Bus Interface Block Diagram............................. 102 Bus Interface Features ...................................... 100 Features of I2C Interface ................................... 350 I2C Interface Operation..................................... 367 Registers of the Bus Interface ............................ 103 Registers of the I2C Interface............................. 352 Internal Internal Vector Mode (Single-chip Mode): Example of Minimum Connection with AF200........ 450 Internal Architecture Internal Architecture........................................... 36 Internal Clock Internal Clock Operation................................... 194 Internal Timer Baud Rate Based on the Internal Timer (16-bit Reload Timer 0) ....................... 332 Internal Vector Mode Internal Vector Mode (Single-chip Mode): Example of Standard Connection............................ 449 Interrupt 8/10-bit A/D Converter Interrupt........................ 290 Block Diagram of the Delayed Interrupt Module............................................... 256 Block Diagram of the External Interrupt Control Block ................................................. 246 Block Diagram of the Interrupt Controller .......... 261 Delayed Interrupt Control Register (DICR)......... 257 External Interrupt Operation .............................. 251 External Interrupt Request Level........................ 252 External Interrupt Source Register (EIRR0, EIRR1: External Interrupt Request Register 0,1) ....................................... 249 Hardware Configuration of Interrupt Controller ........................................... 260 Interrupt Control .............................................. 432 Interrupt Control Register (ICR00 to ICR47) ...... 264 Interrupt Enable Register (ENIR0,ENIR1: Interrupt ENable Register 0,1)............................ 248 Interrupt Level ................................................... 55 510 Interrupt Number ............................................. 258 Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) .......... 220 Interrupt Stack ................................................... 56 Interrupt Vectors.............................................. 460 Level Mask for Interrupts ................................... 55 List of Delayed Interrupt Module Registers ........ 256 List of External Interrupt Control Block Registers ............................................ 247 List of Interrupt Control Registers ..................... 262 Main Functions of the Interrupt Controller ......... 260 Notes on Using a Resource Interrupt Request as a DMA Transfer Request........................ 390 Notes on using External Interrupt to Return from STOP State where Clock Oscillation is Stopped.............................................. 252 Receive-interrupt Generation and Flag Set Timing............................................... 324 Releasing Interrupt Factors ............................... 269 Send-interrupt Generation and Flag Set Timing............................................... 326 Setting Procedure for an External Interrupt......... 251 Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt ...................... 390 UART Interrupts.............................................. 322 UART-related Interrupts................................... 323 User Interrupt Operation ..................................... 61 Interrupt Control Interrupt Control .............................................. 432 Interrupt Control Register (ICR00 to ICR47) ...... 264 List of Interrupt Control Registers ..................... 262 Interrupt Control Register Interrupt Control Register (ICR00 to ICR47) ...... 264 List of Interrupt Control Registers ..................... 262 Interrupt Controller Block Diagram of the Interrupt Controller .......... 261 Hardware Configuration of Interrupt Controller........................................... 260 Main Functions of the Interrupt Controller ......... 260 Interrupt Enable Register Interrupt Enable Register (ENIR0,ENIR1: Interrupt ENable Register 0,1) ........................... 248 Interrupt Level Interrupt Level................................................... 55 Interrupt Sources Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) .......... 220 Interrupt Vectors Interrupt Vectors.............................................. 460 IPCP Input Capture Data Register (IPCP0 to IPCP3)................................ 236 K -K lib Specification of the -K lib Option During Use of a Character-string Handling Function............................................. 473 L Latch-up Latch-up Prevention ........................................... 26 LER Little-endian Register (LER) ............................. 116 Level Levels that can be Set for Hold Request Cancellation Requests............................................. 271 Level Mask Level Mask for Interrupts ................................... 55 Level Mode Notes on Level Mode ....................................... 387 List List of Delayed Interrupt Module Registers ........ 256 List of External Interrupt Control Block Registers ............................................ 247 List of Interrupt Control Registers ..................... 262 List of Registers for the 8/16-bit Up/Down Counter/Timer .................................... 168 List of the 8-bit D/A Converter Registers ........... 298 Register List of PPG Timer ............................... 203 Register List of the 16-bit Reload Timer............. 190 Little-endian Allocation of Stacks in the Little-endian area.................................................... 474 Comparison of External Access in Big-endian and Little-endian Mode.............................. 117 Differences and Similarities of Access in Little-endian and in Big-endian Mode ...................... 124 Little-endian Bus Access .................................. 117 Little-endian Register (LER) ............................. 116 Little-endian Register Little-endian Register (LER) ............................. 116 Logical Operation Instructions Logical Operation Instructions .......................... 484 Long-double Type Using Double Type and Long-double Type ........ 474 Low-power Consumption Mode Low-power Consumption Mode Operations ......... 90 Status Transition of the Low-power Consumption Mode ................................................... 97 M Macro Block Diagram of Calendar Macros ................... 416 Registers of Calendar Macros............................ 416 When the Clock Function (Calendar Macro) is not Used.....................................................30 Macroinstructions 20-bit Delayed Branch Macroinstructions ...........494 20-bit Ordinary Branch Macroinstructions ..........493 32-bit Delayed Branch Macroinstructions ...........496 32-bit Ordinary Branch Macroinstructions ..........495 Main Functions Main Functions of the Interrupt Controller ..........260 Manipulation Manipulation of a Non-character Type Array by Using a Character-string Handling Function .............................................473 Master Master/Slave-type Communication Function .......344 MB91150 Functions of the MB91150 Pins ...........................13 MB91150 Features ...............................................2 MB91150 Memory Map......................................47 MB91154 Block Diagram for MB91154 ................................6 Memory Map for MB91154.................................34 MB91F155A Basic Configuration of MB91F155A Serial Onboard Writing ...............................................446 Pin Assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) ...............12 MB91F155A, MB91155, MB91154 Pin Assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) ...............12 MB91FV150 Pin Assignment of MB91FV150 (PGA-299C-A01) ..................................10 MB91FV150 Only Package Dimensions of PGA-299C-A01 (MB91FV150 Only).................................7 MB91FV150,MB91F155A and MB91155 Block Diagram for MB91FV150,MB91F155A and MB91155................................................5 Memory Map for MB91FV150,MB91F155A and MB91155..............................................33 MDH and MDL Multiplication and Division Result Registers (MDH and MDL) ..................................44 Memory Load Memory Load Instructions.................................488 Memory Map MB91150 Memory Map......................................47 Memory Map ...................................................425 Memory Map for MB91154.................................34 Memory Map for MB91FV150,MB91F155A and MB91155..............................................33 511 Memory Store Memory Store Instructions ................................ 489 Minimum Connection Internal Vector Mode (Single-chip Mode): Example of Minimum Connection with AF200........ 450 Minute Data Register Minute Data Register (CA2).............................. 418 Mode Addressing Mode Symbols................................ 479 Area Mode Register 0 (AMD0) ......................... 106 Area Mode Register 1 (AMD1) ......................... 108 Area Mode Register 32 (AMD32)...................... 109 Area Mode Register 4 (AMD4) ......................... 110 Area Mode Register 5 (AMD5) ......................... 111 Burst Transfer Mode......................................... 382 Combinations of Request Sense Modes and Transfer Modes ................................................ 383 Comparison of External Access in Big-endian and Little-endian Mode .............................. 117 Continuous Transfer Mode................................ 382 Conversion Modes of 8/10-bit A/D Converter .................................... 276 Differences and Similarities of Access in Little-endian and in Big-endian Mode....................... 124 DMA Transfer Operation in Sleep Mode ............ 391 DREC Signal Sense Modes ............................... 383 FR-CPU Programming Mode (16 Bits,Read/Write)............................ 431 FR-CPU ROM Mode (32 Bits,Read Only).......... 430 Internal Vector Mode (Single-chip Mode): Example of Minimum Connection with AF200........ 450 Internal Vector Mode (Single-chip Mode): Example of Standard Connection............................ 449 Low-power Consumption Mode Operations.......... 90 Mode Data......................................................... 68 Mode Pins ......................................................... 67 Mode Register (MODR) ................................... 116 Mode Register (SMR0 to SMR3)....................... 314 Notes on During Operation of PLL Clock Mode ................................................... 28 Notes on Edge Mode ........................................ 388 Notes on Level Mode........................................ 387 Operation in Asynchronous Mode (Operation Modes 0 and 1) ................... 337 Operation in Continuous-conversion Mode ......... 291 Operation in Single-conversion Mode ................ 291 Operation in Stop-conversion Mode ................... 292 Operation in Synchronous Mode (Operation Mode 2) ............................. 340 Operation Mode ................................................. 67 Phase Difference Counting Mode (Two Multiplication/Four Multiplication) .................................... 179 Return from Standby (Stop or Sleep) Mode ........ 270 Selecting Counting Mode.................................. 178 Single/Block Transfer Mode.............................. 381 512 Status Register (FLCR) (CPU Mode) ................. 427 Status Transition of the Low-power Consumption Mode ................................................... 97 Timer Mode [Down Count]............................... 178 Timing Chart of Read Cycles in Each Mode ....... 138 Transfer Termination in Continuous Transfer Mode (When both Addresses are Changed), 16/8-bit Data ...................................... 397 Transfer Termination in Continuous Transfer Mode (When Either address is Fixed), 16/8-bit Data ...................................... 396 Up/down Counting Mode ................................. 178 Write Cycle Timing in Each Mode .................... 140 Mode Data Mode Data ........................................................ 68 Mode Pins Mode Pins ......................................................... 67 Mode Register Mode Register (MODR) ................................... 116 Mode Register (SMR0 to SMR3) ...................... 314 MODR Mode Register (MODR) ................................... 116 Module Block Diagram of the Bit-search Module ........... 402 Block Diagram of the Delayed Interrupt Module .............................................. 256 List of Delayed Interrupt Module Registers ........ 256 Registers of the Bit-search Module .................... 402 Monitor Emulator Debugger and Monitor Debugger ........ 477 Month Data Register Month Data Register (CA6) .............................. 419 MSS Contention Among SCC,MSS,and INT Bits ....... 360 Multifunctional Timer Block Diagram of Multifunctional Timer ........... 228 Configuration of the Multifunctional Timer ........ 226 Explanation of Multifunctional Timer Operation ........................................... 238 Registers of Multifunctional Timer .................... 229 Multiplication Phase Difference Counting Mode (Two Multiplication/Four Multiplication).................................... 179 Multiplication and Division Instructions Multiplication and Division Instructions............. 486 Multiplication and Division Result Registers Multiplication and Division Result Registers (MDH and MDL).................................. 44 N No Delay Ordinary Branch (No Delay) Instructions ........... 490 Non-character Type Array Manipulation of a Non-character Type Array by Using a Character-string Handling Function............................................. 473 Normal Bus Access Normal Bus Access .......................................... 133 Normal Polarity Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) .......... 220 Note Note on Writing Data to the Flash Memory ........ 441 Notes on During Operation of PLL Clock Mode ................................................... 28 Notes on Edge Mode ........................................ 388 Notes on EIT ..................................................... 54 Notes on Level Mode ....................................... 387 Notes on Power-on............................................. 29 Notes on Using a Resource Interrupt Request as a DMA Transfer Request........................ 390 Notes on Using the 8/10-bit A/D Converter ........ 294 Notes on Using the UART ................................ 347 Operation of Peripheral Stop Control and Applicable Notes ................................................. 410 Other Note ...................................................... 448 O OCCP Compare Register (OCCP0 to OCCP7) .............. 233 OCRH,OCRI Open-drain Control Register (OCRH,OCRI)....... 161 OCS Output Control Register (OCS0 to OCS7) .......... 233 One-shot Operation One-shot Operation .......................................... 218 Open-drain Control Register Open-drain Control Register (OCRH,OCRI)....... 161 Open-drain Output Function Block Diagram of I/O Port with Open-drain Output Function............................................. 157 Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor .............. 155 Operation Comparison Operation Instruction ..................... 483 Counter Operation States .................................. 197 DMA Transfer Operation in Sleep Mode ............ 391 Explanation of 16-bit Free-run Timer Operation ........................................... 239 Explanation of 16-bit Output Compare Operation ........................................... 241 Explanation of Multifunctional Timer Operation ........................................... 238 Explanation of Operation for Branch Instructions without a Delay Slot .............................. 53 Explanation of the Operation for Branch Instructions with Delay Slots.................................... 50 External Interrupt Operation ..............................251 I2C Interface Operation .....................................367 Internal Clock Operation ...................................194 Logical Operation Instructions ...........................484 Low-power Consumption Mode Operations ..........90 Notes on During Operation of PLL Clock Mode....................................................28 One-shot Operation...........................................218 Operation for an Undefined Instruction Exception..............................................64 Operation for INT Instruction ..............................62 Operation for INTE Instruction ............................63 Operation for RETI Instruction ............................65 Operation for Step Trace Trap..............................63 Operation in Asynchronous Mode (Operation Modes 0 and 1) ...................337 Operation in Continuous-conversion Mode .........291 Operation in Single-conversion Mode.................291 Operation in Stop-conversion Mode ...................292 Operation in Synchronous Mode (Operation Mode 2) .............................340 Operation Mode .................................................67 Operation of 16-bit Input Capture.......................243 Operation of Peripheral Stop Control and Applicable Notes..................................................410 Operation of the 8-bit D/A Converter .................301 Operations for 8 Bits x 2 Channels and 16 Bits x 1 Channel........................186 Program Example for External Bus Operation............................................149 PWM Operation ...............................................216 Specification Example of a Program for External Bus Operation............................................148 Transfer Operation to DMAC Internal Register ..............................................391 Transfer Termination Operation (When both Addresses are Changed) ..........................................................399 Transfer Termination Operation (When Either address is Fixed) .............398 UART Operations.............................................335 Underflow Operation ........................................195 User Interrupt Operation......................................61 Operation Mode Operation in Asynchronous Mode (Operation Modes 0 and 1) ...................337 Operation in Synchronous Mode (Operation Mode 2) .............................340 Operation Mode .................................................67 Option Specification of the -K lib Option During Use of a Character-string Handling Function .............................................473 Ordinary Branch 20-bit Ordinary Branch Macroinstructions ..........493 32-bit Ordinary Branch Macroinstructions ..........495 513 Ordinary Branch (No Delay) Instructions ........... 490 Oscillation Clock Frequency Oscillation Clock Frequency ............................. 448 Other Other Note....................................................... 448 Other Instructions Other Instructions............................................. 492 Output Compare Explanation of 16-bit Output Compare Operation ........................................... 241 Timing of 16-bit Output Compare ...................... 242 Output Control Register Output Control Register (OCS0 to OCS7)........... 233 Output Pin Function of Output Pin...................................... 196 Output-data Register Output-data Register (SODR0 to SODR3) .......... 319 Overview Overview of Flash Memory............................... 424 Overview of Instructions..................................... 48 Overview of the Sleep Status ............................... 89 Overview of the Stop Status ................................ 89 Overview of Writing and Erasing Flash Memory..................................... 439 P Package Dimensions Package Dimensions of FPT-144P-M01 ................. 9 Package Dimensions of FPT-144P-M08 ................. 8 Package Dimensions of PGA-299C-A01 (MB91FV150 Only) ................................ 7 PC Program Counter (PC) ........................................ 43 PCNH Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5) .............................. 205 PCNL Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5) .............................. 205 PCR Pull-up Resistor Control Register (PCR6 to PCRI) .................................. 160 PCSR PWM Cycle Set Register (PCSR0 to PCSR5) .......................................................... 209 PCTR PLL Control Register (PCTR) ............................. 79 PDR Port Data Register (PDR) .................................. 158 PDRR DMA Request Suppression Register (PDRR) ........ 78 514 PDUT PWM Duty Set Register (PDUT0 to PDUT5) ......................................................... 210 Peripheral Stop Control Operation of Peripheral Stop Control and Applicable Notes ................................................. 410 Peripheral Stop Control Registers Peripheral Stop Control Registers ...................... 410 PGA-299C-A01 Package Dimensions of PGA-299C-A01 (MB91FV150 Only)................................ 7 Pin Assignment of MB91FV150 (PGA-299C-A01) ................................. 10 Phase Difference Counting Mode Phase Difference Counting Mode (Two Multiplication/Four Multiplication).................................... 179 Pin Assignment Pin Assignment of MB91FV150 (PGA-299C-A01) ................................. 10 Pin Assignments of MB91F155A, MB91155, MB91154 (FPT-144P-M08) and MB91F155A (FPT-144P-M01) .............. 12 Pin Processing Pin Processing ................................................... 26 Pin Status Pin Status in Each CPU State ............................ 465 Terms Related to Pin Status .............................. 464 Pins Used for Fujitsu Standard Serial Onboard Writing Pins Used for Fujitsu Standard Serial Onboard Writing .............................................. 447 Placing Placing the Flash Memory in Read/Reset Status................................................. 440 PLL Example of Setting the PLL Clock....................... 86 Example of the Related Assembler Source Code (Example of Switching to the PLL System)................................................ 88 Notes on During Operation of PLL Clock Mode ................................................... 28 PLL Control Register (PCTR) ............................. 79 PLL Clock Example of Setting the PLL Clock....................... 86 PLL Clock Mode Notes on During Operation of PLL Clock Mode ................................................... 28 PLL Control Register PLL Control Register (PCTR) ............................. 79 Port Block Diagram of Basic I/O Port ....................... 153 Block Diagram of I/O Port with a Pull-up Resistor.............................................. 154 Block Diagram of I/O Port with Open-drain Output Function............................................. 157 Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor .............. 155 I/O Port Block Diagrams .................................. 152 I/O Port Registers............................................. 152 Port Data Register (PDR).................................. 158 Port Data Register Port Data Register (PDR).................................. 158 Power-on Notes on Power-on............................................. 29 PPG Block Diagram of One Channel for the PPG Timer................................................. 202 Block Diagram of the Entire PPG Timer ............ 201 Features of PPG Timer ..................................... 200 Register List of PPG Timer ............................... 203 PPG Timer Block Diagram of One Channel for the PPG Timer................................................. 202 Block Diagram of the Entire PPG Timer ............ 201 Features of PPG Timer ..................................... 200 Register List of PPG Timer ............................... 203 Priority EIT Source Acceptance Priority .......................... 59 Priority Evaluation ........................................... 267 Priority of Channels ......................................... 390 Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt ...................... 390 Procedure Procedure for Flash Memory Write.................... 441 Setting Procedure for an External Interrupt ......... 251 Processing Pin Processing ................................................... 26 Processing for Saving and Restoring .................. 407 Program Causes of Reset Delays Other than Programs........ 81 Program Counter (PC) ........................................ 43 Specification Example of a Program for External Bus Operation ........................................... 148 Program Access Program Access ................................................. 46 Program Counter Program Counter (PC) ........................................ 43 Program Example Program Example for External Bus Operation ........................................... 149 Program Status Program Status (PS) ........................................... 40 Programmer System Configuration of AF200 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation .............. 448 PS Program Status (PS)............................................40 PTMR PWM Timer Register (PTMR0 to PTMR5).........211 Pull-up Resistor Block Diagram of I/O Port with a Pull-up Resistor ..............................................154 Block Diagram of I/O Port with Open-drain Output Function and Pull-up Resistor ...............155 Pull-up Resistor Control Register Pull-up Resistor Control Register (PCR6 to PCRI)...................................160 PWM Examples for Setting PWM Output to All-low or All-high ..............................................220 Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) ...........220 PWM Cycle Set Register (PCSR0 to PCSR5) ..........................................................209 PWM Duty Set Register (PDUT0 to PDUT5) ..........................................................210 PWM Operation ...............................................216 PWM Timer Register (PTMR0 to PTMR5).........211 PWM Cycle Set Register PWM Cycle Set Register (PCSR0 to PCSR5) ..........................................................209 PWM Duty Set Register PWM Duty Set Register (PDUT0 to PDUT5) ..........................................................210 PWM Output Examples for Setting PWM Output to All-low or All-high ..............................................220 Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) ...........220 PWM Timer PWM Timer Register (PTMR0 to PTMR5).........211 PWM Timer Register PWM Timer Register (PTMR0 to PTMR5).........211 R RCR Reload/Compare Register 0/1 (RCR 0, RCR 1) ..................................177 RDY Ready/Busy Signal (RDY/BUSYX) ...................436 Read Cycle Basic Read Cycle Timing Chart .........................134 Timing Chart of Read Cycles in Each Mode........138 Read/Reset Status Placing the Flash Memory in Read/Reset Status .................................................440 Read/Write Calendar Block Read/Write Control Register (CAC) ................................................417 515 FR-CPU Programming Mode (16 Bits,Read/Write)............................ 431 Read/Write Cycles Timing Chart for Mixed Read/Write Cycles........ 142 Reading Calendar Values Reading Calendar Values .................................. 421 Ready/Busy Signal Ready/Busy Signal (RDY/BUSYX) ................... 436 Receive-interrupt Generation Receive-interrupt Generation and Flag Set Timing ............................................... 324 Reference Chart Reference Chart for the Clock System .................. 87 Register 0 Detection Data Register (BSD0) ..................... 403 1 Detection Data Register (BSD1) ..................... 403 16-bit Reload Register (TMRLR0 to TMRLR3) ...................... 193 16-bit Timer Register (TMR0 to TMR3)............. 193 A/D Control Status Register 0 (ADCS0)............. 285 A/D Control Status Register 1 (ADCS1)............. 282 A/D Data Register (ADCR)............................... 288 Address Register (IADR) .................................. 364 Analog Input Control Register (AICR) ............... 162 Area Mode Register 0 (AMD0) ......................... 106 Area Mode Register 1 (AMD1) ......................... 108 Area Mode Register 32 (AMD32)...................... 109 Area Mode Register 4 (AMD4) ......................... 110 Area Mode Register 5 (AMD5) ......................... 111 Area Select Registers (ASR) and Area Mask Registers (AMR) ............................................... 104 Bus Control Register (IBCR)............................. 353 Bus Status Register (IBSR) ............................... 361 Calendar Block Read/Write Control Register (CAC) ................................................ 417 Calendar Test Register (CAS)............................ 420 Clock Control Register (ICCR).......................... 365 Communication Prescaler Control Register (CDCR).............................................. 320 Compare Clear Register .................................... 230 Compare Register (OCCP0 to OCCP7) .............. 233 Control Register ............................................... 272 Control Register (SCR0 to SCR3)...................... 312 Control Status Register (TMCSR0 to TMCSR3) ....................... 191 Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5) .............................. 205 Counter Control Register H/L ch.0 (CCRH0, CCRL0) ............................... 169 Counter Control Register H/L ch.1 (CCRH1, CCRL1) ............................... 173 Counter Status Register 0/1 (CSR0,CSR1).......... 174 D/A Control Registers (DACR0, DACR1, DACR2) ................ 299 D/A Data Registers (DADR2, DADR1, DADR0) ................ 300 516 Data Direction Register (DDR) ......................... 159 Data Register (IDAR)....................................... 364 Data Register (TCDT) ...................................... 230 Day Data Register (CA4).................................. 419 Day-of-the-week Data Register (CA5) ............... 419 Delayed Interrupt Control Register (DICR) ........ 257 Detection Result Register (BSRR) ..................... 404 DMA Request Suppression Register (PDRR) ....... 78 DMAC Control Status Register (DACSR) .......... 374 DMAC Pin Control Register (DATCR).............. 376 External Interrupt Source Register (EIRR0, EIRR1: External Interrupt Request Register 0,1) ....................................... 249 External Level Register (ELVR0,ELVR1: External Level Register) ................................... 250 External Pin Control Register 0 (EPCR0) ........... 112 External Pin Control Register 1 (EPCR1) ........... 115 Gear Control Register (GCR) .............................. 75 General Control Register 1 (GCN1) ................... 212 General Control Register 2 (GCN2) ................... 215 General-purpose Registers .................................. 39 Hold-request Cancellation Request Level Set Register (HRCL) ............................................. 266 Hour Data Register (CA3) ................................ 418 I/O Port Registers ............................................ 152 Input Capture Control Register (ICS01, ICS23) ................................... 236 Input Capture Data Register (IPCP0 to IPCP3)................................ 236 Input-data Register (SIDR0 to SIDR3) ............... 318 Interrupt Control Register (ICR00 to ICR47) ...... 264 Interrupt Enable Register (ENIR0,ENIR1: Interrupt ENable Register 0,1) ........................... 248 List of Delayed Interrupt Module Registers ........ 256 List of External Interrupt Control Block Registers ............................................ 247 List of Interrupt Control Registers ..................... 262 List of Registers for the 8/16-bit Up/Down Counter/Timer .................................... 168 List of the 8-bit D/A Converter Registers ........... 298 Little-endian Register (LER) ............................. 116 Minute Data Register (CA2) ............................. 418 Mode Register (MODR) ................................... 116 Mode Register (SMR0 to SMR3) ...................... 314 Month Data Register (CA6) .............................. 419 Multiplication and Division Result Registers (MDH and MDL).................................. 44 Open-drain Control Register (OCRH,OCRI) ...... 161 Output Control Register (OCS0 to OCS7) .......... 233 Output-data Register (SODR0 to SODR3).......... 319 Peripheral Stop Control Registers ...................... 410 PLL Control Register (PCTR) ............................. 79 Port Data Register (PDR).................................. 158 Pull-up Resistor Control Register (PCR6 to PCRI) .................................. 160 PWM Cycle Set Register (PCSR0 to PCSR5) ......................................................... 209 PWM Duty Set Register (PDUT0 to PDUT5) .......................................................... 210 PWM Timer Register (PTMR0 to PTMR5) ........ 211 Register Configuration of Clock Generator........... 69 Register List of PPG Timer ............................... 203 Register List of the 16-bit Reload Timer............. 190 Registers of Calendar Macros............................ 416 Registers of Multifunctional Timer .................... 229 Registers of the Bit-search Module .................... 402 Registers of the Bus Interface............................ 103 Registers of the DMA Controller ....................... 372 Registers of the I2C Interface ............................ 352 Register-to-register Transfer Instructions............ 489 Reload/Compare Register 0/1 (RCR 0, RCR 1).................................. 177 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) ...................... 71 Schema of the 8/10-bit A/D Converter Registers ............................................ 281 Second Data Register (CA1) ............................. 418 Standby Control Register (STCR)........................ 73 Status Register (FLCR) (CPU Mode) ................. 427 Status Register (SSR0 to SSR3)......................... 316 Stop Control Register 0 (STPR0)....................... 411 Stop Control Register 1 (STPR1)....................... 412 Stop Control Register 2 (STPR2)....................... 413 Table Base Register (TBR) ................................. 43 Timebase Timer Clear Register (CTBR)............... 74 Timer Control Status Register (TCCS) ............... 231 Transfer Operation to DMAC Internal Register.............................................. 391 UART Registers .............................................. 311 Up/down Count Register 0/1 (UDCR 0, UDCR 1) ............................ 176 Value Change Detection Data Register (BSDC).............................................. 404 Watchdog Reset Generation Delay Register (WPR) ................................................. 77 Writing Data to the Up/Down Count Register (UDCR) ............................................. 185 Year Data Register (CA7) ................................. 420 Register-to-register Register-to-register Transfer Instructions............ 489 Related Assembler Source Code Example of the Related Assembler Source Code (Example of Switching to the PLL System)................................................ 88 Relationship Relationship Between Data Bus Width and Control Signals ....................................... 117, 118 Releasing Bus Right Releasing Bus Right ......................................... 145 Releasing Interrupt Factors Releasing Interrupt Factors ............................... 269 Reload 16-bit Reload Register (TMRLR0 to TMRLR3).......................193 Baud Rate Based on the Internal Timer (16-bit Reload Timer 0)........................332 Block Diagram of the 16-bit Reload Timer..........189 Features of 16-bit Reload Timer.........................188 Register List of the 16-bit Reload Timer .............190 Reload and Compare Function ...........................181 Reload/Compare Register 0/1 (RCR 0, RCR 1) ..................................177 When the Reload and Compare Functions are Started Simultaneously....................................182 When the Reload Function is Started ..................181 Reload Register 16-bit Reload Register (TMRLR0 to TMRLR3).......................193 Reload Timer Baud Rate Based on the Internal Timer (16-bit Reload Timer 0)........................332 Block Diagram of the 16-bit Reload Timer..........189 Features of 16-bit Reload Timer.........................188 Register List of the 16-bit Reload Timer .............190 When the 16-bit Reload Timer is Used for Activation ......................................223 Reload/Compare Register Reload/Compare Register 0/1 (RCR 0, RCR 1) ..................................177 Request Sense Modes Combinations of Request Sense Modes and Transfer Modes ................................................383 Reset Block Diagram of the Reset Source Retention Circuit ..................................................84 Causes of Reset Delays Other than Programs ........81 Delaying Reset Generation ..................................81 External Reset Input............................................28 Initialization by Reset .........................................66 Initialization Reset ............................................421 Placing the Flash Memory in Read/Reset Status .................................................440 Reset Sequence ..................................................66 Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR).......................71 Reset Sources .....................................................66 Watchdog Reset Generation Delay Register (WPR) ..................................................77 Reset Source Register Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR).......................71 Reset Source Retention Circuit Block Diagram of the Reset Source Retention Circuit ..................................................84 517 Resource Notes on Using a Resource Interrupt Request as a DMA Transfer Request ........................ 390 Resource Instructions........................................ 497 Resource Interrupt Request Notes on Using a Resource Interrupt Request as a DMA Transfer Request ........................ 390 Restoring Processing for Saving and Restoring .................. 407 Restriction Restriction on Section Types ............................. 476 Restrictions on Branch Instructions with Delay Slots..................................................... 52 Result Detection Result Register (BSRR) ..................... 404 Multiplication and Division Result Registers (MDH and MDL) .................................. 44 RETI Operation for RETI Instruction ............................ 65 Return Notes on using External Interrupt to Return from STOP State where Clock Oscillation is Stopped .............................................. 252 Return from EIT................................................. 54 Return from Standby (Stop or Sleep) Mode ........ 270 Return from Stop State...................................... 251 Return from the Sleep Status ............................... 95 Return from the Stop Status................................. 93 Return Operation from STOP State .................... 253 Return Pointer (RP) ............................................ 43 Return Pointer Return Pointer (RP) ............................................ 43 RP Return Pointer (RP) ............................................ 43 RSRR Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) ...................... 71 S Saving Processing for Saving and Restoring .................. 407 SCC Contention Among SCC,MSS,and INT Bits........ 360 Schema Schema of the 8/10-bit A/D Converter Registers ............................................ 281 SCR Control Register (SCR0 to SCR3)...................... 312 Second Data Register Second Data Register (CA1).............................. 418 Second Word Second Word in the Descriptor .......................... 380 Section Data Transfer Section,16/8-bit Data ................... 395 518 Descriptor Access Section ................................ 393 Restriction on Section Types............................. 476 Sections .......................................................... 475 Section Types Restriction on Section Types............................. 476 Sector Address Table Sector Address Table ....................................... 426 Sector Erase Sector Erase .................................................... 443 Selecting Counting Mode Selecting Counting Mode ................................. 178 Selection Clock Selection Method ................................... 146 UART Baud-rate Selection ............................... 327 UART Baud-Rate Selection Circuit ................... 328 Send-interrupt Generation Send-interrupt Generation and Flag Set Timing............................................... 326 Serial Onboard Writing Basic Configuration of MB91F155A Serial Onboard Writing .............................................. 446 Pins Used for Fujitsu Standard Serial Onboard Writing .............................................. 447 Serial Programming Connection Example of Serial Programming Connection ...... 448 Setting Example of Setting the PLL Clock....................... 86 Examples for Setting PWM Output to All-low or All-high ............................................. 220 Setting .............................................................. 84 Settings of the Gear Function .............................. 83 Setting Calendar Values Setting Calendar Values ................................... 421 Setting Procedure Setting Procedure for an External Interrupt......... 251 Shift Instructions Shift Instructions.............................................. 487 SIDR Input-data Register (SIDR0 to SIDR3) ............... 318 Similarities Differences and Similarities of Access in Little-endian and in Big-endian Mode ...................... 124 Simulator Simulator Debugger ......................................... 477 Single/Block Transfer Single/Block Transfer Mode ............................. 381 Step Transfer (Single/Block Transfer)................ 384 Single-chip Mode Internal Vector Mode (Single-chip Mode): Example of Minimum Connection with AF200 ....... 450 Internal Vector Mode (Single-chip Mode): Example of Standard Connection ........................... 449 Single-conversion Mode Operation in Single-conversion Mode ................ 291 Slave Master/Slave-type Communication Function ...... 344 Sleep Block Diagram of the Sleep Control Block ........... 94 DMA Transfer Operation in Sleep Mode ............ 391 Overview of the Sleep Status............................... 89 Return from Standby (Stop or Sleep) Mode ........ 270 Return from the Sleep Status ............................... 95 Transition to the Sleep Status .............................. 94 SMR Mode Register (SMR0 to SMR3)....................... 314 SODR Output-data Register (SODR0 to SODR3).......... 319 Specification Specification of the -K lib Option During Use of a Character-string Handling Function............................................. 473 Specification Example Specification Example of a Program for External Bus Operation ........................................... 148 SSP System Stack Pointer (SSP) ................................ 43 SSR Status Register (SSR0 to SSR3)......................... 316 Stack Allocation of Stacks in the Little-endian area.................................................... 474 Interrupt Stack ................................................... 56 System Stack Pointer (SSP) ................................ 43 User Stack Pointer (USP).................................... 44 Standard Connection Internal Vector Mode (Single-chip Mode): Example of Standard Connection ........................... 449 Standby Return from Standby (Stop or Sleep) Mode ........ 270 Standby Control Register Standby Control Register (STCR)........................ 73 Start Word Descriptor Start Word....................................... 378 State Pin Status in Each CPU State ............................ 465 Return from Stop State ..................................... 251 Status A/D Control Status Register 0 (ADCS0) ............ 285 A/D Control Status Register 1 (ADCS1) ............ 282 Bus Status Register (IBSR) ............................... 361 Control Status Register (TMCSR0 to TMCSR3)....................... 191 Control Status Registers (PCNH0 to PCNH5, PCNL0 to PCNL5).............................. 205 Counter Status Register 0/1 (CSR0,CSR1) ......... 174 DMAC Control Status Register (DACSR) .......... 374 Execution Status of Automatic Algorithm .......... 431 Overview of the Sleep Status............................... 89 Overview of the Stop Status.................................89 Pin Status in Each CPU State .............................465 Placing the Flash Memory in Read/Reset Status .................................................440 Program Status (PS)............................................40 Return from the Sleep Status................................95 Return from the Stop Status .................................93 Status Register (FLCR) (CPU Mode)..................427 Status Register (SSR0 to SSR3) .........................316 Status Transition of the Low-power Consumption Mode....................................................97 Terms Related to Pin Status ...............................464 Timer Control Status Register (TCCS)................231 Transition to Stop Status .....................................92 Transition to the Sleep Status...............................94 Status Register Status Register (FLCR) (CPU Mode)..................427 Status Register (SSR0 to SSR3) .........................316 Status Transition Status Transition of the Low-power Consumption Mode....................................................97 STCR Standby Control Register (STCR) ........................73 Step Trace Trap Operation for Step Trace Trap..............................63 Step Transfer Step Transfer (Single/Block Transfer).................384 Stop Block Diagram of the Stop Control Block .............91 Operation in Stop-conversion Mode ...................292 Operation of Peripheral Stop Control and Applicable Notes..................................................410 Overview of the Stop Status.................................89 Peripheral Stop Control Registers.......................410 Return from Standby (Stop or Sleep) Mode.........270 Return from Stop State ......................................251 Return from the Stop Status .................................93 Stop Control Register 0 (STPR0) .......................411 Stop Control Register 1 (STPR1) .......................412 Stop Control Register 2 (STPR2) .......................413 Transition to Stop Status .....................................92 Stop Control Register Stop Control Register 0 (STPR0) .......................411 Stop Control Register 1 (STPR1) .......................412 Stop Control Register 2 (STPR2) .......................413 STOP State Notes on using External Interrupt to Return from STOP State where Clock Oscillation is Stopped ..............................................252 Return Operation from STOP State ....................253 STPR Stop Control Register 0 (STPR0) .......................411 Stop Control Register 1 (STPR1) .......................412 Stop Control Register 2 (STPR2) .......................413 519 Structure Insertion Structure Insertion ............................................ 472 Subtraction Addition and Subtraction Instructions................. 483 Suppression Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt ...................... 390 Switching to the PLL System Example of the Related Assembler Source Code (Example of Switching to the PLL System) ................................................ 88 Symbols Addressing Mode Symbols................................ 479 Symbols Used in the Timing Charts ................... 392 Synchronous Mode Operation in Synchronous Mode (Operation Mode 2) ............................. 340 System Configuration System Configuration of AF200 Flash Microcontroller Programmer by Yokogawa Digital Computer Corporation .............. 448 System Stack Pointer System Stack Pointer (SSP)................................. 43 T Table Base Register Table Base Register (TBR).................................. 43 TBR Table Base Register (TBR).................................. 43 TCCS Timer Control Status Register (TCCS) ............... 231 TCDT Data Register (TCDT) ...................................... 230 Terms Terms Related to Pin Status............................... 464 Third Word Third Word in the Descriptor............................. 380 Timebase Timer Timebase Timer ................................................. 81 Timebase Timer Clear Register Timebase Timer Clear Register (CTBR) ............... 74 Timer Control Status Register Timer Control Status Register (TCCS) ............... 231 Timer Mode Timer Mode [Down Count] ............................... 178 Timer Register 16-bit Timer Register (TMR0 to TMR3)............. 193 Timing Timing of 16-bit Output Compare ...................... 242 Timing to Clear the 16-bit Free-run Timer .......... 240 Timing Chart Automatic Wait Cycle Timing Chart .................. 143 Basic Read Cycle Timing Chart......................... 134 520 Basic Write Cycle Timing Chart........................ 136 Interrupt Sources and Timing Chart (PWM Output: Normal Polarity) .......... 220 Symbols Used in the Timing Charts................... 392 Timing Chart for Mixed Read/Write Cycles ....... 142 Timing Chart of External Wait Cycle................. 144 Timing Chart of Read Cycles in Each Mode ....... 138 TMCSR Control Status Register (TMCSR0 to TMCSR3) ...................... 191 TMR 16-bit Timer Register (TMR0 to TMR3) ............ 193 TMRLR 16-bit Reload Register (TMRLR0 to TMRLR3) ...................... 193 Transfer Burst Transfer.................................................. 386 Burst Transfer Mode ........................................ 382 Combinations of Request Sense Modes and Transfer Modes................................................ 383 Continuous Transfer......................................... 385 Continuous Transfer Mode ............................... 382 Data Transfer Section,16/8-bit Data ................... 395 DMA Transfer Operation in Sleep Mode............ 391 Immediate Value Set,16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions ........................................ 487 Notes on Using a Resource Interrupt Request as a DMA Transfer Request........................ 390 Register-to-register Transfer Instructions ........... 489 Single/Block Transfer Mode ............................. 381 Step Transfer (Single/Block Transfer)................ 384 Suppression of DMA Transfer upon Generation of a Higher-priority Interrupt ...................... 390 Transfer Operation to DMAC Internal Register ............................................. 391 Transfer-acceptance Signal Output .................... 389 Transfer-end Signal Output ............................... 389 Transfer Instructions Immediate Value Set,16-bit Immediate Value, and 32-bit Immediate Value Transfer Instructions ........................................ 487 Register-to-register Transfer Instructions ........... 489 Transfer Operation Transfer Operation to DMAC Internal Register ............................................. 391 Transfer Termination Transfer Termination in Continuous Transfer Mode (When both Addresses are Changed), 16/8-bit Data ...................................... 397 Transfer Termination in Continuous Transfer Mode (When Either address is Fixed), 16/8-bit Data ...................................... 396 Transfer Termination Operation (When both Addresses are Changed) ......................................................... 399 Transfer Termination Operation (When Either address is Fixed)............. 398 Transfer-acceptance Signal Output Transfer-acceptance Signal Output .................... 389 Transfer-end Signal Output Transfer-end Signal Output ............................... 389 Transition Status Transition of the Low-power Consumption Mode ................................................... 97 Transition to Stop Status..................................... 92 Transition to the Sleep Status .............................. 94 Trap Coprocessor Absence Trap.................................. 64 Coprocessor Error Trap ...................................... 65 Operation for Step Trace Trap ............................. 63 U UART Notes on Using the UART ................................ 347 UART Baud-rate Selection ............................... 327 UART Baud-Rate Selection Circuit ................... 328 UART Block Diagram...................................... 306 UART Features................................................ 304 UART Interrupts.............................................. 322 UART Operations ............................................ 335 UART Pin Block Diagram ................................ 310 UART Pins...................................................... 308 UART Registers .............................................. 311 UART-related Interrupts ................................... 323 UDCR Up/down Count Register 0/1 (UDCR 0, UDCR 1) ............................ 176 Writing Data to the Up/Down Count Register (UDCR) ............................................. 185 Undefined Instruction Exception Operation for an Undefined Instruction Exception ............................................. 64 Underflow Operation Underflow Operation........................................ 195 Up/Down Count Register Writing Data to the Up/Down Count Register (UDCR) ............................................. 185 Up/down Count Register Up/down Count Register 0/1 (UDCR 0, UDCR 1) ............................ 176 Up/Down Counter/Timer Block Diagram of the 8/16-bit Up/Down Counter/Timer .................................... 166 Characteristics of the 8/16-bit Up/Down Counter/Timer .................................... 164 List of Registers for the 8/16-bit Up/Down Counter/Timer .................................... 168 Up/down Counting Mode Up/down Counting Mode.................................. 178 User Interrupt Operation User Interrupt Operation......................................61 User Stack Pointer User Stack Pointer (USP) ....................................44 Using Double Type and Long-double Type Using Double Type and Long-double Type .........474 USP User Stack Pointer (USP) ....................................44 V Value Change Detection Data Register Value Change Detection Data Register (BSDC) ..............................................404 Variables Allocation of Variables Having Initial Values ................................................472 Vector Table Vector Table ......................................................57 W Wait Cycle Automatic Wait Cycle Timing Chart ..................143 Timing Chart of External Wait Cycle .................144 Wait Cycle .......................................................133 Watchdog Control Block Diagram of the Watchdog Control Block....................................................80 Watchdog Cycle Control Register Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR).......................71 Watchdog Reset Generation Delay Register Watchdog Reset Generation Delay Register (WPR) ..................................................77 Watchdog Timer Activating the Watchdog Timer ...........................80 Watchdog Timer Function ...................................28 When the 16-bit Reload Timer is Used for Activation When the 16-bit Reload Timer is Used for Activation ......................................223 When the Compare Function is Started When the Compare Function is Started ...............182 When the Reload and Compare Functions are Started Simultaneously When the Reload and Compare Functions are Started Simultaneously....................................182 When the Reload Function is Started When the Reload Function is Started ..................181 Word Access Word Access ....................................................128 WPR Watchdog Reset Generation Delay Register (WPR) ..................................................77 521 Write Cycle Basic Write Cycle Timing Chart ........................ 136 Write Cycle Timing in Each Mode..................... 140 Writing and Erasing Overview of Writing and Erasing Flash Memory..................................... 439 Writing Data Note on Writing Data to the Flash Memory......... 441 Writing Data to the Flash Memory ..................... 441 Writing Data to the Up/Down Count Register (UDCR) ............................................. 185 WTCR Reset Source Register (RSRR) and Watchdog Cycle Control Register (WTCR) ...................... 71 522 X x Operations for 8 Bits x 2 Channels and 16 Bits x 1 Channel....................... 186 Y Year Data Register Year Data Register (CA7)................................. 420 CM71-10110-5E FUJITSU SEMICONDUCTOR FR30 32-BIT MICROCONTROLLER MB91150 Series HARDWARE MANUAL June 2006 the fifth edition Published FUJITSU LIMITED Edited Business Promotion Dept. Electronic Devices