FDS3692
N-Channel PowerTrench® MOSFET
100V, 4.5A, 60mΩ
Features
Applications
• r DS(ON) = 50mΩ (Typ.), VGS = 10V, ID = 4.5A
• DC/DC converters and Off-Line UPS
• Qg(tot) = 11nC (Typ.), VGS = 10V
• Distributed Power Architectures and VRMs
• Low Miller Charge
• Primary Switch for 24V and 48V Systems
• Low QRR Body Diode
• High Voltage Synchronous Rectifier
• Optimized efficiency at high frequencies
• Direct Injection / Diesel Injection Systems
• UIS Capability (Single Pulse and Repetitive Pulse)
• 42V Automotive Load Control
• Electronic Valve Train Systems
Formerly developmental type 82745
Branding Dash
5
1
2
3
4
5
4
6
3
7
2
8
1
SO-8
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDSS
Drain to Source Voltage
Parameter
Ratings
100
Units
V
VGS
Gate to Source Voltage
±20
V
Drain Current
ID
Continuous (TA = 25oC, VGS = 10V, R θJA = 50oC/W)
4.5
A
Continuous (TA = 100oC, VGS = 10V, RθJA = 50oC/W)
2.8
A
Pulsed
E AS
PD
TJ, TSTG
Figure 4
A
Single Pulse Avalanche Energy (Note 1)
171
mJ
Power dissipation
2.5
W
Derate above 25oC
20
mW/oC
Operating and Storage Temperature
o
-55 to 150
C
Thermal Characteristics
RθJA
Thermal Resistance, Junction to Ambient at 10 seconds (Note 3)
50
oC/W
RθJA
Thermal Resistance, Junction to Ambient at 1000 seconds (Note 3)
85
o
C/W
25
o
C/W
RθJC
Thermal Resistance, Junction to Case (Note 2)
Package Marking and Ordering Information
Device Marking
FDS3692
©2002 Fairchild Semiconductor Corporation
Device
FDS3692
Package
SO-8
Reel Size
13''
Tape Width
12mm
Quantity
2500 units
FDS3692 Rev. C
FDS3692
April 2013
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
100
-
-
V
-
-
1
-
-
250
µA
VGS = ±20V
-
-
±100
nA
V GS = VDS, ID = 250µA
2
-
4
V
ID = 4.5A, VGS = 10V
-
0.050
0.060
ID = 2A, VGS = 6V
-
0.064
0.096
ID = 4.5A, VGS = 10V,
TC = 150oC
-
0.101
0.122
-
746
-
-
115
-
pF
-
27
-
pF
nC
VDS = 80V
VGS = 0V
TC = 150oC
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
VDS = 25V, VGS = 0V,
f = 1MHz
pF
Qg(TOT)
Total Gate Charge at 10V
VGS = 0V to 10V
-
11
15
Qg(TH)
Threshold Gate Charge
VGS = 0V to 2V
-
1.4
1.9
nC
Qgs
Gate to Source Gate Charge
-
3.5
-
nC
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
VDD = 50V
ID = 4.5A
Ig = 1.0mA
-
2.1
-
nC
-
2.8
-
nC
ns
Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
54
td(ON)
Turn-On Delay Time
-
9.8
-
ns
tr
Rise Time
-
26
-
ns
td(OFF)
Turn-Off Delay Time
-
34
-
ns
tf
Fall Time
-
26
-
ns
tOFF
Turn-Off Time
-
-
90
ns
VDD = 50V, ID = 4.5A
VGS = 10V, RGS = 26Ω
Drain-Source Diode Characteristics
ISD = 4.5A
-
-
1.25
V
ISD = 2A
-
-
1.0
V
Reverse Recovery Time
ISD= 4.5A, dISD/dt= 100A/µs
-
-
47
ns
Reverse Recovered Charge
ISD= 4.5A, dISD/dt= 100A/µs
-
-
64
nC
VSD
Source to Drain Diode Voltage
trr
QRR
Notes:
1: EAS of 171mJ is based on starting T J = 25°C, L = 38mH, IAS = 3A. 100% test at L = 1mH, IAS = 10.3A.
2: RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins. R θJC is guaranteed by design while RθCA is determined by the user’s board design.
3: RθJA is measured with 1.0 in2 copper on FR-4 board
©2002 Fairchild Semiconductor Corporation
FDS3692 Rev. C
FDS3692
Electrical Characteristics TA = 25°C unless otherwise noted
5
1.0
VGS = 10V
4
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
3
2
1
0.2
0
0
0
25
50
75
100
125
150
25
50
TA , AMBIENT TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
2
0.1
150
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
1
ZθJA, NORMALIZED
THERMAL IMPEDANCE
75
100
125
TC, CASE TEMPERATURE (oC)
RθJA=50oC/W
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.001
10-5
10 -4
10-3
10-2
10-1
100
t , RECTANGULAR PULSE DURATION (s)
101
102
103
Figure 3. Normalized Maximum Transient Thermal Impedance
200
100
IDM, PEAK CURRENT (A)
TA = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
I = I25
VGS = 10V
150 - TC
125
10
1
10-5
10-4
10 -3
10-2
10-1
t, PULSE WIDTH (s)
100
10 1
102
103
Figure 4. Peak Current Capability
©2002 Fairchild Semiconductor Corporation
FDS3692 Rev. C
FDS3692
Typical Characteristics TA = 25°C unless otherwise noted
FDS3692
Typical Characteristics TA = 25°C unless otherwise noted
7
STARTING TJ = 25 oC
10µs
10
100µs
1
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
100ms
0.1
SINGLE PULSE
TJ = MAX RATED
TC = 25o C
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
200
100
STARTING TJ = 150o C
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(I AS*R)/(1.3*RATED BVDSS - VDD) +1]
1s
0.01
0.1
1
0.1
10
100
300
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
30
Figure 6. Unclamped Inductive Switching
Capability
30
20
15
o
TJ = 150 C
TJ = 25oC
10
TA = 25 oC
VGS = 10V
25
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
25
100
TJ = -55o C
5
20
VGS = 7V
15
VGS = 6V
10
VGS = 5V
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0
0
3.5
4.0
4.5
5.0
5.5
6.0
VGS , GATE TO SOURCE VOLTAGE (V)
0
6.5
Figure 7. Transfer Characteristics
2.0
Figure 8. Saturation Characteristics
2.5
70
VGS = 6V
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
DRAIN TO SOURCE ON RESISTANCE (m Ω)
0.5
1.0
1.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
65
60
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
55
VGS = 10V
50
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
VGS = 10V, ID = 4.5A
0.5
45
1.0
1.5
2.0
2.5
3.0
3.5
ID, DRAIN CURRENT (A)
4.0
4.5
Figure 9. Drain to Source On Resistance vs Drain
Current
©2002 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
Figure 10. Normalized Drain to Source On
Resistance vs Junction Temperature
FDS3692 Rev. C
FDS3692
Typical Characteristics TA = 25°C unless otherwise noted
1.2
1.2
ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
1.0
0.9
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
10
CISS = CGS + CGD
1000
COSS ≅ CDS + C GD
C RSS = CGD
100
VGS = 0V, f = 1MHz
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE (o C)
160
Figure 12. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
VGS , GATE TO SOURCE VOLTAGE (V)
2000
-80
160
Figure 11. Normalized Gate Threshold Voltage vs
Junction Temperature
C, CAPACITANCE (pF)
1.1
VDD = 50V
8
6
4
2
WAVEFORMS IN
DESCENDING ORDER:
ID = 4.5A
ID = 2A
0
10
0.1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 13. Capacitance vs Drain to Source
Voltage
©2002 Fairchild Semiconductor Corporation
100
0
2
4
6
8
Qg, GATE CHARGE (nC)
10
12
Figure 14. Gate Charge Waveforms for Constant
Gate Currents
FDS3692 Rev. C
FDS3692
Test Circuits and Waveforms
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
+
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
IAS
0V
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
Figure 16. Unclamped Energy Waveforms
VDS
VDD
Qg(TOT)
VDS
L
VGS = 10V
VGS
+
VDD
VGS
-
VGS = 2V
DUT
Qgs2
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
RL
tr
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
50%
50%
PULSE WIDTH
VGS
0
Figure 19. Switching Time Test Circuit
©2002 Fairchild Semiconductor Corporation
10%
Figure 20. Switching Time Waveforms
FDS3692 Rev. C
(T
–T )
JM
A
P
= ------------------------------DM
R θJA
maximum transient thermal impedance curve.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. The area, in square inches is the top copper
area including the gate and source pads.
26
0.23 + Area
R θ JA = 64 + -------------------------------
(EQ. 2)
(EQ. 1)
In using surface mount devices such as the SO8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of PDM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 22 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package.
Therefore, CTHERM1 through CTHERM5 and RTHERM1
through RTHERM5 remain constant for each of the thermal
models. A listing of the model component values is available
in Table 1.
4. The use of thermal vias.
200
5. Air flow and board orientation.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
RθJA = 64 + 26/(0.23+Area)
RθJA (o C/W)
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
150
100
50
0.001
0.01
0.1
1
AREA, TOP COPPER AREA (in2)
10
Figure 21. Thermal Resistance vs Mounting
Pad Area
ZθJA, THERMAL
IMPEDANCE (o C/W)
150
120
90
COPPER BOARD AREA - DESCENDING ORDER
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.00 in2
60
30
0
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
102
103
Figure 22. Thermal Impedance vs Mounting Pad Area
©2002 Fairchild Semiconductor Corporation
FDS3692 Rev. C
FDS3692
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
rev Aug 2002
LDRAIN
DPLCAP
10
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
RLDRAIN
RSLC1
51
RSLC2
5
51
Ebreak 11 7 17 18 109.7
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
-
It 8 17 1
DRAIN
2
5
EVTHRES
+ 19 8
+
LGATE
GATE
1
Lgate 1 9 5.61e-9
Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9
ESLC
11
+
17
EBREAK 18
-
50
RDRAIN
6
8
ESG
DBREAK
+
.SUBCKT FDS3692 2 1 3 ;
Ca 12 8 2.82e-10
Cb 15 14 2.82e-10
Cin 6 8 7.0e-10
EVTEMP
RGATE +
18 22
9
20
21
16
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
7
RSOURCE
RLgate 1 9 56.1
RLdrain 2 5 10
RLsource 3 7 19.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
S1A
12
S2A
13
8
14
13
S1B
CA
18
RVTEMP
5
8
EDS
-
19
VBAT
+
IT
14
+
+
EGS
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 28.0e-3
Rgate 9 20 3.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 14.0e-3
Rvthres 22 8 Rvthresmod 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
17
CB
6
8
RLSOURCE
RBREAK
15
S2B
13
SOURCE
3
-
8
22
RVTHRES
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*40),2.5))}
.MODEL DbodyMOD D (IS=2.4E-12 N=1.03 RS=8.2e-3 TRS1=2.1e-3 TRS2=4.7e-7
+ CJO=5.5e-10 M=0.57 TT=3.25e-8 XTI=4.6)
.MODEL DbreakMOD D (RS=1.6 TRS1=2.4e-3 TRS2=-1.0e-5)
.MODEL DplcapMOD D (CJO=1.55e-10 IS=1e-30 N=10 M=0.54)
.MODEL MmedMOD NMOS (VTO=3.8 KP=2.1 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=3.7)
.MODEL MstroMOD NMOS (VTO=4.3 KP=26 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.26 KP=0.04 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=37 RS=0.1)
.MODEL RbreakMOD RES (TC1=1.1e-3 TC2=-1.0e-8)
.MODEL RdrainMOD RES (TC1=9.0e-3 TC2=2.9e-5)
.MODEL RSLCMOD RES (TC1=2.5e-3 TC2=2.2e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-4.8e-3 TC2=-1.1e-5)
.MODEL RvtempMOD RES (TC1=-3.0e-3 TC2=1.5e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.0 VOFF=-2.0)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.0 VOFF=-3.0)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=1.0)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=1.0 VOFF=-1.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
FDS3692 Rev. C
FDS3692
PSPICE Electrical Model
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
spe.ebreak n11 n7 n17 n18 = 109.7
spe.eds n14 n8 n5 n8 = 1
GATE
spe.egs n13 n8 n6 n8 = 1
1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
LGATE
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
-
MMED
MSTRO
RLGATE
CIN
8
i.it n8 n17 = 1
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
l.lgate n1 n9 = 5.61e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 19.8
DBREAK
50
12
S2A
13
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
15
14
13
S1B
CA
RBREAK
17
18
RVTEMP
S2B
13
CB
+
-
IT
14
+
6
8
EGS
19
VBAT
5
8
EDS
-
+
8
22
RVTHRES
res.rbreak n17 n18 = 1, tc1=1.1e-3,tc2=-1.0e-8
res.rdrain n50 n16 = 28.0e-3, tc1=9.0e-3,tc2=2.9e-5
res.rgate n9 n20 = 3.7
res.rslc1 n5 n51 = 1e-6, tc1=2.5e-3,tc2=2.2e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 14.0e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-4.8e-3,tc2=-1.1e-5
res.rvtemp n18 n19 = 1, tc1=-3.0e-3,tc2=1.5e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/40))** 2.5))
}
©2002 Fairchild Semiconductor Corporation
FDS3692 Rev. C
FDS3692
SABER Electrical Model
REV Aug 2002
template FDS3692 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2.4e-12,nl=1.03,rs=8.2e-3,trs1=2.1e-3,trs2=4.7e-7,cjo=5.5e-10,m=0.57,tt=3.25e-8,xti=4.6)
dp..model dbreakmod = (rs=1.6,trs1=2.4e-3,trs2=-1.0e-5)
dp..model dplcapmod = (cjo=1.55e-10,isl=10e-30,nl=10,m=0.54)
m..model mmedmod = (type=_n,vto=3.8,kp=2.1,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=4.3,kp=26,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.26,kp=0.04,is=1e-30, tox=1,rs=0.1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.0,voff=-2.0)
LDRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2.0,voff=-3.0)
DPLCAP 5
DRAIN
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.5,voff=1.0)
2
10
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=1.0,voff=-1.5)
RLDRAIN
c.ca n12 n8 = 2.82e-10
RSLC1
51
c.cb n15 n14 = 2.82e-10
RSLC2
c.cin n6 n8 = 7.0e-10
FDS3692
SPICE Thermal Model
JUNCTION
th
REV Aug 2002
FDS3692
Copper Area =1.0 in2
CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 TL 2
RTHERM1
CTHERM1
8
RTHERM2
RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23
RTHERM3
SABER Thermal Model
RTHERM4
CTHERM2
7
CTHERM3
6
CTHERM4
2
Copper Area = 1.0 in
template thermal_model th tl
thermal_c th, tl
{
CTHERM1 TH 8 4e-4
CTHERM2 8 7 5e-3
CTHERM3 7 6 6e-2
CTHERM4 6 5 9e-2
CTHERM5 5 4 3e-1
CTHERM6 4 3 4e-1
CTHERM7 3 2 9e-1
CTHERM8 2 TL 2
5
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM1 TH 8 5e-1
RTHERM2 8 7 6e-1
RTHERM3 7 6 4
RTHERM4 6 5 5
RTHERM5 5 4 8
RTHERM6 4 3 9
RTHERM7 3 2 15
RTHERM8 2 TL 23
}
CTHERM7
RTHERM7
2
CTHERM8
RTHERM8
CASE
tl
TABLE 1. THERMAL MODELS
0.04 in2
0.28 in2
0.52 in2
0.76 in2
1.0 in2
CTHERM6
3.2e-1
3.5e-1
4.0e-1
4.0e-1
4.0e-1
CTHERM7
8.5e-1
9.0e-1
9.0e-1
9.0e-1
9.0e-1
CTHERM8
0.3
1.8
2.0
2.0
2.0
RTHERM6
24
18
12
10
9
RTHERM7
36
21
18
16
15
RTHERM8
53
37
30
28
23
COMPONANT
©2002 Fairchild Semiconductor Corporation
FDS3692 Rev. C
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Rev. I64