FSUSB45 — High-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Features Description The FSUSB45 is a bi-directional, low-power, two-port, High-Speed, USB2.0 switch. Configured as a doublepole, double-throw (DPDT) switch, it is optimized for switching between two HS (480 Mbps) sources or an HS source and a Full-Speed (12 Mbps) source. Low On Capacitance: 7.0 pF Typical Low On Resistance: 3.9 Ω Typical Low Power Consumption: 1 μA Maximum - 15 μA Maximum ICCT over an Expanded Voltage Range (VIN=1.8 V, VCC=4.3 V) Wide -3 db Bandwidth: > 720 MHz Packaged in: - 10-Lead MicroPak™ (1.6 x 2.1 mm) - 10-Lead UMLP (1.4 x 1.8 mm) 8 kV ESD Rating, >16 kV Power/GND ESD Rating Power-Off Protection on All Ports When VCC=0 V - D+/D- Pins Tolerate up to 5.25 V Applications Cell Phone, PDA, Digital Camera, and Notebook LCD Monitor, TV, and Set-Top Box IMPORTANT NOTE: For additional performance information, please contact [email protected]. The FSUSB45 is compatible with the requirements of USB2.0 and features an extremely low on capacitance (CON) of 7.0 pF. The wide bandwidth of this device (720 MHz) exceeds the bandwidth needed to pass the third harmonic, resulting in signals with minimum edge and phase distortion. Superior channel-to-channel crosstalk also minimizes interference. The FSUSB45 contains special circuitry on the switch I/O pins for applications where the VCC supply is powered-off (VCC=0), which allows the device to withstand an over-voltage condition. This device is designed to minimize current consumption even when the control voltage applied to the SEL pin is lower than the supply voltage (VCC). This feature is especially valuable to mobile applications, such as cell phones, allowing for direct interface with the general-purpose I/Os of the baseband processor. An additional feature is the detection of the 1,1 state on D+/D- to signal an interrupt (INT) to the processor when entering a dedicated charging port mode of operation. INT HSD1+ D+ HSD2+ HSD1DHSD2Sel Figure 1. Analog Symbol Ordering Information Part Number Top Mark Operating Temperature Range FSUSB45L10X JA -40 to +85°C 10-Lead, MicroPak™ 1.6 x 2.1 mm, JEDEC MO-255B FSUSB45UMX JB -40 to +85°C 10-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.4 x 1.8 mm Package MicroPak™ is a trademark of Fairchild Semiconductor Corporation. © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 www.fairchildsemi.com FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect July 2013 Vcc 1 Sel 10 9 INT HSD1+ 2 8 HSD1- D+ 3 HSD2+ 3 7 HSD2- GND 4 4 6 D- D- 5 D+ 5 HSD1+ HSD2+ 2 1 6 10 Sel 9 Vcc 8 INT 7 HSD2- HSD1- GND Figure 2. Pad Assignments for MicroPak (Top Through View) Figure 3. Pin Assignments for UMLP (Top Through View) Pin Definitions MicroPak™ Pin # UMLP Pin # Name 9 8 INT Interrupt Signaling Output Pin 1 10 Sel Switch Select 4, 6 3, 5 D+, D- USB Data Bus 2, 3, 7, 8 1, 2, 6, 7 HSDn+, HSDn- 5 4 GND Description Multiplexed Source Inputs Ground Truth Table Sel Switch Connection INT Output L D+, D-=HSD1+, HSD1- LOW H D+, D-=HSD2+, HSD2- HIGH © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Pin Assignments www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC Parameter Supply Voltage VCNTRL (1) DC Input Voltage (S) (1) VSW DC Switch I/O Voltage IIK DC Input Diode Current IOUT DC Output Current TSTG Storage Temperature Max. Unit -0.5 +5.5 V -0.5 VCC V -0.50 5.25 V -50 -65 Human Body Model, JEDEC: JESD22-A114 ESD Min. mA 50 mA +150 °C All Pins 7 I/O to GND 8 Power to GND 16 Charged Device Model, JEDEC: JESD22-C101 kV 2 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VCNTRL VSW TA Parameter Min. Max. Unit 3.0 4.3 V 0 VCC V Switch I/O Voltage -0.5 VCC V Operating Temperature -40 85 °C Supply Voltage (2) Control Input Voltage (Sel) Note: 2. The control input must be held HIGH or LOW; it must not float. © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Absolute Maximum Ratings www.fairchildsemi.com 3 All typical value are at 25°C, VCC=3.3 V unless otherwise specified. Symbol Parameter VIK Clamp Diode Voltage VIH Input Voltage High Conditions IIN=-18 mA VCC (V) TA=- 40ºC to +85ºC Min. Typ. 3.0 Max. -1.2 3.0 to 3.6 1.3 4.3 1.7 Units V V V 3.0 to 3.6 0.5 V 4.3 0.7 V VIL Input Voltage Low VOH Output Voltage High IOH=-2 mA VOL Output Voltage Low IOL=2 mA Control Input Leakage VSW=0 to VCC 4.3 -1 1 µA INC(OFF), INO(OFF) Off State Leakage HSD1n or HSD2n=0 V, 3.6 V or floating, D+/-=0 or 3.6 V 4.3 -2 2 µA IDn(ON) ON State Leakage HSD1n or HSD2n=0 V, 3.6 V or floating, D+/-=0 or 3.6 V 4.3 -2 2 µA IOFF Power-Off Leakage Current (All I/O Ports) VSW=0 V to 4.3 V, VCC=0 V, Figure 5 0 -2 2 µA RON HS Switch On Resistance 6.5 IIN ∆RON ICC ICCT 3.0 to 3.6 2.4 4.3 2.4 V 3.0 to 3.6 0.25 4.3 0.25 V VSW=0.4 V, ION=-8 mA, Figure 4 3.0 3.9 HS Delta RON VSW=0.4 V, ION=-8 mA 3.0 0.65 Quiescent Supply Current VCNTRL=0 or VCC, IOUT=0 4.3 1.0 µA Increase in ICC Current per Control Voltage and VCC VCNTRL=2.6 V, VCC=4.3 V 4.3 10.0 µA VCNTRL=1.8 V, VCC=4.3 V 4.3 20.0 µA (3) (4) Notes: 3. Measured by the voltage drop between HSDn and Dn pins at the indicated current through the switch. On resistance is determined by the lower of the voltage on the two (HSDn or Dn ports). 4. Guaranteed by characterization. © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect DC Electrical Characteristics www.fairchildsemi.com 4 All typical value are for VCC=3.3 V at 25°C unless otherwise specified. Parameter tON Turn-On Time, S to Output RL=50 Ω, CL=5 pF, VSW=0.8 V, Figure 6, Figure 7 3.0 to 3.6 13 30 ns tOFF Turn-Off Time, S to Output RL=50 Ω, CL=5 pF, VSW=0.8V, Figure 6, Figure 7 3.0 to 3.6 12 25 ns tPD Propagation Delay CL=5 pF, RL=50 Ω, Figure 6, Figure 8 3.3 0.25 tBBM Break-Before-Make RL=50 Ω, CL=5 pF, VSW1=VSW2=0.8 V, Figure 12 3.0 to 3.6 RL=50 Ω, CL=5 pF 3.0 to 3.6 tPLH/HL Conditions (5) INT Propagation Delay (5) VCC (V) TA=- 40 to +85°C Symbol Min. Typ. Max. 2.0 Units ns 6.5 ns 10 ns OIRR Off Isolation RL=50 Ω, f=24 0MHz, Figure 14 3.0 to 3.6 -30 dB Xtalk Non-Adjacent Channel Crosstalk RL=50 Ω, f=240 MHz, Figure 15 3.0 to 3.6 -45 dB 720 MHz 550 MHz BW -3 db Bandwidth RL=50 Ω, CL=0 pF, Figure 13 RL=50 Ω, CL=5 pF, Figure 13 3.0 to 3.6 Note: 5. Guaranteed by characterization. USB Hi-Speed-Related AC Electrical Characteristics Symbol tSK(P) tJ Parameter Skew of Opposite Transitions of (6) the Same Output Total Jitter (6) Conditions VCC (V) TA=- 40 to +85°C Min. Typ. Max. Units CL=5 pF, RL=50 Ω, Figure 9 3.0 to 3.6 20 ps RL=50 Ω, CL=5 pF, tR=tF=500 ps (10-90%) at 15 480 Mbps (PRBS=2 – 1) 3.0 to 3.6 200 ps Note: 6. Guaranteed by characterization. Capacitance Symbol CIN Parameter Conditions TA=- 40 to +85°C Min. Typ. Max. Units Control Pin Input Capacitance VCC=0 1.5 pF COUT INT Pin Output Capacitance VCC=0 2.5 pF CON D+/D- On Capacitance VCC=3.3 V, f=1 MHz, Figure 11 7.0 COFF D1n, D2n Off Capacitance VCC=3.3 V, Figure 10 2.0 © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 7.9 FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect AC Electrical Characteristics pF pF www.fairchildsemi.com 5 VON HSD1n D+, D- HSDn A Dn HSD2n VSW VSW I ON GND Select R ON = V Sel = VON / ION Sel GND 0 or VCC 0 orV cc Figure 4. On Resistance HSDn Figure 5. Off/On Leakage tRISE = 2.5ns Dn VSW CL GND RS RL tFALL = 2.5ns VCC V OUT Input – V/OE , VSel GND 10% GND V Sel 90% 90% VCC /2 VCC /2 10% VOH 90% GND 90% Output- VOUT RL , RS , and C L are functions of the application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance. VOL Figure 6. AC Test Circuit Load tON tOFF Figure 7. Turn-On / Turn-Off Waveforms tRISE = 500ps tFALL = 500ps +400mV 90% 0V - 400mV 10% 90% 10% Output t PHL Figure 8. Propagation Delay (tRtF – 500ps) HSDn Capacitance Meter S S VSel = 0 or Vcc V Sel = 0 or Vcc HSDn HSDn Figure 10. Channel Off Capacitance © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 t PLH Figure 9. Intra-Pair Skew Test tSK(P) HSDn Capacitance Meter FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Test Diagrams Figure 11. Channel On Capacitance www.fairchildsemi.com 6 tRISE = 2.5ns Vcc HSDn Dn VSW1 GND 10% 0V VOUT CL VSW2 90% Vcc/2 Input - VSel RL V OUT GND GND 0.9*Vout 0.9*Vout RS tBBM VSel RL , RS , and C L are functions of the application environment (see AC Tables for specific values) CL includes test fixture and stray capacitance. GND Figure 12. Break-Before-Make Interval Timing Network Analyzer RS V IN VS GND GND VSel GND VOUT GND RT GND RS and RT are functions of the application environment (see AC Tables for specific values). Figure 13. Bandwidth Network Analyzer RS VSel V IN GND RT VS GND GND V OUT GND GND RT RS and RT are functions of the application environment (see AC Tables for specific values). GND Off isolation = 20 Log (V OUT / VIN) FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Test Diagrams (Continued) Figure 14. Channel Off Isolation Network Analyzer NC RS GND V IN VS VSel GND GND RT GND GND RS and RT are functions of the application environment (see AC Tables for specific values). RT V OUT GND Crosstalk = 20 Log (VOUT / VIN) Figure 15. Non-Adjacent Channel-to-Channel Crosstalk © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 www.fairchildsemi.com 7 0.10 C 2.10 2X A 1.62 B KEEPOUT ZONE, NO TRACES OR VIAS ALLOWED (0.11) 0.56 1.12 1.60 PIN1 IDENT IS 2X LONGER THAN OTHER LINES 0.10 C 2X TOP VIEW (0.35) 10X (0.25) 10X 0.50 RECOMMENDED LAND PATTERN 0.55 MAX 0.05 C 0.05 C 0.05 0.00 (0.20) C 0.35 0.25 SIDE VIEW (0.15) D 0.65 0.55 DETAIL A 0.35 0.25 (0.36) 0.35 0.25 DETAIL A 2X SCALE 4 1 0.56 5 10 (0.29) 0.35 9X 0.25 6 9 0.50 0.25 9X 0.15 1.62 0.10 0.05 C A B C ALL FEATURES BOTTOM VIEW Figure 16. NOTES: A. PACKAGE CONFORMS TO JEDEC REGISTRATION MO-255, VARIATION UABD . B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. PRESENCE OF CENTER PAD IS PACKAGE SUPPLIER DEPENDENT. IF PRESENT IT IS NOT INTENDED TO BE SOLDERED AND HAS A BLACK OXIDE FINISH. E. DRAWING FILENAME: MKT-MAC10Arev5. FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Physical Dimensions 10-Lead MicroPak™ Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/MA/MAC10A.pdf. © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 www.fairchildsemi.com 8 1.40 0.10 C A B 2X (9X) 1.70 0.563 0.663 1.80 1 PIN#1 IDENT 2.10 0.10 C TOP VIEW 0.40 2X (10X) 0.225 0.55 MAX. 0.10 C RECOMMENDED LAND PATTERN (0.15) 1.45 0.08 C SEATING C PLANE 0.05 0.00 0.55 SIDE VIEW 0.40 1.85 0.35 (9X) 0.45 3 (10X) 0.225 6 DETAIL A OPTIONAL MINIMIAL TOE LAND PATTERN 0.40 1 NOTES: PIN#1 IDENT A. PACKAGE DOES NOT CONFORM TO ANY JEDEC STANDARD. B. DIMENSIONS ARE IN MILLIMETERS. 0.15 (10X) 0.25 10 BOTTOM VIEW 0.10 C A B 0.05 C C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. D. LAND PATTERN RECOMMENDATION IS BASED ON FSC DESIGN ONLY. 0.55 0.45 0.25 0.15 9X 0.45 PACKAGE EDGE 45° DETAIL A SCALE : 2X E. DRAWING FILENAME: MKT-UMLP10Arev5. F. FAIRCHILD SEMICONDUCTOR. LEAD OPTION 2 LEAD OPTION 1 SCALE : 2X FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect Physical Dimensions SCALE : 2X Figure 17. 10-Lead Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/UM/UMLP10A.pdf. © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 www.fairchildsemi.com 9 FSUSB45 — Hi-Speed USB2.0 (480Mbps) Switch with Dedicated Charger Port Detect © 2007 Fairchild Semiconductor Corporation FSUSB45 • Rev. 1.0.7 www.fairchildsemi.com 10