www.fairchildsemi.com AN-5844 Green Mode Fairchild Buck Switch FSL306LR Introduction This application note describes a detailed design method and procedure for a buck offline converter. Design consideration and formula are presented. The FSL306LR is designed for non-isolated topology; such as buck, buckboost converter, and non-isolated flyback converter. This device is an integrated current-mode Pulse Width Modulation (PWM) controller and SenseFET. The integrated PWM controller includes: 10 V regulator for no external bias circuit, Under-Voltage Lockout (UVLO), Leading-Edge Blanking (LEB), an optimized gate turnon / turn-off driver, EMI attenuator, Thermal Shutdown (TSD), temperature-compensated precision current sources for optimized loop compensation, and fault-protection circuitry. Protections include: Overload Protection (OLP), Figure 1. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Over-Voltage Protection (OVP), Feedback Open Loop Protection (FB_OLP), and Abnormal Over-Current Protection (AOCP) designed for the case of output short. FSL306LR offers stable soft-start performance during startup. The internal high-voltage startup switch and the Burst-Mode operation for extremely low operating current reduce the power loss in Standby Mode. As the result of those built-in circuitry, this device is able to achieve power loss less than 25 mW with external bias and 120 mW without external bias at 230 VAC. When compared to a linear power supply, the FSL306LR reduces total size and weight; while increasing efficiency, productivity, and system reliability. Application of the FSL306LR is suitable for cost-effective platform designs. Typical Application www.fairchildsemi.com AN-5844 APPLICATION NOTE Device Block Description Startup Circuit and Soft-Start Feedback Control During startup, an internal high-voltage current source (ICH) of the high-voltage regulator supplies the internal bias current (ISTART) and charges the external capacitor (CA) connected to the VCC pin, as illustrated in Figure 2. This internal high-voltage current source is enabled until VCC reaches 10 V. During steady-state operation, this internal high-voltage regulator (HVREG) maintains the VCC with 10 V and provides operating current (IOP) for all internal circuits. Therefore, FSL306LR needs no external bias circuit. The high-voltage regulator is disabled when the external bias is higher than 10 V. FSL306LR employs current-mode control with a transconductance amplifier for feedback control, as shown in Figure 4. Two resistors are typically used on the VFB pin to sense output voltage. An external compensation circuit is recommended on the VCOMP pin to control output voltage. A built-in transconductance amplifier accurately controls output voltage without external components, such as Zener diode and transistor. Figure 4. Figure 2. Transconductance Amplifier (gm Amplifier) The output of the transconductance amplifier sources and sinks the current, respectively, to and from the compensation circuit connected on the VCOMP pin (see Figure 5). This compensated VCOMP pin voltage controls the switching duty cycle by comparing with the voltage across the RSENSE. When the feedback pin voltage exceeds the internal reference voltage (VREF) of 2.5 V; the transconductance amplifier sinks the current from the compensation circuit, VCOMP is pulled down, and the duty cycle is reduced. This typically occurs when input voltage is increased or output load is decreased. A two-pole and one-zero compensation network is recommended for optimal output voltage control and AC dynamics. Startup Block The internal soft-start circuit slowly increases the SenseFET current after it starts. The typical soft-start time is 10 ms, as shown in Figure 3, where progressive increments of the SenseFET current are allowed during startup. The pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is gradually increased to smoothly establish the required output voltage. Soft-start also helps prevent transformer saturation and reduces the stress on the secondary diode. Figure 3. Pulse-Width Modulation (PWM) Circuit Soft-Start Function Figure 5. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Characteristics of gm Amplifier www.fairchildsemi.com 2 AN-5844 APPLICATION NOTE Pulse-by-pulse Current Limit Because current-mode control is employed, the peak current flowing through the SenseFET is limited by the inverting input of PWM comparator, as shown in Figure 4. Assuming that 50 µA current source flows only through the internal resistors (3R + R = 46 kΩ), the cathode voltage of diode D2 is about 2.4 V. Since D1 is blocked when VCOMP exceeds 2.4 V, the maximum voltage of the cathode of D2 is clamped at this voltage. Therefore, the peak value of the current of the SenseFET is limited. Overload Protection (OLP) Overload is defined as the load current exceeding a set level due to an unexpected event. In this situation, the protection circuit should be activated to protect the SMPS. However, even when the SMPS operates normally, the OLP circuit can be enabled during the load transition or startup. To avoid this undesired operation, an internal fixed-delay (40 ms) circuit determines whether it is a transient situation or a true overload situation (see Figure 6). The currentmode feedback path limits the maximum power current and, when the output consumes more than this maximum power, the output voltage (VO) decreases below its rated voltage. This reduces feedback pin voltage, which increases the output current of the internal transconductance amplifier. Eventually VCOMP is increased. When VCOMP reaches 3 V, the fixed OLP delay (40 ms) is activated. After this delay, switching operation is terminated, as shown in Figure 7. Leading-Edge Blanking (LEB) At the instant the internal SenseFET is turned on; primaryside capacitance and secondary-side rectifier diode reverse recovery of flyback application, the freewheeling diode reverse recovery, and other parasitic capacitance of the buck application typically cause a high-current spike through the SenseFET. Excessive voltage across the sensing resistor (RSENSE) leads to incorrect feedback operation in the current-mode control. To counter this effect, the FSL306LR has a Leading-Edge Blanking (LEB) circuit (see Figure 4). This circuit inhibits the PWM comparator for a short time (tLEB) after the SenseFET is turned on. Protection Functions The protective functions include Overload Protection (OLP), Over-Voltage Protection (OVP), Under-Voltage Lockout (UVLO), Feedback Open-Loop Protection (FB_OLP), Abnormal Over-Current Protection (AOCP), and Thermal Shutdown (TSD). All of the protections operate in Auto-Restart Mode. Since these protection circuits are fully integrated in the IC without external components, reliability is improved without increasing cost and PCB space. If a fault condition occurs, switching is terminated and the SenseFET remains off. At the same time, internal protection timing control is activated to decrease power consumption and stress on passive and active components during auto restart. When internal protection timing control is activated, VCC is regulated with 10 V through the internal high-voltage regulator until switching is terminated. This internal protection timing control continues until restart time (650 ms) is counted. After counting to 650 ms, the internal high-voltage regulator is disabled and VCC is decreased. When VCC reaches the UVLO stop voltage VSTOP (7 V), the protection is reset and the internal high-voltage current source charges the VCC capacitor via the drain pin. When VCC reaches the UVLO start voltage, VSTART (8 V), normal operation resumes. In this manner, auto restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Figure 6. Overload Protection Internal Circuit Figure 7. Overload Protection (OLP) Waveform Abnormal Over-Current Protection (AOCP) When the output is shorted at high input voltage, much higher drain current peak than the pulse-by-pulse current limit can flow through the SenseFET because turn-on time is the same as the minimum turn-on time of FSL306LR. The OLP is occasionally not enough to protect the FSL306LR in that abnormal case, because severe current stress is imposed on the SenseFET until OLP is triggered. FSL306LR includes the internal Abnormal Over-Current Protection (AOCP) circuit shown in Figure 8. The voltage across the RSENSE is compared with the AOCP level (VAOCP) after tLEB and, if the voltage across the RSENSE is greater than the AOCP level, the set signal is triggered after four switching times by an internal 2-bit counter, shutting down the SMPS, as shown in Figure 9. This LEB time can inhibit mis-triggering due to the leading-edge spike. www.fairchildsemi.com 3 AN-5844 APPLICATION NOTE activation during startup, this function is disabled during soft-start time. Figure 8. AOCP Circuit Figure 11. Feedback Open-loop Protection Circuit Thermal Shutdown (TSD) The SenseFET and control IC integrated on the same package makes it easier to detect the temperature of the SenseFET. When the junction temperature exceeds 135°C, thermal shutdown is activated. FSL306LR is restarted after the temperature decreases to 60°C. Burst Operation Figure 9. Abnormal OCP Waveform To minimize power dissipation in Standby Mode, FSL306LR enters Burst Mode. As the load decreases, the comp voltage (VCOMP) decreases. As shown in Figure 12, the device automatically enters Burst Mode when the feedback voltage drops below VBURL. At this point, switching stops and the output voltages start to drop at a rate dependent on the standby current load. This causes VCOMP to rise. Once it passes VBURH, switching resumes. VCOMP then falls and the process repeats. Burst Mode alternately enables and disables switching of the SenseFET and reduces switching loss in Standby Mode. Over-Voltage Protection (OVP) If any feedback loop components fail due to a soldering defect, VCOMP climbs up in manner similar to the overload situation, forcing the maximum current to be supplied to the SMPS until OLP is triggered. In this case, excessive energy is provided to the output and the output voltage may exceed the rated voltage before OLP is activated. To prevent this situation, an Over-Voltage Protection (OVP) circuit is employed. In general, output voltage can be monitored through VCC and, when VCC exceeds 24.5 V, OVP is triggered, resulting in switching termination. To avoid undesired activation of OVP during normal operation, VCC should be designed below 24.5 V (see Figure 10). Figure 10. Over Voltage Protection Circuit Feedback Open-Loop Protection (FB_OLP) In the event of a feedback loop failure, especially a shorted lower-side resistor of the feedback pin; not only does VCOMP rise in a similar manner to the overload situation, but VFB starts to drop to IC ground level. Although OLP and OVP also can protect the SMPS in this situation, FB_OLP can reduce stress on the SenseFET. If there is no FB_OLP, the output voltage is much higher than the rated voltage before OLP or OVP trigger. When VFB drops below 0.5 V, FB_OLP is activated, switching off. To avoid undesired © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Figure 12. Burst Mode Operation www.fairchildsemi.com 4 AN-5844 APPLICATION NOTE Green Mode Operation Detail Design Procedure As output load condition is reduced, the switching loss becomes the largest power loss factor. FSL306LR uses the VCOMP pin voltage to monitor output load condition. As output load decreases, VCOMP decreases and switching frequency declines, as shown in Figure 13. Once VCOMP falls to 0.8 V, the switching frequency varies between 21 kHz and 23 kHz before Burst Mode operation. At Burst Mode operation, random frequency fluctuation still functions. System Specifications Line voltage range (VAC.min and VAC.max): Standard worldwide input line voltage ranges are 85-264 VAC for universal input, 195-264 VAC for European input range Line frequency (fL): 50 or 60 Hz Output voltage (VO) Estimated efficiency: η Determining AC Input Rectification Type The typical AC-DC SMPS solution rectifies AC input with full-wave rectification. However, half-wave rectification can be selected for under 3 W designs with buck and buckboost topology to reduce BOM cost. For designs > 3 W, full-wave rectification is typically selected to reduce the size of the input capacitor with small ripple voltage on it. Random Frequency modulation range Switching frequency 53 kHz 47 kHz Determining DC Link Capacitor (CDC) and DC Link Voltage Range 23 kHz 21 kHz VBURL VBURH 0.8V Figure 13. 1.9V The DC link capacitor is selected by rectification type and input voltage range. For full-wave rectification, it is typical to select the DC link capacitor as 2-3 µF per watt of input power for universal input range (85-264 VAC) and 1 µF per watt of input power for European input range (195264 VAC). DC link capacitance of half-wave rectification is twice full-wave rectification, 4-6 µF per watt of input power for universal input range (85-264 VAC) and 2 µF per watt of input power for European input range (195264 VAC). Figure 14 shows the input voltage waveform of full-wave and half-wave rectification, respectively. VCOMP Green Mode Operation Adjusting Current Limit As shown in Figure 14, a combined 46 kΩ internal resistance (3R + R) is connected to the inverting lead on the PWM comparator. An external resistance of RX on the ILIMIT pin forms a parallel resistance with the 46 kΩ when the internal diodes are biased by the main current source of 50 µA. For example, FSL306LR has a typical SenseFET peak current limit of 0.45 A. Current limit can be adjusted to 0.3 A by inserting RX between the ILIMIT pin and the ground. The value of the RX can be estimated by the following equation: 0.45 A: 0.3 A = (46 kΩ + RX): RX (1) Figure 15. Figure 14. Bridge Rectifier and Bulk Capacitor Voltage Waveform With selecting AC rectification, the link voltages are obtained as: Current Limit Adjustment 2 VDC. min 2V AC. min - © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 2 PO ( 1/ 2-DCH ) η C DC f L (2) www.fairchildsemi.com 5 AN-5844 APPLICATION NOTE 2 VDC.min 2V AC. min - 2 PO ( 1-DCH ) η C DC f L VDC. max 2V AC. max (3) Reverse recovery time is also an important factor to choose the freewheeling diode. The smaller the reverse-recovery time, the lower the switching loss. (4) Table 2. Quick Selection Guide for Freewheeling Diode for Universal Input Range where DCH is the DC link capacitor charging duty ratio defined as shown in Figure 15, which is typically about 0.15 for full-wave rectification and about 0.3 for halfwave rectification. Equations (2) and (3) are minimum link voltage of full-wave and half-wave rectification, respectively, and Equation (4) is maximum link voltage. Determining Operation Mode Part # VRRM IF(AV) trr Package Type ES1J 600 V 1A 35 ns DO-204AC UF4005 600 V 1A 75 ns DO-204AL EGP10J 600 V 1A 75 ns DO-204AL EGP20J 600 V 2A 75 ns DO-204AC ES3J 600 V 3A 45 ns DO-214AB EGP30J 600 V 3A 75 ns DO201-AD Before selecting the inductor, freewheeling diode, and output capacitor; the operating mode should be determined: continuous conduction mode (CCM) or discontinuous conduction mode (DCM). DCM not only has smaller inductor size and lower freewheeling diode cost, but also higher efficiency due to lower switching loss than CCM in low-power buck applications. But DCM requires a higher current limit than CCM and increases output voltage ripple. Therefore, compromised selection is needed according to the system requirements. The forward voltage drop (VF) of the selected freewheeling diode is an important factor for other equations. Especially when the equations are related to output voltage, the output voltage must include forward-voltage drop for more exact calculation, as shown in Equation (7): Table 1. Brief Comparison of CCM and DCM Selecting Output Inductor CCM DCM Larger Smaller Efficiency (Switching Loss) Lower (Larger) Higher (Smaller) Output Voltage Ripple Smaller Larger Lower Higher Output Inductor Size Current Limit VOUT VO VF The inductance operating with boundary conduction mode (BCM) at minimum input DC voltage is represented in Equation (8). Smaller inductance than LBoundary can be selected for DCM operation and larger for CCM operation. LBoundary Higher current limit means that, potentially, a highercurrent-rated device may be needed to deliver maximum output power. Although a transformer for buck topology doesn’t exist, other leakage inductance and capacitance creates a voltage spike on the freewheeling diode when the SenseFET is turned off. Since this voltage spike must be considered, typically 30% voltage derating of maximum DC input is required, as described Equation (5). (8) Since FSL306LR has green mode function, the practical operating switching frequency at full load condition can be smaller than fS.HIGH. By two simultaneous equations representing relation between switching frequency and peak drain current, the operating switching frequency is calculated. Each equation, (9) and (10), includes two simultaneous equations. These are for CCM operation and DCM operation, respectively: (5) The diode is one of the components generating high temperature in the SMPS. To decide the current rating of freewheeling diode, consider thermal performance of 150% design margin of the output full load current, as recommended as Equation (6): I F(AV) 2.5 I O V 2 η 1- O VOUT V DC.min 2 PO f S .HIGH where VOUT is the sum of target output voltage (VO) and freewheeling diode forward-voltage drop (VF), as determined by Equation (7), and fS.HIGH is maximum switching frequency in Green Mode operation, as illustrated on Figure 13. Selecting Freewheeling Diode VRRM 1.3 VDC,max (7) f S ( I ds. peak 0.8V ) 22kHz I ds. peak (6) VDC . min VDC . min VO VOUT / VDC . min VOUT 2 Lf S (9) where VRRM is peak repetitive reverse voltage and IF(AV) denotes average rectified forward current. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 www.fairchildsemi.com 6 AN-5844 APPLICATION NOTE f S ( I ds. peak 0.8V ) 22kHz I ds. peak 2VDC . min VO Lf S optimized through connecting one resistor between the ILIMIT pin and the IC ground pin. (10) I ds.peak where: f S .HIGH f S .LOW VGREEN .HIGH VGREEN .LOW PO I LIMIT I ds.peak (11) V DC. min 2.4V VO V SL t CLD DC . min t CLD L Normally, the buck converter designed for CCM at the minimum input voltage and full-load condition can enter DCM as the input voltage increases. The maximum input voltage guaranteeing CCM operation in full-load condition is obtained as: VO 2 PO f S L 1 2 η VOUT I LIMIT.adj I LIMIT (12) IL C O .recommend Ripple ( I I ds. peak RX I ds . peak 46 kΩ R X (15) 5 8 ESR f S 1 8C O f S (16) ESR) ΔI ESR ΔI where CO.recommend is the recommended capacitance, typically is larger than 100 µF. (17) output Designing the Feedback Network IL The feedback network is comprised of one diode for sensing output voltage, one capacitor to maintain sensed output voltage during the SenseFET turn-on period, and two resistors to determine output voltage, as shown in Figure 17. I IL 2 Figure 16. (14) The maximum output voltage ripple is determined by the output capacitance and the equivalent series resistance (ESR) of the output capacitor. Since the output voltage ripple by capacitance is negligibly small when over than 100 µF is selected, the output ripple is mostly determined by the ESR of output capacitor: I 2 P I L OUT VOUT PO Selecting the Output Capacitor I ds. peak IL (13) where ILIMIT is pulse-by-pulse current limit of the FPS, typically it is 450 mA. For better noise immunity at ILIMIT pin, a small capacitor (1 nF~100 nF) is recommended. where, fS is the operating switching frequency considering green mode function. I V 21 O VDC.min ηLf S VOUT Adjusting Pulse-by-pulse Current Limit The resistor is determined by Equation (15) and this adjusted pulse-by-pulse current limit must be higher than the maximum drain current peak defined by Equations (13) and (14). This function is disabled by letting ILIMIT pin be open-circuited, such as: where ILIMIT is the peak current limit; SL is the test slope (di/dt) of ILIMIT; and tCLD is the current limit delay. Typically α, ILIMIT, SL, and tCLD are 25.5 kHz/V, 450 mA, 300 mA/µs, and 100 ns, respectively. VDC .CCM PO ηVOUT VO 1 VDC. min 2 Lf S MOSFET Drain Current Maximum drain current peak (Ids.peak) at full-load condition is decided by the selected output inductor. If the maximum drain current peak is larger than the pulse-by-pulse current limit, larger output inductance or higher current rating of the device is needed. Equations (13) and (14) show the maximum drain current peak of CCM and DCM operation, respectively. If this maximum drain current peak is smaller than pulse-by-pulse current limit, the output inductor size is © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Figure 17. Feedback Network www.fairchildsemi.com 7 AN-5844 APPLICATION NOTE The IC ground is pulsed between input DC voltage and the ground of output voltage, respectively, when the SenseFET is turned on and freewheeling diode is conducted. Output voltage is sensed through a feedback diode (DFB) during the conduction time of the freewheeling diode. This feedback diode is typically selected to remove difference of forward voltage drop between feedback diode and freewheeling diode. As this voltage difference is increased, the output voltage regulation can degrade. To express the small signal AC transfer functions, the small-signal variations of compensation voltage (νCOMP) and output voltage (νO) are introduced as and vˆCOMP and vˆO . For Since the output voltage is sensed only during freewheeling diode conduction time, a feedback capacitor helps maintain sensed output voltage, especially for Burst Mode operation. A value larger than 1 µF is typically recommended. Larger feedback capacitance results in better output voltage regulation performance. where K is specified in Equation (19) and RL is the load resistance of the output port, defined as VO/IO. The pole and zero of Equation (20) are expressed as: CCM operation, the control-to-output function of the buck converter applying current-mode control is given by: Gvc ( s) R A RB RB vˆcomp Gvc 0 1 s / z 1 s / p (20) Gvc 0 K RL z Two feedback resistors determine output voltage, as in Equation (18), and, by reducing the voltage difference between sensed output voltage (VO) and feedback capacitor voltage (VFB*), more accurate output control is possible: VFB * VO K REG I O 2.5V vˆo 1 1 & p ESR CO ( ESR RL ) CO (21) where ESR is equivalent series resistance of the output capacitor and CO is the output capacitance. For DCM operation, the control-to-output transfer function of the buck converter adopting current-mode control is given by: (18) where KREG is regulation factor regarding mismatched voltage between output voltage (VO) and feedback capacitor voltage (VFB*). It is typically 2 [V/A]. Determining Compensation Network Because FSL306LR devices employ current-mode control and transconductance amplifier (gm amp) internally, compensation network can be simply implemented. As illustrated on Figure 18, a two-pole and one-zero circuit can secure enough phase margin and bandwidth. Gvc ( s) Gvc0 1 s / z 1 s / p Gvc 0 K VO VDC / VO 1 2 VDC / VO 3 (22) 2 L f s V PO 1 O VDC (23) z 1 ESR CO p 2 3 VO / VDC CO 2 ESR RL (3 ESR RL ) VO / VDC where η is the efficiency of the converter and VDC is the input DC voltage. Figure 19 shows the variation of a CCM converter control-tooutput transfer function for various input voltages. DC gain, pole, and zero do not change for different input voltages. Figure 18. Compensation Network The current control factor of FSL306LR, K is defined as: K I ds . peak VCOMP I LIMIT VCOMP .sat (19) where Ids.peak is the peak drain current and VCOMP denotes the compensation voltage, respectively, for a given fullload condition, ILIMIT is the current limit of the FSL306LR and VCOMP.sat is the compensation saturation voltage, which is typically 2.4 V. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Figure 19. CCM Control-to-Output Transfer Function Variation for Different Input Voltages www.fairchildsemi.com 8 AN-5844 APPLICATION NOTE Figure 20 shows the variation of a DCM converter controlto-output transfer function for various input voltages. It has the lowest DC gain at low-line input condition. Figure 22. Compensation Network Transfer Function Design Tips for Compensation Network a) To secure enough phase margin compensation, the second pole (fpc2) and zero (fzc) should be separated as much as possible. Large CF1 and small CF2 are recommended. DCM Control-to-Output Transfer Function Variation for Different Input Voltage Figure 20. Figure 21 shows the variation of the converter control-tooutput transfer function for variation in the output load current. Both CCM and DCM operation have similar variation, where gain is increased and pole is decreased as output load is decreased. b) For wide bandwidth of transfer function, compensation zero (fzc) should be as small as possible. c) The recommended minimum capacitance of CF2 is 100~470 pF to avoid noise. Based on design tips; typically 330 pF, 220 nF, and 220 kΩ are recommended for CF2, CF1, and RF, respectively. Selecting Dummy Load Resistor Since the feedback capacitor voltage sensed from output voltage is not accurately matched with output voltage, the output voltage regulation can be poor at light-load condition. The dummy load resistor increases output load and this small load helps output voltage regulation at light-load condition. A 5~20 kΩ resistor is typically selected. Figure 21. Control-to-Output Transfer Function Variation for Different Output Loads The transfer function of the compensation network is obtained as: Gvc ( s) pc1 pc 2 1 s / zc ( s / pc1 ) /(1 s / pc 2 ) g m RB , (C F 1 C F 2 ) ( R A RB ) 1 RF 1 1 1 & zc RF C F 1 CF1 CF 2 (24) (25) where RA and RB are defined in Figure 17 and RF, CF1 and CF2 are shown in Figure 18. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 www.fairchildsemi.com 9 AN-5844 APPLICATION NOTE Design Example Step 1-1. Define System Specification (AC Input Condition)) Minimum AC Input Voltage VAC.min 85 VAC Maximum AC Input Voltage VAC.max 265 VAC fL 60 Hz AC_F 0 Line Frequency Selection of AC Rectification Method (Full or Half) → Half-Wave Rectification Step 1-2. Define System Specification (DC Output Condition) Output Voltage Vo 12 V Output Full Load Io 0.15 A Output Power Pout 1.800 W Estimated Efficiency η 80% Target Input Power Pin 2.250 W Step 2. Determine DC Link Capacitor and DC Link Voltage Range Input Capacitance CDC 9.6 µF Minimum DC Input Voltage VDC.min 91.4 V Maximum DC Input Voltage VDC.max 374.8 V Step 3. Select Freewheeling Diode Minimum Voltage Rating of Output Diode VRRM 487 V Minimum Current Rating of Output Diode IF(AV) 0.375 A VF 1.00 V Forward Voltage Drop of Output Diode Output Voltage Including VD Recommended Diode Part Name VOUT 13.0 V DIP Type EGP10J SMD Type ES1H Step 4. Determine Inductor and Check Maximum Drain Current Peak Typical Current Limit ILIMIT 0.450 A Distribution of Current Limit Dis_ILIM 12% Test slope of Current Limit SLLIMIT 300 mA/µs tCLD 100 ns Maximum Switching Frequency of Green Mode fS.HIGH 50 kHz Distribution of Switching Frequency Dis_fs 10% LBoundary 0.644 mH L 0.68 mH Dis_L 10% Current Limit Delay Inductance with BCM with fs.max at VDC.min Selected Inductance Distribution of Inductance Switching Frequency Considering Green Mode Maximum Input Voltage for CCM Maximum Drain Current Peak at VDC.max fS 48.2 kHz VDC.CCM 102 V Ids.peak 0.409 A DCM Operation Step 5. Determine Adjusted Current Limit using Current Limit Adjustable Resistor Adjustable Current Limit Resistor Rpeak NC kΩ Adjusted Typical Current Limit ILIM.adj 0.473 A Adjusted Maximum Current Limit ILIM.adj.max Adjusted Minimum Current Limit ILIM.adj.min 0.533 A 0.414 A > 0.409 A → OK Continued on the following page… © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 www.fairchildsemi.com 10 AN-5844 APPLICATION NOTE Step 6. Check RMS Value of Drain Current Operation Mode at VDC.min CCM Drain Current Peak at VDC.min Ids.pk 0.343 A Duty Ratio at VDC.min Dmax 0.142 Duty Ratio at VDC.max Dmin 0.033 Maximum Drain RMS Current at VDC.min Ids.rms 0.075 A Step 7. Determine Output Ripple by Selecting Output Capacitor Recommended Output Capacitor 130 µF Output Capacitance COUT 100 µF ESR of Output Capacitor ESR 0.1 Ω Maximum Inductor Current Ripple ∆iL.max 0.364 A Output Ripple by Capacitor ESR 36.398 mV Step 8. Design Feedback Compensation Circuit DC Gain of Power Stage Gvc(0) 15.0 dB fz 15915.5 Hz Pole of Power Stage fp 19.9 Hz Upper-Side Resistance on FB Pin RA 20 kΩ KREG 2.000 V/A Zero of Power Stage Regulation Factor by Mismatched VO and VFB Lower-Side Resistance on FB Pin (Recommended) 5.102 kΩ Lower-Side Resistance on FB Pin (Selected) RB 5.1 kΩ Compensation Resistance RF 220 kΩ Series Connected Capacitor with RF CF1 220 nF Parallel Connected Capacitor with RF CF2 0.33 nF First Pole of Compensation Circuit fpc1 35.2 Hz Zero of Compensation Circuit fzc 3.3 Hz Second Pole of Compensation Circuit fpc2 2195.5 Hz Bandwidth of Loop Gain BW 2250.0 Hz Phase Margin of Loop Gain PM 52.8 © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 → OK www.fairchildsemi.com 11 AN-5844 APPLICATION NOTE Typical Application Circuit with Single Output Application Output Power Input Voltage Range Output Voltage/Maximum Current Home Appliance Auxiliary Power 1.8 W 85-265 VAC 12 V / 0.15 A Description of Schematic Half-wave rectification is selected for AC line rectification. For better EMI performance, one more AC diode (DAC2) and Pi-type AC filter (CDC1, CDC2, Lfilter1, Lfilter2, and Rfilter) are selected. For small standby power consumption, VCC is externally supplied from output voltage through DVCC and RVCC. CLIMIT is used on the ILIMIT pin for better noise immunity. Figure 23. Schematic Table 3. Bill of Materials for Evaluation Board Part # Value Note Part # Value IC IC Note Capacitor FSL306LRN Fairchild Buck Switch Resistor CDC1 4.7 µF 400 V Electrolytic Capacitor CDC2 4.7 µF 400 V Electrolytic Capacitor Rfilter 3.3 kΩ 5% 0805 SMD COUT 100 µF 50 V Electrolytic Capacitor RVcc 10 R 5% 0805 SMD CFB 2.2 µF 0805 SMD RA 20 kΩ 1% 0805 SMD CVCC 1 µF 0805 SMD RB 5.2 kΩ 1% 0805 SMD CLIMIT 1 µF 0805 SMD RF 220 kΩ 5% 0805 SMD CF1 220 nF 0805 SMD RDummy 20 kΩ 5% 0805 SMD CF2 330 pF Inductor 0805 SMD Diode Lfilter1 1 mH Axial Type DAC1 1N4007 Fairchild General Rectifier Lfilter2 680 µH Axial Type DAC2 1N4007 Fairchild General Rectifier L 680 µH MF0809-681K (3L Corp.) Fuse F1 10 Ω / 2 W © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Fusible Resistor DF UF4005 Fairchild Ultra-Fast Diode DFB UF4005 Fairchild Ultra-Fast Diode DVcc 1N4148 Fairchild Signal Diode www.fairchildsemi.com 12 AN-5844 APPLICATION NOTE Experimental Results Table 4. No-Load Input Wattage, Full-Load Efficiency, IC Temperature, Experimental Result Input Voltage Input Wattage, Including Dummy Resistor Loss (No Load) Efficiency (Full Load) IC Temperature (Full Load) 85 V / 60 Hz 0.022 W 78.53% 37°C 110 V / 60 Hz 0.022 W 80.21% 36°C 230 V / 60 Hz 0.026 W 80.21% 37°C 265 V / 60 Hz 0.032 W 79.33% 38°C Experimental Waveforms CH3:VOUT [2V/div] CH3:VOUT [2V/div] CH1:VCC [5V/div] CH1:VCC [5V/div] CH2:VDS [200V/div] CH2: [200V/div] Figure 24. Figure 25. Normal Operation at Input Voltage 85 VAC (CH1: VCC, CH2: VDS, CH3: VOUT) Normal Operation at Input Voltage 265 VAC (CH1: VCC, CH2: VDS, CH3: VOUT) CH3:VOUT [2V/div] CH3:VOUT [2V/div] CH1:VCC [5V/div] CH1:VCC [5V/div] CH2:VDS [200V/div] CH2:VDS [200V/div] Figure 27. Burst Operation at Input Voltage 265 VAC and No Load (CH1: VCC, CH2: VDS, CH3: VOUT) Figure 26. Burst Operation at Input Voltage 85 VAC and No Load (CH1: VCC, CH2: VDS, CH3: VOUT) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 www.fairchildsemi.com 13 AN-5844 APPLICATION NOTE Conduction EMI Performance Att dBµV 1 100 10 RBW MT PREAMP dB 9 kHz 15 ms OFF MHz Marker 1 [T1 ] 47.39 dBµV 274.000000000 kHz 10 MHz 90 1 PK MAXH 2 AV MAXH 80 TDF 70 EN55022Q 60 PRN EN55022A 1 50 6DB 40 30 20 10 0 150 Comment: Date: kHz 30 2-230N 14.DEC.2012 15:56:05 Figure 28. 110 VAC with Full Load Condition Att dBµV MHz 1 100 10 RBW MT PREAMP dB MHz 9 kHz 15 ms OFF Marker 1 [T1 ] 45.72 dBµV 274.000000000 kHz 10 MHz 90 1 PK MAXH 2 AV MAXH 80 TDF 70 EN55022Q 60 PRN EN55022A 50 1 6DB 40 30 20 10 0 150 Comment: Date: kHz 30 2-230N 14.DEC.2012 15:53:37 Figure 29. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 MHz 230 VAC with Full Load Condition www.fairchildsemi.com 14 AN-5844 APPLICATION NOTE Typical Application Circuit with Multi-Output Application Output Power Input Voltage Range Output Voltage / Maximum Current Home Appliance Auxiliary Power 2.05 W 85-300 VAC 12 V / 0.15 A and 5 V / 0.05 A Description of Schematic Half-wave rectification is selected for AC line rectification. For better EMI performance, one more AC diode (D2) and Pi-type AC filter (C1, C2, L1, L2, and R1) are selected. For small standby power consumption, VCC is externally supplied from output voltage through D5 and R2. C7 is used on the ILIMIT pin for better noise immunity. Since there is minimum load by 5 V positive voltage regulator, a dummy resistor is not needed. Figure 30. Schematic Table 5. Bill of Materials for Evaluation Board Part # Value Note Part# Value IC Note Capacitor U1 FSL306LRN Fairchild Buck Switch U2 KA78L05AI Fairchild Voltage Regulator C1 Resistor 4.7 µF 400 V Electrolytic Capacitor C2 6.8 µF 400 V Electrolytic Capacitor C3 100 µF 25 V Electrolytic Capacitor R1 3.3 kΩ 5% 0805 SMD C4 47 µF 25 V electrolytic Capacitor R2 10R 5% 0805 SMD C5 2.2 µF 0805 SMD R3 20 kΩ 1% 0805 SMD C6 1 µF 0805 SMD R4 5.2 kΩ 1% 0805 SMD C7 10 nF 0805 SMD R5 NC 1% 0805 SMD C8 220 nF 0805 SMD R6 220 kΩ 5% 0805 SMD C9 330 pF R7 NC 5% 0805 SMD 0805 SMD Diode Inductor Axial Type D1 S1M Fairchild General Rectifier D2 S1M Fairchild General Rectifier L1 470 µH L2 470 µH Axial Type D3 ES1J Fairchild Super-Fast Diode L3 680 µH PKS0807-681K (3L Corp.) D4 ES1J Fairchild Super-Fast Diode D5 1N4148 Fairchild Signal Diode Fuse F1 10 Ω / 1 W © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Fusible Resistor www.fairchildsemi.com 15 AN-5844 APPLICATION NOTE Experimental Results Table 6. No-Load Input Wattage, Full-Load Efficiency, IC Temperature, Experimental Result Input Voltage Input Wattage (No Load) Efficiency (Full Load) IC Temperature (Full Load) 85 V / 60 Hz 0.043 W 65.76% 48°C 110 V / 60 Hz 0.044 W 67.12% 47°C 230 V / 60 Hz 0.050 W 66.07% 49°C 265 V / 60 Hz 0.054 W 65.04% 51°C 300 V / 60 Hz 0.067 W 63.87% 51°C Experimental Waveforms CH2:VCC [5V/div] CH2:VCC [5V/div] CH1:VDS [100V/div] CH1:VDS [100V/div] Figure 31. Normal Operation at Input Voltage 85 VAC (CH1: VDS, CH2: VCC) Figure 32. Normal Operation at Input Voltage 300 VAC (CH1: VDS, CH2: VCC) CH2:VCC [5V/div] CH2:VCC [5V/div] CH1:VDS [100V/div] CH1:VDS [100V/div] Figure 33. Burst Operation at Input Voltage 85 VAC and No Load (CH1: VDS, CH2: VCC) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 Figure 34. Burst Operation at Input Voltage 300 VAC and No Load (CH1: VDS, CH2: VCC) www.fairchildsemi.com 16 AN-5844 APPLICATION NOTE Output Voltage Regulation, Experimental Results Figure 35. 12 V Output Voltage Regulation Figure 36. 5 V Output Voltage Regulation Conduction EMI Performance Att dBµV 1 100 10 RBW MT PREAMP dB 9 kHz 10 ms OFF MHz 10 MHz 90 1 PK MAXH 2 AV MAXH 80 TDF 70 EN55022Q 60 PRN EN55022A 50 6DB 40 30 20 10 0 150 kHz 30 Att dBµV 1 100 MHz 110 VAC with Full Load Condition Figure 37. 10 RBW MT PREAMP dB MHz 9 kHz 10 ms OFF 10 MHz 90 1 PK MAXH 2 AV MAXH 80 TDF 70 EN55022Q 60 PRN EN55022A 50 6DB 40 30 20 10 0 150 kHz 30 Figure 38. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 MHz 230 VAC with Full Load Condition www.fairchildsemi.com 17 AN-5844 APPLICATION NOTE Appendix A — Equation Details Equation 2: Minimum DC Input Voltage The voltage ripple at the DC link capacitor can be calculated with the power delivered to converter system. ( 1-DCH ) 1 2 2 for half-wave rectification. C DC ( 2V AC.min VDC.min ) Pin 2 fL ( 1/ 2-DCH ) 1 2 2 for full-wave rectification. C DC ( 2V AC.min VDC.min ) Pin 2 fL Therefore, the calculation methods for minimum DC input voltage are: 2 VDC,min 2V AC.min 2 VDC, min 2V AC.min - 2 PO ( 1-DCH ) for half-wave rectification. η C DC f L 2 PO ( 1/ 2-DCH ) for full-wave rectification. η C DC f L Since DCH in the above equations is difficult to estimate exactly, calculating VDC.min through the below two simultaneous equations is an alternative. Equation A below is the equation about the input voltage discharging waveform by input power and equation B is about AC input voltage waveform. Through these simultaneous equations, a more exact minimum input voltage can be calculated without the estimation of DCH. Figure 39. Full-Wave Rectification Equation A:VDC . min VAC. min 2 Figure 40. Half-Wave Rectification PO t AC_dis η C DC VAC. min 2 1 AC_F) 2 fL where, AC_F is “0” for half-wave rectification and “1” for full-wave rectification. Equation B:VDC . min VAC. min 2 cos 2πf L(t AC_dis © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 www.fairchildsemi.com 18 AN-5844 APPLICATION NOTE Equation 7: Inductance at Boundary Conduction Mode To be operated in BCM, the average value of inductor current should be identical to the half of the ripple of inductor current, as shown below. IL I I 2 IL I I 2 IL IL Figure 41. Inductor Current at BCM Figure 42. Inductor Current at CCM 1 ΔiL 2 I (V VO )D in DC . min D 2 Lboundary f S .HIGH IL VOUT I in (V VO )VOUT / VDC . min DC . min / VDC . min 2 Lboundary f S .HIGH The inductance to be operated in BCM is: η( 1 Lboundary VO )VOUT 2 VDC . min 2 f S . HIGH PO Equation 8, 11: Operating Switching Frequency and Drain Peak Current at CCM By Green Mode levels (refer to Figure 13): fS f S . HIGH f S . LOW (VCOMP 0.8V ) 22 kHz VGREEN . HIGH VGREEN . LOW The relationship between VCOMP and Ids.peak is: 2.4V I ds. peak VDC . min VO I LIMIT SL t CLD t CLD L The calculation method of Ids.peak for CCM operation is: VCOMP I ds . peak VO )VOUT / VDC . min I in I L PO (V DC . min D 2 VOUT 2 Lf S For simplicity, some of constants are substituted as: f S . HIGH f S . LOW PO , , VGREEN . HIGH VGREEN . LOW VDC . min 2.4V V VO I LIMIT SL t CLD DC . min t CLD L There are two simultaneous equations having two variables, Ids.peak and fs: Equation A:f S α(γ I ds.peak 0.8V) 22kHz Equation B:I ds.peak β VDC.min VDC.min VO VOUT /VDC.min VOUT 2 Lf S © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 www.fairchildsemi.com 19 AN-5844 APPLICATION NOTE Equation 9, 12: Operating Switching Frequency and Drain Peak Current at DCM As above CCM calculation: fS f S . HIGH f S . LOW (VCOMP 0.8V ) 22 kHz VGREEN . HIGH VGREEN . LOW 2.4V I ds. peak VO V SL t CLD DC . min t CLD L VCOMP I LIMIT However, the calculation method of Ids.peak for DCM operation is: V Vo 1 I ds.peak D1 & I ds.peak DC . min D1 Lfs 2 Lfs 1 2 I in I ds.peak 2 VDC . min Vo I in Po ηVDC . min I ds.peak Lfs 1 2 I ds.peak 2 VDC . min Vo Po 2(VDC . min Vo ) Lfs ηVDC . min For simplicity, some of constants are substituted with the same as for CCM operation: f S .HIGH f S .LOW PO , , VDC . min VGREEN .HIGH VGREEN . LOW I LIMIT 2.4V V VO SL t CLD DC . min t CLD L There are two simultaneous equations having two variables, Ids.peak and fs: Equation A : f S ( I ds. peak 0.8V ) 22kHz Equation B : I ds. peak 2VDC . min VO Lf S Related Datasheets FSL306LRN − Green Mode Fairchild Buck Switch DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.2 • 4/22/14 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness www.fairchildsemi.com 20