MAXIM MAX1897EGP

19-2188; Rev 0; 10/01
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
♦ Quick-PWM Slave Controller
♦ Precise, Active Current Balance (±1.25mV )
♦ Accurate, Adjustable Current-Limit Threshold
♦ Optimized for Low-Output Voltages (≤2.0V)
♦ 4.0V to 28V Battery Input Range
♦ Fixed 300kHz (MAX1887) or Selectable
200kHz/300kHz/550kHz (MAX1897) Switching
Frequency
♦ Drive Large Synchronous-Rectifier MOSFETs
♦ 525µA (typ) ICC Supply Current
♦ 20µA Standby Supply Current
♦ <1µA Shutdown (MAX1897) Supply Current
♦ Small 16-Pin QSOP (MAX1887) or Compact
20-Pin 5mm x 5mm QFN (MAX1897) Package
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX1887EEE
-40°C to +85°C
16 QSOP
MAX1897EGP
-40°C to +85°C
20 QFN 5mm ✕ 5mm
LIMIT
V+
BST
TOP VIEW
ILIM
Pin Configuration
TRIG
The MAX1887 triggers on the rising edge of the master’s low-side gate driver, which staggers the on-times
of both master and slave, providing out-of-phase operation that can reduce the input ripple current and consequently the number of input capacitors. The
MAX1897 features a selectable trigger polarity, allowing
out-of-phase or simultaneous in-phase operation.
Features
20
19
18
17
16
CM+
1
15
LX
CM-
2
14
DH
Notebook Computers
TON
3
13
SHDN
CPU Core Supply
CS-
4
12
VCC
Single-Stage (BATT to VCORE) Converters
CS+
5
11
VDD
Applications
MAX1897
7
8
9
10
GND
PGND
DL
Telecom
6
POL
Servers/Desktop Computers
COMP
Two-Stage (+5V to VCORE) Converters
QFN 5mm x 5mm
Pin Configurations continued at end of data sheet.
Quick-PWM is a registered trademark of Maxim Integrated
Products, Inc.
Typical Operating Circuit appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1887/MAX1897
General Description
The MAX1887/MAX1897 step-down slave controllers are
intended for low-voltage, high-current, multiphase DC-toDC applications. The MAX1887/MAX1897 slave controllers can be combined with any of Maxim’s
Quick-PWM™ step-down controllers to form a multiphase
DC-to-DC converter. Existing Quick-PWM controllers,
such as the MAX1718, function as the master controller,
providing accurate output voltage regulation, fast transient response, and fault protection features.
Synchronized to the master’s low-side gate driver, the
MAX1887/MAX1897 include the Quick-PWM constant ontime controller, gate drivers for a synchronous rectifier,
active current balancing, and precision current-limit circuitry.
The MAX1887/MAX1897 provide the same high efficiency, ultra-low duty factor capability, and excellent
transient response as other Quick-PWM controllers. The
MAX1887/MAX1897 differentially sense the inductor
currents of both the master and the slave across current-sense resistors. These differential inputs and the
adjustable current-limit threshold derived from an external reference allow the slave controller to accurately
balance the inductor currents and provide precise current-limit protection. The MAX1887/MAX1897’s dualpurpose current-limit input also allows the slave
controller to automatically enter a low-power standby
mode when the master controller shuts down.
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
ABSOLUTE MAXIMUM RATINGS
V+ to GND ..............................................................-0.3V to +30V
VCC, VDD to GND (Note 3) .......................................-0.3V to +6V
PGND to GND.....................................................................±0.3V
TRIG, LIMIT to GND .................................................-0.3V to +6V
SHDN to GND (MAX1897)........................................-0.3V to +6V
ILIM, CM+, CM-, CS+, CS-, COMP
to GND....................................................-0.3V to (VCC + 0.3V)
TON, POL to GND (MAX1897) ...................-0.3V to (VCC + 0.3V)
DL to PGND................................................-0.3V to (VDD + 0.3V)
BST to GND ............................................................-0.3V to +36V
DH to LX ....................................................-0.3V to (VBST + 0.3V)
LX to BST..................................................................-6V to +0.3V
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
20-Pin 5mm x 5mm QFN (derate 20.0mW/°C
above +70°C)..............................................................1.60W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VOUT = VCOMP = 1.2V, VCM+ = VCM- = VCS+ = VCS- = 1.2V, SHDN = VCC
(MAX1897), TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
Input Voltage Range
On-Time (Note 1)
Trigger Delay (Note 2)
tON
Battery voltage, V+
4.0
28
VCC, VDD
4.5
5.5
MAX1887 (300kHz), V+ = 12V, VCOMP = 1.2V
TON = GND
MAX1897,
320
355
390
171
190
209
TON = open
320
355
390
TON = VCC
464
515
566
V+ = 12V,
VCOMP = 1.2V
tTRIG
75
V
ns
ns
SUPPLY CURRENTS
Quiescent Supply Current (V+)
2
I+
Measured at V+; VILIM > 0.35V
25
40
MAX1887
525
800
MAX1897
<1
5
Measured at VCC; VILIM > 0.35V
525
800
µA
Standby Supply Current (V+)
Measured at V+; ILIM = GND
<1
5
µA
Standby Supply Current (VDD)
(Note 3)
Measured at VDD; ILIM
= GND
MAX1887
20
40
MAX1897
<1
5
Standby Supply Current (VCC)
(MAX1897, Note 3)
Measured at VCC; ILIM = GND
20
40
µA
Shutdown Supply Current (V+)
(MAX1897)
Measured at V+; VCC = VDD = 0 or 5V,
SHDN = GND
<1
5
µA
Shutdown Supply Current (VDD)
(MAX1897, Note 3)
Measured at VDD; SHDN = GND
<1
5
µA
Shutdown Supply Current (VCC)
(MAX1897, Note 3)
Measured at VCC; SHDN = GND
<1
5
µA
Quiescent Supply Current (VDD)
(Note 3)
IDD
Measured at VDD; VILIM
> 0.35V
Quiescent Supply Current (VCC)
(MAX1897, Note 3)
ICC
_______________________________________________________________________________________
µA
µA
µA
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VOUT = VCOMP = 1.2V, VCM+ = VCM- = VCS+ = VCS- = 1.2V, SHDN = VCC
(MAX1897), TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT SENSING
On-Time Adjustment Range
COMP Output Current
ICOMP
0.42 < VCOMP < 2.8V, VOUT ≥ 0.7V
-40
Sink and source
30
(VCM+ - VCM-) (VCS+ - VCS-), ICOMP =
0, -100mV ≤ (VCM+ VCM-) ≤ +100mV
Current-Balance Offset
-1.25
+1.25
MAX1897
-1.25
+1.25
mV
(VCM+ - VCM-) - (VCS+ - VCS-) = ±25mV
Current-Sense, Common-Mode
Range
CM+, CM-, CS+, CS-
Current-Sense Input Current
CM+, CM-, CS+, CSVC_LIM
Negative Current-Limit
Threshold
VCM+ - VCM- and
VCS+ - VCSVCS+ - VCS-
%
µA
MAX1887
Current-Balance
Transconductance
Positive Current-Limit Threshold
+40
1.2
-0.2
-1
mS
+2.0
V
1
µA
VILIM = 0.5V
47.5
50
52.5
VILIM = 1V
97.5
100
102.5
VILIM = 0.5V
-80
-75
-70
VILIM = 1V
-160
-150
-140
mV
mV
ILIM Standby Threshold Voltage
0.2
0.3
V
ILIM Input Current
-100
100
nA
LIMIT Propagation Delay
tLIMIT
LIMIT Output Low Voltage
VOL(LIMIT)
LIMIT Leakage Current
ILIMIT
Falling edge, 3mV over trip threshold
1.5
ISINK = 1mA
LIMIT forced to 5.5V
< 0.01
µs
0.1
V
1
µA
3.85
V
FAULT PROTECTION
VCC/VDD Undervoltage Lockout
Threshold (Note 3)
Rising edge, hysteresis = 20mV, switching
disabled below this level
Thermal Shutdown Threshold
Rising, hysteresis = 15°C (typ)
3.45
160
°C
GATE DRIVERS
DH Gate Driver On-Resistance
(Note 4)
RON(DH)
VBST - VLX forced to 5V
High state (pullup)
DL Gate Driver On-Resistance
(Note 4)
RON(DL)
Low state (pulldown)
DH Gate Driver Source/Sink
Current
MAX1887
1.0
3.5
MAX1897
1.0
4.5
MAX1887
1.0
3.5
MAX1897
1.0
4.5
MAX1887
0.4
1.0
MAX1897
0.4
2.0
Ω
Ω
IDH
DH forced to 2.5V, VBST - VLX forced to 5V
1.3
A
DL Gate Driver Sink Current
IDL
DL forced to 2.5V
4.0
A
DL Gate Driver Source Current
IDL
DL forced to 2.5V
1.3
A
DL rising
35
DH rising
26
Dead Time
ns
_______________________________________________________________________________________
3
MAX1887/MAX1897
ELECTRICAL CHARACTERISTICS (continued)
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VOUT = VCOMP = 1.2V, VCM+ = VCM- = VCS+ = VCS- = 1.2V, SHDN = VCC
(MAX1897), TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC
Logic Input High Voltage
(MAX1897)
VIH
SHDN, POL; VCC = 4.5V to 5.5V
Logic Input Low Voltage
(MAX1897)
VIL
SHDN, POL; VCC = 4.5V to 5.5V
TRIG Logic Levels
VTRIG
TON Logic Levels (MAX1897)
VTON
High
350mV hysteresis
2.4
V
0.8
3.0
Low
Logic high (VCC; 200kHz operation)
Open (300kHz operation)
1.2
V
VCC - 0.4
1.5
3.1
Logic low (GND; 550kHz operation)
Logic Input Current
V
V
0.5
TRIG
-1
SHDN (MAX1897)
-1
+1
+1
POL (MAX1897)
-2
+1
TON = GND or VDD (MAX1897)
-2
+3
µA
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VOUT = VCOMP = 1.2V, VCM+ = VCM- = VCS+ = VCS- = 1.2V, SHDN = VCC
(MAX1897), TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONTROLLER
On Time (Note 3)
tON
MAX1887 (300kHz), V+ = 12V, VCOMP = 1.2V
320
390
TON = GND (550kHz)
171
209
TON = open (300kHz)
320
390
TON = VCC (200kHz)
464
566
MAX1897,
V+ = 12V,
VCOMP = 1.2V
ns
SUPPLY CURRENTS
Quiescent Supply Current (V+)
I+
Quiescent Supply Current (VDD)
(Note 3)
IDD
Measured at VDD;
VILIM > 0.35V
Quiescent Supply Current (VCC)
(MAX1897, Note 3)
ICC
Measured at VCC; VILIM > 0.35V
Standby Supply Current (V+)
4
Measured at V+; VILIM > 0.35V
40
MAX1887
800
MAX1897
5
Measured at V+; ILIM = GND
µA
µA
800
µA
5
µA
MAX1887
40
MAX1897
5
Standby Supply Current (VDD)
(Note 3)
Measured at VDD;
ILIM = GND
Standby Supply Current (VCC)
(MAX1897, Note 3)
Measured at VCC; ILIM = GND
40
µA
Shutdown Supply Current (V+)
(MAX1897)
Measured at V+; VCC = VDD = 0 or 5V,
SHDN = GND
5
µA
Shutdown Supply Current (VDD)
(MAX1897, Note 3)
Measured at VDD; SHDN = GND
5
µA
_______________________________________________________________________________________
µA
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
(Circuit of Figure 1, V+ = +15V, VCC = VDD = 5V, VOUT = VCOMP = 1.2V, VCM+ = VCM- = VCS+ = VCS- = 1.2V, SHDN = VCC
(MAX1897), TA = -40°C to +85°C, unless otherwise noted.) (Note 5)
PARAMETER
SYMBOL
Shutdown Supply Current (VCC)
(MAX1897, Note 3)
CONDITIONS
MIN
Measured at VCC; SHDN = GND
TYP
MAX
UNITS
5
µA
+40
%
CURRENT SENSING
On-Time Adjustment Range
COMP Output Current
ICOMP
-40
Sink and source
30
(VCM+ - VCM-) (VCS+ - VCS-), ICOMP = 0,
-100mV ≤ (VCM+ - VCM-)
≤ +100mV
Current Balance Offset
Current-Sense, Common-Mode
Range
Positive Current-Limit Threshold
0.42 < VCOMP < 2.8V, VOUT ≥ 0.7V
MAX1887
-2.0
+2.0
MAX1897
-2.0
+2.0
-0.2
+2.0
mV
CM+, CM-, CS+, CSVC_LIM
Negative Current-Limit
Threshold
VCM+ - VCM- and
VCS+ - VCSVCS+ - VCS-
µA
VILIM = 0.5V
47.5
52.5
VILIM = 1V
97.5
102.5
V
mV
VILIM = 0.5V
-80
-70
VILIM = 1V
-160
-140
0.2
0.3
V
3.45
3.85
V
ILIM Standby Threshold Voltage
mV
FAULT PROTECTION
VCC/VDD Undervoltage Lockout
Threshold (Note 3)
Rising edge, hysteresis = 20mV, switching
disabled below this level
GATE DRIVERS
DH Gate Driver On-Resistance
(Note 4)
RON(DH)
VBST - VLX forced to
5V
High state (pullup)
DL Gate Driver On-Resistance
(Note 4)
RON(DL)
Low state (pulldown)
MAX1887
3.5
MAX1897
4.5
MAX1887
3.5
MAX1897
4.5
MAX1887
1.0
MAX1897
2.0
Ω
Ω
LOGIC
TRIG Logic Levels
VTRIG
TON Logic Levels (MAX1897)
VTON
350mV hysteresis
High
3.0
Low
Logic high (VCC; 200kHz operation)
Open (300kHz operation)
Logic low (GND; 550kHz operation)
1.2
V
VCC - 0.4
1.5
3.1
V
0.5
Note 1: On-time and off-time specifications are measured from 50% point to 50% point at the DH pin with LX = PGND, VBST = 5V,
and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times may be different due to MOSFET switching speeds.
Note 2: The trigger delay time, tTRIG, is measured from the time the TRIG pin transitions to time when the DL pin goes low.
Note 3: The 20-pin MAX1897 has a separate analog PWM supply voltage input (VCC) and gate-driver supply input (VDD). For the 16pin MAX1887 device, the analog PWM supply voltage input and the gate-driver supply voltage input are internally connected and named VDD.
Note 4: Production testing limitations due to package handling require relaxed maximum on-resistance specifications for the
MAX1897’s QFN package. The MAX1887 and MAX1897 contain the same die, and the QFN package imposes no additional
resistance in-circuit.
Note 5: Specifications to -40°C are guaranteed by design and not production tested.
_______________________________________________________________________________________
5
MAX1887/MAX1897
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Circuit of Figure 1, V+ = +12V, VCC = VDD = 5V, VOUT = 1.3V (ZMODE = GND) and 1.0V (ZMODE = VCC), SHDN = VCC (MAX1897))
VIN = 12V
50
VIN = 20V
40
100
VIN = 8.0V
90
VIN = 5.0V
80
1.27
EFFICIENCY (%)
60
1.28
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
70
VIN = 12.0V
1.29
MAX1887 toc02
VIN = 8.0V
VIN = 5.0V
80
1.30
MAX1887 toc01
100
90
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.0V)
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.3V, VOFFSET = -10mV)
1.26
1.25
1.24
MAX1887 toc03
EFFICIENCY vs. LOAD CURRENT
(VOUT = 1.3V)
70
60
VIN = 12V
50
1.23
VIN = 20V
40
1.22
30
20
1.20
0.1
10
1
100
0
10
30
40
10
1
100
LOAD CURRENT (A)
OUTPUT VOLTAGE vs. LOAD CURRENT
(VOUT = 1.0V, VOFFSET = -10mV)
NO LOAD INPUT CURRENT
vs. INPUT VOLTAGE
INDUCTOR CURRENT BALANCE
vs. LOAD CURRENT
0.96
0.95
IBIAS = IDD + ICC
50
40
IIN
30
0.94
20
0.93
10
0.92
0
MASTER AND SLAVE
20
30
5
10
15
20
25
30
0.6
IOUT = 40A
0.5
0.4
0.3
IOUT = NO LOAD
0.1
OUT = CM+ = CM- = CS+ = CS25
0
-25
-50
0
15
INPUT VOLTAGE (V)
MAX1887 toc06
0
10
20
25
20
30
40
50
LOAD CURRENT (A)
50
OFFSET VOLTAGE DEVIATION (µV)
MAX1887 toc07
0.7
10
0.2
OFFSET VOLTAGE DEVIATION vs.
CURRENT-SENSE COMMON-MODE VOLTAGE
INDUCTOR CURRENT BALANCE
vs. INPUT VOLTAGE
5
0.4
INPUT VOLTAGE (V)
LOAD CURRENT (A)
0.2
0.6
0
0
40
OFFSET VOLTAGE DEVIATION
vs. COMPENSATION VOLTAGE
0.3
OUT = CM+ = CM- = CS+ = CSOFFSET VOLTAGE DEVIATION (mV)
10
MAX1887 toc08
0
0.8
MAX1887 toc09
0.97
60
1.0
INDUCTOR CURRENT OFFSET: ILM - ILS (A)
70
INPUT CURRENT (mA)
0.98
MAX1887 toc05
80
MAX1887 toc04
0.99
0
0.1
50
LOAD CURRENT (A)
VIN = 12.0V
6
20
LOAD CURRENT (A)
1.00
OUTPUT VOLTAGE (V)
30
1.21
20
IL(MASTER) - IL(SLAVE) (A)
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
0.2
0.1
0
-0.1
-0.2
-0.3
-0.5
0
0.5
1.0
VOUT (V)
1.5
2.0
0
0.5
1.0
VCOMP (V)
_______________________________________________________________________________________
1.5
2.0
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
MINIMUM TRIGGER PULSE WIDTH
vs. OVERDRIVE VOLTAGE
20
0
-20
-40
350
300
200
150
-80
50
-100
0
-50
0
50
100
FALLING (IN-PHASE)
450
400
350
300
250
RISING (OUT-OF-PHASE)
FALLING (IN-PHASE)
200
150
100
50
0
0
150
500
0.5
1.0
1.5
2.0
OVERDRIVE VOLTAGE (V)
VCS+ - VCS- (V)
0
0.5
1.0
1.5
2.0
OVERDRIVE VOLTAGE (V)
POSITIVE CURRENT-LIMIT THRESHOLD
vs. ILIM VOLTAGE
MAX1887 toc13
160
140
120
STANDBY MODE
-100
RISING (OUT-OF-PHASE)
250
100
-150
ON-TIME TRIGGERED
ABOVE THE LINE
400
-60
POSITIVE CURRENT LIMIT (mV)
ICOMP (µV)
40
450
MAX1887 toc12
60
500
MAX1887 toc11
OUT = CM+ = CM- = CSICOMP = GM(VCS+ - VCS-)
TRIGGER PULSE WIDTH (ns)
80
MAX1887 toc10
100
TRIGGER PROPAGATION DELAY
vs. OVERDRIVE VOLTAGE
TRIGGER PROPAGATION DELAY (ns)
COMPENSATION OUTPUT CURRENT vs.
CURRENT-SENSE VOLTAGE DIFFERENTIAL
100
80
60
MASTER OR SLAVE
40
20
0
0
0.5
1.0
1.5
VILIM (V)
_______________________________________________________________________________________
7
MAX1887/MAX1897
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = +12V, VCC = VDD = 5V, VOUT = 1.3V (ZMODE = GND) and 1.0V (ZMODE = VCC), SHDN = VCC (MAX1897))
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = +12V, VCC = VDD = 5V, VOUT = 1.3V (ZMODE = GND) and 1.0V (ZMODE = VCC), SHDN = VCC (MAX1897))
SWITCHING WAVEFORMS
(IN-PHASE)
SWITCHING WAVEFORMS
(OUT-OF-PHASE)
MAX1887 toc15
MAX1887 toc14
A
20mV/div
A
20mV/div
B
5A/div
20A
20A
B
5A/div
10V
10V
C
10V/div
0
C
10V/div
0
1µs/div
1µs/div
A. OUTPUT VOLTAGE, VOUT = 1.290V (NO LOAD),
B. MASTER/SLAVE INDUCTOR CURRENTS
C. MASTER/SLAVE LX WAVEFORMS,
VIN = 12.0V, IOUT = 40A, POL = VCC (MAX1897)
A. OUTPUT VOLTAGE, VOUT = 1.290V (NO LOAD),
B. MASTER/SLAVE INDUCTOR CURRENTS
C. MASTER/SLAVE LX WAVEFORMS,
VIN = 12.0V, IOUT = 40A, POL = GND (MAX1897)
LOAD TRANSIENT
(IN-PHASE)
LOAD TRANSIENT
(OUT-OF-PHASE)
MAX1887 toc17
MAX1887 toc16
40A
40A
A
40A/div
5A
B
50mV/div
1.282V
C
10A/div
D
10A/div
0
0
20µs/div
A. LOAD CURRENT, IOUT = 5A TO 40A
B. OUTPUT VOLTAGE, VOUT = 1.290V (NO LOAD)
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
VIN = 12.0V, POL = VCC (MAX1897)
8
A
40A/div
B
50mV/div
5A
1.282V
C
10A/div
D
10A/div
0
0
20µs/div
A. LOAD CURRENT, IOUT = 5A TO 40A
B. OUTPUT VOLTAGE, VOUT = 1.290V (NO LOAD)
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
VIN = 12.0V, POL = GND (MAX1897)
_______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
STARTUP WAVEFORM
(NO LOAD)
DYNAMIC OUTPUT VOLTAGE TRANSITION
MAX1887 toc19
MAX1887 toc18
5V
A
5V/div
0
B
200mV/div
1.30V
1.10V
A
5V/div
5V
0
B
1.0V/div
1.0V
0
C
10A/div
D
10A/div
0
0
0
C
10A/div
0
D
10A/div
100µs/div
40µs/div
A. MASTER SHUTDOWN, VSHDN = 0 TO 5V
B. OUTPUT VOLTAGE, VOUT = 1.290V (NO LOAD)
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
A. ZMODE = 0 TO 5V
B. OUTPUT VOLTAGE, VOUT = 1.30V (ZMODE = GND)
OR 1.10V (ZMODE = VCC)
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
STARTUP WAVEFORM
(20A LOAD)
SHUTDOWN WAVEFORM
MAX1887 toc20
MAX1887 toc21
A
5V/div
5V
0
A
5V/div
5V
0
B
1.0V/div
1.0V
B
1.0V/div
0
0
C
10A/div
C
10A/div
D
10A/div
0
0
100µs/div
A. MASTER SHUTDOWN, VSHDN = 5V TO 0
B. OUTPUT VOLTAGE, VOUT = 1.290V (NO LOAD)
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
0
D
10A/div
0
100µs/div
A. MASTER SHUTDOWN, VSHDN = 0 TO 5V
B. OUTPUT VOLTAGE, VOUT = 1.290V (NO LOAD)
C. SLAVE INDUCTOR CURRENT
D. MASTER INDUCTOR CURRENT
ROUT = 65mΩ (IOUT = 20A)
_______________________________________________________________________________________
9
MAX1887/MAX1897
Typical Operating Characteristics (continued)
(Circuit of Figure 1, V+ = +12V, VCC = VDD = 5V, VOUT = 1.3V (ZMODE = GND) and 1.0V (ZMODE = VCC), SHDN = VCC (MAX1897))
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
MAX1887/MAX1897
Pin Description
PIN
MAX1887
1
10
MAX1897
19
NAME
DESCRIPTION
ILIM
Dual-Mode Current-Limit Adjustment and Standby Input. The current-limit threshold
voltage is 1/10 the voltage seen at ILIM (VILIM) over a 400mV to 1.5V range. If VILIM
drops below 250mV, the slave controller enters a low-power standby mode, forcing
DL high and DH low.
Trigger Input. Connect to the master controller’s low-side gate driver. For the
MAX1887, a rising edge triggers a single cycle. For the MAX1897, the trigger input’s
polarity is pin selectable. POL = VCC or floating triggers on the rising edge (out-ofphase operation), and POL = GND triggers on the falling edge (in-phase operation).
2
20
TRIG
3
1
CM+
Master Controller’s Positive Current-Sense Input
4
2
CM-
Master Controller’s Negative Current-Sense Input
TON
On-Time Selection Control Input. This is a three-level input used to determine the DH
on time (see On-Time Control and Active Current Balancing). For the MAX1897,
connect TON as follows for the indicated switching frequencies:
GND = 550kHz
floating = 300kHz
VCC = 200kHz.
For the MAX1887, the switching frequency is internally configured for 300kHz
operation. The slave controller’s switching frequency should be selected to closely
match the frequency of the master PWM controller.
--
3
5
4
CS-
Slave Controller’s Negative Current-Sense Input
6
5
CS+
Slave Controller’s Positive Current-Sense Input
7
6
COMP
—
7
POL
8
8
GND
9
9
PGND
10
10
DL
Low-Side Gate-Driver Output. DL swings from PGND to VDD. DL is forced high when
the MAX1897 enters standby or shutdown mode.
Current Balance Compensation. Connect a series resistor and capacitor between
COMP and OUT. See the Current Balance Compensation section.
TRIG Polarity Select Input. Connect POL to VCC or float to trigger on the rising edge of
TRIG (out-of-phase operation). Connect POL to GND to trigger on the falling edge of TRIG
(in-phase operation). For the MAX1887, POL is internally connected to VCC.
Analog Ground. Connect the MAX1897’s exposed pad to analog ground.
Power Ground
11
11
VDD
Supply Voltage Input for the DL Gate Driver. For the MAX1887, VDD also serves as
the analog supply voltage input that powers the PWM core. Connect to the system
supply voltage (4.5V to 5.5V). Bypass to PGND with a 1µF or greater ceramic
capacitor, as close to the IC as possible.
—
12
VCC
Analog Supply Voltage Input for PWM Core. Connect VCC to the system supply
voltage (4.5V to 5.5V) through a series 10Ω resistor. Bypass to GND with a 0.22µF or
greater ceramic capacitor, as close to the MAX1897 as possible.
—
13
SHDN
Active-Low Shutdown Input. A logic low shuts down the MAX1897 slave controller,
immediately pulling DL high and DH low. Connect to VCC for normal operation.
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
PIN
NAME
DESCRIPTION
MAX1887
MAX1897
12
14
DH
High-Side Gate-Driver Output. DH swings from LX to BST.
13
15
LX
Inductor Connection. Connect LX to the switched side of the inductor. LX serves as
the lower supply rail for the DH high-side gate driver.
14
16
BST
Boost Flying-Capacitor Connection. Connect to an external capacitor and diode
according to the Standard Application Circuit (Figure 1). An optional resistor in
series with BST allows DH pullup current to be adjusted.
15
17
V+
Battery Voltage Sense Connection. Connect V+ to the input power source. V+ is
used only for PWM one-shot timing (see On-Time Control and Active Current
Balancing).
16
18
LIMIT
Open-Drain Current-Limit Output. Connect to the master controller’s adjustable currentlimit input (ILIM) according to the Standard Application Circuit (Figure 1). When the voltage
across the master controller’s current-sense resistor (VCM+ - VCM-) exceeds the currentlimit threshold (VILIM/10), the MAX1887/MAX1897 pulls LIMIT low.
Table 1. Component Selection for Standard
Applications
COMPONENT
Output Voltage
CIRCUIT OF FIGURE 1
0.6V to 1.75V
Input Voltage Range
7V to 24V
Maximum Load Current
40A
Inductor (each phase)
0.6µH
Sumida CDEP134H-0R6 or
Panasonic ETQP6F0R6BFA
Frequency
300kHz (TON = float)
High-Side MOSFET
(NH, each phase)
International Rectifier
(2) IRF7811W
Low-Side MOSFET
(NL, each phase)
International Rectifier
(2) IRF7822 or
Fairchild (3) FDS7764A or
Input Capacitor (CIN)
(6) 10µF 25V
Taiyo Yuden
TMK432BJ106KM or
TDK C4532X5R1E106M
Output Capacitor (COUT)
(8) 270µF 2.0V
Panasonic EEFUE0E271R
Current-Sense Resistors
(RCS and RCM)
1.5mΩ
Voltage Positioning Gain
(AVPS)
2
Detailed Description
The MAX1887/MAX1897 step-down slave controllers
are intended for low-voltage, high-current, multiphase
DC-to-DC applications. The MAX1887/MAX1897 slave
controllers can be combined with any of Maxim’s
Quick-PWM step-down controllers to form a multiphase
DC-to-DC converter. When compared to single-phase
operation, multiphase conversion lowers the peak
inductor current by distributing the load current
between parallel power paths. This simplifies component selection, power distribution to the load, and thermal layout. Existing Quick-PWM controllers, such as the
MAX1718, function as the master controller, providing
accurate output voltage regulation, fast transient
response, and multiple fault protection features.
Synchronized to the master’s low-side gate driver, the
MAX1887/MAX1897 include a constant on-time controller, synchronous rectifier gate drive, active current
balancing, and precision current-limit circuitry.
On-Time Control and Active
Current Balancing
The MAX1887/MAX1897 slave controller uses a constant on-time, voltage feed-forward architecture similar
to Maxim’s Quick-PWM controllers (Figure 2). The control algorithm is simple: the high-side switch on-time is
determined solely by a one-shot whose period is
inversely proportional to input voltage and directly proportional to the compensation voltage (V COMP ).
Another one-shot sets a minimum off-time (130ns typical). The on-time one-shot is triggered when the follow-
______________________________________________________________________________________
11
MAX1887/MAX1897
Pin Description (continued)
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Table 2. Component Suppliers
PHONE
[COUNTRY CODE]
WEBSITE
Fairchild Semiconductor
[1] 888-522-5372
www.fairchildsemi.com
International Rectifier
[1] 310-322-3331
www.irf.com
Siliconix
[1] 203-268-6261
www.vishay.com
MANUFACTURER
MOSFETS
CAPACITORS
Panasonic
Sanyo
Taiyo Yuden
Kemet
[1] 847-468-5624
www.panasonic.com
[65] 281-3226 (Singapore)
[1] 408-749-9714
www.secc.co.jp
[03] 3667-3408 (Japan)
[1] 408-573-4150
www.t-yuden.com
[1] 408-986-0424
www.kemet.com
INDUCTORS
Sumida
[1] 408-982-9660
www.sumida.com
Coilcraft
[1] 800-322-2645
www.coilcraft.com
Coiltronics
[1] 561-752-5000
www.coiltronics.com
ing conditions are satisfied: The slave detects a transition on the TRIG input, the slave controller’s inductor
current is below its current-limit threshold, and the minimum off time has expired. For the MAX1887, a rising
edge on the trigger input (TRIG) initiates a new cycle.
For the MAX1897, the trigger input’s polarity is selected
by connecting POL to VCC (rising edge) or to GND
(falling edge).
At the slave controller’s core is the one-shot that sets
the high-side switch’s on-time. This fast, low-jitter oneshot adjusts the on-time in response to the input voltage and the difference between the inductor currents in
the master and the slave. Two identical transconductance amplifiers (GMM = GMS) integrate the difference
between the master and slave current-sense signals.
The summed output is connected to COMP, allowing
adjustment of the integration time constant with a compensation capacitor connected at COMP. The resulting
compensation current and voltage may be determined
by the following equations:
ICOMP = GMM (VCM+ − VCM− ) − GMS (VCS+ − VCS− )
VCOMP = VOUT + ICOMPZ COMP
where ZCOMP is the impedance at the COMP output.
The PWM controller uses this integrated signal (VCOMP)
to set the slave controller’s on time. When the master
12
and slave current-sense signals (CM+ to CM- and CS+
to CS-) become unbalanced, the transconductance
amplifiers adjust the slave controller’s on time, allowing
the slave inductor current to increase or decrease until
the current-sense signals are properly balanced.
V

t ON = K  COMP 
 VIN 
I
V

Z 
= K  OUT  + K  COMP C 
VIN


 VIN 
= (Master’s on time) + (Slave’s on-time
correction due to current imbalance)
This control algorithm results in balanced inductor currents with the slave switching frequency synchronized
to the master. Since the master operates at nearly constant frequency, the slave will as well. The benefits of a
constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive
regions of the spectrum; second, the inductor ripplecurrent operating point remains relatively constant,
resulting in easy design methodology and predictable
output voltage ripple.
Multiple phase switching effectively distributes the load
among the external components, thereby improving the
overall efficiency. Distributing the load current between
multiple phases lowers the peak inductor current by the
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
VCC
VGATE
D0
D1
TO LOGIC
DAC
INPUTS
C1
1µF
INPUT
8V TO 24V
CIN
(6) 10µF 25V CERAMIC
V+
DM
BST
CBST(M)
0.1µF
NH(M)
DH
S0
S1
SUSPEND
INPUTS
5V BIAS
SUPPLY
VDD
D2
D3
D4
MAX1887/MAX1897
R6
10Ω
C2
0.22µF
RCM
1.5mΩ
LM
0.6µF
LX
ZMODE
SUS
MUX CONTROL
CCC
47pF
R13
0Ω
GND
CC
CREF
0.22µF
NL(M)
DL
5V BIAS
SUPPLY
OVP
R5
510Ω
REF
FLOAT
(300kHz)
RFB
100Ω
MAX1718
FB
TON
CFB
1000pF
SKP/SDN
ON
MAX4322
R8
53.6kΩ
OFF
NEG
R9
100kΩ
POS
ILIM
C5
470pF
R2
2.8kΩ
DS
R1
301kΩ
5V BIAS
SUPPLY
TRIG
V+
BST
VDD
SHDN
R7
10Ω
LIMIT
VCC
C4
0.22µF
FLOAT
(300kHz)
FB
(MASTER)
NH(S)
DH
LX
LS
0.6µH
NL(S)
DL
RCOMP
10kΩ
OUTPUT
RCS
1.5mΩ
COUT
(8) 270µF
TON
PGND
COMP
REF
(MAX1718)
R13
200Ω
CS+
C7
4700pF
R11
113kΩ
C6
100pF
MAX1897
CBST(S)
0.1µF
POL
CCOMP
470pF
R4
1kΩ
TIME
R10
34.8kΩ
C3
1µF
R3
1kΩ
RTIME
62kΩ
R14
200Ω
CS-
POWER GROUND
ILIM
CM+
R12
30.1kΩ
C8
4700pF
GND
R15
200Ω
CM-
ANALOG GROUND
(MASTER)
ANALOG GROUND
(SLAVE)
R16
200Ω
Figure 1. Standard Application Circuit
______________________________________________________________________________________
13
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Q
MAX1887
(MAX1897)*
TRIG
TOFF
ONE-SHOT
BST
DH
LX
(VCC)*
TRIG
CONTROLLER
BIAS
(SHDN)*
Q
TON
ONE-SHOT
R
Q
S
Q
VDD
DL
(TON)*
PGND
ON-TIME
COMPUTE
V+
COMP
CS-
Q
GMS
CS+
NEGATIVE
CS LIMIT
POSITIVE
CS LIMIT
TRIG
EDGE
DETECTOR
TRIG
(POL)*
CM+
GMM
CM-
17R
ILIM
R
LIMIT
2R
GND
POSITIVE
CM LIMIT
Figure 2. Functional Diagram
number of phases (1/η) when compared to a singlephase converter. This significantly reduces the I2R losses across the inductor’s series resistance, the
MOSFETs on-resistance, and the board resistance.
14
In-Phase and Out-of-Phase Operation
Multiphase systems can stagger the on times of each
phase (out-of-phase operation) or simultaneously turn
on all phases at the beginning of a new cycle (in-phase
operation). When configured for out-of-phase operation, high input-to-output differential voltages (VIN >
η V OUT ) prevent the on times from overlapping.
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
During in-phase operation, the input capacitors must
support large, instantaneous input currents when the
high-side MOSFETs turn on simultaneously, resulting in
increased ripple voltage and current when compared
to out-of-phase operation. The higher RMS ripple current degrades efficiency due to power loss associated
with the input capacitor’s effective series resistance
(ESR). This typically requires a large number of lowESR input capacitors in parallel to meet input ripple
current ratings or minimize ESR-related losses.
For the MAX1897, the polarity select input (POL) determines whether rising edges (POL = V CC ) or falling
edges (POL = GND) trigger a new cycle. For low dutycycle applications (duty factor < 50%), triggering on
the rising edge of the master’s low-side gate driver prevents both high-side MOSFETs from turning on at the
same time. Staggering the phases in this way lowers
the input ripple current, thereby reducing the input
capacitor requirements. For applications operating with
approximately a 50% duty factor, out-of-phase operation (POL = VCC) causes the slave controller to complete an on-pulse coincident to the master controller
determining when to initiate its next on-time. The noise
generated when the slave controller turns off its highside MOSFET could compromise the master controller’s
feedback voltage and current-sense inputs, causing
inaccurate decisions that lead to more jitter in the
switching waveforms. Under these conditions, triggering off of the falling edge (POL = GND) of the master’s
low-side gate driver forces the controllers to operate inphase, improving the system’s noise immunity.
Forced-PWM Mode
The MAX1887/MAX1897 controllers do not allow lightload pulse skipping. Therefore, the master controller
must be configured for forced-PWM operation. This
PWM control scheme forces the low-side gate drive
waveform to be the complement of the high-side gate
drive waveform, allowing the inductor current to
reverse. During negative load and downward output
voltage transitions, forced-PWM operation allows the
converter to sink current, rapidly pulling down the output voltage. Another benefit of forced-PWM operation,
the switching frequency remains relatively constant
over the full load and input voltage ranges.
+5V Bias Supply (VCC and VDD)
The MAX1887/MAX1897 require an external +5V bias
supply in addition to the battery. Typically this +5V bias
supply is the notebook’s 95% efficient +5V system supply. Keeping the bias supply external to the IC
improves efficiency, eliminates power dissipation limitations, and removes the cost associated with the internal, +5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
standalone capability is needed, the +5V supply can
be generated with an external linear regulator.
The 20-pin MAX1897 has a separate analog PWM supply voltage input (VCC) and gate-driver supply input
(V DD ). For the 16-pin MAX1887 device, the analog
PWM supply voltage input and the gate-driver supply
voltage input are internally connected and named VDD.
The battery input (V+) and +5V bias inputs (VCC and
VDD) can be tied together if the input source is a fixed
4.5V to 5.5V supply.
The maximum current required from the +5V bias supply to power VCC (PWM controller) and VDD (gate-drive
power) is:
IBIAS = ICC + fSW(QG1 + QG2) = 10mA to 45mA (typ)
where I CC is 525µA typical, f SW is the switching
frequency, and QG1 and QG2 are the MOSFET data
sheets’ total gate charge specification limits at
VGS = 5V.
Shutdown (MAX1897 only)
When SHDN is driven low, the MAX1897 enters the
micropower shutdown mode (Table 3). Shutdown
immediately forces DL high, pulls DH low, and shuts
down the PWM controller so the total supply current
(ICC + IDD + I+) drops below 1µA. When SHDN is driven high, the MAX1897 operates normally with the
PWM controller enabled.
Table 3. Approximate K-Factor Errors
TON
FREQUENCY
K-FACTOR
CONNECTION
SETTING
(µs)
(MAX1897)*
(kHz)
MAX
K-FACTOR
ERROR
(%)
VCC
200
5
Float
300
3.3
10
10
GND
550
1.8
10
*The MAX1887 is internally preset for 300kHz operation.
______________________________________________________________________________________
15
MAX1887/MAX1897
Therefore, the instantaneous input current peaks of
each phase do not overlap, resulting in reduced input
and output voltage ripple and RMS ripple current. This
lowers the input and output capacitor requirements,
which allows fewer or less expensive capacitors, and
decreases shielding requirements for EMI. When the
on-times overlap at low input-to-output differential voltages (VIN < ηVOUT), the input currents of the overlapping phases may sum together, increasing the total
input and output ripple voltage and RMS ripple current.
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Table 4. Operating Mode Truth Table
SHDN
ILIM
DL
MODE
GND
X
High
Shutdown
VCC
GND
(< 0.25V)
High
Standby
VCC
High
(> 0.25V)
Switching
Normal
Operation
COMMENTS
Micropower, shutdown mode (ICC +IDD < 1µA typ). DL forced high,
DH forced low, and the PWM controller disabled.
Low-power, standby mode (ICC + IDD = 20µA typ). DL forced high,
DH forced low, and the PWM controller disabled. However, the bias
and fault protection circuitry remain active so the MAX1887/MAX1897
can continuously monitor the ILIM input.
Low-noise, fixed-frequency, PWM operation. The inductor current
reverses with light loads.
X = Don’t Care
Several Quick-PWM converters that may be used as the
master controller ramp down the output voltage at a
controlled slew rate when shut down. When combined
with these master controllers, the MAX1897 must not be
deactivated until the output voltage is fully discharged.
Otherwise the slave’s low side switch will turn on while
the master is still attempting to regulate the output. In
these applications, delay the shutdown input signal to
the MAX1897 or permanently connect SHDN to VCC
and use standby mode to conserve power (see
Standby Mode).
Standby Mode
The MAX1887/MAX1897 slave controllers enter a lowpower standby mode when the ILIM voltage (VILIM)
drops below 250mV (Table 4). Similar to shutdown
mode, standby forces DL high, pulls DH low, and disables the PWM controller to inhibit switching; however,
the bias and fault protection circuitry remain active so
the MAX1887/MAX1897 can continuously monitor the
ILIM input. When V ILIM is driven above 250mV, the
PWM controller is enabled.
When the slave controller’s current-limit voltage (VILIM)
is set through a resistive divider between the master
controller’s reference and GND (see Current Limit
Circuit), the MAX1887/MAX1897 automatically enters
low-power standby mode when the master controller
shuts down. As the master’s reference powers down,
the resistive divider pulls ILIM below 250mV, automatically activating the MAX1887/MAX1897’s low-power
standby mode.
Current-Limit Circuitry
When the master’s inductor current exceeds its valley
current limit, the master extends its off time by forcing
DL high until the inductor current falls below the currentlimit threshold. Without a transition on the master’s low16
side gate driver, the slave cannot initiate a new on-time
pulse so the slave’s inductor current ramps down as
well, maintaining the current balance. Therefore, the
slave’s valley current limit only needs to protect the
slave controller if the current balance circuitry or the
master current limit fails. The slave’s ILIM input voltage
should be selected to properly adjust the master’s current-limit threshold.
Dual-Mode ILIM Input
The current-limit input (ILIM) features dual-mode operation, serving as both the standby mode control input
and the current-limit threshold adjustment. The slave
controller enters a low-power standby mode when the
ILIM voltage (VILIM) is pulled below 250mV. For ILIM
voltages from 400mV to 1.5V, the current-limit threshold
voltage is precisely 0.1 ✕ VILIM. The current-limit voltage may be accurately set with a resistive voltagedivider between the master controller’s reference and
GND, allowing the MAX1887/MAX1897 to automatically
enter the low-power standby mode.
Slave Current Limit
The slave current-limit circuit employs a unique “valley”
current-sensing algorithm. If the current-sense signal is
above the current-limit threshold, the MAX1887/ MAX1897
will not initiate a new cycle (Figure 3). The actual peak
inductor current is greater than the current-limit threshold
by an amount equal to the inductor ripple current.
Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-limit
threshold, inductor value, and input voltage. The reward
for this uncertainty is robust, overcurrent sensing. When
combined with master controllers that contain output
undervoltage protection circuits, this current-limit method
is effective in almost every circumstance.
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
INDUCTOR CURRENT
ILOAD
ILIMIT
ILIMIT(VALLEY) = ILOAD(MAX)
(
2 - LIR
2η
)
0
TIME
Figure 3. “Valley” Current-Limit Threshold Point
There also is a negative current limit that prevents
excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to
approximately 150% of the positive current-limit threshold, and tracks the positive current limit when ILIM is
adjusted.
The MAX1887/MAX1897 uses CS+ and CS- to differentially measure the current across an external sense
resistor (RCS) connected between the inductor and output capacitors. This configuration provides precise current balancing, current limiting, and voltage positioning
with a 1% current-sense resistor. Reducing the sense
voltage decreases power dissipation but increases the
relative measurement error.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the current-sense signals measured at CS+ and CS-. The IC
should be mounted relatively close to the current-sense
resistor with short, direct traces making a Kelvin sense
connection.
Master Current-Limit Adjustment (LIMIT)
The Quick-PWM controllers that may be used as the
master controller typically use the low-side MOSFET’s
on-resistance as its current-sense element. This dependence on a loosely specified resistance with a large
temperature coefficient causes inaccurate current limiting. As a result, high current-limit thresholds are needed to guarantee full-load operation under worst-case
conditions. Furthermore, the inaccurate current limit
mandates the use of MOSFETs and inductors with
excessively high current and power dissipation ratings.
High-Side, Gate Driver Supply (BST)
The gate drive voltage for the high-side, N-channel
MOSFET is generated by the flying capacitor boost circuit (Figure 4). The capacitor between BST and LX is
alternately charged from the external 5V bias supply
(VDD) and placed in parallel with the high-side MOSFET’s gate-source terminals.
On startup, the synchronous rectifier (low-side MOSFET) forces LX to ground and charges the boost
capacitor to 5V. On the second half of each cycle, the
switch-mode power supply turns on the high-side MOSFET by closing an internal switch between BST and DH.
This provides the necessary gate-to-source voltage to
turn on the high-side switch, an action that boosts the
5V gate drive signal above the system’s main supply
voltage (V+).
INPUT
(VIN)
CBYP
V+
DBST
BST
(RBST)*
CBST
DH
NH
L
LX
MAX1887
MAX1897
( )* OPTIONAL–THE RESISTOR REDUCES
THE SWITCHING-NODE RISE TIME.
Figure 4. High-Side Gate Driver Boost Circuitry
______________________________________________________________________________________
17
MAX1887/MAX1897
IPEAK
The slave includes a precision current-limit comparator
that supplements the master’s current-limit circuitry.
The MAX1887/MAX1897 uses CM+ and CM- to differentially sense the master’s inductor current across a
current-sense resistor, providing a more accurate current limit. When the master’s current-sense voltage
exceeds the current limit set by ILIM in the slave (see
Dual-Mode ILIM Input), the open-drain current-limit
comparator pulls LIMIT low (Figure 2). Once the master
triggers the current limit, a pulse-width-modulated output signal appears at LIMIT. This signal is filtered and
used to adjust the master’s current-limit threshold.
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
MOSFET Gate Drivers (DH, DL)
Thermal Fault Protection
The DH and DL drivers are optimized for driving moderately sized, high-side and larger, low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VIN - VOUT differential exists. An adaptive dead-time
circuit monitors the DL output and prevents the highside FET from turning on until DL is fully off. There must
be a low resistance, low inductance path from the DL
driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the sense
circuitry in the MAX1887/MAX1897 will interpret the
MOSFET gate as “off” while there is actually charge still
left on the gate. Use very short, wide traces (50mils to
100 mils wide if the MOSFET is 1 inch from the device).
The dead time at the other edge (DH turning off) is
determined by a fixed 35ns internal delay.
The MAX1887/MAX1897 feature a thermal fault-protection circuit. When the junction temperature rises above
+160°C, a thermal sensor activates the standby logic,
forces the DL low-side gate driver high, and pulls the
DH high-side gate driver low. This quickly discharges
the output capacitors, tripping the master controller’s
undervoltage lockout protection. The thermal sensor
reactivates the slave controller after the junction temperature cools by 15°C.
The internal pulldown transistor that drives DL low is
robust, with a 0.4Ω (typ) on-resistance. This helps prevent DL from being pulled up during the fast rise-time of
the LX node, due to capacitive coupling from the drain
to the gate of the low-side synchronous-rectifier MOSFET. However, for high-current applications, some combinations of high- and low-side FETs may cause
excessive gate-drain coupling, leading to poor efficiency, EMI, and shoot-through currents. This is often remedied by adding a resistor less than 5Ω in series with
BST, which increases the turn-on time of the high-side
FET without degrading the turn-off time (Figure 4).
Undervoltage Lockout
During startup, the VCC undervoltage lockout (UVLO)
circuitry forces the DL gate driver high and the DH gate
driver low, inhibiting switching until an adequate supply
voltage is reached. Once VCC rises above 3.75V, valid
transitions detected at the trigger input initiate a corresponding on-time pulse (see On-Time Control and
Active Current Balancing). To ensure correct startup,
the MAX1887/MAX1897 slave controller’s undervoltage
lockout voltage must be lower than the master controller’s undervoltage lockout voltage.
If the VCC voltage drops below 3.75V, it is assumed that
there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, DL
is forced high in this mode—to force the output to
ground. This results in large negative inductor current
and possibly small negative output voltages. If VCC is
likely to drop in this fashion, the output can be clamped
with a Schottky diode to PGND to reduce the negative
excursion.
18
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design:
Input Voltage Range: The maximum value (VIN(MAX))
must accommodate the worst-case high AC adapter
voltage. The minimum value (VIN(MIN)) must account for
the lowest input voltage after drops due to connectors,
fuses, and battery selector switches. If there is a choice
at all, lower input voltages result in better efficiency.
Maximum Load Current: There are two values to consider. The peak load current (ILOAD(MAX)) determines
the instantaneous component stresses and filtering
requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the
current-limit circuit. The continuous load current (ILOAD)
determines the thermal stresses and thus drives the
selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook
CPUs generally exhibit ILOAD = ILOAD(MAX) ✕ 80%.
For multiphase systems, each phase supports a fraction of the load, depending on the current balancing.
The highly accurate current sensing and balancing
implemented by the MAX1887/MAX1897 slave controller evenly distributes the load among each phase:
I
ILOAD(SLAVE) = ILOAD(MASTER) = LOAD
η
where η is the number of phases.
Switching Frequency: This choice determines the
basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency also is a moving target, due to rapid improvements
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
V

t ON = K  COMP 
 VIN 
Set the nominal on time in the slave to match the on
time in the master. An exact match is not necessary
because the MAX1887/MAX1897 have wide tON adjustment ranges (±40%). For example, if tON in the master
is set to 250kHz, the slave can be set to either 200kHz
or 300kHz and still achieve good performance. Care
should be taken to ensure that the COMP voltage
remains within its output voltage range (0.42V to
2.80V).
Inductor Operating Point: This choice provides tradeoffs between size vs. efficiency and transient response
vs. output noise. Low inductor values provide better
transient response and smaller physical size, but also
result in lower efficiency and higher output noise due to
increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the
edge of critical conduction (where the inductor current
just touches zero with every cycle at maximum load).
Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 50% ripple current.
Inductor Selection
The switching frequency and operating point (% ripple
or LIR) determine the inductor value as follows:
VOUT x (VIN − VOUT ) x η
VIN xfSW xILOAD(MAX) xLIR
where η is the number of phases. Example: η = 2,
ILOAD = 40A, VIN = 12V, VOUT = 1.3V, fSW = 300kHz,
30% ripple current or LIR = 0.3:
L=
1.3V x (12V − 1.3V ) x 2
12V x 300kHz x 40A x 0.3
 2 + LIR 
IPEAK = ILOAD(MAX) 

 2η 
where η is the number of phases.
where K is internally preset to 3.3µs for the MAX1887 or
externally set by the TON pin-strap connection for the
MAX1897 (Table 3)
L=
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current (IPEAK):
= 0.64µH
Transient Response
The inductor ripple current affects transient-response
performance, especially at low VIN - VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of
output sag also is a function of the maximum duty factor, which can be calculated from the on time and minimum off time:
 V

K
L ∆ILOAD(MAX) 2  OUT  + t OFF(MIN) 
 VIN 

VSAG =
 (VIN − VOUT )K 

− t OFF(MIN) 
2ηCOUT VOUT 

VIN



(
)
where tOFF(MIN) is the minimum off time (see Electrical
Characteristics), η is the number of phases, and K is
from Table 3.
The amount of overshoot due to stored inductor energy
can be calculated as:
VSOAR
(∆ILOAD(MAX) )
≈
2
L
2ηCOUT VOUT
Setting the Current Limits
The master and slave current-limit thresholds must be
great enough to support the maximum load current,
even under worst-case operating conditions. Since the
master’s current limit determines the maximum load
(see Current-Limit Circuitry), the procedure for setting
the current limit is sequential. First, the master’s current
limit is set based on the operating conditions and the
characteristics of the low-side MOSFETs. Then the
slave controller is configured to adjust the master’s current-limit threshold based on the precise current-sense
resistor value and variation in the MOSFET characteristics. Finally, the resulting valley current limit for the
slave’s inductor occurs above the master’s current-limit
______________________________________________________________________________________
19
MAX1887/MAX1897
in MOSFET technology that are making higher frequencies more practical.
Setting Switch On Time: The constant on-time control
algorithm in the master results in a nearly constant
switching frequency despite the lack of a fixed-frequency clock generator. In the slave, the high-side switch on
time is inversely proportional to V+ and directly proportional to the compensation voltage (VCOMP):
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
SLAVE
CONTROLLER
MASTER
CONTROLLER
RC
ILIM
REF
VITHM(HIGH) =
1  RB 
VREF
10  RA + RB 
VITHM(HIGH) =

RB // RLIMIT
1 
VREF

10  RA + (RB // RLIMIT ) 
CREF
RD
MAX1887
MAX1897
MAX1718
RA
RLIMIT
LIMIT
ILIM
CLIMIT
RB
VITHS =
1  RD 
VREF
10  RC + RD 
Figure 5. Setting the Adjustable Current Limits
threshold. This is acceptable since the slave’s inductor
current limit only serves as a fail-safe in case the master and slave inductor currents become significantly
unbalanced during a transient.
The basic operating conditions are determined using
the same calculations provided in any Quick-PWM regulator data sheet. The valley of the inductor current
(ILIMIT(VALLEY)) occurs at ILOAD(MAX) divided by the
number of phases minus half of the peak-to-peak
inductor current:
 ILOAD(MAX)   ∆IINDUCTOR 
ILIMIT(VALLEY) ≥ 

 − 

η
2


where the peak-to-peak inductor current may be determined by the following equation:
∆IINDUCTOR =
VOUT (VIN − VOUT )
VINfSWL
The master’s high current-limit threshold must be set
high enough to support the maximum load current,
even when the master’s current-limit threshold is at its
minimum tolerance value, as described in the master
controller’s data sheet. Most Quick-PWM controllers
that may be chosen as the master controller use the
low-side MOSFET’s on-resistance to sense the inductor
current. In these applications, the worst-case maximum
value for R DS(ON) plus some margin for the rise in
RDS(ON) over temperature must be used to determine
the master’s current-limit threshold. A good general rule
is to allow 0.5% additional resistance for each °C of
temperature rise. Set the master current-limit threshold
20
to support the maximum load current for the maximum
RDS(ON) and minimum current-limit tolerance value:
VITHM(HIGH) ≥ (ILIMIT(VALLEY))RDS(ON)(MAX)
where VITHM, the master’s current-limit threshold, is typically 1/10th the voltage seen at the master’s ILIM input
(V ITHM = 0.1 x V LIM(MASTER) , see the master controller’s data sheet). Connect a resistive voltage-divider
from the master controller’s internal reference to GND,
with the master’s ILIM input connected to the center tap
(Figure 5). Use 1% tolerance resistors in the divider with
10µA to 20µA DC bias current to prevent significant
errors due to the ILIM pin’s input current:
VILIM(MASTER)
20µA
≤ RB ≤
VILIM(MASTER)
10µA
 VREF(MASTER)  
RA = 
 − 1RB
 VILIM(MASTER)  
Configure the slave controller so its LIMIT output begins
to roll off after the master current-limit threshold occurs:
 VITHM (HIGH)

VITHS ≥ RCM 
+ ∆IINDUCTOR 
 RDS(ON)(MAX)

where VITHS, the slave’s current-limit threshold, is precisely one-tenth the voltage seen at the slave’s ILIM
input (VITHS = 0.1 ✕ VILIM(SLAVE)). Connect a second
resistive voltage-divider from the master controller’s
internal reference to GND, with the slave’s ILIM input
connected to the center tap (Figure 5). The external
adjustment range of 400mV to 1.5V corresponds to a
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
VILIM(SLAVE)
20µA
≤ RD ≤
VILIM(SLAVE)
10µA
 VREF(MASTER)  
RC = 
 − 1RD
 VILIM(SLAVE)  
A ADJ ≥ AROS
 R // R  RDS(ON)(MAX)
1+  A B  ≥
 RLIMIT  RDS(ON)(MIN)
(RA // RB )RDS(ON)(MIN)
RDS(ON)(MAX) − RDS(ON)(MIN)
Finally, verify that the total load on the master’s reference does not exceed 50µA:

  VREF 
VREF
IBIAS( TOTAL) = 
 +
 ≤ 50µA
R
R
R
+
//
 A ( B
LIMIT )   RC + RD 
Current Limit Design Example
For the typical application circuit shown in Figure 1: VIN
= 12V, VOUT = 1.3V, fSW = 300kHz, η = 2, ILOAD(MAX)
= 50A, L = 0.6µH, RDS(ON)(MAX) = 6mΩ, RDS(ON)(MIN )
= 3mΩ
1) Determine the peak-to-peak inductor current and
the valley current limit:
1.3V x (12V − 1.3V )
12V x 300kHz x 0.6µH
Now select the resistive-divider values (RA and RB
in Figure 5) to set the appropriate voltage at the
master’s ILIM input:
Selecting RB = 100kΩ ±1% provides the following
value for RA:


2.0V
RA = 
− 1 x100kΩ ≈ 54kΩ
10
130
x
mV


3) Determine the slave’s current-limit threshold:
Increasing AADJ improves the master’s current-limit
accuracy but also increases the current limit’s noise
sensitivity. Therefore, RLIMIT may be selected using the
following equation:
∆IINDUCTOR =
VITH(MASTER) ≥ 21.8A ✕ 6mΩ = 130mV
 10 x130mV   10 x130mV 
RB = 
 to 
 = 65kΩ to130kΩ
 20µA   10µA

Now, set the current-limit adjustment ratio (A ADJ =
VITHM(HIGH)/VITHM(LOW)) greater than the maximum to
minimum on-resistance ratio (ARDS = RDS(ON)(MAX)/
RDS(ON)(MIN)):
RLIMIT ≤
2) Determine the master’s current-limit threshold from
the valley current limit and low-side MOSFETs’ maximum on-resistance over temperature:
= 6.4A
 50A   1

ILIMIT(VALLEY) = 
 −  x 6.4A = 21.8A
 2  2

 130mV

VITHS ≥ 1.5mΩ x 
+ 6.4 A ≈ 42mV
 6mΩ

Select the resistive-divider values (RC and RD in
Figure 5) to set the appropriate voltage at the
slave’s ILIM input:
 10 x 42mV   10 x 42mV 
RD = 
 to 
 = 21kΩ to 42kΩ
 20µA   10µA 
Selecting RD = 30.1kΩ ±1% provides the following
value for RA:
 2.0V

RC = 
− 1 x 30.1kΩ ≈ 113kΩ
10
x
42
mV


4) Determine RLIMIT (Figure 5) from the above equation:
RLIMIT ≤
(53.6kΩ // 100kΩ) x 3mΩ ≈ 35kΩ
6mΩ − 3mΩ
5) Finally, verify that that the total bias currents do not
exceed the 50µA maximum load of the master’s reference:


2.0V
IBIAS(TOTAL) = 
+
 54kΩ + (100kΩ // 34.8kΩ) 
2.0V



 = 36µA
 30.1kΩ + 113kΩ 
______________________________________________________________________________________
21
MAX1887/MAX1897
current-limit threshold of 40mV to 150mV. Use 1% tolerance resistors in the divider with 10µA to 20µA DC bias
current to prevent significant errors due to the ILIM
pin’s input current. Reducing the current-limit threshold
voltage lowers the sense resistor’s power dissipation,
but this also increases the relative measurement error:
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
SLAVE CURRENT-LIMIT VOLTAGES
vs. AVERAGE INDUCTOR CURRENT
160
V
IADJ(MIN) = IPEAK = ITHS
RCM
VITHM(HIGH)
140
VOLTAGE (mV)
120
MASTER
CONTROLLER
100
VITHM(LOW)
80
RCMILM(PEAK) = RCSILS(PEAK)
60
RCMILM(VALLEY) = RCSILS(VALLEY)
40
SLAVE
CONTROLLER
VITHS
20
∆IADJ - ∆IINDUCTOR =
0
0
10
20
30
40
[
]
VOUT(VIN - VOUT)
VINfSWL
50
AVERAGE INDUCTOR CURRENT (A)
MASTER CURRENT-LIMIT VOLTAGES
vs. AVERAGE INDUCTOR CURRENT
160
UNADJUSTED ∆ILIMIT ≤ ∆ILIMIT = VITHM(HIGH)
140
VITHM(HIGH)
VOLTAGE (mV)
120
(
)
ARDS - 1
RDS(ON)(MAX)
ADJUSTED ∆ILIMIT ≤ ∆IINDUCTOR
100
80
60
VITHM(LOW)
RDS(ON)(MIN) = LLM(VALLEY)
40
RDS(ON)(MIN) = LLM(VALLEY)
20
0
0
10
20
30
40
50
AVERAGE INDUCTOR CURRENT (A)
Figure 6. Master/Slave Current-Limit Thresholds
When unadjusted, the on-resistance variation of the
low-side MOSFETs results in a maximum current-limit
variation (∆ILIMIT) determined by the following equation:
rent-limit variation from 21.7A (unadjusted) to less than
6.4A (adjusted).
 A

RDS − 1
Unadjusted ∆ILIMIT = VITHM(HIGH) 

 RDS(ON)(MAX) 
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
In CPU VCORE converters and other applications where
the output is subject to large load transients, the output
capacitor selection typically depends on how much
ESR is needed to prevent the output from dipping too
low under a load transient. Ignoring the sag due to
finite capacitance:
where ARDS = RDS(ON)(MAX)/RDS(ON)(MIN). Using the
MAX1887/MAX1897 to adjust the master’s current-limit
threshold results in a maximum current-limit variation
less than the peak-to-peak inductor current:
Adjusted ∆ILIMIT ≤ ∆IINDUCTOR
Output Capacitor Selection
As shown in Figure 6, the resulting current-limit variation of the master is dramatically reduced. For the
above example, this control scheme reduces the cur22
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
VSTEP
∆ILOAD(MAX)
In non-CPU applications, the output capacitor selection
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capacitor’s ESR. When operating multiphase systems out-ofphase, the peak inductor currents of each phase are
staggered, resulting in lower output ripple voltage by
reducing the total inductor ripple current. For out-ofphase operation, the maximum ESR to meet ripple
requirements is:
RESR ≤
VRIPPLE




 η  VIN − ηVOUT  VOUT 
− ( η − 1)VOUT t TRIG 
  



 L  
fSW
  VIN 

This equation may be rewritten as the single phase ripple current minus a correction due to the additional
phases:
RESR ≤
VRIPPLE


 VOUT 
 (t ON + t TRIG )
ILOAD(MAX)LIR − η( η − 1)
L 


where tTRIG is the MAX1887/MAX1897’s trigger propagation delay, η is the number of phases, and K is from
Table 3. When operating the MAX1897 in-phase (POL
= GND), the high-side MOSFETs turn on together, so
the output capacitors must simultaneously support the
combined inductor ripple currents of each phase. For
in-phase operation, the maximum ESR to meet ripple
requirements is:
RESR ≤
VRIPPLE
VRIPPLE
=
ILOAD(MAX)LIR  η   VOUT 
 f L   V  (VIN − VOUT )
 SW   IN 
The actual capacitance value required relates to the
physical size needed to achieve low ESR, as well as to
the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums, OS-CONs, and other electrolytics).
When using low-capacity filter capacitors such as
ceramic or polymer types, capacitor size is usually
determined by the capacity needed to prevent VSAG
and VSOAR from causing problems during load tran-
sients. Generally, once enough capacitance is added to
meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and
VSOAR equations in the Transient Response section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
f
fESR ≤ SW
π
where fESR =
1
2πRESRCOUT
For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below
50kHz. Tantalum, Sanyo POSCAP, and Panasonic SP
capacitors in wide-spread use at the time of publication
have typical ESR zero frequencies below 30kHz. In the
standard application used for inductor selection, the
ESR needed to support a 30mVp-p ripple is 30mV/(40A
x 0.3) = 2.5mΩ. Eight 270µF/2.0V Panasonic SP capacitors in parallel provide 1.9mΩ (max) ESR. Their typical
combined ESR results in a zero at 39kHz.
Don’t put high-value ceramic capacitors directly across
the output without taking precautions to ensure stability.
Ceramic capacitors have a high ESR zero frequency
and may cause erratic, unstable operation. However,
it’s easy to add enough series resistance by placing
the capacitors a couple of centimeters downstream
from the junction of the inductor and FB pin.
Unstable operation manifests itself in two related but
distinctly different ways: double-pulsing and feedback
loop instability. Double-pulsing occurs due to noise on
the output or because the ESR is so low that there isn’t
enough voltage ramp in the output voltage signal. This
“fools” the error comparator into triggering a new cycle
immediately after the minimum off-time period has
expired. Double-pulsing is more annoying than harmful,
resulting in nothing worse than increased output ripple.
However, it can indicate the possible presence of loop
instability due to insufficient ESR. Loop instability can
result in oscillations at the output after line or load
steps. Such perturbations are usually damped, but can
cause the output voltage to rise above or fall below the
tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor
______________________________________________________________________________________
23
MAX1887/MAX1897
RESR ≤
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
the switching waveforms (VLX and/or IINDUCTOR). Don’t
allow more than one cycle of ringing after the initial
step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The MAX1887/MAX1897 multiphase slave controllers
operate out-of-phase (MAX1897 POL = VCC or float),
staggering the turn-on times of each phase. This minimizes the input ripple current by dividing the load current among independent phases:


I
 VOUT (VIN − VOUT )

IRMS =  LOAD  
VIN

 η 


for out-of-phase operation.
When operating the MAX1897 in-phase (POL = GND),
the high-side MOSFETs turn on simultaneously, so
input capacitors must support the combined input ripple currents of each phase:
 V

OUT (VIN − VOUT )


IRMS = ILOAD
VIN




for in-phase operation.
For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred because of
their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series
with the input. If the MAX1887/MAX1897 is operated as
the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either
configuration, choose an input capacitor that exhibits
less than +10°C temperature rise at the RMS input current for optimal circuit longevity.
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Calculate both of these sums.
Ideally, the losses at VIN(MIN) should be roughly equal
to losses at VIN(MAX), with lower losses in between. If
the losses at VIN(MIN) are significantly higher than the
24
losses at VIN(MAX), consider increasing the size of NH.
Conversely, if the losses at VIN(MAX) are significantly
higher than the losses at VIN(MIN), consider reducing
the size of NH. If VIN does not vary over a wide range,
the minimum power dissipation occurs where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two SO-8s, DPAK or
D2PAK), and is reasonably priced. Make sure that the
DL gate driver can supply sufficient current to support
the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction problems may occur.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the
minimum input voltage:
2
V
I

PD (NH Re sistive) =  OUT   LOAD  RDS(ON)
 VIN   η 
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power-dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (RDS(ON)) losses. Highside switching losses don’t usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation of the high-side
MOSFET (NH) due to switching losses is difficult since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching-loss calculation
provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including
verification using a thermocouple mounted on NH:
PD (NH
(VIN(MAX) )
Switching) =
2
CRSSfSW ILOAD
IGATE η
where CRSS is the reverse transfer capacitance of NH
and IGATE is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
2
  V
  I

PD(NL Re sistive) = 1−  OUT   LOAD  RDS(ON)
  VIN(MAX)   η 
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
ILOAD(MAX) but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to
tolerate:
 ILOAD(MAX)LIR 
ILOAD = ηIVALLEY(MAX) + 

2


where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-sized heatsink to handle the overload power dissipation.
Choose a Schottky diode (D1) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal
to 1/(3η) of the load current. This diode is optional and
can be removed if efficiency is not critical.
Current Balance Compensation (COMP)
The current balance compensation capacitor (CCOMP)
integrates the difference of the master and slave current-sense signals, while the compensation resistor
improves transient response by increasing the phase
margin. This allows the user to optimize the dynamics
of the current balance loop. Excessively large capacitor
values increase the integration time constant, resulting
in larger current differences between the phases during
transients. Excessively small capacitor values allow the
current loop to respond cycle by cycle but can result in
small DC current variations between the phases.
Likewise, excessively large series resistance can also
cause DC current variations between the phases. Small
series resistance reduces the phase margin, resulting
in marginal stability in the current balance loop. For
most applications, a 470pF capacitor and 10kΩ series
resistor from COMP to the converter’s output voltage
works well.
The compensation network can be tied to V OUT to
include the feed-forward term due to the master’s on
time. (See On-time Control and Active Current
Balancing.) To reduce noise pick-up in applications
that have a widely distributed layout, it is sometimes
helpful to connect the compensation network to quiet
analog ground rather than VOUT.
Applications Information
Voltage Positioning and
Effective Efficiency
Powering new mobile processors requires careful
attention to detail to reduce cost, size, and power dissipation. As CPUs became more power hungry, it was
recognized that even the fastest DC-DC converters
were inadequate to handle the transient power requirements. After a load transient, the output instantly
changes by ESRCOUT ✕ ∆ILOAD. Conventional DC-DC
converters respond by regulating the output voltage
back to its nominal state after the load transient occurs
(Figure 7). However, the CPU only requires that the output voltage remain above a specified minimum value.
Dynamically positioning the output voltage to this lower
limit allows the use of fewer output capacitors and
reduces power consumption under load.
For a conventional (nonvoltage-positioned) circuit, the
total voltage change is:
Vp-p1 = 2 ✕ (ESRCOUT ✕ ∆ILOAD) + VSAG + VSOAR
where VSAG and VSOAR are defined in Figure 8. Setting
the converter to regulate at a lower voltage when under
load allows a larger voltage step when the output current suddenly decreases (Figure 7). So the total voltage
change for a voltage-positioned circuit is:
Vp-p2 = (ESRCOUT ✕ ∆ILOAD) + VSAG + VSOAR
where V SAG and V SOAR are defined in the Design
Procedure. Since the amplitudes are the same for both
circuits (Vp-p1 = Vp-p2), the voltage-positioned circuit
tolerates twice the ESR. Since the ESR specification is
achieved by paralleling several capacitors, fewer units
are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Since the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in
R SENSE . For a nominal 1.6V, 22A output (R LOAD =
72.7mΩ), reducing the output voltage 2.9% gives an
______________________________________________________________________________________
25
MAX1887/MAX1897
voltages are applied, due to the squared term in the C
2
✕ VIN ✕ ƒSW switching-loss equation. If the high-side
MOSFET chosen for adequate RDS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
CAPACITIVE SOAR
(dV/dt = IOUT/COUT)
VOLTAGE POSITIONING THE OUTPUT
ESR VOLTAGE STEP
(ISTEP x RESR)
A
1.4V
VOUT
1.4V
B
CAPACITIVE SAG
(dV/dt = IOUT/COUT)
RECOVERY
A. CONVENTIONAL CONVERTER (50mV/div)
B. VOLTAGE-POSITIONED OUTPUT (50mV/div)
Figure 7. Voltage Positioning the Output
output voltage of 1.55V and an output current of 21.3A.
Given these values, CPU power consumption is
reduced from 35.2W to 33.03W. The additional power
consumption of RSENSE is:
50mV x 21.3A = 1.06W,
which results in an overall power savings of:
35.2W - (33.03W + 1.06W) = 1.10W.
In effect, 2.2W of CPU dissipation is saved and the
power supply dissipates much of the savings, but both
the net savings and the transfer of dissipation away
from the hot CPU are beneficial. Effective efficiency is
defined as the efficiency required of a nonvoltage-positioned circuit to equal the total dissipation of a voltagepositioned circuit for a given CPU operating condition.
Calculate effective efficiency as follows:
1) Start with the efficiency data for the positioned circuit (VIN, IIN, VOUT, IOUT).
2) Model the load resistance for each data point:
RLOAD = VOUT / IOUT
3) Calculate the output current that would exist for each
RLOAD data point in a nonpositioned application:
INP = VNP / RLOAD
where VNP = 1.6V (in this example).
4) Calculate effective efficiency as:
26
ILOAD
Figure 8. Transient Response Regions
Effective efficiency = (VNP ✕ INP) / (VIN ✕ IIN) = calculated nonpositioned power output divided by the
measured voltage-positioned power input.
5) Plot the efficiency data point at the nonpositioned
current, INP.
The effective efficiency of voltage-positioned circuits is
shown in the Typical Operating Characteristics.
One-Stage (Battery Input) Versus
Two-Stage (5V Input) Applications
The MAX1887/MAX1897 can be used with a direct battery connection (one stage) or can obtain power from a
regulated 5V supply (two-stage). Each approach has
advantages, and careful consideration should go into
the selection of the final design.
The one-stage approach offers smaller total inductor
size and fewer capacitors overall due to the reduced
demands on the 5V supply. Due to the high input voltage, the one-stage approach requires lower DC input
currents, reducing input connection/bus requirements
and power dissipation due to input resistance. The
transient response of the single stage is better due to
the ability to ramp the inductor current faster. The total
efficiency of a single stage is better than the two-stage
approach.
The two-stage approach allows flexible placement due
to smaller circuit size and reduced local power dissipation. The power supply can be placed closer to the
CPU for better regulation and lower I2R losses from PC
board traces. Although the two-stage design has slow-
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
Ceramic Output Capacitor Applications
Ceramic capacitors have advantages and disadvantages. They have ultra-low ESR and are noncombustible, relatively small, and nonpolarized. However,
they are also expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies. In addition, their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load conditions, unless a small
inductor value is used (high switching frequency), or
there are some bulk tantalum or electrolytic capacitors
in parallel to absorb the stored inductor energy. In
some cases, there may be no room for electrolytics,
creating a need for a DC-DC design that uses nothing
but ceramics.
The MAX1887/MAX1897 can take full advantage of the
small size and low ESR of ceramic output capacitors in
a voltage-positioned circuit. The addition of the positioning resistor increases the ripple at FB, lowering the
effective ESR zero frequency of the ceramic output
capacitor.
Output overshoot (V SOAR) determines the minimum
output capacitance requirement (see Output Capacitor
Selection). Often the switching frequency is increased
to 550kHz, and the inductor value is reduced to minimize the energy transferred from inductor to capacitor
during load-step recovery. The efficiency penalty for
operating at 550kHz is about 3% when compared to
the 300kHz circuit, primarily due to the high-side MOSFET switching losses.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching power stage requires particular attention
(Figure 9). If possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. Follow these
guidelines for good PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This is essential for stable, jitterfree operation
2) Connect all analog grounds to a separate solid
copper plane, which connects to the GND pin of
the MAX1887/MAX1897. This includes the V CC
bypass capacitor, COMP components, and the
resistive-divider connected to ILIM.
3) The master controller also should have a separate
analog ground. Return the appropriate noise sensi-
tive components to this plane. Since the reference
in the master is sometimes connected to the slave,
it may be necessary to couple the analog ground in
the master to the analog ground in the slave to prevent ground offsets. A low value (≤10Ω) resistor is
sufficient to link the two grounds.
4) Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PC boards (2oz vs. 1oz) can enhance fullload efficiency by 1% or more. Correctly routing PC
board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single mΩ of excess trace resistance causes a measurable efficiency penalty.
5) Keep the high-current gate-driver traces (DL, DH,
LX, and BST) short and wide to minimize trace
resistance and inductance. This is essential for
high-power MOSFETs that require low-impedance
gate drivers to avoid shoot-through currents.
6) CS+, CS-, CM+, and CM- connections for current
limiting and balancing must be made using Kelvin
sense connections to guarantee the current-sense
accuracy.
7) When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
8) Route high-speed switching nodes away from sensitive analog areas (COMP, ILIM). Make all pinstrap control input connections (SHDN, ILIM, POL)
to analog ground or VCC rather than power ground
or VDD.
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT,
and D1 anode). If possible, make all these connections on the top layer with wide, copper-filled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate trace must be short and
wide (50mils to 100mils wide if the MOSFET is 1
inch from the controller IC).
3) Group the gate-drive components (BST diode and
capacitor, VDD bypass capacitor) together near the
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 1. This diagram can be viewed as
______________________________________________________________________________________
27
MAX1887/MAX1897
er transient response than the single stage, this can be
offset by the use of a voltage-positioned converter.
MAX1887/MAX1897
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
MAX1718
(MASTER)
MAX1897
(SLAVE)
CONNECT THE EXPOSED
PAD TO GND
VIA TO POWER
GROUND
VIA TO POWER
GROUND
CONNECT GND AND PGND
BENEATH THE CONTROLLER AT
ONE POINT ONLY AS SHOWN
≤10Ω
MASTER
VIA TO CM+
AND FB
SLAVE
LM
DS
DM
LS
VIA TO CS+
COUT
COUT
COUT
COUT
VIA TO CM-
VIA TO CSCOUT
POWER
GROUND
COUT
COUT
TOP LAYER
COUT
OUTPUT
MASTER
SLAVE
INPUT (V+)
CIN
CIN
CIN
CIN
CIN
CIN
CIN
CIN
POWER
GROUND
BOTTOM LAYER
Figure 9. Power-Stage PC Board Layout Example
28
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
5V BIAS
SUPPLY
VDD
(VCC)*
BST
(POL)*
REF
(MASTER)
INPUT
V+
DH
SHDN
LX
ILIM
DL
OUTPUT
MAX1887
(MAX1897)*
FLOAT
(300kHz)
(TON)*
ILIM
(MASTER)
LIMIT
PGND
CS+
FB
(MASTER)
COMP
CSCM+
MASTER CURRENT
SENSE RESISTOR
CMGND
MASTER LOW-SIDE GATE DRIVER
TRIG
( )* MAX1897 PINS ONLY
having four separate ground planes: input/output
ground, where all the high-power components go;
the power ground plane, where the PGND pin and
V DD bypass capacitor go; the master’s analog
ground plane where sensitive analog components,
the master’s GND pin and VCC bypass capacitor
go; and the slave’s analog ground plane where the
slave’s GND pin, and VCC bypass capacitor go.
The master’s GND plane must meet the PGND
plane only at a single point directly beneath the IC.
Similarly, the slave’s GND plane must meet the
PGND plane only at a single point directly beneath
the IC. The respective master and slave ground
planes should connect to the high-power output
ground with a short metal trace from PGND to the
source of the low-side MOSFET (the middle of the
star ground). This point must also be very close to
the output capacitor ground terminal.
5) Connect the output power planes (VCORE and system ground planes) directly to the output filter
capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit
as close to the CPU as is practical.
Pin Configurations (continued)
TOP VIEW
ILIM 1
16 LIMIT
TRIG 2
15 V+
CM+ 3
14 BST
CM- 4
MAX1887
13 LX
CS- 5
12 DH
CS+ 6
11 VDD
10 DL
COMP 7
9
GND 8
PGND
QSOP
Chip Information
TRANSISTOR COUNT: 1422
PROCESS: BiCMOS
______________________________________________________________________________________
29
MAX1887/MAX1897
Typical Operating Circuit
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
QSOP.EPS
MAX1887/MAX1897
Package Information
30
______________________________________________________________________________________
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
______________________________________________________________________________________
31
MAX1887/MAX1897
Package Information (continued)
Quick-PWM Slave Controllers for
Multiphase, Step-Down Supplies
MAX1887/MAX1897
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.