FAIRCHILD FAN6753

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AN-6753
FAN6753 — Highly Integrated Green-Mode PWM Controller
Abstract
This application note describes a detailed design strategy for
a high-efficiency compact flyback converter. Design
considerations, mathematical equations, and guidelines for a
Printed-Circuit-Board (PCB) layout are presented.
Features
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High-Voltage Startup
Low Operating Current: 2.7mA
Linearly Decreasing PWM Frequency to 22KHz
Frequency Hopping to Reduce EMI Emission
Fixed PWM Frequency: 65KHz
Peak-Current-Mode Control
Cycle-by-Cycle Current Limiting
Leading-Edge Blanking (LEB)
Synchronized Slope Compensation
Internal Open-Loop Protection
Gate Output Maximum Voltage Clamp: 18V
VDD Under-Voltage Lockout (UVLO)
VDD Over-Voltage Protection (OVP)
Programmable Over-Temperature Protection (OTP)
Internal Latch Circuit (OTP)
Built-In 5ms Soft-Start Function
Constant Power Limit (Full AC Input Range)
Internal OTP Sensor with Hysteresis
Introduction
The highly integrated FAN6753 series of PWM controllers
provides several features to enhance the performance of
flyback converters.
To minimize standby power consumption, a proprietary
green-mode function provides off-time modulation to
linearly decrease the switching frequency at light-load
conditions. To avoid acoustic-noise problems, the minimum
PWM frequency is set above 22KHz. This green-mode
function enables the power supply to meet international
power conservation requirements. With the internal highvoltage startup circuitry, the power loss due to bleeding
resistors is also eliminated. To further reduce power
consumption, FAN6753 is manufactured using the BiCMOS
process, which allows an operating current of only 2.7mA.
Built-in synchronized slope compensation achieves stable
peak-current-mode control. The proprietary external line
compensation ensures a constant output-power limit over a
wide AC input voltage range, from 90VAC to 264VAC.
FAN6753 provides many protection functions. In addition to
cycle-by-cycle current limiting, the internal open-loop
protection circuit ensures safety should an open-loop or
output short-circuit failure occur.
FAN6753
OVP (VDD)
OLP (FB)
External Latch
(LATCH)
Auto Restart
Auto Restart
Latch
Applications
General-purpose, switch-mode power supplies and flyback
power converters, including:
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Power Adapters
Open-Frame Switch-Mode Power Supply (SMPS)
SOP-8
RT
1
8
HV
FB
2
7
NC
SENSE
3
6
VDD
GND
4
5
GATE
Figure 1. Pin Configuration (Top View)
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
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AN-6753
APPLICATION NOTE
Typical Application
Figure 2. Typical Application
Block Diagram
HV
GND
8
4
VDD
PWM
Latch
Soft
Driver
VDD-OVP
IHV
S
Frequency
Hopping
5
GATE
3
SENSE
2
FB
Q
R
Internal
BIAS
VDD 6
Soft-Start
UVLO
Vlimit
VDD-ON /VDD-OFF
VFB-OPEN
Slope
Compensation
3R
Green
Mode
Controller
I LATCH
R
LATCH 1
Limit-Power
Controller
VDD
VFB-OLP
100 μs
Counter
IDD-OLP
VDD
VLATCHth
VTH-OLP
Figure 3. Functional Block Diagram
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
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AN-6753
APPLICATION NOTE
Internal Block Operation
Startup Circuitry
Under-Voltage Lockout (UVLO)
When the power is turned on, the internal current source
(typically 2mA) charges the hold-up capacitor C1 through a
startup resistor RHV. During the startup sequence, the VAC
provides a startup current of about 2mA and charges the VDD
capacitor C1. RHV and D2 are series connections and can be
directly connected by VAC to the HV pin. As the VDD pin
reaches the start threshold voltage VDD-ON, the FAN6753
activates and signals the MOSFET. The high-voltage source
current is switched off and the supply current is drawn from
the auxiliary winding of the main transformer, as shown in
Figure 4. For higher 6KV surge test, RHV of 100KΩ or
above is recommended.
The FAN6753 has a voltage detector on the VDD pin to
ensure that the chip has enough power to drive the
MOSFET. Figure 6 shows a hysteresis of the turn-on and
turn-off threshold levels and an open-loop-release voltage.
IDD
2.7mA
70µA
10µA
7.5V 9.5V
15.5V
VDD
Figure 6. UVLO Specification
The turn-on and turn-off thresholds are internally fixed at
15.5V and 9.5V. During startup, the VDD capacitor must be
charged to 15.5V to enable the IC. The capacitor continues
to supply the VDD until the energy can be delivered from the
auxiliary winding of the main transformer. The VDD must not
drop below 9.5V during startup.
If the secondary output short circuit or the feedback loop is
open, the FB pin voltage rises rapidly toward the open-loop
voltage, VFB-OPEN. If the FB voltage remains above VFB-OLP
and lasts for tD-OLP, the FAN6753 stops emitting output
pulses and enters auto-restart mode. To further limit the
input power under a short-circuit or open-loop condition, a
special two-step UVLO mechanism prolongs the discharge
time of the VDD capacitor. Figure 7 shows the traditional
UVLO method, along with the special two-step UVLO
method. In the two-step UVLO mechanism, an internal
sinking current, IDD-OLP, pulls the VDD voltage toward the
VDD-OLP. This sinking current is disabled after the VDD drops
below VDD-OLP; after which the VDD voltage is again charged
towards VDD-ON. With the two-step UVLO mechanism, the
average input power during a short-circuit or open-loop
condition is greatly reduced. As a result, over-heating does
not occur.
Figure 4. Startup Circuit for Power Transfer
When the supply current is drawn from the transformer, it
draws a leakage current of about 1µA from the HV pin. The
maximum power dissipation of the RHV is:
PRHV = IHV −LC( Typ.) × RHV
2
(1)
where IHV-LC is the supply current drawn from HV pin.
PRHV = 1μA 2 × 100KΩ ≅ 0.1μW
(2)
Soft Start
For many applications, it is necessary to minimize the inrush
current during the startup period. The built-in 5ms soft-start
circuit significantly reduces the startup current spike and
output-voltage overshoot.
15.5V
VDD
9.5V
General UVLO
Gate
15.5V
VDD
Figure 5.
9.5V
Soft-Start Circuit
7.5V
Two-Step UVLO
Gate
Figure 7.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
UVLO Effect
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AN-6753
APPLICATION NOTE
FB Input
Built-In Slope Compensation
The FAN6753 is designed for peak-current-mode control. A
current-to-voltage conversion is accomplished externally
with current-sense resistor RS. Under normal operation, the
FB level controls the peak inductor current:
A flyback converter can be operated in Discontinuous
Current Mode (DCM) or Continuous Current Mode (CCM).
There are many advantages when operating the converter in
CCM. With the same output power, a converter in CCM
exhibits a smaller peak inductor current than one in DCM.
Therefore, a small-sized transformer and a low-rated
MOSFET can be applied. On the secondary side of the
transformer, the RMS output current of DCM can be twice
that of CCM. Larger wire gauge and output capacitors with
larger ripple-current ratings are required. DCM operation
also results in a higher output voltage spike. A large LC
filter is added. Therefore, a flyback converter in CCM
achieves better performance with lower component cost.
IPEAK =
VFB − 0.6
4 × RS
(3)
where VFB is the voltage on the FB pin and 4 is an internal
divider ratio.
When VFB is less than 0.6V, the FAN6753 terminates the
output pulses.
FB
RFB
Rb
VO
Despite the above advantages of CCM operation, there is
one concern—stability. In CCM operation, the output power
is proportional to the average inductor current, while the
peak current remains controlled. This causes sub-harmonic
oscillation when the PWM duty cycle exceeds 50%. Adding
slope compensation (reducing the current-loop gain) is an
effective way to prevent oscillation. The FAN6753
introduces a synchronized positive-going ramp (VSLOPE) in
every switching cycle to stabilize the current loop.
Therefore, FAN6753 helps design a cost-effective, highly
efficient, compact, flyback power supply that operates in
CCM without additional external components.
CFB
R3
R1
C1
R2
The positive ramp added is:
VSLOPE = VSL • D
Figure 8. Feedback Circuit
where VSL = 0.33V and D = duty cycle.
Figure 8 is a typical feedback circuit consisting mainly of a
shunt regulator and an opto-coupler. R1 and R2 form a
voltage divider for the output-voltage regulation. R3 and C1
are adjusted for control-loop compensation. A small-value
RC filter (e.g. RFB= 47Ω, CFB= 1nF) placed on the FB pin to
the GND can further increase stability. The maximum
sourcing current of the FB pin is 1.5mA. The phototransistor
must be capable of sinking this current to pull the FB level
down at no load. The value of the biasing resistor, Rb, is
determined as follows:
VOUT − VD − VZ
⋅ K ≥ 1.5mA
Rb
(5)
(4)
where:
VD is the drop voltage of photodiode, approximately 1.2V;
VZ is the minimum operating voltage, 2.5V of the shunt
regulator; and
Figure 9.
Synchronized Slope Compensation
K is the current transfer rate (CTR) of the opto-coupler.
For an output voltage VOUT = 5V, with CTR = 100%, the
maximum value of Rb is 860Ω.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
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AN-6753
APPLICATION NOTE
Constant Output-Power Limit
The maximum output power of a flyback converter can
generally be determined from the current-sense resistor RS.
When the load increases, the peak inductor current increases
accordingly. When the output current arrives at the
protection value, the Output-Current-Protection (OCP)
comparator dominates the current-control loop. OCP occurs
when the current-sense voltage reaches the threshold value.
The output GATE driver is turned off after a small
propagation delay, tPD. The delay time results in unequal
power-limit levels under universal input. A sawtooth power
limiter (saw limiter) is designed to solve the unequal power
limit problem. As shown in Figure 10, the saw limiter is
designed as a positive ramp signal (Vlimit_ramp) and is fed into
the inverting input of the OCP comparator. This results in a
lower current limit at high-line inputs than at low-line inputs.
However, with the fixed propagation delay tPD, the peak
primary current would be the same for various line-input
voltages. Therefore, the maximum output power can remain
a constant value within a wide input voltage range without
adding any external circuitry.
Figure 10.
The FAN6753 contains an open-loop protection function. If
the output load is higher than the maximum output current,
the output voltage drops and the feedback error amplifier is
saturated. Once the FB voltage trips the OLP threshold of
4.8V for longer than 56ms, the protection is activated to
turns off the gate output to stop the switching of power
circuit. As shown in Figure 1, the FB voltage is compared
with 4.8V reference voltage. If the FB voltage is higher than
4.8V, the OLP timer starts counting. If the OLP condition
persists for 56ms, the OLP signal could be asserted. This
protection is reset after UVLO.
0.56V
Low-Line
Sense Voltage
0
ton1 tPD
ton2
LEB Circuit
Open-Loop Protection (OLP)
0.9V
Actual Power
Limit Point
High-Line
Sense Voltage
Figure 11.
Constant Power-Limit Compensation
Leading-Edge Blanking (LEB)
FB
A voltage signal proportional to the MOSFET current
develops on the current-sense resistor RS. Each time the
MOSFET is turned on, a spike induced by the diode reverse
recovery and the output capacitances of the MOSFET and
diode appears on the sensed signal. A leading-edge blanking
time of about 140ns is introduced to avoid premature
termination of the MOSFET by the spike. Therefore, only a
small-value RC filter (e.g. 100Ω + 470pF) is required
between the SENSE pin and RS. Still, a non-inductive
resistor for the RS is recommended.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
OLP
56ms
Timer
4.8V
Figure 12.
Open-Loop Protection Circuit
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AN-6753
APPLICATION NOTE
Output Driver / Soft Driving
External Latch Function (LATCH Pin)
The output stage is a fast totem-pole gate driver capable of
directly driving an external MOSFET. An internal Zener
diode clamps the driver voltage under 18V to protect the
MOSFET against over-voltage. By integrating special
circuits to control the slew rate of switch-on rising time, the
external resistor RG may not be necessary to reduce
switching noise, improving Electromagnetic Interference
(EMI) performance.
The LATCH pin can be used to control the FAN6753
entering latch mode by pulling this pin over 5.2V for 100µs.
If floating, the LATCH pin is internally pulled HIGH to
3.5V. It is not recommended to float or short the LATCH
pin to GND. This pin also includes a test mode to disable
the jitter function. LATCH pin internally sources 100µA, so
place a resistor in series to GND. Do not let this voltage
exceed 5.2V for the FAN6753 to function normally.
Over-Temperature Protection (OTP)
The built-in temperature-sensing circuit shuts down PWM
output once the junction temperature exceeds 135°C. While
PWM output is shut down, VDD gradually drops to the
UVLO voltage (around 7.5V). VDD then charges up to the
startup threshold voltage of 15.5V through the startup
resistor until PWM output is restarted. This hiccup-mode
protection occurs repeatedly as long as the temperature
remains above 130°C. The temperature hysteresis window
for the OTP circuit is 25°C.
Figure 13.
Gate Driver
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
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AN-6753
APPLICATION NOTE
Printed Circuit Board Layout
Two suggestions with pros and cons for ground connections
are recommended.
ƒ GND3→2→4→1: Possible method for circumventing the
sense signals and common impedance interference.
ƒ GND3→2→1→4: Potentially better for ESD testing
where a ground is not available for the power supply. The
charges for the ESD discharge path go from secondary,
through the transformer stray capacitance, to the GND2
first. Then, the charges go from GND2 to GND1 and
back to the mains. It should be noted that control circuits
should not be placed on the discharge path. Point
discharge for common choke can decrease high-frequency
impedance and help increase ESD immunity.
ƒ Should a Y-cap between primary and secondary be
required, the Y-cap should be connected to the positive
terminal of the Cbulk (VDC). If this Y-cap is connected to
the primary GND, it should be connected to the negative
terminal of the Cbulk (GND1) directly. Point discharge of
the Y-cap also helps with ESD. However, according to
safety requirements, the creepage between the two
pointed ends should be at least 5mm.
Current, voltage, and switching frequency make PCB layout
and design very important. Good PCB layout minimizes
excessive EMI and prevents the power supply from being
disrupted during surge/ESD tests. The following are some
general guidelines:
ƒ For better EMI performance and to reduce line frequency
ƒ
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ripples, the output of the bridge rectifier should be
connected to capacitor Cbulk first, then to switching circuits.
The high-frequency current loop is found in the loop
Cbulk – Transformer – MOSFET – RS – Cbulk in Figure 14.
The area enclosed by this current loop should be as small
as possible. Keep the traces (especially 4→1) short,
direct, and wide. High-voltage drain traces related to the
MOSFET and RCD snubber should be kept far from
control circuits to prevent unnecessary interference. If a
heatsink is used for the MOSFET, grounding the heatsink
is recommended.
As indicated by 3 in Figure 14, the control circuits’
ground should be connected first, then to other circuitry.
As indicated by 2 in Figure 14, the area enclosed by the
transformer auxiliary winding, D1, and C1 should also be kept
small. Place C1 close to FAN6753 for good decoupling.
FAN6753
Figure 14.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
Layout Considerations
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AN-6753
APPLICATION NOTE
PCB Layout Suggestions for LCD monitor / TV Application:
1.
Safety distance for EMI loop requirement in LCD monitor /TV application:
UL60950 safety distance for lightening surge standard.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
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8
AN-6753
APPLICATION NOTE
The UL60950 standard defines the safety distance for product operation where voltage is under 600V. The following table
details distance for the power system PCB layout requirements from LCD monitor / TV specifications.
Application Surge Voltage (V)
Location
Layout Distance
Design Rule (Practical)
30000
L-FG / N-FG / L-N
2mm
2.6mm
4000V
L-FG / N-FG / L-N
3mm
4mm
5000V
L-FG / N-FG / L-N
4mm
5mm
6000V
L-FG / N-FG / L-N
5.5mm
6mm
9000V
L-FG / N-FG / L-N
9mm
9mm
12000V
L-FG / N-FG / L-N
14mm
14mm
From the surge discharge loop function, it is necessary to lead the surge energy to ground. Two concepts can solve the issue:
ƒ
Provide enough distance (follow no.1).
ƒ
Use air and gap to replace SPA tube and reduce the cost by PCB layout.
ƒ
The location is as the table below describes:
Location
Safety Distance( CL )
Gap Width
Discharge (Gap / Air )(Point Discharge)
L -> FG(SG)
Table G.2
1mm
Yes
N -> FG(SG)
Table G.2
1mm
Yes
YC1 -> FG
Table G.2
1mm
Yes
YC2 -> FG
Table G.2
1mm
Yes
CM CHOKE
Table G.2
1mm
Yes
The ground path has the shortest loop and largest area in the primary side. (The PCB layout trace is the good loop.)
Use the AC inlet’s mechanic component (ground clip and heat sink) to reduce the ground impedance and lead the surge
energy to ground path in the building.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
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AN-6753
APPLICATION NOTE
Design Example, 19V/3.42A for NB Adaptor
In this equation, the CCM duty-cycle does not exceed 50%.
The design should therefore be free of sub-harmonic
oscillations in steady-state conditions.
Following is the specification of the design example:
VIN min = 100 VDC (bulk valley in low-line conditions)
VIN max = 375 VDC
VOUT = 19V
IOUT = 3.42A
Operating mode is CCM
η= 0.8
fSW = 65 kHz
3. To obtain the primary inductance, use the following
equation, which expresses the inductance in relationship
to a ripple factor KRF. This coefficient dictates the depth of
the CCM operation.
(
(6)
Knowing a maximum bulk voltage of 375V, the clamp
voltage must be set to:
Vclamp = 510 − 375 = 135V
Selecting a KRF factor of 0.8 (40% ripple) ensures good
operation over universal mains. It leads to an inductance of:
(7)
Based on the above level, adopt a headroom between the
reflected voltage and the RCD clamp level of 50V. If this
headroom is too small, a high dissipation can occur on the
RCD clamp network and efficiency suffers. A leakage
inductance of around 1% of the magnetizing value should
give good results with this choice (kc = 1.6). The turn ratio
between primary and secondary is:
(VOUT
+ Vf ) / n = Vclamp / kc
(12)
ΔIL = (VIN _ min • dmax ) / (fSW • L )
= (100 • 0.43 ) / (65k • 433 µH ) = 1.53 A peak - to - peak
(13)
(
IIN _ avg = POUT / η • VIN _ min
)
(14)
= (19 • 3.42 ) / (0.8 • 100 ) = 812 mA
IPEAK = IIN _ avg / dmax + ΔIL / 2 =
0.813 / 0.43 + 1.53 / 2 = 2.66 A
Solving for n gives:
n = N S / N P = kc • (VOUT + Vf ) / Vclamp =
L = (100 • 0.43 )2 / (65 k • 0.8 • 82 ) = 433 µH
The peak current can be evaluated as:
(8)
1.6 • (19 + 0.8 ). / 135 = 0.234
(11)
where KRF = △IL/I1 and defines the amount of ripple
desired in CCM (see Figure 15).
ƒ Small KRF: deep CCM, implying a large primary
inductance, a low bandwidth, and a large leakage
inductance.
ƒ Large KRF: approaching BCM, where the RMS losses
are the worse, but smaller inductance, leading to a better
leakage inductance.
1. Turn Ratio.
The MOSFET BVdss dictates the amount of reflected
voltage needed. Considering a 600V MOSFET and a 15%
de-rating factor, limit the maximum drain voltage to:
VDS _ max = 600 • 0.85 = 510V
)
L = VIN _ min • d max 2 / (fSW • K RF • Pin )
Follow below steps to design a transformer:
(15)
Based on Figure 15, I1 can also be calculated as:
(9)
I1 = I peak - ΔIL / 2 = 2.66 - (1.53 / 2) = 1.9A
Round it to 0.25 or 1/n = 4.
(16)
The valley current is found to be:
Ivalley = I peak - ΔIL = 2.66 - 1.53 = 1.13A
(17)
4. Based on the above, evaluate the RMS current
circulating in the MOSFET and the sense resistor:
Id_rms = I1 • d •
(1 + 1/3 • (ΔIL ) / (2 • I1 ))2 )
= 1.9 × 0.66 • ( 1 + 1/3 • (1.53 / (2 • 1.9)) 2 ) = 1.29A
(18)
5. The current peaks to 2.66A. If the desired OCP is
120% of Ipeak and FAN6753’s Vlimit_L clamps 0.9V drop
across the sense resistor, compute its value as:
Rsense = 0.9V / (2.66A • 120%) = 0.282 Ω
Figure 15.
Using Equation 18, the power dissipated in the sense
element reaches:
Primary Inductance Current Evolution in CCM
2. Calculate the maximum operating duty-cycle for this
flyback converter operated in CCM:
(
d max = (VOUT / n ) / VOUT / n + VIN _ max
= (19 • 4 ) / (19 • 4 + 100 ) = 0.43
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
)
(19)
Psense = R sense • I d_rms 2 = 0.282 • 1.29 2 = 470mW
(20)
(10)
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AN-6753
APPLICATION NOTE
Related Datasheets
FAN6753 — Highly Integrated Green-Mode PWM Controller
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1.
Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 5/13/09
2.
A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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