www.fairchildsemi.com AN-4164 Design Guideline for 3-Channel Interleaved CCM PFC Using the FAN9673 2.5 kW CCM PFC Controller Incorporating circuits for the implementation of leading edge, average current mode, boost-type power factor correction; the FAN9673 enables the design of a power supply that fully complies with the IEC1000-3-2 specification. The FAN9673 also features an innovative channel management function, which allows the power level of the slave channels to be loaded / unloaded smoothly according to the voltage on CM pin, thereby improving the PFC converter’s load transient response. Introduction The interleaved boost Power Factor Correction (PFC) converter has become the topology of choice for highpower applications due to the improved efficiency that can be achieved through load current sharing. By sharing the load current in more than one balanced phase, the RMS current stress, current ripple, and boost inductor size per phase can be significantly reduced. Therefore, the heavy load efficiency can be significantly improved, which allows for the selection of cost effective power MOSFET and boost diode as well as improved longevity of the power supply. This application note presents practical design considerations for a 3-channel interleaved CCM boost PFC employing the FAN9673. It includes the procedure for designing the boost inductor and output filter, selecting the components, and implementing average current mode control. The design procedure is then verified through an experimental 2.5 kW prototype converter. Figure 1 shows the typical application circuit of the PFC converter. The FAN9673 advanced PFC controller can be an optimal solution for implementing high-power PFC (above several kilowatts). The FAN9673 is a Continuous Conduction Mode (CCM) PFC controller for a three-channel interleaved boost-type pre-regulator. * DBP RB1 VIN LPFC1 DPFC1 LPFC2 DPFC2 LPFC3 DPFC3 VPFC CB+ AC Line In RFB1 COUT EMI Filter RFB2 RB1 RA1 RB2 RA2 SPFC1 SPFC2 SPFC3 RF RSEN3 CFB3 Driver Circuit RSEN2 Driver Circuit Driver Circuit RSEN1 RFB3 CF1 CF2 RB3 OPFC1 CS1+ CS1- OPFC2 CS2+ CS2- OPFC3 CS3+ IAC CS3FBPFC CVC2 BIBO CB1 CB2 VEA CSS RB4 SS CILIMIT2 RILIMIT2 IEA1 ILIMIT2 FAN9673 MCU RDY MCU signal (DC) PVO IEA2 LS RLS CVC1 CIC12 RIC1 CIC11 CVI22 RIC2 CIC21 CIC32 IEA3 CGC RVC1 RIC3 CIC31 VDD GC RGC CVDD LPK CM1 CM2 CM3 GND RLPK RI ILIMIT VIR Standby Power RRI MCU CLPK RILIMIT RRLPK RLPK Channel Enable CRLPK CVIR RVIR CILIMIT * About DBP please reference System Design Precautions Figure 1. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 Typical Application Circuit of FAN9673 www.fairchildsemi.com AN-4164 Design Procedure In this section, a design procedure is presented using the schematic of Figure 1 as the reference. A 2.5 kW rated output power, three-channel CCM interleaved PFC with universal input range is selected as a design example. The design specifications are as follows: Table 1. Design Specifications Line Voltage Range 180~264 VAC PFC Output Voltage Ripple 5% Line Frequency 50 Hz Switching Frequency fSW = 40 kHz Nominal PFC Output Voltage VPFC = 393 V PFC Efficiency η > 0.95 Minimum PFC Output Voltage VPFC2 = 350 V Brownout Line Voltage 160 VAC Output Power PO = 2.5 kW Brown-In Line Voltage 170 VAC Number of Channel 3 Channel Management Method External Signal from MCU [STEP-1] Estimate Input Rated Power and Output Current [STEP-2] Frequency Setting The internal oscillator frequency of the FAN9673 is determined by the external resistor RRI on the RI pin. The switching frequency is determined by the timing resistor RRI, calculated as: The overall system is comprised of three parallel boost PFC stages, as shown in Figure 2, so the input power of the PFC stage is given as: PIN POUT TOT 8 108 RRI The guaranteed switching frequency 18 kHz~40 kHz and 55 kHz~75 kHz. f SW (1) where is the combined efficiency of the PFC stages. (4) ranges are The output current of PFC stage is given by: I OUT -TOT (Design Example) RRI of 20 k is selected to obtain POUT TOT 40 kHz switching frequency. (2) VPFC RRI The output current of each boost stage is given by: I OUT POUT TOT (3) VPFC Channel Number [STEP-3] VIN Range & RIAC Setting I OUT The FAN9673 senses the peak value of line voltage using the IAC pin, as shown in Figure 3. The peak value of the line voltage is obtained by a peak detect circuit using a sample-and-hold method. Meanwhile, the instantaneous line voltage information is obtained by sensing the current that flows into the IAC pin through RIAC. I OUT-TOT PIN Boost PFC Boost PFC Boost PFC Figure 2. POUT-TOT V PFC PFC Stage Configuration RIAC should be selected according to the input voltage range. For universal AC input (85 V~264 V), VVIR should be set <1.5 V and RIAC should chosen as 6 MΩ. If the input is high-voltage single-AC input (180 V~264 V), VVIR should be set >3.5 V (maximum is 5 V) and RIAC should be chosen as 12 MΩ. VVIR determines the application based on AC input range. The change of VVIR influences gain of gain modulator and brown-in/out hysteresis. (Design Example) PIN POUT POUT -TOT 2500 2631W 0.95 POUT -TOT 2500 Channel Number IOUT -TOT IOUT POUT -TOT VPFC 393 I OUT -TOT Channel Number 833W 3 2500 VAC 85V ~ 265V RIAC 6M ,VVIR 1.5V 6.37 A 6.37 3 VAC 180V ~ 265V RIAC 12M ,VVIR 3.5V (5) The controller needs to set VVIR for the different input range as: 2.12 A © 2013 Fairchild Semiconductor Corporation Rev. 1.2 8 108 8 108 20k f SW 40 103 VVIR IVIR RVIR (6) www.fairchildsemi.com 2 AN-4164 The maximum current of boost inductor is: VPFC VIN IL I L PK I L AVG (1 RFB1 COUT RIAC IIAC VFBPFC RFB2 RCS A C (LPK) Peak Detector LPK Current Command (C. Comd.) C I L AVG B B (VEA) (11) (Design Example) The average of the boost inductor current over one switching cycle at the peak of the minimum AC line (assume it’s brownout of PFC) is obtained as: A (IAC) IAC 2 POUT K RF K ) (1 RF ) 2 VLINE MIN 2 2 POUT 2 833 7.75A VLINE MIN 160 0.95 Gain Modulator The boost inductor is obtained as: 2VLINE MIN VPFC 2VLINE MIN 1 K RF I L AVG VPFC f SW VEA LPFC 2.5V VFBPFC Figure 3. Line Sensing Circuits 2 160 393 2 160 1 221 H 1.4 7.75 393 40 103 The maximum current of the boost inductor is given as: (Design Example) The PFC is designed for high-voltage single-AC input (180 V~264 V). RIAC should be chosen as 12 MΩ and RVIR is: I L PK VVIR IVIR RVIR 10 A 470k 4.7V >3.5V 2 POUT K (1 RF ) VLINE MIN 2 2 833 1.4 (1 ) 13.17A 160 0.95 2 470 k is selected as RVIR for the AC input range of 180 V~264 V. [STEP-5] PFC Output Capacitor Selection [STEP-4] PFC Inductor Design ID The duty cycle of the boost switch at the peak of line voltage is given as: DL VPFC 2VLINE VPFC (7) I D AVG Then, the maximum current ripple of the boost inductor at the peak of minimum AC line voltage is given as: I L 2VLINE MIN VPFC 2VLINE MIN 1 LPFC VPFC f SW IDAVG IOUT TOT (1 cos(4 fLINE t)) IOUT TOT (8) The average of boost inductor current over one switching cycle at the peak of the line voltage for minimum AC input is given by: I L AVG VPFC RIPPLE VPFC 2 POUT (9) VLINE MIN I L. AVG K RF Figure 5. I L . PK I L I L. AVG Figure 4. Inductor Current IOUT -TOT (12) 2 f LINE VPFC RIPPLE where IOUT is nominal output current of the boost PFC stage and VPFC-RIPPLE is the peak-to-peak output voltage ripple. COUT For a given current ripple factor (KRF=IL/ILAVG), the boost inductor value can be obtained as: LPFC 2VLINE MIN VPFC 2VLINE MIN 1 K RF I L AVG VPFC f SW © 2013 Fairchild Semiconductor Corporation Rev. 1.2 PFC Output Voltage Ripple The output voltage ripple should be considered when selecting the PFC output capacitor. Figure 5 shows the line frequency ripple on the output voltage. With a given specification of output ripple, the value for the output capacitor can be obtained from: I L. AVG IL I OUT TOT 2 f LINE COUT (10) www.fairchildsemi.com 3 AN-4164 VPFC The hold-up time should also be considered when determining the output capacitor value: VO IL 393V COUT 2 POUT -TOT tHOLD VPFC 2 VPFC MIN 2 (13) 354V RCS External Signal (MCU) where POUT-TOT is nominal output power of boost PFC stage; tHOLD is the required holdup time; and VPFC-MIN is the allowable minimum PFC output voltage during the hold-up time. VFBPFC PVO gmv (Design Example) With peak-to-peak voltage ripple specification of 5% of VPFC, the capacitor should be: COUT 2 2500 15 103 3932 3002 RFB1 RFB 2 1V Two-Level PFC Output Block RFB 3 (VPFC VREF ) VREF 23.7 103 (393 2.5) 3.7 M 2.5 Set VPFC2 =350 V for low input AC 200 V, the required VPVO is then: 1163 F RFB 3 VPVO 4 VREF VPFC 2 ( ) R R R FB1 FB 2 FB 3 23.7 103 4 2.5 350( ) 1.09V 6 3 3.7 10 23.7 10 The PVO function is used to change the output voltage of PFC,V PFC, which should be kept at least 25 V higher than V IN. [STEP-6] Output Sensing & PVO Setting To improve system efficiency, the FAN9673 incorporates the programmable PFC output voltage function (PVO). As shown in Figure 6, when the PFC output voltage is much higher than the peak voltage of the AC input, the user can input a DC level from the MCU to the PVO pin to decrease the PFC output voltage. (It is recommended that the PFC output voltage is set at least 25 V higher than the peak voltage of AC input. Otherwise, it is necessary to consider other factors closely related to the PFC output voltage regulation, such as hold-up time, PF, and THD standard of input current.) [STEP-7] Current-Sensing & Current-Limit VIN VPFC IL RCS The relationship between the feedback voltage level for the PFC output voltage and VPVO is given as: CS- CS+ LS VPVO 4 RFB3 4 VREF VPFC 2 ( ) R R R FB1 FB 2 FB 3 gmi LPT IEA (14) CM CM RI1 RIAC Once the desired PFC output voltage, VPFC2, for low AC input is determined; the required DC voltage level VPVO is given by: VPVO VPVO (Design Example) Set the PFC output level at 393 V, RFB3=23.7 k: In this case, three parallel connected capacitors of 390 F are selected for the PFC output capacitor. In this design example, the target application for the three-channel PFC is a home appliance power supply, so there is no hold-up time requirement. VFBPFC VREF 2.25V 0V Figure 6. Since the minimum allowable output voltage during one cycle (15 ms) drop-out is 300 V, the capacitor value should be: VPFC 2 VPFC MIN 2 RFB3 Voltage Protection 6.36 1030 F 2 50 (393 5%) COUT 2.5V RFB2 VFBPFC FBPFC 2.5V I OUT -TOT 2 f LINE VPFC RIPPLE 2 POUT -TOT tHOLD RFB1 RM IAC LPK CI2 CI1 IMO Drive Logic Peak Detecter VEA OPFC OSC (15) RI RV1 RFB1+FB2 gmv CV2 CV1 2.5V PVO FBPFC Figure 7. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 RFB3 PFC Compensation Circuits www.fairchildsemi.com 4 AN-4164 Figure 7 shows the PFC compensation circuits. The first step in compensation network design is to select the current-sensing resistor of the PFC converter, considering the control window of voltage loop. Since line feedforward is used in FAN9673, the output power is proportional to the output of voltage control error amplifier, VVEA, as shown below: Case 3, current limit 2 (saturation state): In case 3, use the level 80%~90% of maximum current of the switch device to be the saturation protection. This current protection is cycle–by-cycle limited. 1.2V I RI V 0.6 POUT (VVEA ) POUT MAX VEA VVEA SAT 0.6 The maximum power limit of PFC is: 5 (16) A 1/4 C 2 V GMAX RM POUT MAX LINE MIN (17) RIAC RCS The RM is the output resistor of for multiplier to transfer the current command to a voltage type signal. GMAX is a coefficient of the internal control loop. Figure 9. Resistor RILIMIT can be calculated from: RILIMIT VILIMIT2 = Saturation Protection VILIMIT2 VCS.PK VILIMIT/4 Case2: >Max. Power (Abnormal), AC cycle drop VVEA = 6V, but“C”abnormal short time, clamp by VILIMIT Right design, max power limited by VVEA Figure 8. Right design at abnormal test, command from Multiplier clamp by VILIMIT 1.8 ( PIN / 3) 2 RCS 4 VLINE MIN I ILIMIT (18) Regarding the choice for ILIMIT2 level, the user can use 150% of maximum power as the setting. It’s used to protect the switching devices. User can also use the maximum current rating of the semiconductor device with 10% to 20% de-rating as the limit level. ILIMIT2 setting is obtained as: VCS Case1: Max. Power (Normal), VVEA-MAX“B”= 6V Internal Block of ILIMIT It is typical to set the maximum power limit of the PFC stage to around 120%~150% of full load, such that the VVEA is around 4~4.5 V. 2 V GMAX RM 1602 2 7.5 103 RCS LINE MIN 0.0295 RIAC POUT MAX 12 106 1.3 833 A 30 m resistor is selected. PFC Command Gmi+ RILIMIT ILIMIT should be triggered before ILIMIT2, because ILIMIT2 is used to prevent saturation of the inductor from damaging switches. ILIMIT signal limits the maximum power /current by clamping level VILIMIT. VILIMIT is set by the external resistor RILIMIT. (Design Example) Setting the maximum power limit of each PFC stage as 1.083 kW (130% of full load per channel), the current sensing resistor is obtained from: Non-Saturation VX B Gain Modulator ILIMIT 3 I*RILIMIT 4 Case3: >Max. Power (Abnormal), AC cycle drop, as left case, but user uses wrong choke can not afford current at Max. command. RILIMIT 2 Wrong design at abnormal test, but protect by VILIMIT2 150% VCS PK I ILIMIT 2 (19) (Design Example) VCS PK RCS I L PK 0.03 13.17 0.395V ILIMIT and ILIMIT2 Function The FAN9673 has three cases of current limit protections via the VEA, ILIMIT, and ILIMIT2 to protect OCP and inductor saturation. The user can program the current limit threshold VILIMIT1 and VILIMIT2 by resistor. fSW=40 kHz, is selected, IILIMIT2 and IILIMIT is: Case 1, power (normal state): In the normal case, current / power should be controlled by a command, VM, from the gain modulator. When VVEA rises to 6 V, the output power and current of the system are at peak. The power and current can’t increase further. I ILIMIT 2 Case 2, current limit 1 (abnormal state): The current command from the gain modulator is k*IAC*VVEA/VLPK2. When the system works in abnormal state, such as when the AC cycle is missed and returns in a short period, the VLPK has a delay before returning to the original level. This delay significantly increases the current command. If the command is greater than the ILIMIT clamp level VILIMIT, it is limited as in Case 2, shown in Figure 8. If the inductor current is not saturated, the peak current of this state can be the maximum current design for each channel. A 10 kΩ resistor is selected for ILIMIT2. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 I ILIMIT 1.2 1.0208 1.225 6.13 10-5 A RRI 20 103 1.2 1.03125 1.2375 6.19 10-5 A RRI 20 103 RILIMIT 2 150% VCS PK 1.5 0.395 9.57k I ILIMIT 2 6.19 10-5 The setting of ILIMIT is obtained as: RILIMIT 1.8 ( PIN / 3) 2 RCS 4 VLINE MIN I ILIMIT 1.8 877 2 0.03 4 27.3k 160 6.13 10-5 A 27 kΩ resistor is selected for ILIMIT. www.fairchildsemi.com 5 AN-4164 [STEP-8] LS & GC Design The transfer function of the compensation circuit is given as: s vIEA 2 f II 2 f IZ s vCS s 1 2 f IP where: 1 IL tON Figure 10. f II tOFF The Linear Predict (LPT) function, shown in Figure 10, is used to anticipate the behavior of inductor current in the switch turn-off region. The Gain Change (GC) pin and LS pin are used to adjust the parameters of LPT function. The resistance can be determined by the following equation. RLS LPFC R RFB 2 RFB 3 1.5 10-9 RCS FB1 RFB 3 vCS vIEA RIAC (21) RFB1 RFB 2 RFB3 RFB3 6 106 3.7 10 23.7 10 23.7 103 6 3 RCS VPFC VRAMP 2 f IC LPFC (26) 1 GMI vCS vIEA (27) @ f f IC (c) Since the control-to-output transfer function of the power stage has -20 dB/dec slope and -90o phase at the crossover frequency of 0 dB, as shown in Figure 11, it is necessary to place the zero of the compensation network (fIZ) around on third (1/3) of the crossover frequency so that more than 45 phase margin is obtained. Then the capacitor CIC1 is determined as: L R RFB 2 RFB 3 1.5 10-9 RCS FB1 RFB 3 -6 220 10 31.1k 3.7 106 23.7 103 -9 1.5 10 0.03 23.7 103 @ f f IC RIC RLS 6 106 (b) Calculate RIC such that it makes the closed loop gain unity at crossover frequency: (Design Example) Inductance of 220 μH is selected. RLS and RGC are obtained as: RGC 2 RIC CIC 2 (a) Determine the crossover frequency (fIC) around 1/10th~1/6th of the switching frequency. Then calculate the gain of the transfer function of Equation (26) at crossover frequency as: (20) RFB1 RFB 2 RFB 3 RFB 3 (25) 1 The procedure to design the feedback loop is as follows: Gain change is to use to adjust the output of the gain modulation. The resistor value is given by: RGC GMI 1 , f IZ and 2 CIC1 2 RIC CIC1 f IP LPT Function for Inductor Current at tOFF (24) CIC1 38.19k RLS and RGC are 33 kΩ and 38.2 kΩ used. 60dB 1 RIC 2 f IC / 3 (28) Control-to-output Closed Loop Gain 40dB Compensation 20dB [STEP-9] PFC Current Loop Design fIP The transfer function that relates the duty cycle to the inductor current of boost power stage is given as: 0dB fIZ fIC -20dB iL VPFC d sLPFC (22) -40dB 10Hz The transfer function relating the output of the current control error amplifier to the inductor current-sensing voltage is obtained by: vCS1 RCS VPFC vIEA VRAMP sLPFC Figure 11. 1kHz 10kHz 100kHz 1MHz Current Loop Compensation (d) Place compensator high-frequency pole (fCP) at least a decade higher than fIC to ensure that it does not interfere with the phase margin of the current loop at its crossover frequency. (23) CIC 2 where VRAMP is the peak-to-peak voltage of the ramp signal for the current-control PWM comparator, which is 3.8 V. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 100Hz 1 2 f IP RIC (29) www.fairchildsemi.com 6 AN-4164 (Design Example) Set crossover frequency as 4 kHz: vCS vIEA RCS VPFC VRAMP 2 f IC LPFC 0.03 393 0.426 (6.5-1.5) 2 4 103 220 106 @ f f IC RIC 1 vCS GMI vIEA RIC 2 f IC / 3 CIC 2 vˆCOMP vˆPFC fVI 1 2 f IP RIC fVP 1 4.49nF 3 26.6 10 2 4 103 / 3 1 0.15nF 2 4 10 26.6 103 [STEP-10] PFC Voltage Loop Design Since FAN9673 employs line feed-forward, the power stage transfer function becomes independent of the line voltage. Then, the low-frequency, small-signal, control-tooutput transfer function is obtained as: 1 sCOUT (30) 1 sCOUT (31) GMV 2.5 1 , fVZ VOUT 2 CVC1 2 RVC CVC1 and 1 (33) 2 RVC CVC 2 (a) Determine the crossover frequency (fVC) around 1/10~1/5 of the line frequency. Since the control-tooutput transfer function of power stage has -20 dB/dec slope and -90o phase at the crossover frequency, shown in Figure 12 as 0 dB; it is necessary to place the zero of the compensation network (fVZ) around the crossover frequency so that 45 phase margin is obtained. Then, the capacitor CVC1 is determined as: 4 (32) The procedure to design the feedback loop is as follows: Modify the DC gain and BW of current loop, use 17.4 kΩ for RIC, 2.2nF for CIC1, and 100 pF for CIC2. vˆPFC I OUT TOT K MAX vˆVEA 5 where: vˆPFC I OUT TOT K MAX vˆVEA 5 s 2 fVI 2 fVZ s s 1 2 fVP 1 where: 1 26.6k 88 106 0.426 @ f f IC 1 CIC1 The transfer function of the compensation network is obtained as: CVC1 GMV I OUT TOT K MAX 2.5 5 COUT (2 fVC )2 VPFC (34) To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: RVC 1 (35) 2 fVC CVC1 (b) Place compensator high-frequency pole (fVP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter so noise can be effectively attenuated. Then, the capacitor CVC2 is determined as: 60dB Closed-Loop Gain 40dB Control-to-Output CVC 2 20dB 1 2 fVP RVC (36) fc 0dB (Design Example) Set the crossover frequency as 20 Hz: -20dB CVC1 Compensation -40dB 1Hz Figure 12. 10Hz 100Hz 1kHz 10kHz Voltage Loop Compensation Proportional and integration (PI) control with highfrequency pole typically used for compensation. The compensation zero (fVZ) introduces phase boost, while the high-frequency compensation pole S(fVP) attenuates the switching ripple, as shown in Figure 12. RVC GMV I OUT -TOT K MAX 2.5 5 COUT (2 fVC ) 2 VPFC 70 106 6.36 1.3 2.5 40nF 5 1170 106 (2 20) 2 393 1 1 196k 2 fVC CVC1 2 20 40.5 109 CVC 2 1 1 8.12nF 2 fVP RVC 2 100 196 103 Modify the DC gain and BW of voltage loop; using 75 kΩ for RVC, 1 F for CVC1, and 0.1 F for CVC2. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 www.fairchildsemi.com 7 AN-4164 [STEP-11] Channel Management Control PO Figure 13 shows the CM pin control with an external voltage signal. The VVEA control voltage is generated by regulation error amplifier and is proportional to average current of input. When VCM is pulled LOW to 0 V, the PFC channel is enabled. When the VCM is pulled HIGH and over 4 V, the channel is disabled. Figure 14 shows that channel 3 is disabled by an external signal when the system is operating at half-load condition. VS 4V VCM Direct VAC IL1 IL2 VO V (V) 6 4V VCM Indirect VCVM-LIMIT (4V) VCVM VAC IL1 VVEA IL2 VO 0 100 Figure 16. Channel Management by MCU VAC IL [STEP-12] Soft Start Figure 13. Figure 17 shows the soft start (SS) waveform. FAN9673 uses soft-start voltage, VSS, to clamp the PFC power command of voltage loop VVEA. To increase the soft-start time, the value of the soft-start capacitance CSS can be increased. Channel Management by MCU Full load, all channel operation IL3 IL2 CSS IL1 I SS tSS VSS (37) Mid. load, disable channel 3 by external signal (Design Example) Assuming that VVEA is out of clamping by VSS at 5 V, the design soft-start time tSS is 50 ms and ISS is 20 μA. The required soft-start capacitor value is: IL3 IL2 120˚à 180˚ IL1 0˚ 120˚ Figure 14. 240˚ CSS Phase Change of External Signal Control The Figure 16 shows an external circuit used to change the slope of VCM2/3. When VCM2/3 is between 4 V ~ 0 V, changing the slope of VCM2/3 can increase / decrease the loading of the channel and decrease the overshoot/undershoot of the PFC output voltage, as the Figure 15 shows. This method significantly improves the dynamic load performance of the PFC converter. I SS t SS 20 106 100 103 0.4 F VSS 5 0.47 F is selected for CSS. VAC IL VREF CM2 /3 VFBPFC PFC Soft Start VSS R=5k~10kΩ VVEA C=470pF Figure 17. Soft-Start Waveform VCM2 /3 Figure 15. Channel Management by MCU © 2013 Fairchild Semiconductor Corporation Rev. 1.2 www.fairchildsemi.com 8 AN-4164 Table 2. AC Input Range with Controller Setting [STEP-13] RLPK Setting The relationship of VIN.PK to VLPK is shown in Figure 18. The peak-detection circuits identify the VIN information from the IAC current through a ratio (the relationship shown in Equation (42). Caution: the maximum VLPK can’t be over 3.8 V when system operation at maximum AC input. Input Range AC (V) Full-Range 85~ 264 10 kΩ 6 MΩ AC 85 V/75 V HV-Single 180~264 470 kΩ 12 MΩ AC 170 V/160 V As with the below design example, assume the maximum VIN.PK at 373 V (AC264V). The relationship of VIN.PK / VLPK is 100, then calculate the VLPK = 3.73 V < 3.8 V. The FAN9673 senses the RMS value and the instantaneous value of the line voltage using the BIBO pins as shown in Figure 19. The RMS value of the line voltage is obtained by an averaging circuit using a low-pass filter with two poles. VLPK VIN .PK RRLPK 100 12.4k The RMS sensing circuit should be designed considering the nominal operation range of line voltage and brownout protection trip point as: (38) VIN VBO VLINE .BO RIAC When VAC is full range input (universal input), the brownout / in thresholds VBO and VBI are 1.05 V (VBIBO-FL) and 1.9 V (VBIBO-FL+∆VBIBO-F). But if the VAC is high voltage single range input (AC 180 V~264 V), the brownout/in thresholds of VBO and VBI should be 1.05 V (VBIBO-HL) and 1.75 V (VBIBO-HL+∆VBIBO-H). Ratio RRLPK LPK Peak Detector It is typical to set RRMS2 as 10% of RRMS1. The poles of the low-pass filter are given as: Relationship of VIN.PK to VLPK (Design Example) Assuming the VLPK is 3.73 V when VIN.PK is 373 V, (AC264V) : RRLPK 12.4k VLPK 100 12.4k VIN .PK [STEP-14] Line Sensing for Brown-In / Out The FAN9673 has an internal AC UVP comparator that monitors the AC input voltage and disables PFC stage when the VBIBO is less than 1.05 V for 450 ms. If the VBIBO voltage is over 1.9 V/1.75 V, the PFC stage enables. The VIR pin is used to set the AC input range, as shown in Table 2. VIN VRMS RB1+2 (41) fP2 1 2 CB 2 RB 4 (42) The resistors of the voltage divider network are selected as RB1= RB2=1 M, RB3=200 k, and RB4=16.2 k. To place the poles of the low-pass filter at 15 Hz and 22 Hz, the capacitors are obtained as: 1 1 CB1 53nF 2 f P1 RB 3 2 15 200 103 120/100Hz VIN PFC Stop RB3 BIBO RB4 fp1 Figure 19. 1 2 CB1 RB 3 VLINE.MIN 2 RB 4 170 2 7.289m 1.752 1.75V RB1 2 RB 3 RB 4 PFC Action CB2 f P1 To properly attenuate the twice line frequency ripple in VRMS, it is typical to set the poles around 10~20 Hz. (Design Example) The brownout protection thresholds are 1.05 V (VBIBO-HL) and 1.75 V (VBIBOHL+∆VBIBO-H) respectively. The scaling down factor of the voltage divider is: V RB 4 BIBO HL RB1 2 RB 3 RB 4 VLINE .BO 2 2 1.05 7.289m 160 2 2 The startup of the PFC controller at the minimum line voltage is checked as: 12.1 k is selected for RRLPK. CB1 (39) 2 RB 4 (40) RB1 2 RB 3 RB 4 where VBO and VBI are brownout/in thresholds of VRMS. RLPK Figure 18. 2 RB 4 2 RB1 2 RB 3 RB 4 VBI VLINE.MIN IAC VLPK RVIR RIAC Brown-In/Out Setting Setting Level fp2 CB 2 Brown-In / Out Circuits © 2013 Fairchild Semiconductor Corporation Rev. 1.2 1 2 f P 2 RB 4 1 447nF 2 22 16.2 103 www.fairchildsemi.com 9 AN-4164 Design Summary Application Output Power Input Voltage Output Voltage / Output Current Single-Stage Three-Channel PFC 2500 W 180~264 VAC 393 V/6.36 A Features AC180V~264 V, Three-Channel PFC Using FAN9673 Switch-Charge Technique of Gain Modulator for Better PF and Lower THD 40 kHz Low Switching Frequency Operation with IGBT Protections: Over-Voltage Protection (OVP), Under-Voltage Protection (UVP), and Over-Current Protection (ILIMIT), Inductor Saturation Protection (ILIMIT2) * DBP 1N5406 RB1 CB 1µF LPFC1 220µH DPFC1 FFH15S60STU LPFC2 220µH DPFC2 FFH15S60STU LPFC3 220µH DPFC3 FFH15S60STU VPFC RFB1 2.2MΩ SPFC1~3 FGH20N60UFD RB1 1MΩ RFB2 1.5MΩ RA1 6MΩ VDD RB2 1MΩ COUT 1170μF VDD VDD RA2 6MΩ Rsen1 30mΩ CFB 470pF Rsen3 30mΩ Rsen2 30mΩ RFB3 23.7kΩ RF1~2 470Ω CF1 1nF CF2 2.2nF RB3 200kΩ OPFC1 CS1- CS1+ OPFC2 CS2- CS2+ OPFC3 CS3- CS3+ IAC FBPFC BIBO CB1 47nF CB2 0.47μF RB4 16.2kΩ CVC2 100nF VEA SS RVC1 75kΩ CSS 0.47µF RLPK IEA1 CRLPK 10nF CVC1 1µF CIC12 100pF RIC11 17.4kΩ CIC11 2.2nF RLPK 12.1kΩ FAN9673 LS CLS 330pF IEA2 CIC122 100pF RIC21 17.4kΩ CIC21 2.2nF RLS 33kΩ IEA3 GC CGC 330pF CIC32 100pF RIC31 17.4kΩ CIC31 2.2nF RGC 38.2kΩ VDD ILIMIT2 CVDD 22μF CILIMIT2 10nF RILIMIT2 10kΩ VIR LPK CLPK 0.1µF RLPK 4.7kΩ CVIR 1nF RVIR 470kΩ CM1 CM2 CM3 DC Setting Level Figure 20. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 Standby Power PVO GND MCU signal (DC) RDY MCU/ Sec. Stage (PFC Ready) RI ILIMIT RRI CILIMIT RILIMIT 20kΩ 10nF 27kΩ Final Schematic of Design Example www.fairchildsemi.com 10 AN-4164 Appendix A Table 3. Parameters of FAN9673 Evaluation Board VDD Maximum Rating 20 V VDD OVP 24 V VCC UVLO 10.3 V/12.8 V PVO 0 V~1 V PFC Soft-Start CSS = 0.47 µF Brown-In/Out 170 V/160 V Gate Clamp 2.4 V/1.55 V (96%/62%) VDD Maximum Rating 20 V Table 4. MOSFET and Diode Reference Specification IGBTs Voltage Rating 600 V (IGBT) FGH20N60UFD Boost Diodes 600 V FFH15S60STU System Design Precautions Pay attention to the inrush current when AC input is first connected to the boost PFC convertor. It is recommended to use NTC and a parallel connected relay circuit to reduce inrush current. Add bypass diode DBP to provide a path for inrush current when PFC starts up. The PFC stage is normally used to provide power to a downstream DC-DC or inverter. It’s recommend that downstream power stage is enabled to operate at full load once the PFC output voltage has reaches a level close to the specified steady-state value. The PVO function is used to change the output voltage of PFC, VPFC. The VPFC should be kept at least 25 V higher than VIN. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 www.fairchildsemi.com 11 AN-4164 Layout Guide The current-sense resistor and current-sense filter (CF1, CF2) should be as close to the CS+/CS- pins as possible. Similar to other power management devices, when laying out the PCB, it is important to use star grounding techniques and to keep the filter capacitor and control components as close to the controller IC and its GND pin as possible. Keep high-current output and power ground paths separate from the signal ground path. Make a singlepoint connection from signal ground to the power ground. Connect the FAN9673’s GND to the power ground at the negative terminal of COUT. The ground of power stage and controller stage only meet at the negative terminal of the output capacitor, COUT. The return path for the gate drive current should be connected to the power ground. Minimize the ground loops between the driver outputs, totem-pole buffer transistors, power switches, and power ground. Keep the controller as close to the switching devices as possible to minimize the length and loop inductance of the high-current gate driving traces. To minimize the possibility of interference caused by magnetic coupling from the boost inductor, the device should be located at least 2.5 cm (1 inch) away from the boost inductor. It is also recommended that the device not be placed underneath magnetic components. Keep the width of PCB track handling the gate drive current to the switching devices wide to handle the high peak current level. DBP LPFC1 RB1 CB DPFC1 LPFC2 DPFC2 LPFC3 DPFC3 RFB1 1 SPFC1~3 RB1 VPFC COUT RFB2 RA1 5 VDD RB2 VDD VDD RA2 Rsen1 CFB Rsen3 Rsen2 RFB3 CF1 CF2 RB3 OPFC1 CS1- CS1+ OPFC2 CS2- CS2+ OPFC3 CS3- CS3+ IAC CB1 CB2 RB4 MCU (Input Information) FBPFC BIBO CVC2 VEA RVC1 CVC1 LPK CLPK CRLPK CIC12 IEA1 RLPK RLPK CIC11 CIC122 FAN9673 SS RIC11 IEA2 RIC21 CIC21 CSS LS IEA3 CLS CIC32 RIC31 CIC31 RLS VDD GC CGC CVDD 2 RGC ILIMIT VDD VIR CVIR CILIMIT RVIR RILIMIT CM1 CM2 CM3 PVO GND RDY RI RRI DC Setting Level MCU signal (DC) 3 Figure 21. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 OPP ROPP MCU/ Sec. Stage (PFC Ready) 4 Layout Diagram www.fairchildsemi.com 12 AN-4164 Related Datasheets FAN9673 — Three Channels Interleaved CCM PFC Controller FEBFAN9673_B01H5000A —User Guide for FEBFAN9673_B01H5000A FAN9612 — Interleaved Dual BCM PFC Controller AN-6086 — Design Consideration for Interleaved Boundary Conduction Mode (BCM) PFC Using FAN9612 FAN6982 — CCM Power Factor Correction Controller AN-8027 — FAN480X PFC+PWM Combo Controller Application DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 13