RT5014 - Richtek

®
RT5014
7+6 Channels Power Management IC for DSC
General Description
The RT5014 is a complete power supply solution for digital
still cameras and other hand held devices. The RT5014 is
a multi-channel DC/DC power management unit including
one synchronous step-up DC/DC converter with load
disconnect (CH1), one selectable synchronous step-up/
step-down DC/DC converter (CH2), two synchronous stepdown DC/DC converters (CH3/4), one synchronous high
voltage step-up DC/DC converter (CH5), one asynchronous
inverting DC/DC converter (CH6) and one WLED driver in
synchronous high voltage step-up mode or current
regulator mode (CH7). Besides, the RT5014 also includes
six LDO regulators: one RTC_LDO, one High Voltage LDO
for CCD+ bias power (CH8), one high PSRR LDO for AFE
power (CH9), and three generic LDOs (CH10 to CH12).
All P-MOSFETs are integrated and all frequency
compensation network needed by DC/DC converters are
built-in. RT5014 uses one sequence selection pin SEQ
to select five preset sequences and uses I2C control
interface to enable channels and adjust CH1/5/6/8/9/10/
11/12 output voltage level and WLED dimming ratio and
OVP threshold. RT5014 also includes a system reset
function to monitor battery voltage.
The RT5014 is designed to fulfill the applications for DSC
as follows : CH1 is a synchronous step-up output for motor
power. CH2 is a selectable synchronous step-up/step-
down output for system I/O power. The operation mode is
auto-selected by detecting external components topology.
CH3 and CH4 are synchronous step-down outputs for DSP
core and memory power supply. CH5 and CH8 HVLDO
are for CCD+ bias power supply. CH6 is an asynchronous
inverting output for negative CCD− bias power supply. CH7
is a WLED driver, auto-selected to be in synchronous high
voltage step-up mode or current regulator mode.
Besides switching converters, RT5014 has some LDO
regulators : CH9 is a LDO for AFE power. CH10 is 3.1V
LDO for system, enabled in the preset power sequence.
CH11 is a LDO enabled via I2C i/f for memory card and
supports Dynamic Voltage Scaling function. CH12 is a
LDO for memory card or PLL. CH10 default voltage and
enabling are controlled in power sequence selected by
pin SEQ. And one keep-alive 3.3V LDO for RTC power
supply.
The RT5014 provides over current protection, thermal
shutdown protection, over voltage protection, over load
protection and under voltage protection to achieve complete
protection.
The RT5014 is available in the WQFN-40L 5x5 package.
Simplified Application Circuit
Battery
Chip Enable
2
I C Control
RT5014
VOUT1
LX2
LX3
LX4
EN
PVD5
VOUT6
PVD7
SCL
LDOH
VOA
SDA
VOD1
VOD2
VOM
GND
VRTC
BAT
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
Step-Up For Motor
Step-Up/Down for I/O
Step-Down for Core
Step-Down for DDR III
HV Step-Up for CCD
HV Inverting for CCD
Step-Up for LED Backlight
HV LDO
LDO for AFE
LDO for System
LDO with DVS
LDO for Digital
LDO for RTC
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT5014
Features
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Input Voltage 1.8V to 5.5V
7-CH DC/DC Converters
6-CH Linear Regulator
` One HVLDO, 4 LVLDO (for Memory Card, PLL,
AFE, SYS), One RTC-LDO
All Power Switches Integrated
All Step-Up Converters with Load Disconnect
Function
All DC/DC Converters with Internal Frequency
Compensation
All DC/DC Converters with Pulse Skip Mode
Function
Fixed 2MHz Operating Frequency for CH1/2/3/4
(Motor, SYS, CORE, MEM)
Fixed 1MHz Operating Frequency for CH5/6/7
(CCD+, CCD−
−, WLED)
CH2 Sync. Step-Up/Step-Down Auto-Selected by
External Topology
CH7 WLED Driver in Synchronous Step-Up or Current
Regulator Auto-Selected by External Topology
` 32 Steps Brightness Control for WLED Driver
2
` 3 Step-Up OVP Thresholds Selected in I C Register
Five Built-in Power On/Off Sequence for CH1/2/3/
4/10/ (9, 11, 12)
Built-in Soft-Start Function
I2C Control Interface : Support Fast Mode up to
400Kb/s
CH1/5/6/8 with Built-in Feedback Resistors and
Programmable Output Voltage Levels
` CH6 can Choose External Feedback Path
` CH1 Supports Dynamic Voltage Scaling
CH10 LDO Output Voltage Programmable by I2C
` Default Voltage Preset in Power Sequence
CH11 LDO Output Voltage Programmable by I2C
2
` Enabled by I C
` Supports Dynamic Voltage Scaling
Rich Protection Functions :
` Under Voltage Protection (UVP) (That is, Short
Circuit Protection)
` Over Load Protection (OLP)
` Over Voltage Protection (OVP)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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2
Over Current Protection (OCP)
` Over Temperature Protection (OTP)
` VDDM and Battery UVLO Function
` Battery OVP Function
μA
Low Power Consumption (Sleep Mode) <20μ
Built-in System Reset Function to Monitor Battery
Voltage
40-Lead WQFN 5x5 Package
RoHS Compliant and Halogen Free
`
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Applications
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CCD-Sensor DSC
CMOS-Sensor DV
Ordering Information
RT5014
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current require-
`
Suitable for use in SnPb or Pb-free soldering processes.
ments of IPC/JEDEC J-STD-020.
Marking Information
RT5014GQW : Product Number
RT5014
GQW
YMDNN
YMDNN : Date Code
is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Pin Configurations
FB2
SYSR
LX2
PVD2
VOUT6
LX6
BAT
VRTC
VOUT1
PVD1
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
FB6
VREF
VNEG
VIA
VOA
VOD1
VID
VOD2
SDA
SCL
1
30
2
29
3
28
4
27
5
26
GND
6
25
7
24
8
23
41
22
9
21
10
LX1
VIM
VOM
VDDM
LX5
PVD5
VIH
LDOH
FBH
PVD3
FB4
SEQ
LX4
PVD4
LX7
PVD7
FB7
FB3
EN
LX3
11 12 13 14 15 16 17 18 19 20
WQFN-40L 5x5
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
FB6
Feedback Input of CH6.
2
VREF
Output of CH6 Reference Voltage.
3
VNEG
Output Pin of Negative Regulator. The output voltage is regulated to BAT − 4.5V. It
provides negative rail power for CH3, CH4, and CH6 P-MOSFET Driver. It needs a
0.1μF external decoupling capacitor.
4
VIA
CH9 LDO Power Input.
5
VOA
CH9 LDO Output.
6
VOD1
CH10 LDO Output.
7
VID
LDO Power Input of CH11 and CH10.
8
VOD2
CH11 LDO Output.
9
SDA
Data Signal Pin of I C Interface.
10
SCL
Clock Signal Pin of I C Interface.
11
FB4
Feedback Input of CH4.
12
SEQ
13
LX4
Input Pin of Power Sequence Selection. The Power Sequence is based on the
external pull down resistance or voltage level at SEQ pin.
Switch Node of CH4.
14
PVD4
Power Input of CH4.
15
LX7
16
PVD7
17
FB7
Feedback Input of CH7 in Step-Up Mode and Current Source Mode.
18
FB3
Feedback Input of CH3.
19
EN
Enable Pin of CH1, CH2, CH3, CH4 and CH10. The power sequence is based an
the setting of SEQ Pin.
2
2
Switch Node of CH7 in Step-Up Mode or Current Output Port of CH7 in Current
Source Mode.
Power Output Pin of CH7 in Step-Up Mode or Power Input Port of CH7 in Current
Source Mode.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT5014
Pin No.
Pin Name
Pin Function
20
LX3
Switch Node of CH3.
21
PVD3
Power Input of CH3.
22
FBH
Feedback Input of HVLDO.
23
LDOH
Output of HVLDO.
24
VIH
Power Input of HVLDO.
25
PVD5
Power Output of CH5.
26
LX5
Switch Node of CH5.
27
VDDM
IC Analog Power Pin.
28
VOM
CH12 LDO Output.
29
VIM
CH12 LDO Power Input.
30
LX1
Switch Node of CH1.
31
PVD1
Power Output of CH1.
32
VOUT1
Feedback Input of CH1 Output Voltage.
33
VRTC
RTC-LDO Power Output.
34
BAT
Battery Sense and Power Input Pin. The BAT pin must be connected to the power
input of each converter (CH1 to CH7).
35
LX6
Switch Node of CH6.
36
VOUT6
Sense Input of CH6 Inverting Output Voltage.
37
PVD2
Power Input for Step-Down of CH2.
Power Output for Step-Up of CH2.
38
LX2
Switch Node of CH2.
39
SYSR
Push-Pull Output Pin of System Reset to Monitor the Voltage Level at Pin BAT.
40
FB2
Feedback Input of CH2.
41
GND
(Exposed Pad)
Exposed PAD Should be Soldered to PCB and Connected to GND.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Function Block Diagram
VDDM
VIH
BAT
VREF
+ DAC
+
-
UVLO & OVP
LDOH
VDDI
SS
CH8 HVLDO
PVD1
UVLO
VDDM
FBH
VDDM
PVD5
Body
Diode
Control
BAT
CH1 C-Mode
Sync. LV
Step-Up
CH5 HV
C-Mode
Sync.
Step-Up
LX5
PVD5
LX1
VOUT1
-
+
GND
VREF + DAC
VDDM
-
PVD2
+
CH2
Mode
Selector
VREF + DAC
VDDI
Body
Diode
Control
CH2 HV
C-Mode
Step-Up
or Step-Down
LX2
RTC_LDO 3.3V w/
Body Diode Control
VRTC
-
System Reset
0.8V
REF
BAT
VDDM
VDDM
SCL
SDA
I C Control Interface
(Fast Mode up to 400kb/s)
CH3 C-Mode
Step-Down
EN
SEQ
Enable Sequence Control
PVD3
2
BAT
Body
Diode
Control
FB7
VDDM
LX4
+
VREF + DAC
VDDM
CH6 HV C-Mode
Async. Inverting
FB4
0.8V
REF
VIA
VOA
CH9 LDO (for
AFE)
Regulator
VREG =
BAT – 4.5V
VNEG
PVD4
CH4 C-Mode
Step-Down
+
BAT
FB3
0.8V
REF
CH7 HV C-Mode
Sync. Step-Up +
Current Regulator
+ Mode Selector
(32 Steps
Dimming)
-
LX7
LX3
+
VDDM
PVD7
LX6
FB2
+
VRTC
VRTC
SYSR
BAT
VDDM
VID
VOD1
CH10 LDO 3.1V
VOUT6
Register File
VDDM
FB6
+
0.4
VREF
VREF
VREF + DAC
VNEG
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
Ch1/5/6/8/9/10/11/12
Output Voltage,
Enable (Ch5, CH6,
CH7, Ch8, Ch9,
CH11, Ch12)
CH7 Dim. Ratio,
CH7 OVP Threshold
CH11
LDO with DVS
VID
VOD2
VDDM
CH12
LDO (for Digital)
VIM
VOM
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT5014
Operation
The RT5014 is a complete power supply solution for digital
still cameras and other hand held devices. It includes 7
DC/DC converters, one High Voltage LDO for CCD+ bias
power, one high PSRR LDO for AFE power, three generic
LDOs, and one RTC LDO.
CH6
CH1
CH7
Step-up synchronous current mode DC/DC converter with
internal power MOSFETs and compensation network. The
P-MOSFET can be controlled to disconnect the load. It is
suitable for providing power to the motor.
WLED driver operating in either current source mode or
synchronous step-up mode with internal power MOSFET
and compensation network. The operation mode is
determined via the I2C interface.
CH2
CH8
Selectable synchronous step-up/step-down output for
system I/O power. The operation mode is auto-selected
by detecting external signals.
High voltage LDO for CCD positive bias power supply.
Asynchronous inverting current mode DC/DC converter
with internal power MOSFET and compensation network.
An external Schottky diode is required. This channel
supplies the CCD negative bias.
CH9
High PSRR LDO for AFE power.
CH3
Step-down synchronous current mode DC/DC converter
with internal power MOSFETs for DSP core power supply.
CH10
CH4
CH11
Step-down synchronous current mode DC/DC converter
with internal power MOSFETs for memory power supply.
LDO for memory card and supports Dynamic Voltage
Scaling function.
CH5
CH12
High voltage step-up synchronous current mode DC/DC
converter with internal power MOSFET and compensation
network. The P-MOSFET can be controlled to disconnect
the load.
Low input voltage LDO for memory card or PLL.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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LDO for system, enabled in the preset power sequence.
RTC LDO
Keep-alive 3.3V LDO for real-time clock.
is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Absolute Maximum Ratings
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(Note 1)
Supply Voltage, VDDM -------------------------------------------------------------------------------------- −0.3V to 6V
Switch Node Voltage, LX1, LX2, LX3, LX4 -------------------------------------------------------------- −0.3V to 6V
Switch Node Voltage, LX5, PVD5, VIH, LDOH -------------------------------------------------------- −0.3V to 24V
Switch Node Voltage, LX7, PVD7 ------------------------------------------------------------------------- −0.3V to 26V
Switch Node Voltage, VOUT6, LX6 ----------------------------------------------------------------------- (BAT − 16V) to (BAT + 0.3V)
Negative Output Voltage VNEG --------------------------------------------------------------------------- (BAT − 6V) to (BAT + 0.3V)
Other Pins ------------------------------------------------------------------------------------------------------ −0.3V to 6V
Power Dissipation, PD @ TA = 25°C
WQFN-40L 5x5 ----------------------------------------------------------------------------------------------- 3.64W
Package Thermal Resistance (Note 2)
WQFN-40L 5x5, θJA ------------------------------------------------------------------------------------------ 27.5°C/W
WQFN-40L 5x5, θJC ----------------------------------------------------------------------------------------- 6°C/W
Junction Temperature ---------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------------- −65°C to 125°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------- 2kV
MM (Machine Model) ---------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
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(Note 4)
Supply Voltage, VDDM -------------------------------------------------------------------------------------- 2.7V to 5.5V
Supply Input Voltage, BAT --------------------------------------------------------------------------------- 1.8V to 5.5V
Junction Temperature Range ------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VDDM = 3.3V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
1.5
--
--
V
--
1.4
--
V
--
0.07
--
V
5.85
6
6.15
V
--
0.25
--
V
2.2
2.4
2.6
V
--
10
20
μA
Supply Voltage
BAT Startup Voltage
VST
BAT UVLO
For bootstrap
Falling
BAT UVLO Hysteresis
VDDM Over Voltage Protection
Rising
VDDM OVP Hysteresis
VDDM UVLO
Rising
Supply Current
Shutdown Supply Current into
BAT (Include IDDQ of RTC LDO)
IOFF-BAT EN = L, and PMU off, VBAT = 3.3V
CH1 + CH2 + CH3 + CH4 Supply
IQ1234
Current into VDDM
Not Switching, VEN = 3.3V
--
--
2000
μA
CH5 Supply Current into VDDM
Not Switching, A5.EN5 = 1
--
--
500
μA
IQ5
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT5014
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
CH6 Supply Current into VDDM
IQ6
Not Switching, VBAT = 3.3V, A5.EN6 = 1
--
--
500
μA
CH7 in Step-Up Mode
Supply Current into VDDM
IQ7B
Not Switching, A5.EN7 = 1
--
--
500
μA
CH7 in Current Source Mode
Supply Current into VDDM
IQ7C
A5.EN7 = 1, VPVD7 = 5V
--
--
400
μA
1800
2000
2200 kHz
CH7 in Step-Up mode
900
1000
1100
kHz
Target voltage defined at A1.VOUT1
−1.5
--
1.5
%
--
100
--
ns
Oscillator
CH1, 2, 3, 4 Operation Frequency
FOSC
CH5, 6, 7 Operation Frequency
FOSC2
CH1 LV Sync Step-Up
Output Voltage Accuracy at VOUT1
Minimum On-Time for PSM
Soft-Start Time
VVOUT1 = 0 to 5V
--
4
--
ms
Maximum Duty Cycle (Step-Up)
VOUT1 < Target defined in A1.VOUT1
80
83
86
%
P-MOSFET, VPVD1 = 3.3V
--
200
300
N-MOSFET, VPVD1 = 3.3V
--
150
250
Current Limit (Step-Up)
2.2
3
4
Over Voltage Protection at PVD1
5.82
On-Resistance of MOSFET
RDS(ON)
Under Voltage protection at PVD1
Under Voltage protection at VOUT1
Over Load protection at VOUT1
Target Voltage is defined in A1.VOUT1
Off Discharge Current at PVD1
VPVD1 = 5V, VVDDM = 3.3V
Discharge Finishing Threshold at
VOUT1
6
6.18
BAT
--− 0.8
1.95 2.25 2.55
Target
--− 0.6
-50
--
mΩ
A
V
V
V
V
mA
--
0.6
--
V
0.788
0.8
0.812
V
--
100
--
ns
VFB2 = 0 to 0.8V
--
4
--
ms
VFB2 = 0.75V (Step-Up)
80
83
86
VFB2 = 0.75V (Step-Down)
--
--
100
P-MOSFET, VPVD2 = 3.3V
--
200
300
N-MOSFET, VPVD2 = 3.3V
--
150
250
(Step-Down)
1.2
1.6
2
(Step-Up)
2.2
3
4
Over Voltage Protection at PVD2
CH2 Step-Up only
5.82
6.18
V
Under Voltage Protection at PVD2
CH2 Step-Up only
--
--
V
0.35
V
CH2 LV Sync Step-Up or Step-Down Selectable
Feedback Regulation Voltage at
FB2
Minimum On-Time for PSM
Soft-Start Time
Maximum Duty Cycle
On-Resistance of MOSFET
Current Limit
RDS(ON)
%
mΩ
A
Under Voltage Protection at FB2
0.25
6
BAT
− 0.8
0.3
Over Load Protection at FB2
0.65
0.7
0.75
V
--
50
--
mA
Off Discharge Current at PVD2
VPVD2 = 3.3V, VVDDM = 3.3V (Step-Up)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Parameter
Symbol
Off Discharge Current at LX2
Discharge Finishing
Threshold at FB2
CH3 LV Sync Step-Down
Feedback Regulation Voltage
at FB3
Minimum On-Time for PSM
Test Conditions
Min
Typ
Max
Unit
VLX2 = 3.3V, VVDDM = 3.3V
(Step-Down)
--
50
--
mA
Both Step-Up and Step-Down
--
0.1
--
V
0.788
0.8
0.812
V
--
50
--
ns
Maximum Duty Cycle
VFB3 = 0.75V
--
--
100
%
Soft-Start Time
VFB3 = 0 to 0.8V
--
4
--
ms
P-MOSFET, VPVD3 = 3.3V
--
250
400
N-MOSFET, VPVD3 = 3.3V
--
150
250
1.5
2
2.5
A
0.35
0.4
0.45
V
0.65
0.7
0.75
V
--
20
--
mA
--
0.1
--
V
0.788
0.8
0.812
V
--
50
--
ns
On-Resistance of MOSFET
RDS(ON)
Current Limit
Under Voltage Protection at
FB3
Over Load Protection at FB3
mΩ
Off Discharge Current at LX3
Discharge Finishing
Threshold at FB3
CH4 LV Sync Step-Down
Feedback Regulation Voltage
at FB4
Minimum On-Time for PSM
VLX3 = 1V, VVDDM = 3.3V
Maximum Duty Cycle
VFB4 = 0.75V
--
--
100
%
Soft-Start Time
VFB4 = 0 to 0.8V
--
4
--
ms
P-MOSFET, VPVD4 = 3.3V
--
250
400
N-MOSFET, VPVD4 = 3.3V
--
250
400
1.2
1.6
2
A
0.35
0.4
0.45
V
0.65
0.7
0.75
V
--
30
--
mA
--
0.1
--
V
On-Resistance of MOSFET
RDS(ON)
Current Limit
Under Voltage Protection at
FB4
Over Load Protection at FB4
Off Discharge Current at LX4
Discharge Finishing
Threshold at FB4
CH5 HV Sync Step-Up
Dropout Voltage Accuracy at
(PVD5 − LDOH)
VLX4 = 1.8V, VVDDM = 3.3V
Target voltage defined at
A2.DV5 = 4’b0000 to 4’b0111
Target voltage defined at
A2.DV5 = 4’b1000 to 4’b1111
Minimum On-Time for PSM
Target
− 0.15
Target
− 0.25
--
mΩ
300
Target
+ 0.15
Target
+ 0.25
--
ns
Target
Target
V
Maximum Duty Cycle
VIH < Target
91
93
97
%
Soft-Start Time
VVIH = 0 to 14V
--
10
--
ms
P-MOSFET, VPVD5 = 10V
--
1.2
1.5
N-MOSFET, VVDDM = 3.3V
--
0.6
0.8
Ω
On-Resistance of MOSFET
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
9
RT5014
Parameter
Current Limit
Symbol
Test Conditions
N-MOSFET
Over Voltage Protection at PVD5
Under Voltage Protection at
PVD5
Target voltage defined at A2.DV5
+ A2.LDOH
Over Load Protection at PVD5
Target voltage defined at A2.DV5
+ A2.LDOH ≠ 4’b0000
Target voltage defined at A2.DV5
+ A2.LDOH = 4’b0000
Off Discharge Current at PVD5
VPVD5 = 14V, VVDDM = 3.3V
Discharge Finishing Threshold
at PVD5
Min
Typ
Max
Unit
0.9
1.2
1.6
A
20
22
24
V
--
V
----
DV5 +
LDOH x
0.5
Target
−2
Target
−1
-V
--
--
20
--
mA
--
0.5
--
V
3.3
--
24
V
--
--
200
μA
--
10
--
ms
--
--
0.2
V
−1.5
--
1.5
%
--
Target x
0.5
--
V
100
150
200
mA
CH8 High Voltage LDO
Input Voltage Range (VIH)
Soft-Start Time
VVIH = 14V, VLDOH = 13V,
IOUT = 0mA
VLDOH = 0 to 13V
Dropout Voltage (VIH − LDOH)
IOUT = 30mA
Output Voltage Accuracy at
LDOH
Under Voltage Protection at
LDOH
Target voltage defined at
A2.LDOH
VDDM = 3.3V, Target voltage
defined at A2.LDOH
Quiescent Current into VIH
Current Limit
PSRR+
IOUT = 20mA, VVIH = 14V,
VLDOH = 13V, at 1kHz
--
−50
--
dB
Off Discharge Current at LDOH
VVDDM = 3.3V
--
--
20
mA
--
0.5
--
V
Target voltage defined at
A1.VOUT6 [2:0] ≠ 3’b111
−1.5
--
1.5
%
A1.VOUT6 [2:0] = 3’b111
0.828
0.84
0.852
V
0.38
0.4
0.42
V
--
--
10
mV
4.1
4.5
4.9
V
--
300
--
ns
Discharge Finishing Threshold
at LDOH
CH6 HV Async Inverting
Output Voltage Accuracy at
VOUT6
(VREF − FB6) Regulation
Voltage
Feedback Regulation Voltage at
FB6
VREF Load Regulation
0μA < IREF < 200μA
(BAT − VNEG) Regulation
Voltage of Negative Regulator
VBAT = 3.3V
Minimum On-Time for PSM
Maximum Duty Cycle
VFB6 = 0.3V
91
93
97
%
Soft-Start Time
VOUT6 = 0 to −7V
--
10
--
ms
On-Resistance of MOSFET
P-MOSFET, VBAT = 3.3V
--
0.5
0.7
Ω
Current Limit
P-MOSFET
1
1.5
2
A
--
−13
--
V
Over Voltage Protection at
VOUT6
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.7
0.8
0.9
V
--
0.55
--
V
--
20
--
mA
--
−0.12
--
V
0.237
0.25
0.263
V
--
300
--
ns
VFB7 = 0.15V
91
93
97
%
P-MOSFET, V PVD7 = 10V
--
2
3
N-MOSFET, VVDDM = 3.3V
--
0.9
1.1
Ω
N-MOSFET, VVDDM = 3.3V
0.6
0.8
1
A0.OVP7 [1:0] = 2’b00
8.3
9
10
A0.OVP7 [1:0] = 2’b01
14.2
15
16
A0.OVP7 [1:0] = 2’b1X
24.5
25.5
26.5
VPVD7 = 10V, V VDDM = 3.3V
--
20
--
mA
(Step-Up Mode)
--
BAT
− 0.2
--
V
2.7
--
5.5
V
--
--
75
μA
3.054
3.1
3.146
V
--
--
0.1
V
--
--
10
mV
--
−60
--
dB
--
Target
x 0.5
--
V
400
550
700
mA
--
--
10
mA
2.7
--
5.5
V
--
--
75
μA
A3.VOA [2:0] = 3’b000 to 3’b011
−1.5
--
1.5
A3.VOA [2:0] = 3’b100 to 3’b111
−2
--
2
Dropout Voltage (VID − VOD1)
IOUT = 100mA, V VOD1 = 3.1V
--
--
0.1
V
PSRR+
IOUT = 10mA, VVID = 3.3V at 1kHz
--
−40
--
dB
Under Voltage Protection at FB6
Over Load Protection at FB6
Off Discharge Current at VOUT6
Discharge Finishing Threshold at
VOUT6
CH7 WLED Driver
Feedback Regulation Voltage at FB7
(Both Step-Up and Current)
Minimum On-Time for PSM (Step-Up)
Maximum Duty Cycle (Step-Up
Mode)
On-Resistance of MOSFET
Current Limit (Step-Up Mode)
Over Voltage Protection at PVD7
(Step-Up Mode)
Off Discharge Current at PVD7
(Step-Up Mode)
Discharge Finishing Threshold at
PVD7
CH9 LDO
VOUT6 = −7V
A0.DIM7 [4:0] = 5’b11111
Input Voltage Range (VIA)
Quiescent Current into VIA
Regulation Voltage VOA
Dropout Voltage (VIA − VOA)
Load Transient Output Voltage drop
at VOA
PSRR+
VVIA = 3.3V, IOUT = 0mA
VVIA = 3.3V, IOUT = 0mA,
A3.VOA [2:0] = 3’b001
IOUT = 100mA, V VOA = 3.1V
VVOA = 3.1V, Load current step
from 10mA to 100mA, COUT = 1μF
IOUT = 10mA, VVIA = 3.3V,
VVOA = 3.1V at 1kHz
Under Voltage Protection at VOA
Target voltage defined at A3.VOA
Maximum Output Current
(Current Limit)
VVIA = 3.3V, V VOA = 3.1V
Off Discharge Current at VOA
VVDDM = 3.3V
A
V
CH10 LDO
Input Voltage Range (VID)
Quiescent Current into VID
Regulation Voltage VOA
VVID = 3.3V, IOUT = 0mA
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
%
is a registered trademark of Richtek Technology Corporation.
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11
RT5014
Parameter
Under Voltage Protection at
VOD1
Maximum Output Current
(Current Limit)
Off Discharge Current at VOD1
Symbol
Test Conditions
Min
Typ
Target
x 0.5
Max
Unit
Target voltage defined at A4.VOD1
--
--
V
400
550
700
mA
--
--
10
mA
2.7
--
5.5
V
--
--
75
μA
A4.VOD2 [2:0] = 3’b000 to 3’b011
−1.5
--
1.5
A4.VOD2 [2:0] = 3’b100 to 3’b111
−2
--
2
IOUT = 100mA, VVOD2 = 3.1V
IOUT = 10mA, VVID = 3.3V,
V VOD2 = 3.1V at 1kHz
--
--
0.06
V
--
−40
--
dB
--
Target
x 0.5
--
V
400
550
700
mA
--
--
10
mA
1.5
--
5.5
V
--
--
75
μA
V VID = 3.3V
V VDDM = 3.3V
CH11 LDO
Input Voltage Range (VID)
Quiescent Current into VID
V VID = 3.3V, IOUT = 0mA
Regulation Voltage VOD2
Dropout Voltage (VID − VOD2)
PSRR+
Under Voltage Protection at
VOD2
Maximum Output Current
(Current Limit)
Off Discharge Current at VOD2
Target voltage defined at A4.VOD2
V VID = 3.3V, VVOD2 = 3.1V
V VDDM = 3.3V
%
CH12 LDO
Input Voltage Range (VIM)
Quiescent Current into VIM
V VIM = 3.3V, IOUT = 0mA
A3.VOM [2:0] = 3’b000 to 3’b011
−1.5
--
1.5
A3.VOM [2:0] = 3’b100 to 3’b111
−2
--
2
IOUT = 100mA, VVOM = 3.1V
IOUT = 10mA, VVIM = 3.3V,
V VOM = 3.1V, at 1kHz
--
--
0.06
V
--
−40
--
dB
--
Target
x 0.5
--
V
400
550
700
mA
V VDDM = 3.3V
--
--
10
mA
V BAT = 4.2V
--
3
6
μA
--
--
1
μA
3.24
3.3
3.36
V
V BAT = 4.2V
60
130
200
mA
IOUT = 50mA
--
--
1000
IOUT = 10mA
--
--
150
IOUT = 3mA
--
--
60
EN Input High Level Threshold
1.3
--
--
V
EN Input Low Level Threshold
--
--
0.4
V
Regulation Voltage VOM
Dropout Voltage (VIM − VOM)
PSRR+
Under Voltage Protection at
VOM
Maximum Output Current
(Current Limit)
Off Discharge Current at VOM
Target voltage defined at A4.VOM
V VIM = 3.3V, V VOM = 3.1V
%
RTC LDO
Standby Quiescent Current
Lockout Current into VRTC
Regulation Voltage at VRTC
Maximum Output Current
(Current Limit)
Dropout Voltage at
(BAT − VRTC)
ILO-VRTC
EN = L, and PMU off, VBAT = 0V,
V RTC = 3.1V, VVDDM = 0V
IOUT = 0mA
mV
Control
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Parameter
Symbol
Min
Typ
Max
Unit
--
1
3
μA
VBAT = VVDDM = 1.8V
0.2
--
--
V
VBAT = VVDDM = 1.8V
36
40
44
kΩ
VBAT = VVDDM = 1.8V
9
10
11
kΩ
VBAT = VVDDM = 1.8V
2.25
2.5
2.75
kΩ
VBAT = VVDDM = 1.8V
--
0.63
0.69
kΩ
1.372
1.4
1.428
V
--
0.07
--
V
--
10
--
μs
-VRTC
− 0.5
0
10
--
ms
--
VRTC
V
--
0.5
V
--
100
--
ms
125
155
--
°C
--
20
--
°C
Min
Typ
Max
Unit
1.4
--
--
V
--
--
0.6
V
--
--
400
kHz
tHD,STA
0.6
--
--
μs
tLOW
1.3
--
--
μs
HIGH Period of the SCL Clock
Set-Up Time for a Repeated
START Condition
Data Hold Time
tHIGH
tSU,STA
0.6
--
--
μs
0.6
--
--
μs
tHD,DAT
0
--
0.9
μs
Data Set-Up Time
tSU,DAT
100
--
--
ns
Set-Up Time for STOP Condition tSU,STO
0.6
--
--
μs
EN Pull Down Current
SEQ Pull High Threshold for
Power Sequence #0
SEQ Pull Down Resistance for
Power Sequence #1
SEQ Pull Down Resistance for
Power Sequence #2
SEQ Pull Down Resistance for
Power Sequence #3
SEQ Pull Down Resistance for
Power Sequence #4
Test Conditions
System RESET
When VBAT < 1.4V, SYSR goes
low.
SYSR Falling Threshold at BAT
SYSR Threshold Hysteresis Gap
at BAT
BAT Deglitching Time for SYSR
SYSR Rising Delay Time
VRTC = 1.6V
VRTC = 3.3V, ISYSR = −1mA
(Source)
VRTC = 3.3V, ISYSR = 1mA (Sink)
SYSR Output High Voltage
SYSR Output Low Voltage
Protection
Protection Fault Delay
Thermal Shutdown
TSD
Thermal Shutdown Hysteresis
ΔTSD
(VDDM = 3.3V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
2
I C
SDA, SCLK Input High Level
Threshold
SDA, SCLK Input Low Level
Threshold
SCLK Clock Rate
Hold Time (Repeated) START
Condition.
After this Period, the First Clock
Pulse is Generated
LOW Period of the SCL Clock
fSCL
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT5014
Parameter
Bus Free Time between a STOP
and START Condition
Rise Time of both SDA and SCL
Signals
Fall Time of both SDA and SCL
Signals
SDA and SCL Output Low Sink
Current
Symbol
Min
Typ
Max
Unit
tBUF
1.3
--
--
μs
tR
20
--
300
ns
tF
20
--
300
ns
2
--
--
mA
IOL
Test Conditions
SDA or SCL voltage = 0.4V
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Typical Application Circuit
34
VBAT
3.4V to 4.2V
C19
10µF
V33 ≥ 3.3V
C3
4.7µF
L2
2.2µH
C4
R1
10µF 470k
C29
10pF
PVD2
VCORE
1.2V
38 LX2
40
FB2
21
C5
4.7µF
R3
232k
PVD3
18
C7
4.7µF
L4
2.2µH
C8
10µF
R5
330k
C17
10µF
C18
4.7µF
FB3
23
C16
10pF
L6
10µH
PVD4
FB4
PVD5
22
VIH
C21
1nF
C22
0.1µF
Chip Enable
3.3V
VOD1 6
3.1V for SYS
VOD2 8
3.1V for SD
VIM 29
3.3V
VOM 28
1.8V
C13
1µF
VIA 4
3.3V
C27
1µF
VOA
5
3.1V for AFE
C28
10µF
R7
SCL 10
9
SDA
PVD7 16
35
I2C Bus
D2
D3
RSEQ
SEQ 12
FBH
D4
D5
27
LX6
Bypass Cap
1µF
FB7 17
VOUT6
1
FB6
2 VREF
3 VNEG
C23
0.1µF
R8
LDOH
VDDM
36
C20
10µF x 2
System Reset
C24
1µF
D1
CCD7V
39
VRTC
Super
Cap
C11
1µF
26 LX5
C14
1µF
C15
2.2µF
C26
0.1µF
3.3V
24
CCD+
13V
33
C10
1µF
13 LX4
11
L5
10µH
C1
10µF x 2
C12
1µF
25
VBAT
Motor 5V
31
EN 19
R6
374k
14V
32
VBAT
C9
1µF
20 LX3
14
VBAT
C2
4.7µF
VID 7
R4
464k
DDRIII
1.5V or 1.8V
VRTC
SYSR
L3
2.2µH
C6
10µF
VOUT1
PVD1
R2
150k
VBAT
L1
2.2µH
RT5014
37
VBAT
LX1
BAT
30
41 (Exposed Pad)
GND
L7
10µH
15
LX7
C25
1µF
D6
D7
R9
10
VBAT
Figure 1. Typical Application Circuit for Li-ion Battery (3.4V to 4.2V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT5014
34
VBAT
1.8V to 4.2V
C19
10µF
VOUT1
38
C3
4.7µF
37
V33 ≥ 3.3V
C4
10µF x 2
R1
470k
C29
4.7pF 40
LX2
PVD1
PVD2
VRTC
FB2
R2
150k
VCORE
1.2V
SYSR
21
VBAT
C5
4.7µF
C6
10µF
DDRIII
1.5V or 1.8V
L3
2.2µH
R3
232k
PVD3
20 LX3
18
14
L4
2.2µH
R5
330k
13
11
C17
10µF
L5
10µH
C18
4.7µF
FB3
PVD4
23
C16
10pF
22
L6
10µH
C21
470pF
C22
0.1µF
System Reset
Chip Enable
V33
C9
1µF
VOD1 6
3.1V for SYS
C10
1µF
VOD2 8
3.1V for SD
VIM 29
V33
FB4
1.8V
C13
1µF
VIA 4
V33
C27
1µF
VOA
5
3.1V for AFE
C28
10µF
PVD5
VIH
R7
35
I2C Bus
C24
1µF
LDOH
D2
D3
RSEQ
SEQ 12
FBH
D4
D5
27
Bypass Cap
1µF
LX6
FB7 17
VOUT6
1 FB6
2 VREF
3 VNEG
C23
0.1µF
R8
SCL 10
9
SDA
16
PVD7
VDDM
36
C20
10µF x 2
39
VOM 28
D1
CCD7V
VRTC
Super
Cap
C26
0.1µF
LX4
26 LX5
C14
1µF
C15
2.2µF
33
3.3V
24
CCD+
13V
C1
10µF x 2
C12
1µF
25
VBAT
Motor 5V
31
VID 7
R6
374k
13.3V
32
VBAT
C11
1µF
C7
4.7µF
C8
10µF
C2
4.7µF
EN 19
R4
464k
VBAT
LX1
L1
2.2µH
RT5014
L2
2.2µH
VBAT
BAT
30
GND
41 (Exposed Pad)
LX7 15
D6
D7
R9
10
L7
10µH
C25
1µF
VBAT
Figure 2. Typical Application Circuit for 2AA Battery (1.8V to 4.2V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
34
VBAT
3.4V to 4.2V
C19
10µF
V33 ≥ 3.3V
C3
4.7µF
L2
2.2µH
C4
10µF
R1
470k
C29
10pF
PVD2
VCORE
1.2V
38 LX2
40
FB2
21
L3
2.2µH
R3
232k
PVD3
20 LX3
18
C7
4.7µF
R5
330k
FB3
PVD4
13 LX4
11
25
L5
10µH
39
System Reset
Chip Enable
V33
VOD1 6
3.1V for SYS
2.3V for
Memory Card
VOD2 8
VIM 29
V33
C12
1µF
2.5V
C13
1µF
VIA 4
V33
C27
1µF
FB4
5
1.3V
C28
10µF
PVD5
R7
26 LX5
24
23
C16
10pF
VRTC
Super
Cap
3.3V
C14
1µF
C15
2.2µF
C26
0.1µF
EN 19
VOA
C18
4.7µF
HDMI
5V
33
VOM 28
C17
10µF
VBAT
C1
10µF x 2
C10
1µF
R6
374k
6V
Motor 5V
31
C11
1µF
L4
2.2µH
C8
10µF
32
VBAT
C9
1µF
14
VBAT
C2
4.7µF
VID 7
R4
464k
DDRIII
1.5V
VRTC
SYSR
C5
4.7µF
C6
10µF
VOUT1
PVD1
R2
150k
VBAT
L1
2.2µH
RT5014
37
VBAT
LX1
BAT
30
VIH
1
R8
I2C Bus
C20
1µF
D2
D3
LDOH
22
FBH
35
LX6
36
SCL 10
9
SDA
PVD7 16
VOUT6
FB6
2 VREF
3 VNEG
SEQ 12
VDDM 27
VBAT
Bypass Cap
1µF
FB7 17
41 (Exposed Pad)
GND
L7
10µH
15
LX7
C25
1µF
D4
D5
D6
D7
R9
10
VBAT
Figure 3. Typical Application Circuit for Ambarella A7 with Li-ion Battery (3.4V to 4.2V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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17
RT5014
34
VBAT
1.8V to 4.2V
C19
10µF
L2
2.2µH
VBAT
C4
4.7µF
C4
10µF x 2
C29
4.7pF
R1
470k
VOUT1
38 LX2
40
PVD2
VCORE
1.2V
21
PVD3
L3
2.2µH
R3
232k
20 LX3
Motor 5V
31
C1
10µF x 2
33
C26
0.1µF
39
18
System Reset
EN 19
Chip Enable
C7
4.7µF
R5
330k
FB3
2.3V for
Memory Card
PVD4
VIM 29
V33
C12
1µF
2.5V
C13
1µF
VIA 4
11
C18
4.7µF
5
1.3V
C28
10µF
PVD5
3.3V
R7
26 LX5
24
C14
1µF
VIH
R8
SCL 10
9
SDA
16
PVD7
I2C Bus
C24
1µF
D2
D3
23
C16
10pF
V33
C27
1µF
FB4
VOA
L5
10µH
C15
2.2µF
3.1V for SYS
VOD2 8
13 LX4
C17
10µF
VBAT
VOD1 6
VOM 28
25
6V
V33
C11
1µF
L4
2.2µH
VRTC
Super
Cap
C10
1µF
R6
374k
HDMI
5V
32
VBAT
C9
1µF
14
VBAT
C8
10µF
C2
4.7µF
VID 7
R4
464k
DDRIII
1.5V
VRTC
SYSR
C5
4.7µF
C6
10µF
PVD1
FB2
R2
150k
VBAT
L1
2.2µH
RT5014
37
V33 ≥ 3.3V
LX1
BAT
30
22
35
36
LDOH
FBH
SEQ 12
VDDM 27
LX6
VOUT6
1
FB6
2 VREF
3 VNEG
VBAT
D4
D5
Bypass Cap
1µF
FB7 17
41 (Exposed Pad)
GND
L7
10µH
15
LX7
C25
1µF
D6
D7
R9
10
VBAT
Figure 4. Typical Application Circuit for Ambarella A7 with 2AA Battery (1.8V to 4.2V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
34
VBAT
3.4V to 4.2V
C19
10µF
C3
4.7µF
L2
2.2µH
V33 ≥ 3.3V
C4
R1
10µF 470k
C29
10pF
PVD2
38 LX2
40
C6
10µF
FB2
21
C5
4.7µF
R3
118k
PVD3
20 LX3
18
C7
4.7µF
L4
2.2µH
C8
10µF
R5
330k
C17
10µF
C18
4.7µF
FB3
23
C16
10pF
L6
10µH
PVD4
FB4
PVD5
22
VIH
C21
1nF
C22
0.1µF
Chip Enable
3.3V
VOD1 6
3V for SYS
VOD2 8
3.1V for SD
VIM 29
3.3V
VOM 28
1.8V
C13
1µF
VIA 4
3.3V
C27
1µF
VOA
5
3.1V for AFE
C28
10µF
R7
SCL 10
9
SDA
PVD7 16
35
I2C Bus
D2
D3
RSEQ
SEQ 12
FBH
D4
D5
27
LX6
Bypass Cap
1µF
FB7 17
VOUT6
1
FB6
2 VREF
3 VNEG
C23
0.1µF
R8
LDOH
VDDM
36
C20
10µF x 2
System Reset
C24
1µF
D1
CCD7V
39
VRTC
Super
Cap
C11
1µF
26 LX5
C14
1µF
C15
2.2µF
C26
0.1µF
3.3V
24
CCD+
13V
33
C10
1µF
13 LX4
11
L5
10µH
C1
10µF x 2
C12
1µF
25
VBAT
Motor 5V
31
EN 19
R6
374k
14V
32
VBAT
C9
1µF
14
VBAT
C2
4.7µF
VID 7
R4
464k
DDRIII
1.5V
VRTC
SYSR
L3
2.2µH
VCORE
1V
VOUT1
PVD1
R2
150k
VBAT
L1
2.2µH
RT5014
37
VBAT
LX1
BAT
30
41 (Exposed Pad)
GND
L7
10µH
15
LX7
C25
1µF
D6
D7
R9
10
VBAT
Figure 5. Typical Application Circuit for Ambarella A7L with Li-ion Battery (3.4V to 4.2V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
19
RT5014
34
VBAT
1.8V to 4.2V
C19
10µF
VOUT1
38
C3
4.7µF
37
V33 ≥ 3.3V
C4
10µF x 2
R1
470k
C29
4.7pF 40
LX2
PVD1
PVD2
VRTC
FB2
R2
150k
VCORE
1V
SYSR
21
VBAT
C5
4.7µF
C6
10µF
DDRIII
1.5V
L3
2.2µH
R3
118k
PVD3
20 LX3
18
14
L4
2.2µH
R5
330k
13
11
C17
10µF
L5
10µH
C18
4.7µF
FB3
PVD4
23
C16
10pF
22
L6
10µH
C21
470pF
C22
0.1µF
System Reset
Chip Enable
V33
C9
1µF
VOD1 6
3V for SYS
C10
1µF
VOD2 8
3.1V for SD
VIM 29
V33
FB4
1.8V
C13
1µF
VIA 4
V33
C27
1µF
VOA
5
3.1V for AFE
C28
10µF
PVD5
VIH
R7
35
I2C Bus
C24
1µF
LDOH
D2
D3
RSEQ
SEQ 12
FBH
D4
D5
27
Bypass Cap
1µF
LX6
FB7 17
VOUT6
1 FB6
2 VREF
3 VNEG
C23
0.1µF
R8
SCL 10
9
SDA
16
PVD7
VDDM
36
C20
10µF x 2
39
VOM 28
D1
CCD7V
VRTC
Super
Cap
C26
0.1µF
LX4
26 LX5
C14
1µF
C15
2.2µF
33
3.3V
24
CCD+
13V
C1
10µF x 2
C12
1µF
25
VBAT
Motor 5V
31
VID 7
R6
374k
13.3V
32
VBAT
C11
1µF
C7
4.7µF
C8
10µF
C2
4.7µF
EN 19
R4
464k
VBAT
LX1
L1
2.2µH
RT5014
L2
2.2µH
VBAT
BAT
30
GND
41 (Exposed Pad)
LX7 15
D6
D7
R9
10
L7
10µH
C25
1µF
VBAT
Figure 6. Typical Application Circuit for Ambarella A7L with 2AA Battery (1.8V to 4.2V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Typical Operating Characteristics
CH1 Efficiency vs. Output Current
100
90
90
70
60
50
40
30
=
=
=
=
=
=
=
=
=
=
4.5V
4.2V
3.9V
3.6V
3.3V
3V
2.7V
2.4V
2.1V
1.8V
80
Efficiency (%)
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
80
Efficiency (%)
CH2 Efficiency vs. Output Current
100
20
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
70
60
50
40
30
10
Step-Up, VOUT = 5V, L = 2.2μH, COUT = 10μF x 2
0
Step-Up, VOUT = 3.3V, L = 2.2μH, COUT = 10μF x 2
0
10
100
1000
10
Output Current (mA)
100
90
90
70
60
50
=
=
=
=
=
80
3.4V
3.7V
3.9V
4.2V
4.5V
Efficiency (%)
VBAT
VBAT
VBAT
VBAT
VBAT
40
30
20
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
70
60
50
40
30
20
10
1000
CH3 Efficiency vs. Output Current
100
80
100
Output Current (mA)
CH2 Efficiency vs. Output Current
Efficiency (%)
3.3V
3V
2.7V
2.4V
2.1V
1.8V
20
10
10
Step-Down, VOUT = 3.3V, L = 2.2μH, COUT = 10μF
0
=
=
=
=
=
=
=
=
=
=
1.8V
2.1V
2.4V
2.7V
3V
3.3V
3.6V
3.9V
4.2V
4.5V
Step-Down, VOUT = 1.2V, L = 2.2μH, COUT = 10μF
0
10
100
1000
10
Output Current (mA)
100
90
90
70
60
50
40
30
=
=
=
=
=
=
=
=
=
=
2V
2.1V
2.4V
2.7V
3V
3.3V
3.6V
3.9V
4.2V
4.5V
80
Efficiency (%)
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
20
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
70
60
50
40
30
20
10
1000
CH5 Efficiency vs. Output Current
100
80
100
Output Current (mA)
CH4 Efficiency vs. Output Current
Efficiency (%)
=
=
=
=
=
=
Step-Down, VOUT = 1.8V, L = 2.2μH, COUT = 10μF
0
10
=
=
=
=
=
=
=
=
=
=
4.5V
4.2V
3.9V
3.6V
3.3V
3V
2.7V
2.4V
2.1V
1.8V
Step-Up, VOUT = 14V, L = 10μH, COUT = 10μF
0
10
100
Output Current (mA)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
1000
10
100
Output Current (mA)
is a registered trademark of Richtek Technology Corporation.
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RT5014
CH7 Efficiency vs. Input Voltage
100
90
90
80
80
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
70
60
50
40
30
20
10
=
=
=
=
=
=
=
=
=
=
4.5V
4.2V
3.9V
3.6V
3.3V
3V
2.7V
2.4V
2.1V
1.8V
Efficiency (%)
Efficiency (%)
CH6 Efficiency vs. Output Current
100
70
60
50
40
30
20
10
Inverting, VOUT = −7V, L = 10μH, COUT = 10μF x 2
6WLEDs, L = 10μH, COUT = 10μF, IOUT = 25mA
0
0
10
1.8
100
2.2
2.6
3
5.075
3.375
5.050
3.350
5.025
4.975
4.950
4.925
=
=
=
=
=
=
=
=
1.8V
2.4V
3V
3.3V
3.6V
4.9V
4.2V
4.5V
4.6
5
3.325
3.300
VBAT
VBAT
VBAT
VBAT
3.275
3.250
=
=
=
=
1.8V
2.4V
3V
3.3V
3.225
Step-Up, VOUT = 5V
Step-Up, VOUT = 3.3V
4.900
3.200
0
100
200
300
400
500
600
0
100
Output Current (mA)
3.375
1.2075
3.350
1.2050
Output Voltage (V)
1.2100
3.325
VBAT
VBAT
VBAT
VBAT
VBAT
3.275
3.250
=
=
=
=
=
300
400
500
600
CH3 Output Voltage vs. Output Current
3.400
3.300
200
Output Current (mA)
CH2 Output Voltage vs. Output Current
Output Voltage (V)
4.2
CH2 Output Voltage vs. Output Current
3.400
Output Voltage (V)
Output Voltage (V)
CH1 Output Voltage vs. Output Current
5.100
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
3.8
Input Voltage (V)
Output Current (mA)
5.000
3.4
3.4V
3.7V
3.9V
4.2V
4.5V
3.225
1.2025
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
1.2000
1.1975
1.1950
1.1925
=
=
=
=
=
=
=
=
1.8V
2.4V
3V
3.3V
3.6V
3.9V
4.2V
4.5V
Step-Down, VOUT = 3.3V
3.200
Step-Down, VOUT = 1.2V
1.1900
0
100
200
300
400
500
Output Current (mA)
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22
600
0
100
200
300
400
500
600
Output Current (mA)
is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
CH5 Output Voltage vs. Output Current
15.00
1.813
14.75
1.812
14.50
Output Voltage (V)
Output Voltage (V)
CH4 Output Voltage vs. Output Current
1.814
1.811
1.810
1.809
VBAT
VBAT
VBAT
VBAT
1.808
=
=
=
=
2V
2.4V
3V
3.3V
VBAT
VBAT
VBAT
VBAT
=
=
=
=
3.6V
3.9V
4.2V
4.5V
14.25
14.00
VBAT
VBAT
VBAT
VBAT
13.75
13.50
=
=
=
=
1.8V
2.4V
3V
3.3V
VBAT
VBAT
VBAT
VBAT
Step-Down, VOUT = 1.8V
Step-Up, VOUT = 14V
1.806
13.00
0
100
200
300
400
500
600
0
20
CH6 Output Voltage vs. Output Current
-7.025
13.125
-7.050
13.100
Output Voltage (V)
13.150
-7.075
-7.100
VBAT
VBAT
VBAT
VBAT
-7.150
=
=
=
=
4.5V
4.2V
3.9V
3.6V
-7.175
VBAT
VBAT
VBAT
VBAT
=
=
=
=
60
80
100
CH8 HV-LDO Output Voltage vs. Output Current
-7.000
-7.125
40
Output Current (mA)
Output Current (mA)
Output Voltage (V)
3.6V
3.9V
4.2V
4.5V
13.25
1.807
3.3V
3V
2.4V
1.8V
Inverting, VOUT = −7V
-7.200
13.075
13.050
13.025
VBAT
VBAT
VBAT
VBAT
13.000
=
=
=
=
1.8V
2.4V
3V
3.3V
VBAT
VBAT
VBAT
VBAT
=
=
=
=
3.6V
3.9V
4.2V
4.5V
12.975
VOUT = 13V
12.950
0
20
40
60
80
100
0
20
Output Current (mA)
3.25
3.175
3.20
3.150
Output Voltage (V)
3.200
3.15
3.10
3.05
3.00
2.95
=
=
=
=
=
60
80
100
CH10 LDO Output Voltage vs. Output Current
3.30
VBAT
VBAT
VBAT
VBAT
VBAT
40
Output Current (mA)
CH9 LDO Output Voltage vs. Output Current
Output Voltage (V)
=
=
=
=
3.3V
3.6V
3.9V
4.2V
4.5V
3.125
3.100
VBAT
VBAT
VBAT
VBAT
VBAT
3.075
3.050
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
4.5V
3.025
VOUT = 3.1V
2.90
VOUT = 3.1V
3.000
0
50
100
150
200
Output Current (mA)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
250
0
50
100
150
200
250
Output Current (mA)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
23
RT5014
CH12 LDO Output Voltage vs. Output Current
3.200
3.175
3.175
3.150
3.150
Output Voltage (V)
Output Voltage (V)
CH11 LDO Output Voltage vs. Output Current
3.200
3.125
3.100
VBAT
VBAT
VBAT
VBAT
VBAT
3.075
3.050
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
4.5V
3.025
3.125
3.100
VBAT
VBAT
VBAT
VBAT
VBAT
3.075
3.050
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
4.5V
3.025
VOUT = 3.1V
3.000
VOUT = 3.1V
3.000
0
50
100
150
200
250
50
100
150
200
Output Current (mA)
Power On Sequence 0
Power On Sequence 0
VOUT_CH1
(10V/Div)
250
VOUT_CH4
(2V/Div)
VOUT_CH12
(5V/Div)
VOUT_CH2
(5V/Div)
VOUT_CH3
(2V/Div)
VOUT_CH9
(2V/Div)
VOUT_CH10
(5V/Div)
VBAT = 3.7V
VOUT_CH11
(5V/Div)
VBAT = 3.7V
Time (10ms/Div)
Time (10ms/Div)
Power Off Sequence 0
Power Off Sequence 0
VOUT_CH4
(2V/Div)
VOUT_CH12
(5V/Div)
VOUT_CH1
(10V/Div)
VOUT_CH2
(5V/Div)
VOUT_CH3
(2V/Div)
VOUT_CH9
(2V/Div)
VOUT_CH10
(5V/Div)
VBAT = 3.7V
Time (2.5ms/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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24
0
Output Current (mA)
VOUT_CH11
(5V/Div)
VBAT = 3.7V
Time (2.5ms/Div)
is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Power On Sequence 1
Power Off Sequence 1
VOUT_CH1
VOUT_CH1
(5V/Div)
(5V/Div)
VOUT_CH2
VOUT_CH2
(5V/Div)
(2V/Div)
(2V/Div)
(2V/Div)
(5V/Div)
VOUT_CH3
VOUT_CH3
(2V/Div)
VOUT_CH12
VOUT_CH12
(2V/Div)
VOUT_CH4
VOUT_CH4
(2V/Div)
VOUT_CH10
VOUT_CH10
(5V/Div)
(5V/Div)
VBAT = 3.7V
VBAT = 3.7V
Time (10ms/Div)
Time (2.5ms/Div)
Power On Sequence 2
Power Off Sequence 2
VOUT_CH1
(10V/Div)
(5V/Div)
(2V/Div)
(5V/Div)
(2V/Div)
(2V/Div)
(5V/Div)
(10V/Div)
VOUT_CH1
VOUT_CH2
(5V/Div)
VOUT_CH2
VOUT_CH3
(2V/Div)
VOUT_CH3
VOUT_CH10
(5V/Div)
VOUT_CH10
VOUT_CH12
(2V/Div)
VOUT_CH12
VOUT_CH4
(2V/Div)
VOUT_CH4
VOUT_CH11
(5V/Div)
VOUT_CH11
VBAT = 3.7V
VBAT = 3.7V
Time (5ms/Div)
Time (2.5ms/Div)
Power On Sequence 3
Power Off Sequence 3
VOUT_CH1
VOUT_CH1
(5V/Div)
(5V/Div)
VOUT_CH2
VOUT_CH2
(5V/Div)
(5V/Div)
VOUT_CH3
VOUT_CH3
(2V/Div)
(2V/Div)
VOUT_CH4
VOUT_CH4
(2V/Div)
(2V/Div)
VOUT_CH10
VOUT_CH10
(5V/Div)
(5V/Div)
VOUT_CH11
VBAT = 3.7V
Time (5ms/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
VOUT_CH11
(5V/Div)
(5V/Div)
VBAT = 3.7V
Time (2.5ms/Div)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
25
RT5014
Power Off Sequence 4
Power On Sequence 4
VOUT_CH1
VOUT_CH1
(5V/Div)
(5V/Div)
VOUT_CH2
VOUT_CH2
(5V/Div)
(5V/Div)
VOUT_CH3
VOUT_CH3
(2V/Div)
(2V/Div)
VOUT_CH10
VOUT_CH10
(5V/Div)
(5V/Div)
VOUT_CH4
VOUT_CH4
(2V/Div)
(2V/Div)
VOUT_CH11
VOUT_CH11
(5V/Div)
(5V/Div)
VBAT = 3.7V
VBAT = 3.7V
Time (5ms/Div)
Time (2.5ms/Div)
CH1 Output Voltage Ripple
CH2 Output Voltage Ripple
LX1
(2V/Div)
LX2
(2V/Div)
VOUT_CH1_ac
(5mV/Div)
VOUT_CH2_ac
(5mV/Div)
VBAT = 3V, VOUT = 3.3V
IOUT = 400mA, L = 2.2μH, COUT = 10μF x 2
VBAT = 3.7V, VOUT = 5V,
IOUT = 400mA, L = 2.2μH, COUT = 10μF x 2
Time (500ns/Div)
Time (1μs/Div)
CH3 Output Voltage Ripple
CH4 Output Voltage Ripple
LX3
(2V/Div)
LX4
(2V/Div)
VOUT_CH3_ac
(5mV/Div)
VOUT_CH4_ac
(5mV/Div)
VBAT = 3.7V, VOUT = 1.2V
IOUT = 400mA, L = 2.2μH, COUT = 10μF
Time (500ns/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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26
VBAT = 3.7V, VOUT = 1.8V
IOUT = 400mA, L = 2.2μH, COUT = 10μF
Time (500ns/Div)
is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
CH6 Output Voltage Ripple
CH5 Output Voltage Ripple
LX6
(5V/Div)
LX5
(5V/Div)
VOUT_CH5_ac
(10mV/Div)
VOUT_CH6_ac
(5mV/Div)
VBAT = 3.7V, VOUT = −7V
IOUT = 50mA, L = 10μH, COUT = 10μF x 2
VBAT = 3.7V, VOUT = 14V
IOUT = 30mA, L = 10μH, COUT = 10μF
Time (1μs/Div)
Time (1μs/Div)
CH1 Load Transient Response
CH2 Load Transient Response
IOUT
(100mA/Div)
IOUT
(100mA/Div)
V OUT_CH1_ac
(100mV/Div)
VOUT_CH2_ac
(20mV/Div)
VBAT = 3V, VOUT = 3.3V
IOUT = 0 to 300mA, L = 2.2μH, COUT = 10μF x 2
VBAT = 3.7V, VOUT = 5V
IOUT = 0 to 300mA, L = 2.2μH, COUT = 10μF x 2
Time (250μs/Div)
Time (250μs/Div)
CH2 Load Transient Response
CH3 Load Transient Response
IOUT
(100mA/Div)
IOUT
(100mA/Div)
VOUT_CH2_ac
(50mV/Div)
VOUT_CH3_ac
(10mV/Div)
VBAT = 3.7V, VOUT = 3.3V
IOUT = 0 to 300mA, L = 2.2μH, COUT = 10μF
Time (250μs/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
VBAT = 3.7V, VOUT = 1.2V
IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF
Time (250μs/Div)
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RT5014
CH4 Load Transient Response
CH5 Load Transient Response
IOUT
(100mA/Div)
IOUT
(10mA/Div)
VOUT_CH4_ac
(20mV/Div)
V OUT_CH5_ac
(100mV/Div)
VBAT = 3.7V, VOUT = 1.8V
IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF
VBAT = 3.7V, VOUT = 14V
IOUT = 10mA to 25mA, L = 10μH, COUT = 10μF
Time (250μs/Div)
Time (250μs/Div)
CH6 Load Transient Response
CH8 Load Transient Response
IOUT
(10mA/Div)
IOUT
(10mA/Div)
VOUT_CH6_ac
(10mV/Div)
VOUT_CH8_ac
(5mV/Div)
VBAT = 3.7V, VOUT = −7V
IOUT = 10mA to 30mA, L = 10μH, COUT = 10μF x 2
VBAT = 3.7V, VOUT5 = 14V
VOUT = 13V, IOUT = 10mA to 25mA, COUT = 2.2μF
Time (250μs/Div)
Time (250μs/Div)
CH9 Load Transient Response
CH10 Load Transient Response
IOUT
(100mA/Div)
IOUT
(100mA/Div)
VOUT_CH9_ac
(20mV/Div)
VOUT_CH10_ac
(20mV/Div)
VBAT = 3.7V, VOUT = 3.1V
IOUT = 100mA to 200mA, COUT = 10μF
Time (250μs/Div)
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VBAT = 3.7V, VOUT = 3.1V
IOUT = 100mA to 200mA, COUT = 1μF
Time (250μs/Div)
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DS5014-01 March 2013
RT5014
CH11 Load Transient Response
CH12 Load Transient Response
IOUT
(100mA/Div)
IOUT
(100mA/Div)
VOUT_CH11_ac
(20mV/Div)
VOUT_CH12_ac
(20mV/Div)
VBAT = 3.7V, VOUT = 3.1V
IOUT = 100mA to 200mA, COUT = 1μF
Time (250μs/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
VBAT = 3.7V, VOUT = 3.1V
IOUT = 100mA to 200mA, COUT = 1μF
Time (250μs/Div)
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RT5014
Application Information
The RT5014 is an integrated power solution for digital still cameras and other small handheld devices. It includes six DC/
DC converters, a WLED driver, one RTC_LDO, one High Voltage LDO for CCD+ bias power, one high PSRR LDO for AFE
power, and three generic LDOs.
CH1 : Synchronous Step-Up DC/DC Converter
The CH1 synchronous step-up DC/DC converter operates in fixed frequency current mode. It includes internal power
MOSFETs, compensation network and feedback resistors. The P-MOSFET can be controlled to disconnect output
loading. It is suitable for providing power to the motor. The output voltage of CH1 can be adjusted by the I2C interface in
the range of 3.6V to 5.3V.
2
CH1 regulation voltage is selectable by I C interface.
The default voltage is 5V.
VOUT1
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
0000
3.6V
0001
3.7V
0010
3.8V
0011
3.9V
0100
4V
0101
4.1V
0110
4.2V
0111
4.3V
1000
4.4V
1001
4.5V
1010
4.6V
1011
4.7V
1100
4.8V
1101
5V
1110
5.2V
1111
5.3V
CH2 : Synchronous Step-Up / Step-Down Selectable DC/DC Converter
The CH2 is a synchronous converter with step-up/step-down auto-select function for system I/O power. In either stepup or step-down, the converter operates in fixed frequency PWM mode, Continuous Conduction Mode (CCM), and
Discontinuous Conduction Mode (DCM) with internal MOSFETs.
In step-up mode, the CH2 converter can disconnect the load from its input power node and discharges output node
when it is turned off.
In step-down mode, the CH2 converter can be operated at 100% maximum duty cycle to extend the input operating
voltage range. When the input voltage is close to the output voltage, the converter enters low dropout mode.
The output voltage can be set by the following equation :
VOUT_CH2 = (1 + R1 / R2) x VFB2
where VFB2 is 0.8V typically.
CH3 : Synchronous Step-Down DC/DC Converter
The synchronous step-down DC/DC converter operates in fixed frequency PWM mode with integrated internal MOSFETs
and compensation network. The CH3 step-down converter can be operated at 100% maximum duty cycle to extend
battery operating voltage range. When the input voltage is close to the output voltage, the converter enters low dropout
mode with low output ripple.
The output voltage can be set by the following equation :
VOUT_CH3 = (1 + R3 / R4) x VFB3
where VFB3 is 0.8V typically.
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RT5014
CH4 : Synchronous Step-Down DC/DC Converter
The synchronous step-down DC/DC converter operates at fixed frequency PWM mode with integrated internal MOSFETs
and compensation network. The CH4 step-down converter can be operated at 100% maximum duty cycle to extend
battery operating voltage range. When the input voltage is close to the output voltage, the converter enters low dropout
mode with low output ripple.
The output voltage can be set by the following equation :
VOUT_CH4 = (1 + R5 / R6) x VFB4
where VFB4 is 0.8V typically.
CH5 : Synchronous Step-Up DC/DC Converter
CH5 is a high voltage synchronous step-up converter for the input power of CH8, high voltage LDO for CCD positive
power. The converter operates at fixed frequency PWM mode, and CCM with integrated internal MOSFETs, compensation
network and load disconnect function. The output voltage of CH5 is adjustable by the I2C interface.
PVD5 = DV5 [3:0] + LDOH [3:0]
2
DV5 regulation voltage can be selectable by I C interface. The default voltage is 0.3V.
DV5 [3:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
0000
0.2V
0001
0.3V
0010
0.4V
0011
0.5V
0100
0.6V
0101
0.7V
0110
0.8V
0111
0.9V
1000
1V
1001
1.5V
1010
2V
1011
2.5V
1100
3V
1101
3.5V
1110
4V
1111
4.5V
Note : PVD5 regulation voltage target = V(LDOH) + V(DV5)
Define CH8 LDOH output voltage level. The default voltage is 9V.
LDOH [3:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
0000
5V
0001
9V
0010
9.5V
0011
10V
0100
10.5V
0101
11V
0110
11.5V
0111
12V
1000
12.5V
1001
13V
1010
13.5V
1011
14V
1100
14.5V
1101
15V
1110
15.5V
1111
16V
CH6 : INV DC/DC Converter
The asynchronous inverting current mode DC/DC converter integrates an internal P-MOSFET with internal compensation
and needs an external Schottky diode to provide CCD negative power supply.
The output voltage of CH6 can be adjusted by the I2C interface in the range of −5V to −8V.
2
CH6 regulation voltage can be selectable by I C interface.
The default voltage is −5V.
VOUT6
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
−5V
001
−5.5V
010
−6V
011
−6.5V
100
−7V
101
−7.5V
110
−8V
111
external
Note : VOUT6 [2:0] = 111 (REF) means using external feedback network to define output voltage
level.
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RT5014
The output voltage using external feedback network can be set by the following equation.
VOUT_CH6 = −(R11 / R12) x (0.84V) + 0.4V
where R11 and R12 are the feedback resistors connected
The feed forward capacitor can be estimated by the following equation.
-6
Cff = 62.5 × 10
R11
For example, when R11 is 125kΩ, the available feed-forward capacitor is 470pF.
VOUT6
Cff
R11
FB6
R12
VREF
0.1µF
CH7 : WLED Driver
CH7 is a WLED driver that can operate in either current source mode or synchronous step-up mode, as determined by
LX7 detection. When CH7 works in current source mode, it sources an LED current out of LX7 pin and regulates the
current by FB7 voltage. The LED current is defined by the FB7 voltage as well as the external resistor between FB7 and
GND. The FB7 regulation voltage can be set in 32 steps from 7.8mV to 250mV via I2C interface. If CH7 works in
synchronous step-up mode, it integrates synchronous step-up mode with an internal MOSFET and internal compensation.
The LED current is also set via an external resistor and FB7 regulation voltage.
CH7 WLED Current Dimming Control
If CH7 is in synchronous step-up mode or current source mode, the WLED current is set by an external resistor.
Regardless of the mode, dimming is always controlled by the I2C interface. The WLED current can be set by the
following equations :
ILED (mA) = [250mV / R (W)] x (DIM7 [4:0] + 1 ) / 32
where R is the current sense resistor from FB7 to GND and (DIM7 [4:0] + 1) / 32 ratio refers to the I2C control register
file.
CH8 High Voltage LDO
CH8 is a high voltage LDO for CCD positive power. It is a linear regulator, designed to be stable over the entire operating
load range with the use of external ceramic capacitors. CH8 has an ON/OFF control which can be set by I2C commands.
The output voltage of CH8 is adjustable by the I2C interface in the range of 5V to 16V.
Define CH8 LDOH output voltage level. The default voltage is 9V.
LDOH [3:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
0000
5V
0001
9V
0010
9.5V
0011
10V
0100
10.5V
0101
11V
0110
11.5V
0111
12V
1000
12.5V
1001
13V
1010
13.5V
1011
14V
1100
14.5V
1101
15V
1110
15.5V
1111
16V
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RT5014
CH9 : Low Voltage LDO
CH9 is a high PSRR LDO for AFE power. It is a linear regulator, designed to be stable over the entire operating load
range with the use of external ceramic capacitors. CH9 has an ON/OFF control which can be set by I2C commands. The
output voltage of CH9 is adjustable by the I2C interface in the range of 1.3V to 3.3V.
Define CH9 LDO preset output voltage level. The default voltage is 1.3V
VOA [2:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.3V
001
3.2V
010
3.1V
011
3V
100
2.8V
101
2.5V
110
1.8V
111
1.3V
CH10 : Low Voltage LDO
CH10 is a low voltage LDO for system power. It is a linear regulator, designed to be stable over the entire operating load
range with the use of external ceramic capacitors. CH10 will turns on after CH1 to CH3 by power on/off sequence table.
The output voltage of CH10 is adjustable by the I2C interface in the range of 1.2V to 3.2V.
Define CH10 LDO output voltage level. The default voltage is 3.1V when SEQ #0, 2, 3, 4 or 3V
when SEQ #1.
VOD1 [2:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.2V
001
3.1V
010
3V
011
2.8V
100
2.5V
101
1.8V
110
1.3V
111
1.2V
CH11 : Low Voltage LDO
CH11 is a low voltage LDO for memory card power. It is a linear regulator, designed to be stable over the entire operating
load range with the use of external ceramic capacitors. CH11 has an ON/OFF control which can be set by I2C commands.
The output voltage of CH11 is adjustable by the I2C interface in the range of 1.3V to 3.2V.
Define CH11 LDO output voltage level. The default voltage is 2.3V when SEQ #0 or 3.1V when
SEQ #1 to SEQ #4.
VOD2 [2:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.2V
001
3.1V
010
3V
011
2.8V
100
2.5V
101
2.3V
110
1.8V
111
1.3V
CH12 : Low Voltage LDO
CH12 is a low voltage LDO for multiple purpose power. It is a linear regulator, designed to be stable over the entire
operating load range with the use of external ceramic capacitors. CH12 has an ON/OFF control which can be set by I2C
commands. The output voltage of CH12 is adjustable by the I2C interface in the range of 1.2V to 3.2V.
Define CH12 LDO preset output voltage level. The default voltage is 2.5V when SEQ #0, or 1.8V
when SEQ #1 to SEQ #4.
VOM [2:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.2V
001
3.1V
010
3V
011
2.8V
100
2.5V
101
1.8V
110
1.3V
111
1.2V
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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RT5014
RTC_LDO : Accuracy 3.3V LDO Output.
The RT5014 provides a 3.3V output LDO for real-time clock. The LDO features low quiescent current (3μA), reverse
leakage prevention from output node and high output voltage accuracy. This LDO is always on, even when the system is
shut down. For better stability, it is recommended to connect a 0.1μF capacitor to the VRTC pin. The RTC LDO includes
pass transistor body diode control to avoid the VRTC node from back-charging into the input node VDDI.
Switching Frequency
The converters of CH1 to CH4 operate in PWM mode with 2MHz and CH5 to CH7 operates in PWM mode with 1MHz
switching frequency.
VDDM Bootstrap
To support bootstrap function, the RT5014 provides a power selection circuit which selects the maximum voltage
between BAT and PVD1 to support the power requirement at node VDDI. The RT5014 includes UVLO circuits to monitor
VDDI and BAT voltage status.
BAT
PVD1
VDDI = Max (BAT, PVD1)
Power On/Off Sequence
SEQ pull down resistance RSEQ defines Power on/off Sequence.
SEQ #
SEQ #0
SEQ #1
SEQ #2
SEQ #3
SEQ #4
RSEQ (kΩ) Range
Min
Typ
Max
Short to Power (>0.2V)
36
40
44
9
10
11
2.25
2.5
2.75
-0.63
0.69
Typical soft-start and on/off sequence waveform.
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RT5014
SEQ #0 : CH1 (5V) → CH2 (3.3V) → CH3 (1.2V) → CH10 (3.1V) → CH4 (1.5V), CH12 (2.5V), CH9 (1.3V),
Power off
Sequence
Power on
Sequence
SEQ detection
POR and Enable
VREF/IREF/OSC
CH11 (2.3V) ; I2C EN9 and EN12 bits have no function (Ambarella A7).
for A7,
SEQ #0
(SEQ pulled to High)
External EN
Latch SEQ
detection
result
Set Ch12 default = 2.5V,
Ch9 default = 1.3V.
tR ≈ 4ms
VOUT1 (5.0V)
tD
≈ 16ms
tR ≈ 4ms
VOUT2 (3.3V)
tD
VOUT3 (1.2V)
≈ 16ms
tR ≈ 4ms
tD
VOUT10 (3.1V)
≈ 16ms
tD
VOUT4 (1.5V)
≈ 16ms
tR ≈ 4ms
VOUT12 (2.5V)
VOUT9 (1.3V)
tR ≈ 1ms
VOUT11 (2.3V)
Power off
Sequence
Power on
Sequence
POR and Enable
VREF/IREF/OSC
SEQ detection
SEQ #1 : CH1 (5V) → CH2 (3.3V) → CH3 (1V) → CH12 (1.8V) → CH4 (1.5V) → CH10 (3V) ; I2C EN12 bit has no
function (Ambarella A7L).
for A7L,
SEQ #1
External EN
Latch SEQ
detection result
VOUT1 (5V)
tR ≈ 4ms
tD
VOUT2 (3.3V)
≈ 16ms
tR ≈ 4ms
tD
VOUT3 (1V)
VOUT12 (1.8V)
≈ 16ms
tR ≈ 4ms
tD
≈ 16ms
VOUT4 (1.5V)
VOUT10 (3.0V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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tR ≈ 4ms
tD
≈ 16ms
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RT5014
Power off
Sequence
Power on
Sequence
SEQ detection
POR and Enable
VREF/IREF/OSC
SEQ #2 : CH1 (5V) → CH2 (3.3V) → CH3 (1.2V) → CH10 (3.1V) → CH12 (1.8V) → CH4 (1.5V) → CH11 (3.1V); I2C
EN12 bit have no function.
SEQ #2
External EN
Latch SEQ
detection result
tR ≈ 4ms
VOUT1 (5V)
tD ≈ 4ms
VOUT2 (3.3V)
tR ≈ 4ms
tD ≈ 4ms
VOUT3 (1.2V)
tR ≈ 4ms
tD ≈ 4ms
VOUT10 (3.1V)
tD ≈ 4ms
VOUT12 (1.8V)
tD ≈ 4ms
VOUT4 (1.5V)
tR ≈ 4ms
tD
VOUT11 (3.1V)
≈ 16ms
tR ≈ 1ms
2
Enabled in I C
VOUT9
Power off
Sequence
Power on
Sequence
SEQ detection
POR and Enable
VREF/IREF/OSC
SEQ #3 : CH1 (5V) → CH2 (3.3V) → CH3 (1.2V) → CH4 (1.8V) → CH10 (3.1V) → CH11 (3.1V)
SEQ #3
External EN
Latch SEQ
detection result
VOUT1 (5V)
tR ≈ 4ms
tD ≈ 4ms
VOUT2 (3.3V)
tR ≈ 4ms
tD ≈ 4ms
VOUT3 (1.2V)
tR ≈ 4ms
tD ≈ 4ms
VOUT4 (1.8V)
tR ≈ 4ms
tD ≈ 4ms
VOUT10 (3.1V)
VOUT11 (3.1V)
tD
≈ 16ms
tR ≈ 1ms
2
VOUT12
Enabled in I C
2
VOUT9
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Enabled in I C
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RT5014
Power off
Sequence
Power on
Sequence
SEQ detection
POR and Enable
VREF/IREF/OSC
SEQ #4 : CH1 (5V) → CH2 (3.3V) → CH3 (1.2V) → CH10 (3.1V) → CH4 (1.8V) → CH11 (3.1V)
SEQ #4
External EN
Latch SEQ
detection
result
tR ≈ 4ms
VOUT1 (5V)
tD ≈ 4ms
VOUT2 (3.3V)
tR ≈ 4ms
tD ≈ 4ms
VOUT3 (1.2V)
tR ≈ 4ms
tD ≈ 4ms
VOUT10 (3.1V)
tD ≈ 4ms
VOUT4 (1.8V)
VOUT11 (3.1V)
tR ≈ 4ms
tD
≈ 16ms
VOUT12
tR ≈ 1ms
2
Enabled in I C
2
VOUT9
Enabled in I C
CH12 :
SEQ #0 : VOUT12 = 2.5V
SEQ #1 and SEQ #2 : VOUT12 = 1.8V
SEQ #3 and SEQ #4 : VOUT12 defined and enabled in I2C (CH12 not in sequence)
CH11 :
SEQ #0 : VOUT11 = 2.3V
SEQ #1 : VOUT11 defined and enabled in I2C (CH11 not in sequence) and VOUT11 has DVS function.
SEQ #2 to SEQ #4 : VOUT11 = 3.1V
CH 9 :
SEQ #0 : VOUT9 = 1.3V
SEQ #1 to SEQ #4 : VOUT9 defined and enabled in I2C (CH9 not in sequence)
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RT5014
I2C Interface
RT5014 I2C slave address = 7'b0011000. I2C interface supports fast mode (bit rate up to 400kb/s). The write or read bit
stream (N ≥ 1) is shown below :
Read N bytes from RT5014
Slave Address
Register Address
S
0
Slave Address
A
1
MSB
A
Data for Address = m
Data 2
LSB
MSB
Data N
LSB
A
A
Register Address
S
0
A
MSB
Data 1
LSB
A
Assume Address = m
R/W
P
Data for Address = m + N - 1
Data for Address = m + 1
Write N bytes to RT5014
Slave Address
LSB
A
Assume Address = m
R/W
Data 1
MSB
A Sr
MSB
Data 2
LSB
A
Data for Address = m
MSB
A
Data for Address = m + 1
Data N
LSB
A P
Data for Address = m + N - 1
Driven by Master,
Driven by Slave (RT5014),
P Stop,
S Start,
Sr Repeat Start
SDA
tLOW
tF
tSU,DAT
tR
tF
tHD,STA
tSP
tR
tBUF
SCL
tHD,STA
S
tHD,DAT
tHIGH
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tSU,STA
tSU,STO
Sr
P
S
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RT5014
I2C Register Map
Register
b [7]
Register Address
Address
(MSB)
Meaning Reserved
A0
0x00
b [6]
b [5]
b [4]
b [3]
OVP7
b [2]
b [1]
b [0]
(LSB)
DIM7 [4:0]
Default
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
1
1
1
1
R/W
R/W
R/W
R/W
2
CH7 allows user to select the OVP level by I C interface
00 : OVP7 = 9V (Typ.), 10V(MAX)
OVP7
01 : OVP7 = 15V (Typ.), 16V(MAX)
1X : OVP7 = 25V (Typ.), 26V(MAX)
DIM7 [4:0]
Register
Register Address
Address
Define FB7 regulation voltage
00000 to 11111 : CH7 dimming ratio : VFB7 = (DIM7 [4:0] + 1) / 32 x 0.25V
b [7]
(MSB)
Meaning
A1
0x01
b [6]
b [5]
b [4]
VOUT1 [3:0]
b [3]
b [2]
Reserved
b [1]
b [0]
(LSB)
VOUT6 [2:0]
Default
1
1
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
CH1 regulation voltage can be selectable by I C interface.
The default voltage is 5V.
VOUT1
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
0000
3.6V
0001
3.7V
0010
3.8V
0011
3.9V
0100
4V
0101
4.1V
0110
4.2V
0111
4.3V
1000
4.4V
1001
4.5V
1010
4.6V
1011
4.7V
1100
4.8V
1101
5V
1110
5.2V
1111
5.3V
2
CH6 regulation voltage can be selectable by I C interface.
The default voltage is −5V.
VOUT6
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
−5V
001
−5.5V
010
−6V
011
−6.5V
100
−7V
101
−7.5V
110
−8V
111
external
Note : VOUT6 [2:0] = 111 (REF) means using external feedback network to define
output voltage level.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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RT5014
Register
Register Address
Address
b [7]
(MSB)
Meaning
A2
0x02
b [6]
b [5]
b [4]
b [3]
DV5 [3:0]
b [2]
b [1]
b [0]
(LSB)
LDOH [3:0]
Default
0
0
0
1
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
DV5 regulation voltage can be selectable by I C interface.
The default voltage is 0.3V.
DV5 [3:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
0000
0.2V
0001
0.3V
0010
0.4V
0011
0.5V
0100
0.6V
0101
0.7V
0110
0.8V
0111
0.9V
1000
1V
1001
1.5V
1010
2V
1011
2.5V
1100
3V
1101
3.5V
1110
4V
1111
4.5V
Note : PVD5 regulation voltage target = V(LDOH) + V(DV5)
Define CH8 LDOH output voltage level. The default voltage is 9V.
LDOH [3:0]
Register
Register Address
Address
A3
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
0000
5V
0001
9V
0010
9.5V
0011
10V
0100
10.5V
0101
11V
0110
11.5V
0111
12V
1000
12.5V
1001
13V
1010
13.5V
1011
14V
1100
14.5V
1101
15V
1110
15.5V
1111
16V
b [7]
(MSB)
b [6]
b [5]
b [4]
b [3]
b [2]
b [1]
b [0]
(LSB)
Meaning
Reserved
Default
0
1
1
Read/Write
R/W
R/W
R/W
0x03
VOA [2:0]
Reserved
VOM [2:0]
1
0
See below
R/W
R/W
R/W
R/W
R/W
Define CH9 LDO preset output voltage level. The default voltage is 1.3V
VOA [2:0]
VOM [2:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.3V
001
3.2V
010
3.1V
011
3V
100
2.8V
101
2.5V
110
1.8V
111
1.3V
Define CH12 LDO preset output voltage level. The default voltage is 2.5V
when SEQ #0, or 1.8V when SEQ #1 to SEQ #4.
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.2V
001
3.1V
010
3V
011
2.8V
100
2.5V
101
1.8V
110
1.3V
111
1.2V
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Register
Register Address
Address
A4
0x04
b [7]
(MSB)
b [6]
b [5]
b [4]
b [3]
b [2]
b [1]
Meaning
Reserved
VOD1 [2:0]
Reserved
VOD2 [2:0]
Default
0
See below
0
See below
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
b [0]
(LSB)
R/W
Define CH10 LDO output voltage level. The default voltage is 3.1V when SEQ #0,
2, 3, 4 or 3V when SEQ #1.
VOD1 [2:0]
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.2V
001
3.1V
010
3V
011
2.8V
100
2.5V
101
1.8V
110
1.3V
111
1.2V
Define CH11 LDO output voltage level. The default voltage is 2.3V when SEQ #0
or 3.1V when SEQ #1 to SEQ #4.
VOD2 [2:0]
Register
Register Address
Address
Meaning
A5
0x05
Code
Voltage
Code
Voltage
Code
Voltage
Code
Voltage
000
3.2V
001
3.1V
010
3V
011
2.8V
100
2.5V
101
2.3V
110
1.8V
111
1.3V
b [6]
b [5]
b [4]
b [3]
b [2]
b [1]
EN6
EN7
EN8
EN9
Reserved
EN11
b [0]
(LSB)
EN12
b [7]
(MSB)
EN5
Default
0
0
0
0
0
0
See below
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EN5
EN6
EN7
EN8
EN9
EN11
EN12
Enable/disable CH5
0 : Disable
1 : Enable
Enable/disable CH6
0 : Disable
1 : Enable
Enable/disable CH7
0 : Disable
1 : Enable
Enable/disable CH8
0 : Disable
1 : Enable
Enable/disable CH9
0 : Disable
1 : Enable
Enable/disable CH11
0 : Disable
1 : Enable
SEQ #1 : Default value is 0. SEQ #0, 2, 3, 4 : Default value is 1.
Enable/disable CH12
0 : Disable
1 : Enable
* RESET Moment :
Register A0 to A4 reset when (BAT UVLO or VDDM UVLO) and after PMU shutdown.
Register A5 reset after (EN = L or BAT/VDDM UVLO) and PMU shutdown completely.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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RT5014
Address
Register Address
Bit7
Name
Meaning Reserved
A0
0x00
0x01
A3
A4
A5
0x02
0x03
0x04
0x05
Bit3
OVP7
Bit2
Bit1
Bit0
DIM7 [4:0]
0
0
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VOUT1 [3:0]
Reserved
VOUT6 [2:0]
Default
1
1
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DV5 [3:0]
LDOH [3:0]
Default
0
0
0
1
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Meaning
Reserved
Default
0
1
1
Read/Write
R/W
R/W
R/W
Meaning
Reserved
VOD1 [2:0]
Reserved
VOD2 [2:0]
Default
0
SEQ dependent
0
SEQ dependent
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Meaning
EN5
EN6
EN7
EN8
EN9
Reserved
EN12
Default
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
EN11
SEQ
dependent
R/W
VOA [2:0]
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Bit4
0
Meaning
A2
Bit5
Default
Meaning
A1
Bit6
Reserved
VOM [2:0]
1
0
SEQ dependent
R/W
R/W
R/W
R/W
R/W
0
R/W
is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Thermal Considerations
Layout Consideration
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
For the best performance of the RT5014, the following
PCB layout guidelines must be strictly followed.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-40L 5x5 package, the thermal resistance, θJA, is
27.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
`
Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
`
Keep the main power traces as wide and short as
possible.
`
The switching node area connected to LX and inductor
should be minimized for lower EMI.
`
Place the feedback components as close as possible
to the FB pin and keep these components away from
the noisy devices.
`
Connect the GND and Exposed Pad to a strong ground
plane for maximum thermal dissipation and noise
protection.
PD(MAX) = (125°C − 25°C) / (27.5°C/W) = 3.64W for
WQFN-40L 5x5 package
Maximum Power Dissipation (W)1
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 7 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
4.0
Four-Layer PCB
3.2
2.4
1.6
0.8
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7. Derating Curve of Maximum Power Dissipation
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43
RT5014
Place the feedback components as close as possible
to the FB pin and keep away from noisy devices.
VOUT_CH2
C4
GND VOUT_CH1
C20
VOUT_CH6
GND
LX should be connected to Inductor by wide and short
trace, keep sensitive compontents away from this trace
C3
D1
L6
GND
VBAT
C19
L2
VOUT6
C1
VBAT
FB2
SYSR
LX2
PVD2
VOUT6
LX6
BAT
VRTC
VOUT1
PVD1
R2
GND
C29
R1
40 39 38 37 36 35 34 33 32 31
C21
FB6
C22
VREF
C23
VNEG
C27
VIA
C28
VOUT_CH9
VOA
VOUT_CH10 VOD1
C10
C9
VID
VOUT_CH11 VOD2
SDA
C11
SCL
L1
1
30
2
29
3
28
4
27
5
26
GND
25
6
24
7
8
23
41
22
9
21
10
C2
VBAT
LX1
C12
VIM
C13
VOM VOUT_CH12
Bypass Cap
VDDM L5
VBAT
LX5
C18
C17
PVD5
VOUT_05
VIH
C14
LDOH
C15
FBH
C16
PVD3
R6
R5
C8
FB4
SEQ
LX4
VBAT PVD4
LX7
PVD7
FB7
FB3
EN
LX3
11 12 13 14 15 16 17 18 19 20
L7
L4
R3
VBAT
C5
L3
R4
C7
C25
GND
GND
C24
R9
VOUT_CH7
D7
GND
VOUT_CH4
D6
D5
D3
D4
D2
VOUT_CH3 GND VOUT_08 GND Connect the Exposed
Pad to a ground plane.
Input/Output capacitors must be placed as
close as possible to the Input/Output pins.
Figure 8. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Protection
Type
BAT
Threshold
(typical value)
Delay
Time
Protection
Methods
UVLO
BAT < 1.4V
No delay Turn off whole IC
OVP
VDDM > 6V
100ms
UVLO
VDDM < 2.4V
No delay Turn off whole IC
Current limit
N-MOSFET current > 3A
100ms
PVD1 OVP
PVD1 > 6V
No delay Turn off whole IC
PVD1 UVP
PVD1 < VBAT − 0.8V
100ms
VOUT1 UVP
VOUT1 < 2.25V
No delay Turn off whole IC
VOUT1 Over
Load
VOUT1 < target − 0.6V
100ms
Turn off whole IC
Current limit
N-MOSFET current > 3A
100ms
Turn off whole IC
PVD2 OVP
PVD2 > 6V
No delay Turn off whole IC
PVD2 UVP
PVD2 < VBAT − 0.8V
100ms
FB2 UVP
FB2 < 0.3V
No delay Turn off whole IC
Turn off whole IC
VDDM
CH1
Step-Up
CH2
Step-Up
FB2 Over Load FB2 < 0.7V
Current limit
CH2
FB2 UVP
Step-Down
Turn off whole IC
Turn off whole IC
Turn off whole IC
100ms
Turn off whole IC
P-MOSFET current > 1.6A 100ms
Turn off whole IC
FB2 < 0.3V
No delay Turn off whole IC
FB2 Over Load FB2 < 0.7V
100ms
Turn off whole IC
Current limit
P-MOSFET current > 2A
100ms
Turn off whole IC
FB3 < 0.4V
No delay Turn off whole IC
CH3
FB3 UVP
Step-Down
FB3 Over Load FB3 < 0.7V
Current limit
CH4
FB4 UVP
Step-Down
100ms
Turn off whole IC
P-MOSFET current > 1.6A 100ms
Turn off whole IC
FB4 < 0.4V
FB4 Over Load FB4 < 0.7V
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5014-01 March 2013
No delay Turn off whole IC
100ms
Turn off whole IC
Reset Method
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN pin set to low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN pin set to low
VDDM power reset or
EN = low
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RT5014
Protection
Type
CH5
Step-Up
CH6 Async
Inverting
Threshold
(typical value)
Current limit
N-MOSFET current > 1.2A
PVD5 OVP
PVDD5 > 22V
PVD5 UVP
PVD5 < DV5 + LDOH x 0.5
PVD5 Over
Load
Delay
Time
VDDM power reset or
EN = low
VDDM power reset or
No delay Turn off whole IC
EN = low
VDDM power reset or
100ms
Turn off whole IC
EN = low
Turn off whole IC
PVD5 < target − 2V for
A2.LODH ≠ 4'b0000;
PVD5 < target − 1V for
A2.LODH = 4'b0000
100ms
Turn off whole IC
Current limit
P-MOSFET current > 1.5A
100ms
Turn off whole IC
VOUT6 OVP
PVD6 < −13V
No delay Turn off whole IC
FB6 UVP
FB6 > 0.8V
100ms
Turn off whole IC
FB6 Over Load FB6 > 0.55V
100ms
Turn off whole IC
Current limit
N-MOSFET current > 0.8A
100ms
Turn off whole IC
PVD7 OVP
PVD7 > 9V for
A0.OVP7 = 2'b00;
PVD7 > 15V for
A0.OVP7 = 2'b01;
PVD7 > 25.5V for
A0.OVP7 = 2'b1X
No delay Turn off whole IC
Current limit
P-MOSFET current > 120mA No delay
LDOH UVP
LDOH < target x 0.5
Current limit
P-MOSFET current > 300mA No delay
Limit P-MOSFET
Current
Reset by load
VOA UVP
VOA < target x 0.5
Turn off whole IC
VDDM power reset or
EN = low
Current limit
P-MOSFET current > 300mA No delay
Limit P-MOSFET
Current
Reset by load
VOD1 UVP
VOD1 < target x 0.5
Turn off whole IC
VDDM power reset or
EN = low
Current limit
P-MOSFET current > 400mA No delay
Limit P-MOSFET
Current
Reset by load
VOD2 UVP
VOD2 < target x 0.5
Turn off whole IC
VDDM power reset or
EN = low
Current limit
P-MOSFET current > 400mA No delay
Limit P-MOSFET
Current
Reset by load
VOM UVP
VOM < target x 0.5
Turn off whole IC
VDDM power reset or
EN = low
Current limit
P-MOSFET current > 130mA No delay
Limit P-MOSFET
Current
Reset by load
Thermal
shutdown
Temperature > 155°C
CH8 LDO
100ms
CH10 LDO
100ms
CH11 LDO
100ms
CH12 LDO
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Limit P-MOSFET
Current
No delay Turn off whole IC
CH9 LDO
Thermal
Reset Method
100ms
CH7 WLED
RTC LDO
Protection
Methods
100ms
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
VDDM power reset or
EN = low
Reset by load
VDDM power reset or
EN = low
Temperature < 135°C,
No delay Turn off whole IC VDDM power reset or
EN = low
is a registered trademark of Richtek Technology Corporation.
DS5014-01 March 2013
RT5014
Outline Dimension
D
SEE DETAIL A
D2
L
1
E2
E
e
b
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
4.950
5.050
0.195
0.199
D2
3.250
3.500
0.128
0.138
E
4.950
5.050
0.195
0.199
E2
3.250
3.500
0.128
0.138
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS5014-01 March 2013
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