RT5002C - Farnell

®
RT5002C
7 + 1 Channel DC/DC PMU with Li-Ion Battery Charger for DSC
General Description
The RT5002C is a complete power supply solution for
digital still cameras and other handheld devices. It includes
a 7+1 channel DC/DC power converter unit, a single-cell
Li-ion battery charger, and an I2C control interface.
The power converter unit includes one synchronous stepup converter and three synchronous step-down converters
for DSP core, I/O, Motor, and memory power supply, one
synchronous high voltage step-up converter and one
asynchronous inverting converter for CCD± bias, one
WLED driver in either synchronous high voltage step-up
or current source operation, and one low quiescent LDO
for RTC application. All converters are internally frequency
compensated and integrate power MOSFETs. The power
converter unit provides complete protection functions: over
current, thermal shutdown, over voltage, over-load, and
under voltage protection.
The battery charger includes Auto Power Path
Management (APPM). No external MOSFETs are required.
The charger enters sleep mode when power is removed.
Charging tasks are optimized by using a control algorithm
to vary the charge rate, including pre-charge mode, fast
charge mode and constant voltage mode. The charge
current can also be programmed with an external resistor
and modified via the I2C control interface. The scope that
the battery regulation voltage can be modified via the I2C
interface depends on the battery temperature. The internal
thermal feedback circuitry regulates the die temperature
to optimize the charge rate for all ambient temperatures.
The charging task will always be terminated in constant
voltage mode when the charging current reduces to the
termination current of 10% x ICHG_FAST. The charger
includes under voltage and over-voltage protection for the
supply input voltage, VIN.
Features
Power Converter Unit :
One Channel LV Sync Step-Up and Three Channel
LV Sync Step-Down
Up to 95% Efficiency
One Sync Step-Up and One Async Inverting for
CCD±
± bias
One WLED Driver in either Sync Step-Up or Current
Source Operation
WLED Driver with Dimming Control
Step-Up Mode with LED Open Protection (OVP7)
One Low Quiescent LDO with Reverse Leakage
Prevention for RTC Power Supply
Preset On/Off Sequence of CH1, CH2, CH3, CH4
(1 → 3 → 4 → 2)
Three Preset On/Off Sequences of CH5, CH6 (5 → 6,
6 → 5, and 5/6 at the same time)
Simplified Application Circuit
Input Power
Chip Enable
2
I C Control
VIN
PVD1
LX2
LX3
EN1234
LX4
PVD5
VOUT6
SCL
PVD7
SDA
RTCPWR
BAT
GND
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
SYS
System Power
RT5002C
Step-Up For Motor
Step-Up/Down for I/O
Step-Down for DDR II
Step-Down for Core
HV Step-Up for CCD
HV Inverting for CCD
Step-Up for LED Backlight
LDO for RTC
Battery
is a registered trademark of Richtek Technology Corporation.
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RT5002C
All Power Switches Integrated with Internal
Compensation
All Step-Up Converters with Load Disconnect
Wake Up Impulse to Monitor BAT and VIN Plug-In
Ordering Information
RT5002C
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free)
Charger Unit :
28V Maximum Rating for VIN Power
Selectable Power Current Limit (0.1A / 0.5A / 1.5A)
Auto Power Path Management (APPM) and
Integrated Power MOSFETs
Battery Charging Current Control
Battery Regulation Voltage Control
Programmable Charging Current and Safe Charge
Timer
Under Voltage and Over Voltage Protection
Charge Status Indicator
Optimized Charge Rate via Thermal Feedback
Interrupt Indicator to Fault/Status Events
I2C Control Interface : Support Fast Mode up to
400kb/s
Small 40-Lead WQFN Package
RoHS Compliant and Halogen Free
Note :
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT5002CZQW : Product Number
RT5002C
ZQW
YMDNN
YMDNN : Date Code
Applications
DSC
Pin Configurations
LX1
PVD1
RTCPWR
VIN
SYS
SYS
BAT
BAT
PVD2
LX2
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
INT
FB1
VDDM
FB7
PVD7
LX7
CHG
LX4
PVD4
FB4
1
30
2
29
3
28
27
4
5
26
GND
6
25
7
24
8
41
23
22
9
21
10
WAKE
FB2
TSSEL
LX5
PVD5
FB5
EN1234
LX3
PVD3
FB3
ISETA
TS
VP
SDA
SCL
PVD6
LX6
VOUT6
FB6
VREF
11 12 13 14 15 16 17 18 19 20
WQFN-40L 5x5
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is a registered trademark of Richtek Technology Corporation.
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RT5002C
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
INT
Interrupt Indicator Open Drain Output. If any toggle events of TS_FAULT, PGOOD,
2
EOC, NoBAT, or SAFE happen, the output INT goes low. After I C register bank
address 0x2 is read or power on reset, INT goes high.
2
FB1
Feedback Input of CH1.
3
VDDM
4
FB7
5
PVD7
IC Analog Power Pin.
Feedback Input of CH7 in Step-Up Mode or Current Sink Pin of CH7 in Current
Source Mode.
Power Output of CH7.
6
LX7
Switch Node of CH7 in Step-Up Mode.
7
CHG
Charger Status Output. Open-drain output.
8
LX4
Switch Node of CH4.
9
PVD4
Power Input of CH4.
10
FB4
Feedback Input of CH4.
11
ISETA
12
TS
Charge Current Set Input. Connect a resistor (RISETA) between ISETA and GND.
Temperature Sense Input. The TS pin connects to a battery’s thermistor to
determine whether the battery is too hot or too cold to be charged. If the battery’s
temperature is out of range, charging is paused until it re-enters the valid range.
TS also detects whether the battery (with NTC) is present or not.
13
VP
Power Output of 3.3V Buffer for Battery Temperature Sensing.
14
SDA
Data Signal Pin of I C Interface.
15
SCL
Clock Signal Pin of I C Interface.
16
PVD6
Power Input of CH6.
17
LX6
Switch Node of CH6.
18
VOUT6
Sense Input of CH6 Inverting Output Node.
19
FB6
Feedback Input of CH6.
20
VREF
1.8V Reference Output.
21
FB3
Feedback Input of CH3.
22
PVD3
Power Input of CH3.
23
LX3
Switch Node of CH3.
24
EN1234
Enable Pin of CH1, CH2, CH3, and CH4.
25
FB5
Feedback Input of CH5.
26
PVD5
Power Output of CH5.
27
LX5
Switch Node of CH5.
28
TSSEL
Input Pin to Select Temperature Sensing Thresholds. Thresholds of TSSEL = H are
60% and 38% of VP voltage. Thresholds of TSSEL = L are 74% and 28% of VP
voltage.
29
FB2
Feedback Input of CH2.
30
WAKE
Wake-Up Impulse Push-Pull Output. If VIN or BAT plugs in, WAKE pin generates
one 90ms width high pulse to notify micro processor.
2
2
31
LX2
Switch Node of CH2.
32
PVD2
Power Input of CH2.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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January 2013
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RT5002C
Pin No.
Pin Name
33, 34
BAT
35, 36
SYS
37
VIN
Pin Function
Battery Charge Current Output.
System Connect. Connect this pin to system with a minimum 10μF ceramic
capacitor to GND.
Supply Voltage Input.
38
RTCPWR
RTC Power Output.
39
PVD1
Power Output of CH1.
40
LX1
41
GND
(Exposed Pad)
Switch Node of CH1.
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum thermal dissipation.
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is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Function Block Diagram
VDDM
SYS
Power On/Off Sequence
Control
EN1234
SCL
SDA
UVLO
SS
2
I C Interface Register File
VDDI
PVD1
VDDM
UVLO
VOUT5
VDDM
Body
Diode
Control
PVD6
Body
Diode
Control
CH1
C-Mode
Step-Up
LX1
CH5
C-Mode
Step-Up
LX5
+
FB5
1.25V
REF
0.8V
REF
FB1
VDDM
EN56
+
PVD2
VDDM
PVD6
CH2
C-Mode
Step-Down
CH6
Async
Inverting
LX6
VOUT6
LX2
FB6
0.6V REF
+
EN56
+
PVD7
FB2
0.8V
REF
VDDM
VDDM
PVD6
Body
Diode
Control
PVD3
CH7
Step-Up or
Current Source
+
31 Level Dimming
CH3
C-Mode
Step-Down
+
-
LX7
EN7
VREF
LX3
-
FB7
+
VREF
FB3
0.8V
REF
VDDM
1.8V
REF
PVD4
EN7_DIM7
TSSEL
ENCH
VIN
USUS
SYS
VSET
BAT
TS
Li+ Battery
Charger with
APPM
CH4
C-Mode
Step-Down
LX4
ISETL
-
ISETU
+
ISET
VP
CHG
VDDI
SAFE
RTC_LDO
w / Body Diode Control
INT
Interrupt Handler
EOC
TS_FAULT
PGOOD
SAFE
NoBAT
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
January 2013
FB4
0.8V
REF
GND
TIMER
ISETA
DS5002C-00
SYS
VIN
BAT
Power Plug-In
Wake Up Detector
RTCPWR
WAKE
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RT5002C
Charge Function Block Diagram
VIN
SYS
Thermal
Circuit
ISETA
Control
Circuit
BAT
ISET
Sleep
Mode
VSET
ISETL
CC/CV/TR
/DPPM
Multi Loop
Controller
Current
Set block
CHG
USUS
INT
OVP
UVLO
ENCH
Logic
ISETU
PGOOD
TS_FAULT
EOC
SAFE
NoBAT
2
I C bank
JEITA
2
I C Bank
TS
VP
TSSEL
NoBAT
I C bank
2
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GND
Timer
I C bank
2
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Operation
The RT5002C is an integrated power system for digital
still cameras and other small handheld devices. It includes
six DC/DC converters as well as one WLED driver, one
RTC LDO, and a fully integrated single-cell Li-ion battery
charger ideal for portable applications.
CH1 : Step-up synchronous current mode DC/DC converter
with internal power MOSFETs and compensation network.
The P-MOSFET body can be controlled to disconnect the
load. It is suitable for providing power to the motor.
CH2 to CH4 : Step-down synchronous current mode DC/
DC converter with internal power MOSFETs and
compensation network.
CH5 : High voltage step-up synchronous current mode
DC/DC converter with internal power MOSFET and
compensation network. The P-MOSFET body can be
controlled to disconnect the load.
CH6 : Asynchronous inverting current mode DC/DC
converter with internal power MOSFET and compensation
network. An external Schottky diode is required. This
channel supplies the CCD− bias.
CH7 : WLED driver operating in either current source mode
or synchronous step-up mode with internal power
MOSFET and compensation network. The operation mode
is determined via the I2C interface.
RTC_LDO : 3.05V output LDO with low quiescent current
and reverse leakage prevention from output node.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
Charger Unit
The RT5002C includes a Li-ion battery charger with
Automatic Power Path Management. The charger is
designed to operate in below modes.
Pre-charge Mode
When the output voltage is lower than 2.8V, the charging
current will be reduced to a fast-charge current ratio set
by RISETA to protect the battery life-time.
Fast-charge Mode
When the output voltage is higher than 3V, the charging
current will be equal to the fast-charge current set by
RISETA.
Constant Voltage Mode
When the output voltage is near 4.2V and the charging
current falls below the termination current, after a deglitch
time check of 25ms, the charger will become disabled
and CHG will go from L to H.
Re-charge Mode
When the chip is in charge termination mode, the charging
current gradually goes down to zero. However, once the
voltage of the battery drops to below 4.1V, there will be a
deglitch time of 100ms and then the charging current will
resume again.
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RT5002C
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, BAT --------------------------------------------------------------------------- −0.3V to 6V
Supply Voltage, VDDM -------------------------------------------------------------------------------- −0.3V to 6V
Supply Input Voltage, VIN ---------------------------------------------------------------------------- −0.3V to 28V
CHG, INT ------------------------------------------------------------------------------------------------- −0.3V to 28V
Other Pins ------------------------------------------------------------------------------------------------ −0.3V to 6V
Power Switch (DC) :
VOUT6 ---------------------------------------------------------------------------------------------------- −10V to 0.3V
LX1, LX2, LX3, LX4 ------------------------------------------------------------------------------------- −0.3V to 6V
PVD5, LX5 ------------------------------------------------------------------------------------------------ −0.3V to 24V
PVD7, LX7 ------------------------------------------------------------------------------------------------ −0.3V to 17V
LX6 --------------------------------------------------------------------------------------------------------- (PVD6 − 16V) to (PVD6 + 0.3V)
CHG, INT Continuous Current ----------------------------------------------------------------------- 20mA
BAT Continuous Current (total in two pins) (Note 2) ----------------------------------------- 2.5A
Power Dissipation, PD @ TA = 25°C
WQFN-40L 5x5 ----------------------------------------------------------------------------------------- 3.64W
Package Thermal Resistance (Note 3)
WQFN-40L 5x5, θJA ------------------------------------------------------------------------------------ 27.5°C/W
WQFN-40L 5x5, θJC ----------------------------------------------------------------------------------- 6°C/W
Junction Temperature ---------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------ 260°C
Storage Temperature Range ------------------------------------------------------------------------- −65°C to 125°C
ESD Susceptibility (Note 4)
HBM (Human Body Model) --------------------------------------------------------------------------- 2kV
MM (Machine Model) ---------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 5)
Supply Voltage, VDDM -------------------------------------------------------------------------------- 2.7V to 5.5V
Supply Input Voltage, VIN (ISETL = 1) ------------------------------------------------------------ 4.4V to 6V
Supply Input Voltage, VIN (ISETL = 0) ------------------------------------------------------------ 4.5V to 6V
Junction Temperature Range ------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
Power Converter Unit : (VDDM = 4.2V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
2.4
--
--
V
SYS UVLO (Hysteresis Low)
--
1.5
--
V
SYS UVLO Hysteresis (Gap)
--
0.2
--
V
Supply Voltage
SYS Startup Voltage for PMU
VST
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
5.82
6.0
6.18
V
--
−0.25
--
V
VDDM UVLO (Hysteresis High)
2.2
2.4
2.6
V
VDDM UVLO Hysteresis (Gap)
--
0.3
--
V
VDDM Over Voltage Protection
(OVP) (Hysteresis High)
VDDM OVP Hysteresis (Gap)
Supply Current
IOFF
All Channels are Off,
VEN1234 = 0V, VBAT = 4.2V
--
10
20
μA
IQ1
No Switching, VEN1234 = 3.3V
--
--
800
μA
IQ2
No Switching, VEN1234 = 3.3V
--
--
800
μA
IQ3
No Switching, VEN1234 = 3.3V
--
--
800
μA
IQ4
No Switching, VEN1234 = 3.3V
--
--
800
μA
IQ5
Non Switching, EN56 = 1
--
--
800
μA
IQ6
No Switching, EN56 = 1
--
--
800
μA
IQ7b
No Switching,
EN7_DIM7 [4:0] = 31
--
--
800
μA
IQ7c
EN7_DIM7 [4:0] = 31
--
--
800
μA
1800
2000
2200
kHz
CH7 in Step-Up Mode
900
1000
1100
kHz
VFB1 = 0.75V
80
83
86
%
VFB2 = 0.75V
--
--
100
%
VFB3 = 0.75V
--
--
100
%
VFB4 = 0.75V
--
--
100
%
VFB5 = 1.15V
91
93
97
%
CH6 Maximum Duty Cycle
(Inverting)
VFB6 = 0.7V
91
93
97
%
CH7 Maximum Duty Cycle (Step-Up)
VFB7 = 0.15V
91
93
97
%
0.788
0.8
0.812
V
1.237
1.25
1.263
V
0.58
0.6
0.62
V
0.237
0.25
0.263
V
Shutdown Supply Current
CH1 (Sync-Step-Up) Supply Current
into VDDM
CH2 (Syn-Step-Down) Supply
Current into VDDM
CH3 (Syn-Step-Down)
Supply Current into VDDM
CH4 (Syn-Step-Down)
Supply Current into VDDM
CH5 (Syn-Step-Up)
Supply Current into VDDM
CH6 (Inverting)
Supply Current into VDDM
CH7 (W LED) in Step-Up Mode
Supply Current into VDDM
CH7 (W LED) in Current Source
mode Supply Current into VDDM
Oscillator
CH1, 2, 3, 4 Operation Frequency
fOSC
CH5, 6, 7 Operation Frequency
fOSC2
CH1 Maximum Duty Cycle (Step-Up)
CH2 Maximum Duty Cycle
(Step-Down)
CH3 Maximum Duty Cycle
(Step-Down)
CH4 Maximum Duty Cycle
(Step-Down)
CH5 Maximum Duty Cycle (Step-Up)
Feedback, Output Regulation Voltage, and Output Regulation Current
Feedback Regulation Voltage @
FB1, FB2, FB3, FB4
Feedback Regulation Voltage @
FB5
Feedback Regulation Voltage @
FB6 (Inverting)
Feedback Regulation Voltage @
FB7 (Step-Up mode and current
EN7_DIM7 [4:0] = 31
source mode)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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January 2013
is a registered trademark of Richtek Technology Corporation.
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RT5002C
Parameter
Reference
VREF Output Voltage
(VREF-FB6) Regulation Voltage
VREF Load Regulation
Power Switch
CH1 On Resistance of MOSFET
Symbol
Test Conditions
Min
Typ
Max
Unit
1.77
1.182
--
1.8
1.2
--
1.83
1.218
10
V
V
mV
--2.2
200
150
3
300
250
4
--1.4
200
150
1.8
300
250
2.2
P-MOSFET, VPVD3 = 3.3V
N-MOSFET, VPVD3 = 3.3V
---
300
300
400
400
P-MOSFET, VPVD4 = 3.3V
N-MOSFET, VPVD4 = 3.3V
1.2
--1.2
1.6
300
300
1.6
2
400
400
2
mΩ
VREF
0μA < IREF < 200μA
P-MOSFET, VPVD1 = 3.3V
N-MOSFET, VPVD1 = 3.3V
CH1 Current Limitation (Step-Up)
CH2 On Resistance of MOSFET
P-MOSFET, VPVD2 = 3.3V
N-MOSFET, VPVD2 = 3.3V
CH2 Current Limitation (Step-Down)
CH3 On Resistance of MOSFET
CH3 Current Limitation (Step-Down)
CH4 On Resistance of MOSFET
CH4 Current Limitation (Step-Down)
mΩ
A
mΩ
A
mΩ
A
A
CH5 On Resistance of P-MOSFET
CH5 On Resistance of N-MOSFET
CH5 Current Limitation (Step-Up)
CH6 On Resistance of MOSFET
CH6 Current Limitation (Inverting)
CH7 On Resistance of P-MOSFET
VPVD5 = 16V
VDDM = 3.3V
N-MOSFET
P-MOSFET, VPVD6 = 3.3V
P-MOSFET
VPVD7 = 10V
--0.9
-1
--
1.1
0.6
1.2
0.5
1.5
2.0
1.5
0.8
1.6
0.7
2
3.0
Ω
Ω
A
Ω
A
Ω
CH7 On Resistance of N-MOSFET
CH7 Current Limitation (Step-Up)
VDDM = 3.3V
N-MOSFET
-0.6
0.9
0.8
1.1
1
Ω
A
5.82
20
6.0
22
6.18
24
V
V
--
−13
--
V
14.2
15
16
V
--
VSYS
−0.8V
--
V
0.35
0.4
0.45
V
0.5
0.6
0.7
V
1.1
1.2
1.3
V
0.65
0.7
0.75
V
1.05
1.1
1.15
V
0.69
0.74
0.79
V
--
100
--
ms
Protection
Over Voltage Protection of PVD1
Over Voltage Protection of PVD5
Over Voltage Protection of VOUT6
Over Voltage Protection of PVD7
(Step-Up mode)
CH1 Step-Up Under Voltage
Protection of PVD1
CH1/2/3/4 Under Voltage Protection
CH5 Under Voltage Protection
CH6 Under Voltage Protection
CH1/2/3/4 Overload Protection
CH5 Overload Protection
CH6 Overload Protection
At VFBx < 0.4V after soft-start
ends
At VFB5 < 0.6V after soft-start
ends
At VFB6 > 1.2V after soft-start end
At VFBx < 0.72V after fault delay
(100ms)
At VFB5 < 1.1V after fault delay
(100ms)
At VFB6 > 0.74V after fault delay
(100ms)
Protection Fault Delay
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Parameter
Control
EN1234, TSSEL
Input Voltage
Threshold
Symbol
Test Conditions
Min
Typ
Max
Logic-High
1.3
--
--
Logic-Low
--
--
0.4
--
1
6
μA
EN1234, TSSEL Sink Current
Unit
V
Thermal Protection
Thermal Shutdown
TSD
--
155
--
°C
Thermal Shutdown Hysteresis
ΔTSD
--
20
--
°C
RTC LDO
Standby Current
VDDM = 4.2V
--
3
6
μA
VOUT (RTCPWR)
Max Output Current
(Current Limit)
IOUT = 0mA, VDDM = 4.2V
3
3.05
3.1
V
VDDM = 4.2V
60
130
200
mA
IOUT = 50mA
--
--
1000
IOUT = 10mA
--
--
150
IOUT = 3mA
--
--
60
--
90
--
Dropout Voltage
mV
WAKE Up Detector
VIN or BAT plug in,
RTCPWR = 3.05V
Source Current 0.5mA,
VWAKE_H
RTCPWR = 3.05V
Sink Current −0.5mA,
VWAKE_L
RTCPWR = 3.05V
RTCPWR = 3.05V
WAKE Impulse High Duration
tWAKEUP
High Level
WAKE Output
ms
RTCPWR
RTCPWR
− 0.3
--
V
0
0.3
--
3.6
3.8
4
V
BAT Threshold to Wake Up
--
3
--
V
BAT Threshold Hysteresis to Wake Up
--
200
--
mV
Low Level
VIN Threshold to Wake Up
Charger Unit : (VIN = 5V, VBAT = 4V, TA = 25°C, unless otherwise specified)
Parameter
Supply Input
VIN Under Voltage Lockout
Threshold
VIN Under Voltage Lockout
Hysteresis
VIN Supply Current
Symbol
Test Conditions
Min
Typ
Max
Unit
VUVLO
VIN = 0V to 5V
3.6
3.8
4
V
ΔVUVLO
VIN = 5V to 0V
--
240
--
mV
ISYS = IBAT = 0mA, ENCH = 1
(VBAT > VREGx)
--
1
2
ISYS = IBAT = 0mA, ENCH = 0
(VBAT > VREGx)
--
0.8
1.5
VIN = 5V, USUS = 1
--
195
300
μA
ISUPPLY
mA
VIN Suspend Current
IUSUS
VIN − BAT VOS Rising
VOS_H
--
200
300
mV
VIN − BAT VOS Falling
VOS_L
10
50
--
mV
4.4
4.5
4.6
V
Voltage Regulation
System Regulation Voltage
VSYS
ISYS = 800mA
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
11
RT5002C
Parameter
Symbol
Battery Regulation Voltage
VREG1
Battery Regulation Voltage
VREG2
APPM Regulation Voltage
ΔVAPPM
Test Conditions
0 to 85°C, Loading = 20mA,
when VSET = 1
0 to 85°C, Loading = 20mA,
when VSET = 0
VSYS − VAPPM
Min
Typ
Max
Unit
4.16
4.2
4.23
V
4.01
4.05
4.08
V
120
200
280
mV
DPM Regulation Voltage
VIN to SYS MOSFET
On-Resistance
BAT to SYS MOSFET
On-Resistance
Re-Charge Threshold
VDPM
ISETL = 0
4.3
4.4
4.5
V
IVIN = 1000mA
--
0.2
0.35
Ω
VBAT = 4.2V, ISYS = 1A
--
0.05
0.1
Ω
ΔVREGCHG Battery Regulation − Recharge Level
60
100
140
mV
VBAT = 4V, R ISETA = 1kΩ
--
2
--
V
100
--
1200
mA
570
600
630
mA
285
1.2
450
90
300
1.5
475
95
315
1.8
500
100
mA
A
2.7
2.8
2.9
V
--
200
--
mV
VBAT = 2V
5
10
15
%
ISETL = 0, ISETU = 1
ISETL = 1, ISETU = X
5
10
15
%
ISETL = 0, ISETU = 0
--
3.3
--
%
Current Regulation
ISETA Set Voltage
(Fast Charge Phase)
VISETA
Charge Current Setting Range ICHG
Charge Current Accuracy1
ICHG1
Charge Current Accuracy2
ICHG2
VIN Current Limit
IVIN
Pre-Charge
BAT Pre-Charge Threshold
BAT Pre-Charge Threshold
Hysteresis
Pre-Charge Current
VPRECH
VBAT = 4V, R ISETA = 1kΩ
ISET = 1
VBAT = 3.8V, RISETA = 1kΩ, ISET = 0
ISETL = 1 (1.5A Mode)
ISETL = 0, ISETU = 1 (500mA Mode)
ISETL = 0, ISETU = 0 (100mA Mode)
BAT Falling
ΔVPRECH
ICHG_PRE
Charge Termination Detection
Termination Current Ratio to
Fast Charge (Except USB 100 ITERM
Mode)
Termination Current Ratio to
I
Fast Charge (USB100 Mode) TERM2
mA
Login Input/Output
CHG Pull Down Voltage
VCHG
ICHG = 5mA
--
200
--
mV
INT Pull Down Voltage
VINT
IINT = 5mA
--
200
--
mV
TREG
--
125
--
°C
TSD
--
155
--
°C
-6.25
20
6.5
-6.75
°C
V
Protection
Thermal Regulation
Thermal Shutdown
Temperature
Thermal Shutdown Hysteresis
Over Voltage Protection
Over Voltage Protection
Hysteresis
Output Short Circuit Detection
Threshold
Battery Installation Detection
Threshold at TS
ΔTSD
VOVP
VIN Rising
ΔVOVP
VIN = 7V to 5V, VOVP − ΔVOVP
--
100
--
mV
VSHORT
VBAT − VSYS
--
300
--
mV
EN1234 = H
--
90
--
% of
VP
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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12
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Parameter
Time
Pre-Charge Fault Time
Fast charge Fault Time
tPCHG
tFCHG
PGOOD Deglitch Time
tPGOOD
Input Over Voltage Blanking
Time
Pre-Charge to Fast-Charge
Deglitch Time
Fast-Charge to Pre-Charge
Deglitch Time
Termination Deglitch Time
Recharge Deglitch Time
Input Power Loss to SYS LDO
Turn-Off Delay Time
Pack Temperature Fault
Detection Deglitch Time
Short Circuit Deglitch Time
Short Circuit Recovery Time
Other
VP Regulation Voltage
VP Load Regulation
VP Under Voltage Lockout
Threshold
TS Battery Detect Threshold
NTC
Symbol
2250 2700
18000 21600
Unit
s
s
s
tOVP
--
50
--
μs
tPF
--
25
--
ms
tFP
--
25
--
ms
tTERMI
tRECHG
---
25
100
---
ms
ms
tNO_IN
--
25
--
ms
tTS
--
25
--
ms
tSHORT
tSHORT-R
---
250
64
---
μs
ms
3.234
--
3.3
--
3.366
−0.1
V
V
--
0.8
--
V
2.75
2.85
2.95
V
73
74
75
59
60
61
--
1
--
27
28
29
37
38
39
--
1
--
63
64
65
53
54
55
--
1
--
34
39
35
40
36
41
--
1
--
VVP
VVP
VDDM = 4.2V
VP Source Out 2mA
Falling Threshold
VTS
ΔVCOLD
High Temperature Trip Point
(60°C)
VHOT
High Temperature Trip Point
Hysteresis (near 60°C)
ΔVHOT
Rising Threshold when
TSSEL = L (100k NTC)
Rising Threshold when
TSSEL = H (10k NTC)
Falling Threshold when
TSSEL = L
Falling Threshold when
TSSEL = H
Rising Threshold when
TSSEL = L (100k NTC)
Rising Threshold when
TSSEL = H (10k NTC)
Falling Threshold when TSSEL = L
Falling Threshold when TSSEL = H
High Temperature Trip Point
Hysteresis (near 45°C) for JEITA
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
January 2013
Max
--
Low Temperature Trip Point
Hysteresis (near 0°C)
DS5002C-00
1800
14400
Typ
1
VCOLD
Low Temperature Trip Point
Hysteresis (near 10°C) for JEITA
High Temperature Trip Point
(45°C) for JEITA
TIMER [3:0] = 0100, (1/8 x tFCHG)
TIMER [3:0] = 0100
Time measured from VIN :
0 to 5V 1μs rise-time to
PGOOD = 1 in I 2C Register
Min
--
Low Temperature Trip Point
(0°C)
Low Temperature Trip Point
(10°C) for JEITA
Test Conditions
%
of VP
%
of VP
%
of VP
%
of VP
%
of VP
%
of VP
%
of VP
%
of VP
is a registered trademark of Richtek Technology Corporation.
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13
RT5002C
(VDDM = 3.3V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Logic-High
2.0
--
--
Logic-Low
--
--
0.8
--
--
400
kHz
Logic Inputs (SDA SCL)
SDA, SCL Input
Threshold Voltage
V
2
I C Timing Characteristics
SCL Clock Rate
Hold Time (Repeated) START
Condition. After this period, the
first clock pulse is generated
f SCL
VDDM = 3.3V
t HD;STA
0.6
--
--
μs
LOW Period of SCL Clock
t LOW
1.3
--
--
μs
HIGH Period of SCL Clock
t HIGH
Set-up Time for Repeated START t SU;STA
Condition
Data Hold Time
t HD;DAT
0.6
--
--
μs
0.6
--
--
μs
0
--
0.9
μs
Data Set-up Time
t SU;DAT
100
--
--
ns
Set-up Time for STOP Condition
Bus Free Time between a STOP
and START Condition
Rise Time of both SDA and SCL
Signals
Fall Time of both SDA and SCL
Signals
SDA and SCL Output Low Sink
Current
t SU;STO
0.6
--
--
μs
t BUF
1.3
--
--
μs
tR
20
--
300
ns
tF
20
--
300
ns
2
--
--
mA
I OL
SDA or SCL Voltage = 0.4V
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. Guaranteed by design.
Note 3. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 4. Devices are ESD sensitive. Handling precaution is recommended.
Note 5. The device is not guaranteed to function outside its operating conditions.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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14
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Typical Application Circuit
For 4-LED Application
L5 10µH
SYS
CCD
15V
27
C14
4.7µF
R9
287k
L1
2.2µH
PVD5
FB1
R10
26.1k
R1
470k
2
16
SYS
C15
10µF
L6 10µH
FB5
PVD2 32
PVD6
LX2
17
LX6
FB2
SYS
C3
10µF
L2
31 2.2µH
C4
10µF
29
18
C17
1nF
PVD3
19
C18
0.1µF
R12
10k
20
5
Back Light
C19
1µF
D2
D3
SYS
D4
VOUT6
R11
63.4k
L7
10µH
6
C20
1µF
D5
4
FB6
TSSEL = VIN
for 10k NTC
ADAPTER
/USB
28
C21
2.2µF
FB3
RISETA
RNTC
~10k
R16
FB7
LX4 8
C8
10µF
1
RTCPWR 38
R20 1k
SYS
30 WAKE
Bypass Cap
1µF
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
2
VDD_I C
R15
1k
SDA 14
EN1234
24
SYS 35, 36
7 CHG
Charge Indicator
C11
47pF
VCORE
C10 1V
10µF
RTCPWR
R14
1k
Interrupt Flag
Wake Up Signal to µP
SYS
Super Cap
TS
INT
1.8V
C6
10µF
R8
931k
SCL 15
R18 10k
January 2013
R7
232k
10
BAT
VP
C7
33pF
L4
2.2µH
11 ISETA
13
DS5002C-00
R5
470k
VDDM 3
12
C23
0.1µF
FB4
SYS
R6
374k
PVD4 9
TSSEL
R3
470k
DDRII
21
LX7
R17
VI/O
3.3V
L3
2.2µH
PVD7
C22
1µF
+
C5
10µF
37 VIN
33, 34
BAT
22
LX3 23
VREF
R13
10
VI/O
3.3V
R4
150k
D1
C16
10µF x 2
C24
4.7pF
R2
88.7k
25
CCD
-7V
Motor
5V
PVD1 39
C1
10µF x 2
C13
10µF x 2
SYS
C2
10µF
RT5002C
26
C12
27pF
LX1 40
LX5
GND
EN1234 Control
Chip Enable CH1 CH3 CH4
5V
1.8V 1V
C9
10µF
CH2
3.3V
SYS
41 (Exposed Pad)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT5002C
For 1-LED Application
L5 10µH
SYS
CCD
15V
27
C14
4.7µF
R9
287k
PVD5
16
SYS
R2
88.7k
L6
10µH
LX2
17
D1
C17
1nF
18
LX6
20
5
5V
C19
1µF
6
4
R13
10
TSSEL = GND
for 100k NTC
ADAPTER
/USB
28
C21
2.2µF
FB6
VREF
FB3
RISETA
RNTC
~100k
3.3V
R3
470k
L3
2.2µH
R5
470k
21
PVD4 9
TSSEL
LX4 8
FB4
C7
33pF
C6
10µF
DDRII
1.8V
R6
374k
C8
10µF
LX7
FB7
SYS
L4
2.2µH
R7
232k
10
SYS
C11
47pF
C10
10µF
VCORE
1V
R8
931k
RTCPWR 38
RTCPWR
Super Cap
BAT
3
Bypass Cap
1µF
11 ISETA
2
VDD_I C
R16
12
R14
1k
TS
R17
R15
1k
SCL 15
13
R18 10k
C23
0.1µF
C5
10µF
PVD7
VDDM
1
VP
R20 1k
SYS
SDA 14
INT
EN1234
Interrupt Flag
Wake Up Signal to µP
30 WAKE
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
24
EN1234 Control
Chip Enable CH1 CH3 CH4
5V
1.8V 1V
SYS 35, 36
C9
10µF
7 CHG
Charge Indicator
www.richtek.com
16
22
LX3 23
C22
1µF
+
VI/O
3.3V
29
37 VIN
33, 34
BAT
VI/O
C4
10µF
Back Light
D6
5V
C3
10µF
L2
31 2.2µH
VOUT6
PVD3
19
R12
10k
FB2
SYS
R4
150k
R11
63.4k
C18
0.1µF
PVD2 32
PVD6
C15
10µF
C24
4.7pF
L1
2.2µH
C2
10µF
FB5
Motor
5V
R1
470k
2
LX1 40
25
C16
10µF x 2
FB1
C13
10µF x 2
R10
26.1k
CCD
-7V
C1
10µF x 2
RT5002C
26
C12
27pF
PVD1 39
LX5
GND
CH2
3.3V
SYS
41 (Exposed Pad)
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Typical Operating Characteristics
CH2 Step-Down Efficiency vs. Output Current
100
90
90
80
80
70
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
60
50
40
30
=
=
=
=
=
=
=
4.5V
4.2V
3.9V
3.6V
3.3V
3V
2.7V
Efficiency (%)
Efficiency (%)
CH1 Step-Up Efficiency vs. Output Current
100
20
70
VBAT
VBAT
VBAT
VBAT
VBAT
60
50
40
=
=
=
=
=
3.4V
3.7V
3.9V
4.2V
4.5V
30
20
10
10
VOUT = 5V, L = 2.2μH, COUT = 10μF x 2
0
VOUT = 3.3V, L = 2.2μH, COUT = 10μF
0
10
100
1000
10
100
Output Current (mA)
Output Current (A)
CH3 Step-Down Efficiency vs. Output Current
CH4 Step-Down Efficiency vs. Output Current
100
100
90
90
80
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
70
60
50
40
=
=
=
=
=
=
=
2.7V
3V
3.3V
3.6V
3.9V
4.2V
4.5V
Efficiency (%)
Efficiency (%)
80
30
20
70
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
60
50
40
30
=
=
=
=
=
=
=
2.7V
3V
3.3V
3.6V
3.9V
4.2V
4.5V
20
10
10
VOUT = 1.8V, L = 2.2μH, COUT = 10μF
0
VOUT = 1V, L = 2.2μH, COUT = 10μF
0
10
100
1000
10
100
Output Current (mA)
CH6 Inverting Efficiency vs. Output Current
100
90
90
80
80
70
70
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
50
40
30
20
10
=
=
=
=
=
=
=
Efficiency (%)
100
60
1000
Output Current (mA)
CH5 Step-Up Efficiency vs. Output Current
Efficiency (%)
1000
4.5V
4.2V
3.9V
3.6V
3.3V
3V
2.7V
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
VBAT
60
50
40
30
=
=
=
=
=
=
=
4.5V
4.2V
3.9V
3.6V
3.3V
3V
2.7V
20
VOUT = 15V, L = 10μH, COUT = 10μF x 2
0
10
VOUT = −7V, L = 10μH, COUT = 10μF x 2
0
1
10
Output Current (mA)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
100
1
10
100
Output Current (mA)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
17
RT5002C
CH1 Step-Up Output Voltage vs. Output Current
CH7 Efficiency vs. Input Voltage
5.15
100
90
5.10
Output Voltage (V)
Efficiency (%)
80
70
60
50
40
30
20
5.05
VBAT = 3.4V
VBAT = 4.5V
5.00
4.95
4.90
10
4LEDs, L = 10μH, COUT = 10μF, IOUT = 25mA
VOUT = 5V
4.85
0
2.7
3
3.3
3.6
3.9
4.2
0
4.5
100
CH2 Step-Down Output Voltage vs. Output Current
400
500
1.825
3.32
1.820
3.31
VBAT = 3.6V
VBAT = 4.5V
3.29
1.815
1.810
VBAT = 4.5V
VBAT = 3.4V
VBAT = 2.7V
1.805
3.28
1.800
VOUT = 3.3V
VOUT = 1.8V
3.27
1.795
0
100
200
300
400
500
600
0
100
Output Current (mA)
300
400
500
600
CH5 Step-Up Output Voltage vs. Output Current
16.5
1.000
16.0
Output Voltage (V)
1.002
0.998
VBAT = 4.5V
VBAT = 3.4V
VBAT = 2.7V
0.996
200
Output Current (mA)
CH4 Step-Down Output Voltage vs. Output Current
Output Voltage (V)
600
CH3 Step-Down Output Voltage vs. Output Current
3.33
Output Voltage (V)
Output Voltage (V)
300
Output Current (mA)
Input Voltage (V)
3.30
200
0.994
0.992
15.5
VBAT = 4.5V
VBAT = 3.4V
VBAT = 2.7V
15.0
14.5
14.0
VOUT = 1V
0.990
VOUT = 15V
13.5
0
100
200
300
400
500
Output Current (mA)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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18
600
0
20
40
60
80
100
Output Current (mA)
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Power On Sequence
CH6 Inverting Output Voltage vs. Output Current
-7.110
VOUT_CH1
(5V/Div)
VOUT_CH2
(2V/Div)
Output Voltage (V)
-7.115
-7.120
VBAT = 4.5V
VBAT = 3.4V
VBAT = 2.7V
-7.125
VOUT_CH3
(2V/Div)
-7.130
VOUT_CH4
(1V/Div)
-7.135
VOUT = −7V
-7.140
0
0.02
0.04
0.06
0.08
VBAT = 3.7V
Time (2.5ms/Div)
0.1
Output Current (A)
Power On Sequence
Power Off Sequence
VOUT_CH1
(5V/Div)
VOUT_CH2
(2V/Div)
VOUT_CH5
(5V/Div)
VOUT_CH6
(5V/Div)
VOUT_CH3
(2V/Div)
VOUT_CH4
(1V/Div)
VBAT = 3.7V, MOD56 = 0, SEQ56 = 1
VBAT = 3.7V
Time (1ms/Div)
Time (5ms/Div)
Power Off Sequence
Power On Sequence
VOUT_CH5
(5V/Div)
VOUT_CH6
(5V/Div)
VOUT_CH5
(5V/Div)
VOUT_CH6
(5V/Div)
VBAT = 3.7V, MOD56 = 0, SEQ56 = 1
Time (5ms/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
VBAT = 3.7V, MOD56 = 0, SEQ56 = 0
Time (5ms/Div)
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
19
RT5002C
Power On Sequence
Power Off Sequence
VOUT_CH5
(5V/Div)
VOUT_CH6
(5V/Div)
VOUT_CH5
(5V/Div)
VOUT_CH6
(5V/Div)
VBAT = 3.7V, MOD56 = 0, SEQ56 = 0
VBAT = 3.7V, MOD56 = 1
Time (5ms/Div)
Time (5ms/Div)
Power Off Sequence
CH1 Output Voltage Ripple
VOUT_CH5
(5V/Div)
VOUT_CH6
(5V/Div)
LX1
(2V/Div)
V OUT_CH1_ac
(5mV/Div)
VBAT = 3.7V, VOUT = 5V,
IOUT = 400mA, L = 2.2μH, COUT = 10μF x 2
VBAT = 3.7V, MOD56 = 1
Time (5ms/Div)
Time (500ns/Div)
CH2 Output Voltage Ripple
CH3 Output Voltage Ripple
LX2
(2V/Div)
LX3
(2V/Div)
V OUT_CH2_ac
(5mV/Div)
V OUT_CH3_ac
(5mV/Div)
VBAT = 3.7V, VOUT = 3.3V,
IOUT = 400mA, L = 2.2μH, COUT = 10μF
Time (500ns/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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20
VBAT = 3.7V, VOUT = 1.8V,
IOUT = 400mA, L = 2.2μH, COUT = 10μF
Time (500ns/Div)
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
CH5 Output Voltage Ripple
CH4 Output Voltage Ripple
LX4
(2V/Div)
LX5
(5V/Div)
V OUT_CH4_ac
(5mV/Div)
V OUT_CH5_ac
(5mV/Div)
VBAT = 3.7V, VOUT = 1V,
IOUT = 400mA, L = 2.2μH, COUT = 10μF
VBAT = 3.7V, VOUT = 15V,
IOUT = 30mA, L = 10μH, COUT = 10μF x 2
Time (500ns/Div)
Time (1μs/Div)
CH6 Output Voltage Ripple
CH1 Load Transient Response
LX6
(5V/Div)
IOUT
(100mA/Div)
V OUT_CH1_ac
(100mV/Div)
V OUT_CH6_ac
(5mV/Div)
VBAT = 3.7V, VOUT = −7V,
IOUT = 50mA, L = 10μH, COUT = 10μF x 2
Time (1μs/Div)
Time (250μs/Div)
CH2 Load Transient Response
CH3 Load Transient Response
IOUT
(100mA/Div)
V OUT_CH2_ac
(50mV/Div)
IOUT
(100mA/Div)
V OUT_CH3_ac
(10mV/Div)
VBAT = 3.7V, VOUT = 3.3V,
IOUT = 0 to 300mA, L = 2.2μH, COUT = 10μF
Time (250μs/Div)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
VBAT = 3.7V, VOUT = 5V,
IOUT = 0 to 300mA, L = 2.2μH, COUT = 10μF x 2
January 2013
VBAT = 3.7V, VOUT = 3.3V,
IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF
Time (250μs/Div)
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21
RT5002C
CH5 Load Transient Response
CH4 Load Transient Response
IOUT
(100mA/Div)
V OUT_CH4_ac
(10mV/Div)
IOUT
(10mA/Div)
V OUT_CH5_ac
(50mV/Div)
VBAT = 3.7V, VOUT = 1V,
IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF
VBAT = 3.7V, VOUT = 15V,
IOUT = 10mA to 25mA, L = 10μH, COUT = 10μF x 2
Time (250μs/Div)
Time (250μs/Div)
CH6 Load Transient Response
Charge On/Off Control from EN
USB 500mA Mode
I 2C EN
(5V/Div)
V CHG
(5V/Div)
IOUT
(10mA/Div)
V OUT_CH6_ac
(20mV/Div)
VBAT
(5V/Div)
IBAT
(500mA/Div)
VBAT = 3.7V, VOUT = −7V,
IOUT = 10mA to 30mA, L = 10μH, COUT = 10μF x 2
VIN = 5V, VBAT = Real Battery, VVP = 3.3V
Time (250μs/Div)
Time (25ms/Div)
Charge On/Off Control from VIN
TS Inserted/Removed
USB 500mA Mode
VIN
(5V/Div)
V CHG
(5V/Div)
VBAT
(5V/Div)
VTS
(5V/Div)
IBAT
(500mA/Div)
VBAT
(2V/Div)
IBAT
(500mA/Div)
VIN = 5V, VBAT = Real Battery, VVP = 3.3V
Time (25ms/Div)
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22
V CHG
(5V/Div)
VIN = 5V, VBAT = Real Battery, VVP = 3.3V
Time (200μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
VIN Hot-Plug with NTC/without Battery
VIN Removal
IBAT
(1A/Div)
I IN
(500mA/Div)
V SYS
(5V/Div)
VBAT
(5V/Div)
V SYS
(5V/Div)
VBAT
(5V/Div)
VIN = 5V, VBAT = Real Battery,
VIN
(5V/Div)
VIN
(5V/Div)
VVP = 3.3V, RSYS = 10Ω, ISETL = 1
VIN = 5V, VVP = 3.3V, RSYS = 10Ω, ISETL = 1
Time (100ms/Div)
Time (100ms/Div)
VIN Hot-Plug without NTC/Battery
VIN Hot-Plug with Battery
IBAT
(500mA/Div)
I IN
(500mA/Div)
V SYS
(5V/Div)
VBAT
(5V/Div)
V SYS
(5V/Div)
VBAT
(5V/Div)
VIN
(5V/Div)
VIN
(5V/Div)
VIN = 5V, VBAT = Real Battery,
VVP = 3.3V, RSYS = 10Ω, ISETL = 1
VIN = 5V, VVP = 3.3V, RSYS = 10Ω, ISETL = 1
Time (100ms/Div)
Time (100ms/Div)
OVP Threshold Voltage vs. Temperature
System Regulation Voltage vs. Temperature
6.50
OVP Threshold Voltage (V)
System Regulation Voltage (V)1
4.550
4.525
4.500
4.475
4.450
4.425
6.45
Rising
6.40
6.35
Falling
6.30
6.25
VIN = 5V, ISYS = 0.5A
VIN = 5V, VBAT = 3.7V, VVP = 3.3V
6.20
4.400
-50
-25
0
25
50
75
100
Temperature (°C)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
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23
RT5002C
VBAT – VSYS Dropout Voltage vs. Temperature
– VSYS Dropout Voltage vs. Temperature
100
470
95
440
90
Dropout Voltage (mV)
Dropout Voltage (mV)
VIN
500
410
380
350
320
290
260
230
85
80
75
70
65
60
55
VIN = 5V, VVP = 3.3V, ISYS = 1A
VBAT = 3.7V, VVP = 3.3V, ISYS = 1A
50
200
-50
-25
0
25
50
75
100
-50
125
-25
0
Temperature (°C)
ICHG Thermal Regulation vs. Temperature
75
100
125
Battery Regulation Voltage vs. Temperature
Battery Regulation Voltage (V)1
450
Charge Current (mA)
50
4.30
500
400
350
300
250
200
150
100
VIN = 5V, VBAT = 3.7V,
VVP = 3.3V, USB 500mA Mode
50
4.25
4.20
4.15
4.10
4.05
VIN = 5V, VVP = 3.3V
4.00
0
-50
-25
0
25
50
75
100
-50
125
-25
Temperature (°C)
0
25
50
75
100
125
Temperature (°C)
Pre-Charge Current vs. Battery Voltage
Fast-Charge Current vs. Battery Voltage
140
800
120
750
Fast-Charge Current (mA)
Pre-Charge Current (mA)
25
Temperature (°C)
100
80
60
40
20
700
650
600
550
500
450
VIN = 5V, VVP = 3.3V, RISETA = 0.5kΩ, ISETL = 1
VIN = 5V, VVP = 3.3V, RISETA = 1kΩ, ISETL = 1
0
400
2
2.2
2.4
2.6
2.8
Battery Voltage (V)
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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24
3
3
3.2
3.4
3.6
3.8
4
4.2
Battery Voltage (V)
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Application Information
Power Converter Unit
Output Voltage Design Equation of CH1 to CH4 :
The RT5002C is an integrated power system for digital
still cameras and other small handheld devices. It includes
six DC/DC converters as well as one WLED driver, one
RTC LDO, and a fully integrated single-cell Li-ion battery
charger ideal for portable applications.
The output voltage can be set by the following equation :
CH1 : Step-up synchronous current mode DC/DC converter
with internal power MOSFETs and compensation network.
The P-MOSFET body can be controlled to disconnect the
load. It is suitable for providing power to the motor.
CH2 to CH4 : Step-down synchronous current mode DC/
DC converter with internal power MOSFETs and
compensation network. These channels supply the power
for I/O, DRAM, and core. They can be operated at 100%
maximum duty cycle to extend battery operating voltage
range. When the input voltage is close to the output
voltage, the converter enters low dropout mode with low
output ripple.
CH5 : High voltage step-up synchronous current mode
DC/DC converter with internal power MOSFET and
compensation network. The P-MOSFET body can be
controlled to disconnect the load. This channel supplies
the CCD+ bias.
CH6 : Asynchronous inverting current mode DC/DC
converter with internal power MOSFET and compensation
network. An external Schottky diode is required. This
channel supplies the CCD− bias.
CH7 : WLED driver operating in either current source mode
or synchronous step-up mode with internal power
MOSFET and compensation network. The operation mode
is determined via LX7 detection. The P-MOSFET body in
step-up mode can be controlled to disconnect the load.
CH1 to CH4 operate in PWM mode with 2MHz, while
CH5 to CH7 operate in PWM mode with 1MHz switching
frequency.
VOUT = (1 + RH / RL) x VFB
where VFB is 0.8V typically, RH is R1, R3, R5, and R7
respectively for CH1 to 4, and RL is R2, R4, R6, and R8
respectively for CH1 to 4.
Output Voltage Design Equation of CH5 :
The output voltage can be set by the following equation:
VOUT_CH5 = (1 + R9 / R10) x VFB5
where VFB5 is 1.25V typically.
Output Voltage Design Equation of CH6 :
The output voltage can be set by the following equation :
VOUT_CH6 = −(R11 / R12) x (1.2V) + 0.6V
where R11 and R12 are the feedback resistors connected
to FB6, 1.2V equals to (VREF − VFB6), and 0.6V is the
typical value of VFB6.
Reference Voltage
The RT5002C provides a precise 1.8V reference voltage,
VREF, with sourcing capability of 100μA. Connect a 0.1μF
ceramic capacitor from the VREF pin to GND. Reference
voltage is enabled by I 2C register bit EN56 = 1.
Furthermore, this reference voltage is internally pulled to
GND at shutdown.
CH5 and CH6 Power Sequence :
CH5 and CH6 are enabled together via I2C interface and
their power on sequence can be chosen via I2C register
setting as following table.
MOD56
0
0
1
SEQ56
0
1
X
Power On
CH6
CH5
CH5
CH6
Same Time
Power Off
CH5
CH6
CH6
CH5
Same Time
RTC_LDO : 3.05V output LDO with low quiescent current
and reverse leakage prevention from output node.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
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25
RT5002C
EN56 (MOD56 = 0, SEQ56 = 1)
EN56
10ms
Wait until VOUT6 > -0.12V
Constant Current Pre-Charge.
CH5 VOUT
18ms
8ms
CH6 VOUT
EN56 (MOD56 = 0, SEQ56 = 0)
EN56
16ms
10ms
Constant
Current PreCharge.
CH5 VOUT
2ms
8ms
Wait until VOUT5 < 0.5V
CH6 VOUT
EN56 (MOD56 = 1, SEQ56 = X)
EN56
10ms
Constant Current Pre-Charge.
CH5 VOUT
2ms
8ms
CH6 VOUT
CH7 : WLED Driver
CH7 is a WLED driver that can operate in either current
source mode or synchronous step-up mode, as determined
by LX7 detection. When CH7 works in current source
mode, it sources an LED current out of LX7 pin and
regulates the current by FB7 voltage. The LED current is
defined by the FB7 voltage as well as the external resistor
between FB7 and GND. The FB7 regulation voltage can
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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26
be set in 31 steps from 8mV to 250mV, typically, via I2C
interface. If CH7 works in synchronous step-up mode, it
integrates synchronous step-up mode with an internal
MOSFET and internal compensation to output a voltage
up to 15V. The LED current is also set via an external
resistor and FB7 regulation voltage.
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
b[7]
(MSB)
b[6]
b[5]
Meaning
MOD56
SEQ56
EN56
Default
0
0
Read/Write
R/W
R/W
Address
0x0
b[4]
b[3]
0
0
0
R/W
R/W
R/W
b[1]
b[0]
(LSB)
0
0
0
R/W
R/W
R/W
b[2]
EN7_DIM7 [4:0]
MOD56
1
0
CH5/6 power on/off sequence at the same time
CH5/6 power sequence is determined by SEQ56
SEQ56
1
0
CH5/6 power on sequence is CH5 Æ CH6, power off sequence is CH6 Æ CH5
CH5/6 power on sequence is CH6 Æ CH5, power off sequence is CH5 Æ CH6
EN56
1
0
Enable (turn on) CH5 and CH6 by preset sequence
Disable (turn off) CH5 and CH6 by preset
Enable CH7 and define FB7 regulation voltage
00000
Ch7 turn off
EN7_DIM7
00001 to
[4:0]
Ch7 turn on and dimming ratio : VFB7 = EN7_DIM7 [4:0] / 31 x 0.25V
11111
CH7 WLED Current Dimming Control
RTC LDO
If CH7 is in synchronous step-up mode or current source
mode, the WLED current is set by an external resistor.
Regardless of the mode, dimming is always controlled
by the I2C interface.
The RT5002C provides a 3.05V output LDO for real-time
clock. The LDO features low quiescent current (3μA) and
high output voltage accuracy. This LDO is always on, even
when the system is shut down. For better stability, it is
recommended to connect a 0.1μF capacitor to the
RTCPWR pin. The RTC LDO includes pass transistor body
diode control to avoid the RTCPWR node from backcharging into the input node VDDI.
The WLED current can be set by the following equations :
ILED (mA) = [250mV / R (W)] x EN7_DIM7 [4:0] / 31
where R is the current sense resistor from FB7 to GND
and EN7_DIM7 [4:0] / 31 ratio refers to the I2C control
register file. It is recommended that CH7 input power
connects to the node SYS in order to prevent abnormal
CH7 start-up.
VDDM Bootstrap
To support bootstrap function, the RT5002C includes a
power selection circuit which selects between SYS and
PVD1 to create the internal node voltage VDDI and VDDM.
VDDM is the power of the RT5002C PMU control circuits
which must be connected to an external decoupling
capacitor by way of the VDDM pin. VDDI is the power
input of the RTC LDO. The output PVD1 of CH1 can
bootstrap VDDM and VDDI. The RT5002C includes UVLO
circuits to monitor VDDM and SYS voltage status.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
Power On/Off Sequence for CH1 to CH4
EN1234 will turn on/off CH1 to CH4 in preset sequence.
CH1 to CH4 Power on Sequence is :
When EN1234 goes high, CH1 will turn on first. 3.5ms
after CH1 is turned on, CH3 will turn on. 3.5ms after CH3
is turned on, CH4 will turn on. 3.5ms after CH4 is turned
on, CH2 will turn on.
CH1 to CH4 Power off Sequence is :
When EN1234 goes low, CH2 will turn off first and internally
discharge output. When FB2 < 0.1V, CH4 will turn off and
also internally discharge output via the LX4 pin. When
FB4 < 0.1V, CH3 will turn off and internally discharge output
via the LX3 pin. Likewise, when FB3 < 0.1V, CH1 will turn
off and discharge output. After FB1 < 0.1V, CH1 to 4
shutdown sequence will be completed.
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27
RT5002C
Charger Unit
Constant Voltage Mode
The RT5002C includes a Li-ion battery charger with
Automatic Power Path Management. The charger is
designed to operate in below modes :
When the output voltage is near 4.2V and the charging
current falls below the termination current, after a deglitch
time check of 25ms, the charger will become disabled
and CHG will go from L to H.
Pre-charge Mode
When the output voltage is lower than 2.8V, the charging
current will be reduced to a fast-charge current ratio set
by RISETA to protect the battery life-time.
Fast-charge Mode
When the output voltage is higher than 3V, the charging
current will be equal to the fast-charge current set by
RISETA.
Re-charge Mode
When the chip is in charge termination mode, the charging
current gradually goes down to zero. However, once the
voltage of the battery drops to below 4.1V, there will be a
deglitch time of 100ms and then the charging current will
resume again.
I2C Register for Charging Status Setting
0x2
b[0]
(LSB)
b[7]
(MSB)
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
Meaning
ISETU
ISETL
USUS
NoBAT
EOC
PGOOD
TS_FAULT
Default
Read/Write
1
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
Address
SAFE
0
R
ISETU and ISETL : Set VIN Input Current Limit
ISETU
ISETL
VIN Input Current Limit
0
0
95mA
1
0
475mA
X
1
1.5A
USUS : VIN Suspend Control Input
1
Suspend
USUS
0
No Suspend
Battery Installation Detection
NoBAT
1
0
No Battery Installed (TS > 90% of VP)
BAT Installed (TS < 90% of VP)
End_Of_Charge Status
EOC
1
0
VIN Power Good Status
0
PGOOD
Charging Done or Recharging after Termination
During Charging
VIN < VUVLO
0
VUVLO < VIN < VBAT + VOS_H
1
VBAT + VOS_H < VIN < VOVP
0
VIN > VOVP
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is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Temperature Sensing Status
1
0
TS_FAULT
TS is at fault (too cold, too hot) or VP triggers UVLO.
TS and VP are normal.
Charger Safety Timer Status
SAFE
1
Safety timer expired.
0
Otherwise
Interrupt Indicator
Battery Installation Detection
The RT5002C provides the interrupt indicator output pin
(INT). INT is an open drain pin.
RT5002C also detect TS voltage to judge the battery
installation status. If PMU is enabled but TS voltage >
90% of VP node voltage, RT5002C would set the bit
NoBAT = 1 in I2C register bank 0x2.
When the status bits (PGOOD, TS_FAULT, EOC, SAFE,
NoBAT) of I2C register address 0x2 toggle, the INT is set
to be low. After Reg 0x2 is read or PMU is turned off, INT
goes high.
End_Of_Charge (EOC) Status
The bit EOC in I2C register bank 0x2 can show the EOC
status. If EOC = 1, the Charger is in EOC State.
Wake-Up Detector
Wake-Up Detector detects VIN or BAT plug-in events. Once
BAT plugs in or VIN plugs in when BAT exist, WAKE pin
asserts one 90ms width high pulse. The timing diagram
is shown below.
Suspend Mode
Set USUS = 1, and the charge will enter Suspend Mode.
In Suspend Mode, CHG is in high impedance and
IUSUS(MAX) < 300μA.
WAKE Timing Diagram
3.8V
VIN
BAT > 3V
3V
3V
BAT
WAKE
90ms
VIN > 3.8V ٛ
↑ WAKE Up
90ms
90ms
BAT > 3V ٛ
↑ WAKE Up
90ms
VIN > 3.8V when BAT > 3V
↑ WAKE Up
When PMU is enabled, WAKEUP impulse would be
masked off. WAKE impulse width 90ms can not be cut
by EN1234 = H.
WAKE
EN1234
90mSec
BAT plug in
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
90mSec
BAT exists
VIN plug in
No WAKE impulse
BAT/VIN plug in
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29
RT5002C
Charge State Indicator CHG
Charger State
CHG Output
Charging Suspended by Thermal Loop
Low
(for first charge cycle)
Charging
Safety Timers Expired
Bit EOC
0
Bit PGOOD
1
Bit SAFE
0
0
1
0
0
1
1
1
1
0
1
1
0
0
0
0
2Hz Flash
Charging Done
Recharging after Termination
High Impedance
IC Disabled or no Valid Input Power
b[7]
(MSB)
Address
Meaning
0x1
b[6]
b[5]
b[3]
b[2]
b[1]
ENCH
JEITA
ISET
b[0]
(LSB)
VSET
b[4]
TIMER [3:0]
Default
0
1
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VIN Power Good Status
TIMER [3:0]
ENCH
JEITA
0000 to
1111
Fast Charge timeout time: tFCHG = (TIMER [3:0] + 1) hours. (ISET = 1)
Pre-Charge timeout time : tPCHG = tFCHG / 8
1
Enable charger
0
Disable charger
1
Charger operation controlled by I C bits VSET and ISET
0
Charger operation automatically in JEITA temperature standard
2
Half Charge Current Set Input
ISET
1
For ICHG1 : time = tFCHG
0
For ICHG2 : time = 2 x tFCHG, ICHG2 = ICHG1 / 2
Battery Regulation Set Input
VSET
1
Battery regulation voltage is 4.2V
0
Battery regulation voltage is 4.05V
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Charging Current Decision
Battery Pack Temperature Monitoring
The charge current can be set according to the following
equations :
The battery pack temperature monitoring function can be
realized by connecting the TS pin to an external Negative
Temperature Coefficient (NTC) thermistor to prevent over
temperature condition. Charging is suspended when the
voltage at the TS pin is out of normal operating range. The
internal timer is then paused, but the value is maintained.
If ISET = 1 (for ICHG1 )
V
ICHG_FAST = ISETA × 300
RISETA
If ISET = 0 (for ICHG2 )
V
ICHG_FAST = ISETA × 150
RISETA
ICHG_PRE = 10% × ICHG_FAST
Time Fault
During the fast charge phase, several events may increase
the charging time.
For example, the system load current may have activated
the APPM loop which reduces the available charging
current or the device has entered thermal regulation
because the IC junction temperature has exceeded TREG.
However, once the duration exceeds the fault time, the
CHG output pin will flash at approximately 2Hz to indicate
a fault condition and the charge current will be reduced to
about 1mA.
When the TS pin voltage returns to normal operating range,
charging will resume and the safe charge timer will continue
to count down from the point where it was suspended.
Note that although charging is suspended due to the
battery pack temperature fault, the CHG pin will remain
low and indicate charging.
The 3.3V at VP pin is buffered by the RT5002C once it is
in charging state or its PMU part is enabled.
For 100kΩ NTC thermistor, the input pin, TSSEL, should
be connected to GND. For 10kΩ NTC thermistor, the input
pin, TSSEL, should be connected to VIN. TSSEL
determines the TS threshold levels for 0°C and 60°C. It
also defines the TS threshold levels used in JEITA
operation. The choosing method of R1 and R2 to meet
battery temperature monitoring is shown below :
Time fault release methods :
(1) Re-plug power
Case 1 : TSSEL = L (For 100kΩ NTC) :
(2) Toggle EN
VP
VP
(3) Enter/exit suspend mode
R1
TS
(4) Remove Battery
0.74 x VP +
-
R2
(5) OVP
If ISET = 1 (for ICHG1 )
time = tFCHG
If ISET = 0 (for ICHG2 )
time = 2 × tFCHG
0.28 x VP
+
Too Cold
Too Hot
RNTC
Figure 1
Too Cold Temperature
JEITA Battery Temperature Standard
CV regulation voltage will change at the following battery
temperature ranges : 0°C to 10°C and 45°C to 60°C.
CC regulation current will change at the following battery
temperature ranges : 0°C to 10°C and 45°C to 60°C.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS5002C-00
January 2013
RCOLD = RNTC
Too Hot Temperature
RHOT = RNTC
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31
RT5002C
R2 + RCOLD
= 0.74
RCOLD + R1+ R2
(1)
R2 + RHOT
= 0.28
RHOT + R1+ R2
(2)
Form (1), (2)
R1 =
RCOLD − RHOT
2.457
R2 = 0.389 × R1− RHOT
If R2 < 0
RCOLD
= 0.74
RCOLD + R1
(3)
The above calculation gives R1 and R2. JEITA control
thresholds for full charging current and 4.2V regulation
voltage are at TS/VP ratio = 40% and 54% (for TSSEL =
H), 35% and 64% (for TSSEL = L). With the ratio, the
corresponding NTC thermistor resistances from the
resistors in the voltage divider circuit can be obtained.
According to the NTC resistances, the corresponding
temperatures can be found. The two temperatures are the
control temperatures used in JEITA operation.
Power Switch
Form (3)
R1 =
The Control Temperature Used in JEITA Operation :
For the charger, there are three power scenarios:
RCOLD
− RCOLD
0.74
(1) When a battery and an external power supply (USB or
adapter) are connected simultaneously :
Case 2 : TSSEL = H (For 10kΩ NTC) :
If the system load requirements exceed that of the input
current limit, the battery will be used to supplement the
current to the load. However, if the system load
requirements are less than that of the input current limit,
the excess power from the external power supply will be
used to charge the battery.
VP
VP
0.6 x VP
R1
TS
+
-
R2
0.38 x VP
+
Too Cold
Too Hot
(2) When only the battery is connected to the system :
RNTC
The battery provides the power to the system.
Figure 2
(3) When only an external power supply is connected to
the system :
Too Cold Temperature
RCOLD = RNTC
The external power supply provides the power to the
system.
Too Hot Temperature
RHOT = RNTC
R2 + RCOLD
= 0.6
RCOLD +R1+R2
(1)
R2 + RHOT
= 0.38
RHOT +R1+R2
(2)
Form (1), (2)
R1 =
RCOLD − RHOT
0.9
R2 = 0.6 × R1− RHOT
Form (3)
R1 =
RCOLD
− RCOLD
0.6
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32
For the charger, the input voltage is monitored when
USB100 or USB500 is selected. If the input voltage is
lower than VDPM, the input current limit will be reduced
to stop the input voltage from dropping any further. This
can prevent the IC from damaging improperly configured
or inadequately designed USB sources.
APPM Mode
If R2 < 0
RCOLD
= 0.6
RCOLD +R1
Input DPM Mode
(3)
Once the sum of the charging and system load currents
becomes higher than the maximum input current limit,
the SYS pin voltage will be reduced. When the SYS pin
voltage is reduced to VAPPM, the RT5002C will
automatically operate in APPM mode. In this mode, the
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
charging current is reduced while the SYS current is
increased to maintain system output. In APPM mode,
the battery termination function is disabled.
Battery Supplement Mode Short Circuit Protect
In APPM mode, the SYS voltage will continue to drop if
the charge current is zero and the system load increases
beyond the input current limit. When the SYS voltage
decreases below the battery voltage, the battery will kick
in to supplement the system load until the SYS voltage
rises above the battery voltage.
While in supplement mode, there is no battery supplement
current regulation. However, a built-in short circuit
protection feature is available to prevent any abnormal
current situations. While the battery is supplementing the
load, if the difference between the battery and SYS voltage
becomes more than the short circuit threshold voltage,
SYS will be disabled. After a short circuit recovery time,
tSHORT_R, the counter will be restarted. In supplement
mode, the battery termination function is disabled. Note
that for the battery supply mode exit condition,
VBAT − VSYS < 0V.
Thermal Regulation and Thermal Shutdown
The charger provides a thermal regulation loop function to
monitor the device temperature. If the die temperature rises
above the regulation temperature, TREG, the charge
current will automatically be reduced to lower the die
temperature. However, in certain circumstances (such as
high VIN, heavy system load, etc.) even with the thermal
loop in place, the die temperature may still continue to
increase. In this case, if the temperature rises above the
thermal shutdown threshold, TSD, the internal switch
between VIN and SYS will be turned off. The switch
between the battery and SYS will remain on, however, to
allow continuous battery power to the load. Once the die
temperature decreases by ΔTSD, the internal switch
between VIN and SYS will be turned on again and the
device returns to normal thermal regulation.
The internal thermal feedback circuitry regulates the die
temperature to optimize the charge rate for all ambient
temperatures.
4.16 to 4.2 to 4.23V
−40°C to 85°C
Battery Voltage
Charging Current
VRECH
If
VPRECH
ISETL = 1, ISETU = 1
ISETL = 0, ISETU = X
ITERMI = 10% x ICHG_FAST
If ISETL = 0, ISETU = 0
ITERMI = 3.3% x ICHG_FAST
ICHG_PRE = 10% x ICHG_FAST
ITERM2
Time
Figure 3
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33
RT5002C
APPM Profile
1.5A Mode :
VIN 5V
VSYS 4.5V
VAPPM 4.2V
VBAT 4.0V
3A
2A
IBAT
1A
ISYS
0
IVIN -1A
-2A
-3A
T1
T2
T3
T5
T4
T6
T7
ISYS
V SYS
IVIN
IBAT
T1, T7
0
SYS Regulation Voltage
CHG_MAX
CHG_MAX
T2, T6
< IVIN_OC − CHG_MAX
SYS Regulation Voltage
ISYS + CHG_MAX
CHG_MAX
VIN_OC
VIN_OC − ISYS
VIN_OC
ISYS − IVIN_OC
T3, T5
> IVIN_OC − CHG_MAX < IVIN_OC Auto Charge Voltage Threshold
V BAT − IBAT x RDS(ON)
> IVIN_OC
T4
USB 500mA Mode :
VUSB
5V
VSYS
4.5V
VAPPM
4.2V
VBAT
4.0V
0.75A
0.5A
IBAT 0.25A
ISYS
0
IUSB -0.25A
-0.5A
-0.75A
T1
T2
T3
T5
T4
T6
T7
ISYS
VSYS
IUSB
IBAT
T1, T7
0
SYS Regulation Voltage
CHG_MAX
CHG_MAX
T2, T6
< IVIN_OC (USB) − CHG_MAX
SYS Regulation Voltage
ISYS + CHG_MAX
CHG_MAX
Auto Charge Voltage
Threshold
IVIN_OC (USB)
IVIN_OC (USB) − ISYS
VBAT − IBAT x RDS(ON)
IVIN_OC (USB)
ISYS − IVIN_OC (USB)
T3, T5
> IVIN_OC (USB) − CHG_MAX
< IVIN_OC (USB)
T4
> IVIN_OC (USB)
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34
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
VSET vs. VREG, ISET vs. ICHG
When JEITA = 1, VREG and ICHG are set by the bits
VSET and ISET, respectively.
When JEITA = 0, VREG and ICHG follows JEITA
temperature standard.
For JEITA Battery Temperature Standard :
CV regulation voltage will change at the following battery Temp ranges
0°C to 10°C and 45°C to 60°C
CC regulation current will change at the following battery Temp ranges
0°C to 10°C and 45°C to 60°C
VSET
4.16 to 4.2 to 4.23V
VREG
4.01 to 4.05 to 4.08V
4.16 to 4.2 to 4.23V
ICHG +/-5%
ICHG
4.01 to 4.05 to 4.08V
4.01 to 4.05 to 4.08V
ISET
0°C
45°C
10°C
0.5 x ICHG +/-5%
60°C
Temperature
+/- 2°C
ICHG +/- 5%
0.5 x ICHG +/- 5%
0.5 x ICHG +/- 5%
Temperature
+/- 2°C
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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January 2013
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35
RT5002C
RT5002C Operation State Diagram for Charging
VBAT > 3V
Fast-Charge State
If ISET = 1
ICHG_FAST = (VISETA / RISETA) x 300
If ISET = 0
ICHG_FAST = (VISETA / RISETA) x 150
Yes
No
No
VIN – VBAT
> VOS_H
Yes
Pre-Charge State
ICHG_PRE =
Sleep State
If VSET = 1
Check VBAT > 4.1V
If VSET = 0
Check VBAT > 3.95V
No
10% x ICHG_FAST
Yes
No
Time > tFCHG
Yes
No
Time > tPCHG
Standby State
ISETL = 0 & ISETU = 1
ISETL = 1 & ISETU = X
Check ICHG < 10% x ICHG_FAST
If ISETL = 0 & ISETU = 0
Check ICHG < 3.3% x ICHG_FAST
If
Yes
No
Yes
No
VUVLO< VIN < VOVP
& ENCH = 1
& USUS = 0
Timer-Out State
CHG = flash 2Hz
& ICHG to 1mA
Yes
Re-Charge State
CHG = High
impedance
Charger
Disable
Any State
or VIN < VUVLO,
Time > tTERMI = 25msec
Yes
Yes
If VSET = 1
Check VBAT < 4.1V
If VSET = 0
Check VBAT < 3.95V
or VIN > VOVP,
Or VIN - VBAT < VOS_H
or USUS = 1
or ENCH = 0
Charge Done State
CHG = High impedance
& ICHG = 0A
No
Operation State Diagram for TS Pin (TSSEL = L)
Any State
No
74% x VVP < VTS < 2.85V
Or VTS < 28% x VVP
No
VTS > 2.85V
Yes
Yes
TS fault State
ICHG = 0A
Keep CHG state
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36
Battery Remove State
ICHG = 0A
CHG = High impedance
Reset timer and CHG
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
I2C Interface
be changed to 0011010 (7bits). The I2C interface supports
The RT5002C I2C slave address is by default = 0011000
(7bits), but if customers request, the slave address can
fast mode (bit rate up to 400kb/s). The write or read bit
stream (N ≥ 1) is shown below :
Read N bytes
S
Slave Address
0 A
Register Address
A Sr
Slave Address
Assume Address = m
R/W
LSB A
Data 2
MSB
1 A MSB
Data 1
LSB A
Data for Address = m
MSB
Data for Address = m+1
Data N
LSB A P
Data for Address = m + N - 1
Write N bytes
S
Slave Address
0 A
Register Address
Assume Address = m
R/W
A MSB
Data 1
Data for Address = m
MSB
LSB A MSB
Data 2
Data for Address = m + 1
Data N
LSB A
LSB A P
Data for Address = m + N - 1
Driven by Master,
Driven by Slave (RT5002C), P Stop,
S Start,
Sr Repeat Start
SDA
tLOW
tF
tSU;DAT
tR
tF
tHD;STA
tBUF
tR
tSP
SCL
tHD;STA
S
tHD;DAT
tSU;STA
tHIGH
tSU;STO
P
Sr
S
I2C Register File
Address
Meaning
0x0
b[7]
(MSB)
b[6]
b[5]
MOD56
SEQ56
EN56
0x2
b[3]
b[2]
b[1]
b[0]
(LSB)
EN7_DIM7 [4:0]
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ENCH
JEITA
ISET
VSET
Meaning
0x1
b[4]
TIMER [3:0]
Default
0
1
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Meaning
ISETU
ISETL
USUS
NoBAT
EOC
PGOOD
TS_FAULT
SAFE
Default
1
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R
R
R
R
R
Reset after EN1234 = L and PMU shutdown completely for register 0x0.
Reset after PGOOD = 0 and EN1234 = L then PMU shutdown completely for register 0x1 and 0x2.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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January 2013
is a registered trademark of Richtek Technology Corporation.
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37
RT5002C
Thermal Considerations
Layout Consideration
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
For the best performance of the RT5002C, the following
PCB layout guidelines must be strictly followed.
`
Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
`
Keep the main power traces as wide and short as
possible.
`
The switching node area connected to LX and inductor
should be minimized for lower EMI.
`
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-40L 5x5 package, the thermal resistance, θJA, is
Place the feedback components as close as possible
to the FB pin and keep these components away from
the noisy devices.
`
27.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
Connect the GND and Exposed Pad to a strong ground
plane for maximum thermal dissipation and noise
protection.
`
The connection of RISETA should be isolated from other
noisy traces. A short wire is recommended to prevent
EMI and noise coupling.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
PD(MAX) = (125°C − 25°C) / (27.5°C/W) = 3.64W for
WQFN-40L 5x5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 4 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)
4.0
Four-Layer PCB
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 4. Derating Curve of Maximum Power Dissipation
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38
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
LX should be connected to Inductor by wide
and short trace, keep sensitive compontents
away from this trace.
VOUT_CH1
SYS
Place the feedback components as
close as possible to the FB pin and
keep away from noisy devices.
GND
C1
VOUT_CH2
C3
C24
GND
R2
C21
R1
SYS
L1
C2
D5
D4
C10
C22
L2
Bypass
Cap
29
3
28
27
26
GND
6
25
7
24
8
23
41
22
9
21
10
11 12 13 14 15 16 17 18 19 20
WAKE
FB2
TSSEL
SYS
L5
C14
LX5
VOUT_CH5
PVD5
FB5
R9
C13
C12
EN1234
LX3
PVD3
R10
L3
FB3
SYS
GND
ISETA
TS
VP
SDA
SCL
PVD6
LX6
VOUT6
FB6
VREF
C8
30
2
5
R8
GND
C5
R5
The RISETA connection copper area
should be minimized and kept far away
from noise sources.
GND
VOUT_CH6
SYS
RNTC
C6
R11
C15
R16
GND
C7
R6
R12
D1
VOUT_CH3
GND
L6
RISETA
R17
C4
R4
1
4
R3
GND
40 39 38 37 36 35 34 33 32 31
GND
INT
FB1
VDDM
D2
FB7
VOUT_CH7
PVD7
L7
C19
LX7
CHG
GND
SYS L4
C20
LX4
VOUT_CH4
SYS PVD4
R7
FB4
C11
D3
C9
LX1
PVD1
RTCPWR
VIN
SYS
SYS
BAT
BAT
PVD2
LX2
R13
C18
C17
C16
Input/Output capacitors must be
placed as close as possible to the
Input/Output pins.
GND
Connect the Exposed
Pad to a ground plane.
Figure 5. PCB Layout Guide
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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January 2013
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39
RT5002C
SYS
PMU
Shutdown
Delay Time
Reset Method
PMU Shutdown.
No-delay
VDDM power reset or
EN1234 pin set to low
VDDM > 6V
Automatic reset at
VDDM < 5.75V
100ms
VDDM power reset or
EN1234 pin set to low
VDDM < 2.4V
PMU Shutdown.
No-delay
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
No-delay
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
No-delay
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
Protection Threshold (Typical) Refer
Type
to Electrical Spec.
Protection Methods
UVLO
SYS < 1.5V
OVP
UVLO
VDDM
CH1
Step-Up
Current
limit
N-MOSFET current > 3A
PVDD1
OVP
PVDD1 > 6V
PVDD1
UVP
FB1 UVP
PVDD1 < (VSYS − 0.8V) or
PVDD1 < 1.28V after
soft-start end.
FB1 < 0.4V after
precharge
FB1 Over
Load (OL)
FB1 < 0.7V
Current
limit
P-MOSFET current > 1.8A
CH2
Step-Down FB2 UVP
FB2 < 0.4V after soft-start
end.
FB2 Over
Load
FB2 < 0.7V
Current
limit
P-MOSFET current > 1.6A
CH3
Step-Down FB3 UVP
FB3 < 0.4V after soft-start
end.
FB3 Over
Load
FB3 < 0.7V
Current
limit
P-MOSFET current > 1.6A
CH4
Step-Down FB4 UVP
FB4 Over
Load
FB4 < 0.4V after soft-start
end.
FB4 < 0.7V
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40
N-MOSFET off,
P-MOSFET off.
Automatic reset at
next clock cycle.
N-MOSFET off,
P-MOSFET off.
N-MOSFET off,
P-MOSFET off.
N-MOSFET off,
P-MOSFET off
PMU Shutdown when
OL occur each cycle
until 100mS.
N-MOSFET off,
P-MOSFET off.
Automatic reset at
next clock cycle.
N-MOSFET off,
P-MOSFET off.
PMU Shutdown when
OL occur each cycle
until 100mS.
N-MOSFET off,
P-MOSFET off.
Automatic reset at
next clock cycle.
N-MOSFET off,
P-MOSFET off.
PMU Shutdown when
OL occur each cycle
until 100mS.
N-MOSFET off,
P-MOSFET off.
Automatic reset at
next clock cycle.
N-MOSFET off,
P-MOSFET off.
PMU Shutdown when
OL occur each cycle
until 100mS.
is a registered trademark of Richtek Technology Corporation.
DS5002C-00
January 2013
RT5002C
Protection Threshold (Typical) Refer
Type
to Electrical spec.
Current
limit
PVDD5
CH5
OVP
Step-Up
FB5 UVP
N-MOSFET current > 1.2A
PVDD5 > 22V
FB5 < 0.6V after soft-start
end.
FB5 Over
Load
FB5 < 1.1V
Current
limit
P-MOSFET current > 1.5A
PVDD6
CH6
OVP
Async
Inverting FB6 UVP
N-MOSFET off,
P-MOSFET off.
Automatic reset at
next clock cycle.
N-MOSFET off,
P-MOSFET off.
N-MOSFET off,
P-MOSFET off.
PMU Shutdown
when OL occur each
cycle until 100mS.
P-MOSFET off.
Automatic reset at
next clock cycle.
PMU
Shutdown
Delay Time
Reset Method
100ms
VDDM power reset or
EN1234 pin set to low
No-delay
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
PVDD6 < −13V
P-MOSFET off.
No-delay
VDDM power reset or
EN1234 pin set to low
FB6 > 1.2V
P-MOSFET off.
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
100ms
VDDM power reset or
EN1234 pin set to low
FB6 Over
Load
FB6 > 0.74V
Current
limit
N-MOSFET current > 0.8A
CH7
WLED
Thermal
Protection
Methods
PVDD7
OVP
PVDD7 > 15V
Thermal
shutdown
Temperature > 155°C
Protection
Type
PMU Shutdown
when OL occur each
cycle until 100mS.
N-MOSFET off,
P-MOSFET off.
Automatic reset at
next clock cycle.
N-MOSFET off,
P-MOSFET off.
Shutdown CH7 by
self
All channels stop
switching
Threshold (Typical) Refer
to Electrical Spec.
Protection
Methods
No-delay
No-delay
VDDM power reset and
Reg0x00[4 to 0] = 00000
reset or EN1234 pin set
to low
VDDM power reset or
EN1234 pin set to low
Charger
Shutdown
Delay Time
Reset Method
VIN UVLO
VIN < 3.3V
No-charge
No-delay
No latch
VIN OVP
VIN > 6.5V
No-charge
No-delay
No latch
VIN
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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January 2013
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41
RT5002C
Outline Dimension
D
SEE DETAIL A
D2
L
1
E2
E
e
b
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
4.950
5.050
0.195
0.199
D2
3.250
3.500
0.128
0.138
E
4.950
5.050
0.195
0.199
E2
3.250
3.500
0.128
0.138
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
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DS5002C-00
January 2013