® RT5072 Multi-Channel PMU with Linear Battery Charger for CMOS DSC/DV General Description The RT5072 is a complete power supply solution for digital still cameras and other hand held devices. The RT5072 is composed of a multi-channel DC/DC power converter unit, a single-cell linear Li-ion battery charger, a charger type detector, and an I2C control interface. The power converter unit includes one synchronous stepup converter (CH1), one synchronous step-up/down converter (CH2), three synchronous step-down converters (CH3/4/5), two LDOs with input power as low as 1.5V (CH6/8), one WLED driver in synchronous high-voltage step-up mode or low-voltage current regulator mode (CH7), and a keep-alive LDO (CH9) for RTC application. All converters are internally frequency compensated and integrate power MOSFETs. The power converter unit provides complete protection functions : over-current, thermal shutdown, over-voltage, and under-voltage protection. The RT5072 has a WAKEUP impulse generation circuitry to monitor VIN or BAT installation event. To fulfill most of applications, the RT5072 has six preset power-on/off sequences. The battery charger includes Auto Power Path Management (APPM). No external MOSFETs are required. The charger can enter sleep mode when power is removed. Charging tasks are optimized by using a control algorithm to vary the charge rate, including pre-charge mode, fast charge mode and constant voltage mode. The charge current can also be programmed via the I2C control interface. The battery regulation voltage and current can be adjusted by JEITA standard temperature control or other schemes set via the I2C interface. The internal thermal feedback circuitry regulates the die temperature to optimize the charge rate for all ambient temperatures. The charging task will always be terminated in constant-voltage mode when the charging current reduces to the termination current of 10% x ICHG_FAST. The charger includes undervoltage and over-voltage protection for the supply input voltage, VIN. The charger includes USB charger detection circuitry via D+ and D- pins of USB interface to detect USB standard downstream ports (SDP), USB charging downstream port (CDP), dedicated charger port (DCP), or Apple/Sony charger ports. RT5072 uses some indicators to show charger states : two open drain ports CHG and CHG2, and an interrupt (INT) to immediately notify the state change. The RT5072 has I2C interface to control rich functions of Power Converter Unit and Charger Unit, and is available in the WQFN-40L 5x5 package. Simplified Application Circuit BAT Adapter/USB System Power 2 VIN SYS SCL I C Control SDA GND Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 RT5072 PVD1 VO2 LX3 LX4 LX5 VO6 PVD7 VO8 VRTC Charger for Battery Step-Up for Motor Step-Up/Down for I/O Step-Down for Core Step-Down for Memory Step-Down LDO Step-Up for LED Backlight LDO LDO for RTC is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT5072 Features CH1 LV Sync Step-Up Support Up to 1A Loading, DVS (Dynamic Voltage Scaling), Load-Disconnect, Up to 95% Efficiency, PSM/PWM Selectable CH2 LV Sync Step-Up/Down Support Up to 1A Loading, DVS, Up to 95% Efficiency, PSM/PWM Selectable CH3/4 LV Sync Step-Down Support Up to 3A (CH3) / 2A (CH4) Loading, DVS, Up to 95% Efficiency, 100% (MAX) Duty Cycle, PSM/ PWM Selectable CH5 LV Sync Step-Down Support Up to 0.6A Loading, Up to 95% Efficiency, 100% (MAX) Duty Cycle Output Voltage can be Selected from Preset List or Set by External Feedback Network CH6 Low Input Power LDO VIN Range 1.5V to 5.5V 2 Output Voltage Level Selectable in I C Register CH7 WLED Driver in Either Sync Step-Up Operation or Current Regulator Operation Step-Up Mode with LED Open Protection (OVP7 16V or 25V, Selectable in I2C Register) Step-Up Mode Support Series 2 to 6 WLED and Load Disconnect Function Current Regulator Mode for 1 WLED 31 WLED Dimming Levels Automatic Mode Selection by External Circuit Topology CH8 Generic LDO VIN Range 1.5V to 5.5V 2 Output Voltage Level Selectable in I C Register CH9 Low Quiescent LDO with Reverse Leakage Prevention for RTC Power Supply Fixed 3.05V Output Six Preset Power On/Off Sequences by One Pin SEQ SEQ # 0 : CH2 CH3 CH4 SEQ # 1 : CH1 CH3 CH2 CH4 SEQ # 2 : CH1 CH3 CH4 CH2 SEQ # 3 : CH1 CH2 CH4 CH3 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 SEQ # 4 : CH1 CH4 CH3 CH2 SEQ # 5 : CH1 CH4 CH2 CH3 All Power Switches Integrated with Internal Compensation Discharge Output of Every Channel when Turning Off Wake Up Impulse to Monitor BAT and VIN Plug-In Fixed 2MHz Switching Frequency for CH1/3/4/5, Fixed 1MHz Switching Frequency for CH2/7 Power Converter Unit Charger Unit 28V Maximum Rating for VIN Power Selectable Power Input Current Limit (0.1A / 0.5A / 1A / 1.5A) Auto Power Path Management (APPM) with Integrated Power MOSFETs Battery Charging Current Control and Regulation Voltage Control Programmable Charging Current and Safe Charge Timer Optimized Charge Rate via Thermal Feedback Under-Voltage Protection, Over-Voltage Protection Charger Status and VIN Power GOOD Indicators Interrupt Indicator to JEITA Temperature/Fault/ Status Events when PMU is Enabled Battery Temperature Events Battery Removing Event Charger in Thermal Regulation Control Safety Timer Timeout End of Charging VIN Power Good VIN < DPM Threshold 4.35V Charger Type Detection Finishing Charger Type Detection Dedicated Charger : Support Apple and Sony Charger Secondary Charger Detection to Distinguish CDP and DCP 2 I C Control Interface : Support Fast Mode up to 400kb/s RoHS Compliant and Halogen Free is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Pin Configurations Applications DSC Power Supply System CMOS-Sensor DV Portable Devices (TOP VIEW) VRTC DN DP VIN SYS SYS BAT BAT PVD3 LX3 40 39 38 37 36 35 34 33 32 31 Ordering Information RT5072 Package Type QW : WQFN-40L 5x5 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : 1 30 2 29 3 28 27 4 5 26 GND 6 25 7 24 8 41 23 22 9 21 10 VP TS FB3 PVD2 LX2A LX2B VO2 FB2 VO8 SCL RoHS compliant and compatible with the current require- FB4 SEQ LX4 EN PVD45 LX5 INT VO5/FB5 PVD8 SDA 11 12 13 14 15 16 17 18 19 20 Richtek products are : WAKE PVD1 LX1 CHG2 FB7 PVD7 LX7 CHG VO6 PVD6 ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. WQFN-40L 5x5 Marking Information RT5072GQW : Product Number RT5072 GQW YMDNN YMDNN : Date Code Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT5072 Functional Pin Description Pin No. Pin Name Pin Function 1 WAKE Wake-Up Impulse Push Pull Output. If VIN or BAT plug in, the WAKE pin generates one 90ms-width high pulse to notify micro processor. 2 PVD1 Power Output of CH1. To make CH1 stable, the power path from the PVD1 pin to its output capacitors must be as short (1mm is better) and wide as possible to reduce its parasitic inductance. The output capacitor must be ceramic capacitor (20F). 3 LX1 Switch Node of CH1. 4 CHG2 2nd Charger Status Indicator (Open-Drain Output). 5 FB7 Feedback Input Pin of CH7 in Step-Up Mode or Current Regulator Mode 6 PVD7 Power Output Pin of CH7 in Step-Up or Power Input Pin of CH7 in Current Regulator Mode. 7 LX7 Switch Node of CH7 in Step-Up Mode. LX7 initial voltage determine CH7 operation mode. 8 CHG Charger Status Indicator Output (Open-Drain Output). 9 VO6 Power Output of CH6. 10 PVD6 Power Input of CH6. 11 FB4 Feedback Voltage Input of CH4. 12 SEQ Power Sequence Selection for CH1 to CH4. 13 LX4 Switch Node of CH4. 14 EN Enable Control Input of Power Converter Unit. 15 PVD45 Power Input of CH4 and CH5. To avoid the crosstalk between CH4 and CH5, the power path from the PVD45 pin to its input capacitors must be as short (1mm is better) and wide as possible to reduce its parasitic inductance. The input capacitance must be 10F with low ESR. 16 LX5 Switch Node of CH5. 17 INT Interrupt Indicator Open-Drain Output. If events of NoBAT, THR, EOC, Battery Temperature Change (TS_METER), PGOOD, SAFE, VIN DPM, or Charge Type 2 Detection Finishing (CHGRUN) happen, the output INT goes low and the INT bit in I C register bank 0x9 is set to be “1”. After INT bit is written to be “0”, INT goes high. 18 VO5/FB5 Output Voltage Sense or Feedback Voltage Input of CH5. The function is selected by 2 I C register. 19 PVD8 Power Input of CH8. 20 SDA Data Signal of I C Interface. 21 SCL Clock Signal of I C Interface. 22 VO8 Power Output of CH8. 23 FB2 Feedback Voltage Input of CH2. 24 VO2 Power Output of CH2. 25 LX2B Switch Node B of CH2. 26 LX2A Switch Node A of CH2. 27 PVD2 Power Input of CH2. 2 2 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Pin No. 28 Pin Name Pin Function FB3 Feedback Voltage Input of CH3. 29 TS Temperature Sense Input. The TS pin connects to a battery’s thermistor to determine if the battery is too hot or too cold to charge. If the battery’s temperature is out of range, charging is paused until it re-enters the valid range. TS also detects whether the battery (with NTC) is present or not. 30 VP Power Output of 3.3V Buffer for Battery Temperature Sensing. 31 LX3 Switch Node of CH3. 32 PVD3 Power Input of CH3. 33, 34 BAT Charger Output for Battery. 35, 36 SYS Power Output for System. Connect this pin to System with a minimum 10F ceramic capacitor to GND. 37 VIN Supply Voltage Input. 38 DP USB D+ Input for Charger Type Detection. 39 DN USB D- Input for Charger Type Detection. 40 VRTC RTC LDO Power Output. 41 (Exposed pad) GND Power Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT5072 Function Block Diagram BAT SYS VIN SYS VDDI + - VP CHG_TYP [2 : 0] CHG_1DET 3.3V Li+ Battery Linear Charge with APPM VP Buffer with NTC Type Detector Battery Charger Type Detector CHG_2DET CHGRUN DP DN CHG2 + SYS Body Diode Control CH1 C-Mode Step-Up for 1A LX1 PVD1 PVD1 SYS PGOOD SAFE DPM TS_MESTER [2 : 0] SYS PVD1 CHG ENCH USUS VSETH VSETC ISETH ISETC ISETL ISETU JEITA TIMER [3 : 0] Mask_DPM TS Comparators THR ECO TS VDDI SYS POR BAT VIN + CH9 RTC LDO with Body Diode Control VRTC Power Plug-In Wake up Detector WAKE SYS VREF + DVS PVD8 CH8 Low VIN LDO PVD2 SYS LX2A LX2B CH2 LV C-Mode Sync. Step-Up/Down For 1A VO8 + VREF + DAC VO2 FB2 VREF + DVS POR + Enable Control EN Sequence Detection & Control SYS PVD3 SEQ SYS CH3 C-Mode Step-Down for 1.3A LX3 FB3 VREF + DVS I2C Control Interface (Fast Mode up to 400kb/s) SYS + THR ECO PGOOD SAFE TS_METER [2 :0 ] No_BAT DPM CHGRUN SYS PVD45 CH4 C-Mode Step-Down for 1.3A LX4 FB4 VREF + DVS INT Interrupt Handler SYS + CH7 HV C-Mode Sync. Step-Up + Current Source + Mode Selector for 1 to 6WLED SYS PVD45 CH5 C-Mode Step-Down for 0.6A LX5 SCL SDA - PVD7 Body Diode Control SYS LX7 FB7 + VO5/FB5 VREF + DAC SYS VREF + DVS + PVD6 CH6 Low VIN LDO VO6 GND + Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 VREF + DAC is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Operation The RT5072 is an integrated power solution for digital still cameras and other small handheld devices. It includes six DC/DC converters, a WLED driver, a RTC LDO, and a fully integrated single-cell Li-ion battery charger. CH1 : Step-Up DC/DC Converter CH1 is a step-up converter for motor driver power. The converter operates at PFM or PWM current mode which can be set by I2C interface. CH8 : Generic LDO CH8 is a generic low voltage LDO for multiple purpose power. CH9 : Keep Alive LDO and RTC CH9 is a LDO providing a 3.05V output for real time clock. Charger Unit A Li-ion battery charger with automatic power path management is designed to operate in below modes. CH2 : Step-Up/Down DC/DC Converter CH2 is a step-up/down converter for I/O power. The converter operates at PFM or PWM current mode which can be set by I2C interface. Pre-Charge Mode When the output voltage is lower than 2.8V, the charging current will be reduced to a ratio of fast-charge current set by A8.ISETA [3:0] to protect the battery life-time. CH3 : Step-Down DC/DC Converter CH3 is a step-down converter for core power. The converter operates at PFM or PWM current mode which can be set by I2C interface. Fast-Charge Mode When the output voltage is higher than 3V, the charging current will be equal to the fast-charge current set by A8.ISETA [3:0]. CH4 : Step-Down DC/DC Converter CH4 is a step-down converter for memory power. The converter operates at PFM or PWM current mode which can be set by I2C interface. CH5 : Step-Down DC/DC Converter CH5 is a step-down converter. The converter operates at PFM/PWM current mode. CH6 : Generic LDO CH6 is a generic low voltage LDO for multiple purpose power. Constant Voltage Mode When the output voltage is near 4.2V and the charging current falls below the termination current for a deglitch time of 25ms, the charger will be turned off and CHG will go to high. Re-Charge Mode When the chip is in charge termination mode, the charging current gradually goes down to zero. Once the battery voltage drops to below 4.1V for 100ms, the charger will resume charging operation. CH7 : WLED Driver CH7 is a WLED driver that can operate in either current source mode or synchronous step-up mode which is determined by I2C interface control signal. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT5072 Absolute Maximum Ratings (Note 1) Supply Voltages, SYS ---------------------------------------------------------------------------------------------------Supply Input Voltage, VIN -----------------------------------------------------------------------------------------------Switch Node Voltage, LX1, LX2, LX3, LX4, LX5 ---------------------------------------------------------------------PVD7, LX7 -------------------------------------------------------------------------------------------------------------------CHG --------------------------------------------------------------------------------------------------------------------------CHG2 -------------------------------------------------------------------------------------------------------------------------Other Pins -------------------------------------------------------------------------------------------------------------------INT, CHG, CHG2 Continuous Current ---------------------------------------------------------------------------------BAT Continuous Current (Total in two pins) -------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN-40L 5x5 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-40L 5x5, θJA -------------------------------------------------------------------------------------------------------WQFN-40L 5x5, θJC ------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions −0.3V to 6V −0.3V to 28V −0.3V to 6V −0.3V to 25V −0.3V to 28V −0.3V to 6V −0.3V to 6V 20mA 2.5A 3.63W 27.5°C/W 6°C/W 150°C 260°C −65°C to 125°C 2kV 200V (Note 4) Supply Input Voltage, BAT ----------------------------------------------------------------------------------------------Supply Input Voltage Range, VIN (A7.ISETL = 1) ------------------------------------------------------------------Supply Input Voltage Range, VIN (A7.ISETL = 0) ------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------- 1.8V to 5.5V 4.4V to 6V 4.5V to 6V −40°C to 125°C −40°C to 85°C Electrical Characteristics Power Converter Unit : (VSYS = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 1.5 -- -- V 2.7 -- 5.5 V 5.82 6 6.18 V -- 0.25 -- V 2.2 2.4 2.6 V -- 0.3 -- V Supply Voltage PMU Startup Voltage at SYS VST SYS Operating Voltage for PMU VSYS For bootstrap VDDI Over Voltage Protection (OVP) (Hysteresis High) VDDI OVP Hysteresis (Gap) VDDI UVLO (Hysteresis High) VDDI UVLO takes effect once CH2 soft-start finish VDDI UVLO Hysteresis (Gap) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Parameter Symbol Test Conditions Min Typ Max Unit Supply Current IOFF-BAT EN = L, and PMU off, BAT = 4.2V -- 10 20 A IQ1234 Non switching, EN = 3.3V -- -- 2000 A IQ5 Non switching, A2.EN5 = 1 -- -- 500 A CH6 Supply Current IQ6 A2.EN6 = 1 -- -- 100 A CH7 in Step-Up Mode Supply Current IQ7b Non switching, A2.EN7_DIM7 [4:0] = 5’b11111 -- -- 500 A CH7 in Current Source mode Supply IQ7c Current CH8 Supply Current IQ8 A2.EN7_DIM7 [4:0] = 5’b11111 PVD7 = 5V A2.EN8 = 1 -- -- 400 A -- -- 100 A 1800 2000 2200 kHz CH7 in Step-Up mode 900 1000 1100 kHz Target voltage defined at A4.VOUT1 [3:0] 1.4 -- 1.4 % -- 100 -- ns Shutdown Supply Current into BAT (Include IDDQ of RTC LDO) CH1 + CH2 + CH3 + CH4 Supply Current CH5 Supply Current Oscillator CH1, 3, 4, 5 Operation Frequency CH2, 7 Operation Frequency CH1 LV Sync Step-Up fOSC_1345 fOSC_27 Output Voltage Accuracy at PVD1 Minimum On-Time for PSM Soft-Start Time -- 4 -- ms 80 83 86 % RDS(ON)_P PVD1 = 0 to 5V PVD1 < Target defined in A4.VOUT1 [3:0] P-MOSFET, PVD1 = 3.3V -- 200 300 m RDS(ON)_N N-MOSFET, PVD1 = 3.3V -- 150 250 m 2.2 3 4 A 5.82 6 SYS 0.8 Target x 0.5 6.18 V -- V -- V Maximum Duty Cycle (Step-Up) On-Resistance of MOSFET Current Limit (Step-Up) ILIM_1 Over-Voltage Protection at PVD1 Under-Voltage Protection -1 at PVD1 Under-Voltage Protection -2 at PVD1 -- Over-Load Protection at PVD1 Off Discharge Current at PVD1 Discharge Finishing Threshold at PVD1 CH2 LV Sync Step-Up/Down Feedback Regulation Voltage at FB2 Soft-Start Time RDS(ON)_2A Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 -- Target Voltage is defined in A4.VOUT1 [3:0] -- Target 0.6 -- V PVD1 = 5V, SYS = 3.3V -- 20 -- mA -- 0.6 -- V 0.788 0.8 0.812 V FB2 = 0 to 0.8V -- 4 -- ms LX2B LX2A LX2A GND, N-MOSFET PVD2 = 3.3V PVD2 LX2A, P-MOSFET PVD2 = 3.3V --- 55 -- -100 % % -- 200 300 m -- 150 250 m A4.FB2 [2:0] = 3’b100 Maximum Duty Cycle On-Resistance of MOSFET Target Voltage is defined in A4.VOUT1 [3:0] is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT5072 Parameter On-Resistance of MOSFET Current Limit Symbol RDS(ON)_2B ILIM_2 Test Conditions VO2LX2B, P-MOSFET, VO2 = 3.3V LX2B GND, N-MOSFET VO2 = 3.3V Both P-MOSFET (PVD2 LX2A) and N-MOSFET (LX2B GND) Over-Voltage Protection at VO2 Target voltage is the chosen one in A4.FB2 [2:0] Under-Voltage Protection at FB2 Min Typ Max Unit -- 200 300 m -- 150 250 m 2 2.5 3 A 5.82 6 6.18 V -- 0.4 -- V -- V -- mA -- Target 0.1 20 -- 0.1 -- V 0.788 0.8 0.812 V -- 50 -- ns FB3 = 0.75V -- -- 100 % Over-Load Protection at FB2 -- Off Discharge Current at VO2 Discharge Finishing Threshold at VO2 CH3 LV Sync Step-Down Feedback Regulation Voltage at FB3 Minimum On-Time for PSM VO2 = 3.3V, SYS = 3.3V A5.FB3 [2:0] = 3’b100 Maximum Duty Cycle Soft-Start Time FB3 = 0 to 0.8V -- 4 -- ms RDS(ON)_P P-MOSFET, PVD3 = 3.3V -- 200 300 m RDS(ON)_N N-MOSFET, PVD3 = 3.3V -- 150 250 m 3 3.5 4 A 0.35 0.4 0.45 V Target voltage is the chosen one in A5.FB3 [2:0] -- Target 0.1 -- V Off Discharge Current at LX3 Discharge Finishing Threshold at FB3 CH4 LV Sync Step-Down Feedback Regulation Voltage at FB4 Minimum On-Time for PSM LX3 = 1V, SYS = 3.3V -- 20 -- mA -- 0.1 -- V 0.788 0.8 0.812 V -- 50 -- ns Maximum Duty Cycle FB4 = 0.75V -- -- 100 % Soft-Start Time FB4 = 0 to 0.8V -- 4 -- ms RDS(ON)_P P-MOSFET, PVD4 = 3.3V -- 300 400 m RDS(ON)_N N-MOSFET, PVD4 = 3.3V -- 200 300 m 2 2.5 3 A 0.35 0.4 0.45 V Target voltage is the chosen one in A5.FB4 [2:0] -- Target 0.1 -- V LX4 = 1V, SYS = 3.3V -- 20 -- mA -- 0.1 -- V On-Resistance of MOSFET Current Limitation ILIM_3 Under-Voltage Protection at FB3 Over-Load Protection at FB3 On-Resistance of MOSFET Current Limit A5.FB4 [2:0] = 3’b100 ILIM_4 Under-Voltage Protection at FB4 Over-Load Protection at FB4 Off Discharge Current at LX4 Discharge Finishing Threshold at FB4 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Parameter Symbol Test Conditions Min Typ Max Unit Target voltage defined at A6.VOUT5 [3:0] = 4’b1000 to 4’b1111 1.4 -- 1.4 % Target voltage defined at A6.VOUT5 [3:0] = 4’b0001 to 4’b0111 2 -- 2 % 0.788 0.8 0.812 V -- -- 100 % -- 4 -- ms CH5 LV Sync Step-Down Output Voltage Accuracy at VO5 Feedback Regulation Voltage at FB5 A6.VOUT5 [3:0 ] = 4’b0000 Maximum Duty Cycle Soft-Start Time VO5 = 0V to Target On-Resistance of MOSFET RDS(ON)_P P-MOSFET, PVD5 = 3.3V RDS(ON)_N N-MOSFET, PVD5 = 3.3V -- 400 550 m -- 250 400 m Current Limit ILIM_5 1 1.5 2 A -- Target x 0.5 -- -- Target 0.1 -- Under-Voltage Protection at VO5 Target voltage is the chosen one in A6.VOUT5 [3:0] = 0000 (FB5 = 0.8) Over-Load Protection at VO5 Off Discharge Current at VO5 Target voltage is the chosen one in A6.VOUT5 [3:0] = 0001 to 0111 Target voltage is the chosen one in A6.VOUT5 [3:0] = 0111 to 1111 VO5 = 1.8V, SYS = 3.3V --- Target 0.167 Target 0.25 V --- -- 30 -- mA -- 0.1 -- V 1.5 -- 5.5 V -- -- 75 A A6.VOUT6 [3:0] = 4’b1000 to 4’b1111 1.5 -- 1.5 % A6.VOUT6 [3:0] = 4’b0000 to 4’b0111 -2 -- 2 % Drop Out Voltage (PVD6-VO6) IOUT = 300mA, VO6 = 1.3V -- -- 0.15 V PSRR+ IOUT = 10mA, PVD6 = 3.3V at 1kHz -- 60 -- dB 300 450 600 mA -- -- 10 mA 0.237 0.25 0.263 V -- 300 -- ns 91 93 97 % Discharge Finishing Threshold at VO5 CH6 LDO Input Voltage Range (PVD6) Quiescent Current into PVD6 Regulation Voltage Accuracy at VO6 Max Output Current (Current Limit) Off Discharge Current at VO6 CH7 WLED Driver Feedback Regulation Voltage at FB7 (Both Step-Up and Current) PVD6 = 3.3V, IOUT = 0mA PVD6 = 1.5V, VO6 = 1.3V SYS = 3.3V A2.EN7_DIM7 [4:0] = 5’b11111 Minimum On-Time for PSM (Step-Up) Maximum Duty Cycle (Step-Up mode) FB7 = 0.15V Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT5072 Parameter On-Resistance of MOSFET Symbol Test Conditions RDS(ON)_P P-MOSFET, PVD7 = 10V RDS(ON)_N N-MOSFET, SYS = 3.3V Min Typ Max Unit -- 2 3 -- 0.9 1.1 Current Limit (Step-Up mode) N-MOSFET, SYS = 3.3V 0.6 0.8 1 A Over-Voltage Protection at PVD7 (Step-Up mode) A0.OVP7 = 0 A0.OVP7 = 1 15 24 16 25 17 26 V V PVD7 = 10V, SYS = 3.3V -- 20 -- mA (Step-Up Mode) -- SYS 0.4 -- V 1.5 -- 5.5 V -- -- 75 A 1.5 -- 1.5 % 2 -- 2 % -- -- 0.2 V -- 60 -- dB 300 450 600 mA Off Discharge Current at PVD7 (Step-Up mode) Discharge Finishing Threshold at PVD7 CH8 LDO Input Voltage Range (PVD8) Quiescent Current into PVD8 IQ_PVD8 Regulation Voltage Accuracy at VO8 Drop Out Voltage (PVD8-VO8) PSRR+ PVD8 = 3.3V, IOUT = 0mA A3.VOUT8 [3:0] = 4’b1000 to 4’b1111 A3.VOUT8 [3:0] = 4’b0000 to 4’b0111 IOUT = 300mA, VO8 = 2.5V IOUT = 10mA, PVD8 = 3.3V at 1kHz Max Output Current (Current Limit) PVD8 = 3V, VO8 = 2.5V Off Discharge Current at VO8 SYS = 3.3V -- -- 10 mA BAT = 4.2V EN = L, and PMU off, BAT = 0V, VRTC = 3.05V, SYS = 0V IOUT = 0mA -- 3 6 A -- -- 1 A 3 3.05 3.1 V Max Output Current (Current Limit) BAT = 4.2V 60 130 200 mA Dropout Voltage at (BAT-VRTC) IOUT = 50mA IOUT = 10mA IOUT = 3mA ---- ---- 1000 150 60 mV mV mV 60 90 120 ms CH9 RTC LDO Standby Quiescent Current Lockout Current into VRTC ILO-VRTC Regulation Voltage at VRTC Wake Up Detector WAKE Impulse High Duration WAKE Output Voltage tWAKEUP High-Level VWAKE_H Low-Level VWAKE_L WAKE Rising Time BAT Wake Up Threshold Voltage BAT Wake Up Threshold Hysteresis tWAKE_R VIN or BAT plug in, VRTC = 3.05V Source Current 0.5mA, VRTC = 3.05V Sink Current 0.5mA, VRTC = 3.05V CLOAD = 100pF at WAKE pin, 10% to 90% of VRTC, VRTC = 3.05V VRTC = 3.05V VRTC = 3.05V Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 -- VRTC VRTC 0.3V V 0 0.3 -- V -- -- 1 s 3 3.1 3.2 V -- 0.28 -- V is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Parameter Symbol Test Conditions Min Typ Max Unit VIN Wake Up Threshold Voltage VRTC = 3.05V 3.55 3.75 4 V VIN Wake Up Threshold Hysteresis VRTC = 3.05V -- 0.24 -- V High-Level 1.3 -- -- V Low-Level -- -- 0.4 V -- 1 3 A 0.2 -- -- V Control EN Input Threshold EN Pull Down Current SEQ Pull High Threshold for Power Sequence #0 SEQ Pull Down Resistance for Power Sequence #1 BAT = SYS = 2.7V 25 40 64 k SEQ Pull Down Resistance for Power Sequence #2 BAT = SYS = 2.7V 6.25 10 16 k SEQ Pull Down Resistance for Power Sequence #3 BAT = SYS = 2.7V 1.56 2.5 4 k SEQ Pull Down Resistance for Power Sequence #4 BAT = SYS = 2.7V -- 0.63 1 k -- -- 0.2 V 100 160 -- k 9 10 11 ms -- 100 -- ms 125 155 -- °C -- 20 -- °C SEQ Pull Low Threshold for Power Sequence #4 SEQ Pull Down Resistance for Power Sequence #5 BAT = SYS = 2.7V Power Sequence Time Gap From previous channel starting to next channel starting Protection Protection Fault Delay Thermal Shutdown TSD Thermal Shutdown Hysteresis TSD Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT5072 Charger Unit : (VIN = 5V, VBAT = 4V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Input VIN Under-Voltage Lockout Threshold VUVLO VIN = 0V to 4.5V 3.1 3.3 3.5 V VIN Under-Voltage Lockout Hysteresis VUVLO VIN = 4.5V to 0V -- 240 -- mV ISYS = IBAT = 0mA, A7.ENCH = 0 (VBAT > VREGx) -- 1 2 mA ISYS = IBAT = 0mA, A7.ENCH = 1 (VBAT > VREGx) -- 0.8 1.5 mA VIN = 5V, A7.USUS = 1 -- 195 300 A VIN Supply Current ISUPPLY VIN Suspend Current IUSUS VINBAT VOS Rising VOS_H -- 200 300 mV VINBAT VOS Falling VOS_L 10 50 -- mV 4.9 5 5.1 V 4.16 4.2 4.23 V 4.01 4.05 4.08 V Voltage Regulation System Regulation Voltage VSYS ISYS = 800mA, VIN = 5.5V 0 to 85°C, Loading = 20mA, When A9. VSETH = 1 and A9.VSETC = 1 0 to 85°C, Loading = 20mA, When A9. VSETH = 0 and A9. VSETC = 0 Battery Regulation Voltage VREG1 Battery Regulation Voltage VREG2 APPM Regulation Voltage VAPPM 4.05 4.15 4.25 V DPM Regulation Voltage VDPM 4.25 4.35 4.45 V VIN to VSYS MOSFET Ron RDS(ON) IVIN = 1000mA -- 0.2 0.35 BAT to VSYS MOSFET Ron RDS(ON) VBAT = 4.2V, ISYS = 1A -- 0.05 0.1 Re-Charge Threshold VREGCHG Battery Regulation - Recharge level 60 100 140 mV 100 -- 1200 mA 570 600 630 mA 285 300 315 mA Current Regulation Charge Current Setting Range ICHG Charge Current Accuracy1 ICHG1 Charge Current Accuracy2 ICHG2 VIN Current Limit ILIM_VIN VBAT = 4V, A8.ISETA [3 : 0] = 4’b0101 VBAT = 3.8V, A8.ISETA [3 : 0] = 4’b0010 A7.ISETL = 1, A7.ISETU = 1 (1.5A Mode) A7.ISETL = 1, A7.ISETU = 0 (1A Mode) A7.ISETL = 0, A7.ISETU = 1 (500mA mode) A7.ISETL = 0, A7.ISETU = 0 (100mA Mode) 1.5 1.8 2.1 A 0.85 0.925 1.0 A 450 475 500 mA 80 85 90 mA BAT Falling 2.7 2.8 2.9 V -- 200 -- mV 5 10 15 % Pre-Charge BAT Pre-Charge Threshold VPRECH BAT Pre-Charge Threshold Hysteresis VPRECH Pre-Charge Current ICHG_PRE VBAT = 2V Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Parameter Symbol Test Conditions Min Typ Max Unit Charge Termination Detection Termination Current Ratio to Fast Charge (Except USB 100 ITERM Mode) A7.ISETL = 0, A7.ISETU = 1 Or A7.ISETL = 1, A7.ISETU = X 5 10 15 % Termination Current Ratio to Fast Charge (USB100 Mode) ITERM2 A7.ISETL = 0, A7.ISETU = 0 -- 3.3 -- % ICHG = 5mA -- 200 -- mV CHG2 Pull Down Voltage VCHG VCHG2 -- 200 -- mV INT Pull Down Voltage VINT ICHG2 = 5mA IINT = 5mA -- 200 -- mV Login Input/Output CHG Pull Down Voltage Protection Thermal Regulation Point TREG -- 125 -- °C Thermal Shutdown Temperature TSD -- 155 -- °C -- 20 -- °C 6.25 6.5 6.75 V Thermal Shutdown Hysteresis TSD Over-Voltage Protection VOVP VIN Rising Over-Voltage Protection Hysteresis VOVP VIN = 7V to 5V, VOVP VOVP -- 100 -- mV Output Short Circuit Detection VSHORT Threshold VBAT VSYS -- 300 -- mV Battery Installation Detection Threshold at TS EN = H (PMU enabled), report at A10. NoBAT bit -- 90 -- % of VP tOVP -- 50 -- s tPF -- 25 -- ms Fast-Charge to Pre-Charge Deglitch Time tFP -- 25 -- ms Termination Deglitch Time tTERMI -- 25 -- ms Recharge Deglitch Time tRECHG -- 100 -- ms Input Power Loss to SYS LDO tNO_IN Turn-Off Delay Time -- 25 -- ms Pack Temperature Fault Detection Deglitch Time tTS -- 25 -- ms Short-Circuit Deglitch Time tSHORT -- 250 -- s Short-Circuit Recovery Time tSHORT-R -- 64 -- ms 3.234 3.3 3.366 V -- -- 0.1 V Time Input Over-Voltage Blanking Time Pre-Charge to Fast-Charge Deglitch Time Other VP Regulation Voltage VVP VSYS = 4.2V VP Load Regulation VVP VP source out 2mA Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT5072 Parameter VP Under-Voltage Lockout Threshold TS Battery Detect Threshold Symbol Test Conditions Falling Threshold VTS Min Typ Max Unit -- 0.8 -- V 2.75 2.85 2.95 V NTC Temperature Sense Low Temperature Trip Point (0°C) Low Temperature Trip Point (10°C) for JEITA High Temperature Trip Point (45°C) for JEITA High Temperature Trip Point (60°C) % of VP % of VP % of VP % of VP % of VP % of VP % of VP VTOO_COLD NTC = 100k 73 74 75 VTOO_COLD NTC = 10k 59 60 61 VCOLD NTC = 100k 63 64 65 VCOLD NTC = 10k 51 52 53 VHOT NTC = 100k 34 35 36 VHOT NTC = 10k 31 32 33 VTOO_HOT NTC = 100k, A8.TSHT [1:0] = 2’b00 27 28 29 VTOO_HOT NTC = 10k, A8.TSHT [1:0] = 2’b00 27 28 29 -- 1 -- 0.5 -- 0.7 V High Temperature Trip Point Hysteresis for JEITA Charger Detection VDP_SRC Voltage VDP_SRC VDAT_REF Voltage VDAT_REF 0.25 -- 0.4 V VLGC Voltage VLGC 0.8 -- 2.0 V IDP_SRC Current IDP_SRC 6.6 -- 11 A D+ and D- Sink Current ICD+_SINK ICD-_SINK 50 -- 150 A D- Pull down Resistor Data Contact Detect Debounce DCD Time OUT RD-_DWN 14.25 -- 24.8 k TDCD_DBNC 10 15 20 ms TDCD_TO 150 -- 450 ms VDAT_SRC ON Time TDP_SRC_ON 50 -- 100 ms Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 With IDAT_SRC = 0 to 200A % of VP % of VP is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 (VSYS = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit High Level 1.4 -- -- Low Level -- -- 0.6 -- -- 400 kHz 2 I C SDA, SCLK Input Voltage V SCLK Clock Rate fSCL Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. tHD,STA 0.6 -- -- s LOW Period of the SCL Clock tLOW 1.3 -- -- s HIGH Period of the SCL Clock Set-Up Time for a Repeated START Condition Data Hold Time tHIGH tSU,STA 0.6 -- -- s 0.6 -- -- s tHD,DAT 0 -- 0.9 s tSU,DAT 100 -- -- ns tSU,STO 0.6 -- -- s tBUF 1.3 -- -- s tR 20 -- 300 ns tF 20 -- 300 ns 2 -- -- mA Data Set-Up Time Set-Up Time for STOP Condition Bus Free Time between a STOP and START condition Rise time of both SDA and SCL signals Fall Time of Both SDA and SCL Signals SDA and SCL Output Low Sink Current IOL SDA or SCL voltage = 0.4V Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT5072 Typical Application Circuit 37 VBUS VIN SYS 35, 36 33, 34 C2 1µF 30 BAT RT5072 VP DP 38 DN 39 D+ DCharge 2 Indicator CHG2 4 R1 NTC R2 TS RNTC Charge Indicator CHG 8 VSYS R12 10k 2 Motor 5V C3 10µF x 2 VRTC 40 3 LX1 27 C5 10µF PVD2 VO8 LX2B C6 10µF x 2 C7 22pF FB2 SDA 21 C8 4.7µF L3 2.2µH Core 1V R5 232k R13 1k R14 1k I2C Bus 20 32 PVD3 VSYS VSYS VSYS SCL 23 Enable SEQ 12 24 VO2 I/O 3.3V 2.8V C19 1µF EN 14 25 C25 68pF 3.3V 22 26 LX2A L2 2.2µH C9 10µF Wake Up Signal to µP C18 1µF VSYS R4 96k Super Cap PVD8 19 C4 4.7µF R3 300k VRTC C17 0.1µF WAKE 1 L1 2.2µH VSYS PVD1 C27 0.1µF Interrupt to µP INT 17 31 LX3 3.3V R15 10k PVD7 6 Backlight C21 1µF D2 D3 D4 D5 D6 D7 28 FB3 R6 931k 15 PVD45 VSYS C10 10µF C28 0.1µF L4 2.2µH DDRIII 1.5V C11 10µF C26 47pF R7 327k 13 LX4 GND 41 (Exposed Pad) 18 C22 1µF PVD6 10 VSYS 1.5V C23 1µF LX5 VO5/FB5 R16 10 L7 10µH 11 FB4 L5 2.2µH 16 C12 10µF FB7 5 LX7 7 R8 374k 1.8V To USB VSYS R11 10k 29 + VSYS C1 10µF C14 2.2µF VO6 9 1.3V C24 1µF Note : To make CH1 stable, C27 must be close to PVD1. To make CH4 and CH5 stable, C28 must be close to PVD45. Figure 1. Typical Application Circuit for DSC with 6-LED Backlight Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 37 VBUS VIN SYS 35, 36 33, 34 C2 1µF 30 BAT RT5072 VP DP 38 DN 39 D+ DCharge 2 Indicator CHG2 4 R1 NTC R2 TS RNTC Charge Indicator CHG 8 R12 10k 2 Motor 5V C3 10µF x 2 L1 2.2µH VSYS PVD1 C27 0.1µF 3 27 C5 10µF LX1 26 PVD2 PVD8 19 VO8 R4 96k LX2B C6 10µF x 2 23 FB2 L3 2.2µH Core 1V C25 68pF R5 232k 31 LX3 28 FB3 SCL 21 20 SDA C11 10µF C26 47pF 13 LX4 PVD7 6 L5 2.2µH 16 R9 470k I2C Bus 3.3V R15 10k Motor 4.3V C20 1µF LX7 7 Backlight D1 PVD6 10 1.5V C23 1µF VO6 9 LX5 R16 10 41 (Exposed Pad) 11 FB4 R8 374k C12 10µF R14 1k Interrupt to µP GND R7 327k R13 1k FB7 5 C28 0.1µF L4 2.2µH VSYS VSYS 15 PVD45 C10 10µF Enable SEQ 12 INT 17 R6 931k VSYS 2.8V C19 1µF 32 PVD3 VSYS C8 4.7µF C9 10µF 3.3V 22 24 VO2 C7 22pF Super Cap Wake Up Signal to µP EN 14 25 R3 300k VRTC C17 0.1µF LX2A L2 2.2µH 1.8V 40 C18 1µF VSYS DDRIII 1.5V VRTC VSYS WAKE 1 C4 4.7µF I/O 3.3V To USB VSYS R11 10k 29 + VSYS C1 10µF C14 2.2µF 1.3V C24 1µF C13 4.7pF 18 VO5/FB5 R10 374k Note : To make CH1 stable, C27 must be close to PVD1. To make CH4 and CH5 stable, C28 must be close to PVD45. Figure 2. Typical Application Circuit for DSC with One LED Backlight Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT5072 Typical Operating Characteristics VIN = 5V, unless otherwise specified. CH1 Step-Up Efficiency vs. Output Current CH2 Step-Up/Down Efficiency vs. Output Current 100 100 90 90 Efficiency (%) 80 70 60 50 = = = = = = 4.5V 4.2V 3.9V 3.6V 3.3V 2.7V VBAT VBAT VBAT VBAT VBAT 80 Efficiency (%) VBAT VBAT VBAT VBAT VBAT VBAT 40 30 20 70 60 50 40 30 10 VOUT = 5V, L = 2.2μH, COUT = 10μF x 2 0 VOUT = 3.3V, L = 2.2μH, COUT = 10μF x 2 0 10 100 1000 10 100 Output Current (mA) 1000 Output Current (mA) CH3 Step-Down Efficiency vs. Output Current CH4 Step-Down Efficiency vs. Output Current 100 100 90 90 80 80 VBAT VBAT VBAT VBAT VBAT 70 60 50 = = = = = 2.7V 3.3V 3.9V 4.2V 5V Efficiency (%) Efficiency (%) 2.7V 3V 3.6V 4.2V 5V 20 10 40 30 20 VBAT VBAT VBAT VBAT VBAT 70 60 50 = = = = = 2.7V 3.3V 3.9V 4.2V 5V 40 30 20 10 10 VOUT = 1V, L = 2.2μH, COUT = 10μF 0 VOUT = 1.5V, L = 2.2μH, COUT = 10μF 0 10 100 1000 10 100 Output Current (mA) 1000 Output Current (mA) CH5 Step-Down Efficiency vs. Output Current CH7 Efficiency vs. Input Voltage 100 100 90 90 VBAT VBAT VBAT VBAT VBAT 70 60 = = = = = 80 2.7V 3.3V 3.9V 4.2V 5V Efficiency (%) 80 Efficiency (%) = = = = = 50 40 30 20 70 60 50 40 30 20 10 VOUT = 1.8V, L = 2.2μH, COUT = 10μF 0 10 L = 10μH, COUT = 1μF, IOUT = 6WLEDs 0 10 100 Output Current (mA) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 1000 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 Input Voltage (V) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 CH2 Step-Up/Down Output Voltage vs. Output Current 5.20 3.55 5.15 3.50 5.10 3.45 Output Voltage (V) Output Voltage (V) CH1 Step-Up Output Voltage vs. Output Current 5.05 5.00 VSYS VSYS VSYS VSYS 4.95 4.90 = = = = 2.7V 3.4V 4.2V 5V 3.40 3.35 VSYS VSYS VSYS VSYS 3.30 3.25 = = = = 2.7V 3.4V 4.2V 5V 3.20 4.85 VOUT = 5V VOUT = 3.3V 4.80 3.15 0 200 400 600 800 1000 0 100 200 1.525 1.015 1.520 1.010 1.515 1.005 1.000 0.995 0.990 = = = = 400 500 2.7V 3.4V 4.2V 5V 1.510 1.505 VSYS VSYS VSYS VSYS 1.500 1.495 = = = = 2.7V 3.4V 4.2V 5V 1.490 0.985 VOUT = 1V VOUT = 1.5V 0.980 1.485 0 200 400 600 800 1000 0 200 Output Current (mA) 1.83 1.375 1.82 1.350 Output Voltage (V) 1.400 1.81 1.80 1.79 1.78 = = = = 600 800 1000 CH6 LDO Output Voltage vs. Output Current 1.84 VSYS VSYS VSYS VSYS 400 Output Current (mA) CH5 Step-Down Output Voltage vs. Output Current Output Voltage (V) 600 CH4 Step-Down Output Voltage vs. Output Current 1.020 Output Voltage (V) Output Voltage (V) CH3 Step-Down Output Voltage vs. Output Current VSYS VSYS VSYS VSYS 300 Output Current (mA) Output Current (mA) 2.7V 3.4V 4.2V 5V 1.325 1.300 PVD6 = 1.5V PVD6 = 3.3V 1.275 1.250 1.225 1.77 VOUT = 1.8V 1.76 VOUT = 1.3V 1.200 0 200 400 600 800 Output Current (mA) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 1000 0 50 100 150 200 250 300 350 400 Output Current (mA) is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT5072 CH8 LDO Output Voltage vs. Output Current CH1 Output Voltage Ripple 2.600 Output Voltage (V) 2.575 2.550 LX1 (5V/Div) 2.525 2.500 V OUT_CH1_ac (5mV/Div) PVD8 = 2.7V PVD8 = 3.3V 2.475 2.450 VBAT = 3.7V, VOUT = 5V, IOUT = 400mA, L = 2.2μH, COUT = 10μF x 2 2.425 VOUT = 1.3V 2.400 0 50 Time (500ns/Div) 100 150 200 250 300 350 400 450 500 Output Current (mA) CH2 Output Voltage Ripple CH3 Output Voltage Ripple LX2 (5V/Div) LX3 (5V/Div) V OUT_CH2_ac (5mV/Div) V OUT_CH3_ac (5mV/Div) VBAT = 3.7V, VOUT = 3.3V, IOUT = 400mA, L = 2.2μH, COUT = 10μF x 2 VBAT = 3.7V, VOUT = 1V, IOUT = 400mA, L = 2.2μH, COUT = 10μF Time (500ns/Div) Time (500ns/Div) CH4 Output Voltage Ripple CH5 Output Voltage Ripple LX4 (5V/Div) LX5 (5V/Div) V OUT_CH4_ac (5mV/Div) V OUT_CH5_ac (5mV/Div) VBAT = 3.7V, VOUT = 1.5V, IOUT = 400mA, L = 2.2μH, COUT = 10μF Time (500ns/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 VBAT = 3.7V, VOUT = 1.8V, IOUT = 400mA, L = 2.2μH, COUT = 10μF Time (500ns/Div) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 CH1 Load Transient Response CH2 Load Transient Response IOUT (200mA/Div) IOUT (200mA/Div) V OUT_CH1_ac (100mV/Div) V OUT_CH2_ac (50mV/Div) VBAT = 3.7V, VOUT = 3.3V, IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF x 2 VBAT = 3.7V, VOUT = 5V, IOUT = 0 to 300mA, L = 2.2μH, COUT = 10μF x 2 Time (250μs/Div) Time (250μs/Div) CH3 Load Transient Response CH4 Load Transient Response IOUT (200mA/Div) IOUT (200mA/Div) V OUT_CH3_ac (20mV/Div) V OUT_CH4_ac (50mV/Div) VBAT = 3.7V, VOUT = 1V, IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF VBAT = 3.7V, VOUT = 1.5V, IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF Time (250μs/Div) Time (250μs/Div) CH5 Load Transient Response CH6 Load Transient Response IOUT (200mA/Div) IOUT (200mA/Div) V OUT_CH5_ac (50mV/Div) V OUT_CH6_ac (50mV/Div) VBAT = 3.7V, VOUT = 1.8V, IOUT = 100mA to 300mA, L = 2.2μH, COUT = 10μF Time (250μs/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 VBAT = 3.7V, VOUT = 1.3V, IOUT = 100mA to 300mA, COUT = 1μF Time (250μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT5072 Power On Sequence 0 CH8 Load Transient Response IOUT (200mA/Div) VOUT_2 (2V/Div) V OUT_CH8_ac (50mV/Div) VOUT_3 (1V/Div) VBAT = 3.7V, VOUT = 2.5V, IOUT = 100mA to 300mA, COUT = 1μF VOUT_4 (1V/Div) Time (250μs/Div) Time (5ms/Div) Power Off Sequence 0 Power On Sequence 1 VOUT_2 (2V/Div) VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_3 (1V/Div) VOUT_3 (1V/Div) VOUT_4 (1V/Div) VOUT_4 (1V/Div) VBAT = 3.7V VBAT = 3.7V Time (500μs/Div) Time (5ms/Div) Power Off Sequence 1 Power On Sequence 2 VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_3 (1V/Div) VOUT_3 (1V/Div) VOUT_4 (1V/Div) VOUT_4 (1V/Div) VBAT = 3.7V Time (1ms/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 24 VBAT = 3.7V VBAT = 3.7V Time (5ms/Div) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Power Off Sequence 2 Power On Sequence 3 VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_3 (1V/Div) VOUT_3 (1V/Div) VOUT_4 (1V/Div) VOUT_4 (1V/Div) VBAT = 3.7V VBAT = 3.7V Time (1ms/Div) Time (5ms/Div) Power Off Sequence 3 Power On Sequence 4 VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_3 (1V/Div) VOUT_3 (1V/Div) VOUT_4 (1V/Div) VBAT = 3.7V VOUT_4 (1V/Div) VBAT = 3.7V Time (1ms/Div) Time (5ms/Div) Power Off Sequence 4 Power On Sequence 5 VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_1 (5V/Div) VOUT_2 (5V/Div) VOUT_3 (1V/Div) VOUT_3 (1V/Div) VOUT_4 (1V/Div) VOUT_4 (1V/Div) VBAT = 3.7V Time (5ms/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 VBAT = 3.7V Time (5ms/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 25 RT5072 Charge On/Off Control by I2C Power Off Sequence 5 VOUT_1 (5V/Div) VOUT_2 (5V/Div) VSDA (5V/Div) V CHG (5V/Div) VOUT_3 (1V/Div) VBAT (5V/Div) IBAT (500mA/Div) VOUT_4 (1V/Div) VBAT = Real Battery, 500mA Mode VBAT = 3.7V Time (1ms/Div) Time (50ms/Div) VTS On/Off VIN Removal VBAT = Real Battery, RSYS = 10Ω, 1.5A Mode VIN (5V/Div) VTS (2V/Div) V CHG1 (5V/Div) V SYS (5V/Div) VBAT (5V/Div) IBAT (500mA/Div) VBAT = Real Battery, 500mA Mode, control VTS by Function Generator VIN (10V/Div) VBAT (5V/Div) IBAT (2A/Div) Time (500ms/Div) Time (10ms/Div) VIN Over Voltage Protection Battery with NTC Resistor Plug-In VIN = 5V to 15V, VBAT = Real Battery, 1.5A Mode IBAT (500mA/Div) V SYS (5V/Div) VBAT (5V/Div) VBAT (5V/Div) IBAT (2A/Div) VIN (5V/Div) VTS (5V/Div) Time (500ms/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 26 VBAT = Real Battery, 500mA Mode Time (50ms/Div) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Battery with NTC Resistor Plug-Out With Battery without NTC Resistor IBAT (500mA/Div) IBAT (500mA/Div) VBAT (5V/Div) VBAT (5V/Div) VIN (5V/Div) VIN (5V/Div) VTS (5V/Div) VBAT = Real Battery, 500mA Mode VTS (5V/Div) Time (250ms/Div) With NTC Resistor without Battery Time (50ms/Div) VIN Exist then Negative Battery and Plug-out IBAT (500mA/Div) VBAT (5V/Div) VBAT (5V/Div) VIN (5V/Div) V SYS (10V/Div) VIN (5V/Div) VTS (5V/Div) VBAT = Real Battery, 500mA Mode VBAT = Real Battery, 500mA Mode I IN (100mA/Div) VBAT = Real Battery, RSYS = 50Ω, 100mA Mode Time (50ms/Div) Time (500ms/Div) Negative Battery then VIN Plug-In The Temperature of Battery Status Normal -> Too Cold (Voltage) VBAT = Real Battery, RSYS = 10Ω, 500mA Mode VBAT (5V/Div) VTS (2V/Div) VIN (5V/Div) V SYS (10V/Div) I IN (500mA/Div) VBAT (2V/Div) Time (50ms/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 JEITA = 0, VSETH = 1, VSETC = 1, or JEITA = 0, VSETH = 0, VSETC = 1, or JEITA = 1, VSETH = 1, VSETC = x VBAT = Real Battery, 1.5A Mode Time (25ms/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 27 RT5072 The Temperature of Battery Status The Temperature of Battery Status Normal -> Cold -> Too Cold (Voltage) Normal -> Too Cold (Current) VTS (2V/Div) JEITA = 0, VSETH = 0, VSETC = 0, or JEITA = 0, VSETH = 1, VSETC = 0 VTS (2V/Div) JEITA = 0, ISETH = 1, ISETC = 1, or JEITA = 0, ISETH = 0, ISETC = 1, or JEITA = 1, ISETH = 1, ISETC = x IBAT (1A/Div) VBAT (2V/Div) VBAT = Real Battery, 1.5A Mode VBAT = Real Battery, 1.5A Mode Time (25ms/Div) Time (25ms/Div) The Temperature of Battery Status The Temperature of Battery Status Normal -> Cold -> Too Cold (Current) Normal -> Too Hot (Voltage) VTS (2V/Div) JEITA = 0, ISETH = 0, ISETC = 0, or JEITA = 0, ISETH = 1, ISETC = 0 VTS (2V/Div) JEITA = 0, VSETH = 1, VSETC = 1, or JEITA = 1, VSETH = 1, VSETC = x IBAT (1A/Div) VBAT (2V/Div) VBAT = Real Battery, 1.5A Mode VBAT = Real Battery, 1.5A Mode Time (25ms/Div) Time (25ms/Div) The Temperature of Battery Status The Temperature of Battery Status Normal -> Hot -> Too Hot (Voltage) Normal -> Too Hot (Current) VTS (2V/Div) VTS (2V/Div) JEITA = 0, VSETH = 0, VSETC = 0, or JEITA = 0, VSETH = 0, VSETC = 1 VBAT (2V/Div) JEITA = 0, VSETH = 1, VSETC = 0, or IBAT (1A/Div) VBAT = Real Battery, 1.5A Mode Time (25ms/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 28 JEITA = 0, ISETH = 1, ISETC = 0, or JEITA = 0, ISETH = 1, ISETC = 1, or JEITA = 1, ISETH = 1, ISETC = x VBAT = Real Battery, 1.5A Mode Time (25ms/Div) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 The Temperature of Battery Status APPM VBAT = Real Battery, 1.5A Mode ISYS = 0A to 2A Normal -> Hot -> Too Hot (Current) VIN VTS (2V/Div) V SYS VBAT JEITA = 0, ISETH = 0, ISETC = 0, or JEITA = 0, ISETH = 0, ISETC = 1, I SYS IBAT (1A/Div) I IN (1V/Div) / (1A/Div) IBAT Time (25ms/Div) Time (1ms/Div) OVP Threshold Voltage vs. Temperature 6.52 5.03 6.50 5.01 6.48 OVP Voltage (V) System Regulation Voltage (V)1 System Regulation Voltage vs. Temperature 5.05 4.99 4.97 4.95 4.93 4.91 Rising 6.46 6.44 6.42 6.40 Falling 6.38 4.89 6.36 4.87 6.34 ISYS = 0.5A 6.32 4.85 -50 -25 0 25 50 75 100 -50 125 -25 0 50 75 100 125 VIN - VSYS Dropout Voltage vs. Temperature VBAT - VSYS Dropout Voltage vs. Temperature 450 100 425 400 375 350 325 300 275 250 225 ISYS = 1A VBAT - VSYS Dropout Voltage (mV) VIN - VSYS Dropout Voltage (mV) 25 Temperature (°C) Temperature (°C) 95 90 85 80 75 70 65 60 55 VBAT = 3.7V, ISYS = 1A, USUS = H 50 200 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 29 RT5072 ICHG Thermal Regulation vs. Temperature Battery Regulation Voltage vs. Temperature 4.26 450 4.24 400 4.22 Battery Voltage (V) I CHG Thermal Regulation (mA) 500 350 300 250 200 150 4.20 4.18 4.16 4.14 100 4.12 50 VBAT = Real Battery VBAT = Real Battery 0 4.10 -50 -25 0 25 50 75 100 125 -50 -25 Temperature (°C) 25 50 75 100 125 Temperature (°C) Pre-charge Current vs. Battery Voltage Fast-charge Current vs. Battery Voltage 80 800 70 750 Fast-charge Current (mA) Pre-charge Current (mA) 0 60 50 40 30 20 10 700 650 600 550 500 450 0 400 2 2.2 2.4 2.6 2.8 Battery Voltage (V) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 30 3 3 3.2 3.4 3.6 3.8 4 4.2 Battery Voltage (V) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Application Information Power Converter Unit The RT5072 is an integrated power solution for digital still cameras and other small handheld devices. It includes six DC/ DC converters, a WLED driver, two low output LDO, a RTC LDO, and a fully integrated single-cell Li-ion battery charger that is ideal for portable applications. CH1 : Synchronous Step-Up DC/DC Converter The synchronous step-up DC/DC converter can be operated in either PFM or Sync-PWM mode by setting I2C. It includes internal power MOSFETs, compensation network and feedback resistors. The P-MOSFET can be controlled to disconnect output loading. It is suitable for providing power to the motor. The output voltage of CH1 can be adjusted by the I2C interface in the range of 3.6V to 5.5V. 2 CH1 regulation voltage can be selected by I C interface. The default voltage is 5V. VOUT1 [3:0] Code Voltage Code Voltage Code Voltage Code Voltage 0000 3.6V 0001 3.7V 0010 3.8V 0011 3.9V 0100 1000 4V 4.8V 0101 1001 4.5V 4.9V 0110 1010 4.6V 5V 0111 1011 4.7V 5.1V 1100 5.2V 1101 5.3V 1110 5.4V 1111 5.5V CH2 : Synchronous Step-Up/Down (Buck-Boost) DC/DC Converter The synchronous step-up/down (Buck-Boost) DC/DC converter can be operated in either PFM or Sync-PWM mode by setting I2C. It includes internal power MOSFETs, compensation network and feedback resistors. This channel supplies the power for I/O. The FB voltage of CH2 can be adjusted by the I2C interface in the range of 0.72V to 0.86V. 2 FB2 regulation voltage can be selected by I C interface. The default voltage is 0.8V. FB2 [2:0] Code VREF If Target = 1.8V If Target = 1V If Target = 3.3V 000 0.72V 1.62V 0.9V 2.97V 001 010 0.74V 0.76V 1.665V 1.71V 0.925V 0.95V 3.0525V 3.135V 011 100 101 110 0.78V 0.8V 0.82V 0.84V 1.755V 1.8V 1.845V 1.89V 0.975V 1V 1.025V 1.05V 3.2175V 3.3V 3.3825V 3.465V 111 0.86V 1.935V 1.075V 3.5475V Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 31 RT5072 CH3 to CH4 : Step-Down Synchronous DC/ DC Converter The step-down synchronous DC/ DC converters include internal power MOSFETs and compensation network. It support PFM or Sync-PWM mode by setting I2C. These channels supply the power for core and DRAM. They can be operated at 100% maximum duty cycle to extend battery operating voltage range. When the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. The FB voltage of CH3 and CH4 can be adjusted by the I2C interface in the range of 0.72V to 0.86V. 2 FB3 regulation voltage can be selected by I C interface. The default voltage is 0.8V. FB3 [2:0] Code VREF If Target = 1.8V If Target = 1V If Target = 3.3V 000 0.72V 1.62V 0.9V 2.97V 001 0.74V 1.665V 0.925V 3.0525V 010 0.76V 1.71V 0.95V 3.135V 011 0.78V 1.755V 0.975V 3.2175V 100 0.8V 1.8V 1V 3.3V 101 0.82V 1.845V 1.025V 3.3825V 110 0.84V 1.89V 1.05V 3.465V 111 0.86V 1.935V 1.075V 3.5475V 2 FB4 regulation voltage can be selected by I C interface. The default voltage is 0.8V. FB4 [2:0] Code VREF If Target = 1.8V If Target = 1V If Target = 3.3V 000 0.72V 1.62V 0.9V 2.97V 001 0.74V 1.665V 0.925V 3.0525V 010 0.76V 1.71V 0.95V 3.135V 011 0.78V 1.755V 0.975V 3.2175V 100 0.8V 1.8V 1V 3.3V 101 0.82V 1.845V 1.025V 3.3825V 110 0.84V 1.89V 1.05V 3.465V 111 0.86V 1.935V 1.075V 3.5475V If CH3/CH4 input voltage (PVD3/PVD45) is higher than 4.2V and the output voltage is lower than 1.5V, a feed forward capacitor can be added to improve the transient response. The capacitance can be estimated by the following equation : 6 Cff = 15.5 10 R1 For example, when R1 is 470kΩ, the available feed-forward capacitor is 33pF. VOUT Cff R1 FB R2 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 32 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 CH5 : Step-Down Synchronous DC/ DC Converter The step-down synchronous DC/ DC converter includes internal power MOSFETs and compensation network. They can be operated at 100% maximum duty cycle to extend battery operating voltage range. When the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. The output voltage can be selected as the following list or set by external feedback network. 2 CH5 regulation voltage can be selected by I C interface. The default voltage is 1.8V. VOUT5 [3:0] Code Voltage Code Voltage Code Voltage Code Voltage 0000 REF 0001 1.1V 0010 1.2V 0011 1.3V 0100 1.4V 0101 1.5V 0110 1.6V 0111 1.7V 1000 1.8V 1001 2V 1010 2.2V 1011 2.3V 1100 2.5V 1101 2.6V 1110 2.7V 1111 2.8V Note : VOUT5 [3:0] = 0000 (REF) means using external feedback network and FB5 regulation target is 0.8V 1.5% CH6 : Low Voltage LDO CH6 is a low voltage LDO and its output voltage is controlled by I2C interface. This supplies the multiple purpose power. The output voltage of CH6 can be adjusted by the I2C interface in the range of 1.1V to 3.3V. 2 CH6 regulation voltage can be selected by I C interface. The default voltage is 1.3V. VOUT6 [3:0] Code Voltage Code Voltage Code Voltage Code Voltage 0000 Switch 0001 1.1V 0010 1.2V 0011 1.3V 0100 1.4V 0101 1.5V 0110 1.6V 0111 1.7V 1000 1.8V 1001 2V 1010 2.2V 1011 2.5V 1100 2.8V 1101 3.1V 1110 3.2V 1111 3.3V CH7 : Current Source/Step-Up WLED Driver The WLED drivers operating in either current source mode or synchronous step-up mode include internal power MOSFET and compensation network. The operation mode is determined by setting I2C. The P-MOSFET in step-up mode can be controlled to disconnect the output loading. When CH7 works in current source mode, it likes a LDO and regulates the current by FB7 voltage. The LED current is defined by the FB7 voltage as well as the external resistor between FB7 and GND. The FB7 regulation voltage can be set in 31 steps from 8mV to 250mV. If CH7 works in synchronous step-up mode, it can support an output voltage up to 15V or 21V controlled by I2C interface. The LED current is also set via an external resistor and FB7 regulation voltage. The WLED current can be set by the following equation : ILED (mA) = [250mV / R (Ω)] x EN7_DIM7 [4:0] / 31 where R is the current sense resistor from FB7 to GND and for the EN7_DIM7 [4:0] / 31 ratio, refer to the I2C control register file. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 33 RT5072 CH8 : Low Voltage LDO CH8 is a low voltage LDO and its output voltage is controlled by I2C interface. It supplies for multiple purpose power. The output voltage of CH8 can be adjusted by the I2C interface in the range of 1.1V to 3.3V. 2 CH8 regulation voltage can be selected by I C interface. The default voltage is 2.8V. VOUT8 [3:0] Code Voltage Code Voltage Code Voltage Code Voltage 0000 Switch 0001 1.1V 0010 1.2V 0011 1.3V 0100 1.4V 0101 1.5V 0110 1.6V 0111 1.7V 1000 1100 1.8V 2.8V 1001 1101 2V 3.1V 1010 1110 2.2V 3.2V 1011 1111 2.5V 3.3V RTC_LDO : Accuracy 3.05V LDO Output. The RT5072 provides a 3.05V output LDO for real-time clock. The LDO features low quiescent current (3μA), reverse leakage prevention from output node and high output voltage accuracy. This LDO is always on, even when the system is shut down. For better stability, it is recommended to connect a 0.1μF capacitor to the RTCPWR pin. The RTC LDO includes pass transistor body diode control to avoid the RTCPWR node from back-charging into the input node VDDI. Switching Frequency The converters of CH1, CH3, CH4 and CH5 operate in PWM mode with 2MHz switching frequency. The converters of CH2 and CH7 operates in PWM mode with 1MHz switching frequency. Power-On/Off Sequence and deglitch function for CH1 to CH4 SEQ pull down resistance RSEQ defines power on/off sequence. SEQ# SEQ #0 SEQ #1 SEQ #2 SEQ #3 SEQ #4 SEQ #5 RSEQ (k) Range Min Typ Max Short to Power (>0.2V) 25 40 64 6.25 10 16 1.56 2.5 4 -0.63 1 100 160 -- SEQ # 0 : CH2 CH3 CH4 (CH1 is decided by register A4 bit3.) SEQ # 1 : CH1 CH3 CH2 CH4 SEQ # 2 : CH1 CH3 CH4 CH2 SEQ # 3 : CH1 CH2 CH4 CH3 SEQ # 4 : CH1 CH4 CH3 CH2 SEQ # 5 : CH1 CH4 CH2 CH3 Floating = resistance greater than 160kΩ Ω = SEQ#5 The power-on sequence of CH1 to CH4 is shown below : (Using SEQ #3 : CH1 CH2 CH4 CH3 to explain) When EN1234 goes high, CH1 will be turned on first then CH2 will be turned on after CH1 turn on for 10ms, likewise, CH4 will be turned on after CH2 turns on for 10ms. Finally, CH3 is turned on after CH4 turns on for 10ms. The soft-start time is 4ms for each channel. The power-off sequence of CH1 to CH4 is : When EN1234 goes low, CH3 will turn off first and internally discharge output via LX3 pin. When FB3 < 0.1V, CH4 will turn off and also internally discharge output via the LX4 pin. When FB4 < 0.1V, CH2 will turn off and internally discharge output via the LX2 pin. Likewise, when FB2 < 0.1V, CH1 will turn off and discharge output. After FB1 < 0.1V, CH1 to CH4 shutdown sequence is completed. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 34 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 Power off Sequence Power on Sequence SEQ detection POR and Enable VREF/IREF/OSC RT5072 External EN VREF/IREF /OSC/POR Latch SEQ detection result SEQ_Ready VOUT1 (5V) tR 4ms tD 10ms VOUT2 (3.3V) tR 4ms tD 10ms VOUT4 (1.5V) tR 4ms tD 10ms VOUT3 (1.1V) 2 Each Enabled in I C VOUT6 Enabled in I C Power on Sequence Power on Sequence External EN VREF/IREF/ OSC/POR Power off Sequence would finish and then re-start POR and Enable VREF/IREF/OSC SEQ detection 2 SEQ detection POR and Enable VREF/IREF/OSC VOUT5 EN going low take no effect during on sequence period. Last channel discharge finish and then reset SEQ detection result and issue next time to re-detect SEQ Latch SEQ detection result Latch SEQ detection result SEQ_Ready VOUT1 (5V) VOUT2 (3.3V) tD tR 4ms tD 10ms tR 4ms 10ms VOUT4 (1.5V) VOUT3 (1.1V) tR 4ms tD 10ms tD tR 4ms 10ms tR 4ms tD 10ms tR 4ms tD 10ms During On sequence period, EN goes low would not take effect. After the sequence finishes, the EN state would be re-checked and decide to keep on or start off sequence. During Off sequence period, EN goes high would not take effect. After the sequence finishes, the EN state would be re-checked and decide to keep off or start on sequence. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 35 RT5072 VDDM Bootstrap To support bootstrap function, the RT5072 provides a power selection circuit which selects the maximum voltage between SYS and PVD1 to support the power requirement at node VDDI. The RT5072 includes UVLO circuits to monitor VDDI and SYS voltage status. SYS PVD1 VDDI = Max (SYS, PVD1) Charger Unit The RT5072 includes a Li-ion battery charger with Automatic Power Path Management. The charger is designed to operate in below modes : Pre-Charge Mode When the output voltage is lower than 2.8V, the charging current will be reduced to a ratio of the fast-charge current set by A8.ISETA [3:0] to protect the battery life-time. The timing diagram is showed in Figure 3. Fast-Charge Mode When the output voltage is higher than 3V, the charging current will be equal to the fast-charge current set by A8.ISETA [3:0] shown as Figure 3. Constant Voltage Mode When the output voltage is near 4.2V and the charging current falls below the termination current for a deglitch time of 25ms, the charger will be disabled and CHG will go high. The timing diagram is showed in Figure 3. Re-Charge Mode When the chip is in charge termination mode, the charging current gradually goes down to zero. Once the battery voltage drops to below 4.1V for a deglitch time of 100ms, the charger will resume charging shown as Figure 3. 4.16 to 4.2 to 4.23V −40°C to 85°C Battery Voltage Charging Current VRECH If VPRECH ISETL = 1, ISETU = 1 ISETL = 0, ISETU = X ITERMI = 10% x ICHG_FAST If ISETL = 0, ISETU = 0 ITERMI = 3.3% x ICHG_FAST ICHG_PRE = 10% x ICHG_FAST ITERM2 Time Figure 3 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 36 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Interrupt Indicator The RT5072 provides an interrupt indicator output pin (INT). INT is an open-drain output which is controlled by A9.INT bit. When the PGOOD, TS_Meter [2:0], EOC, THR, SAFE, NoBAT, CHGRUN, DPM status bits toggle, the A9.INT bit will be set to high. In order to reset the interrupt status, a “0” must be written to the A9.INT bit or power on the PMU again. The timing diagram is shown below : Interrupt vs. Events (I2C Status Bits) INT assert (Turn to low) PGOOD NoBAT When PMU turns on with event condition Event has No Event (0) occurred (1) No Yes No Yes During PMU on Event appear (0 1) Yes Yes Event disappear (1 0) Yes Yes TS_METER [2:0] = 000 (Event may be cold or hot, VP UVLO, NoBAT) No Yes Yes Yes EOC THR SAFE No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes DPM CHGRUN No No Yes No Yes No Yes Yes INT vs. Fault/Status Timing Diagram NoBAT PGOOD EOC THR SAFE TS_Meter [2:0] CHGRUN DPM (Mask_DPM = 0) INT A9.INT bit is written to "0" When the A9.INT bit is written to "0", the INT will be set to high. When Mask_DPM = 1 and DPM event change, the INT would not be asserted. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 37 RT5072 Battery Installation Detection The RT5072 also detects TS voltage to monitor the battery status. If PMU is enabled but TS voltage > 90% of VP node voltage, the RT5072 sets the bit. NoBAT = 1 an I2C register A10.NoBAT and sets A9.INT bit to “1”. NoBAT 1 No Battery Installed (TS > 90% of VP) 0 BAT Installed VIN Power Good Status PGOOD 0 VIN < VUVLO 0 VUVLO < VIN < VBAT + VOS_L 1 VBAT + VOS_H < VIN < VOVP 0 VIN > VOVP End_Of_Charge (EOC) Status The bit EOC in I2C register A10.EOC can show the EOC status. If EOC = 1, the charger is in EOC state and A9.INT bit is set to “1” EOC 1 Charging Done or Recharging after Termination 0 During Charging Wake-Up Detector Wake-Up Detector detects VIN or BAT plug-in events. Once BAT plugs in or VIN plugs in for a 19ms deglitch time, the WAKE pin will provide a 90ms width high pulse. The timing diagram is shown as below : SDP VIN > 3.75V VIN 3.75V BAT > 3.1V 3.1V BAT > 3.1V 3.1V 3.1V BAT 20ms WAKE 90ms 20ms 90ms BAT > 3.1V WAKE Up VIN > 3.75V when BAT >3.1V WAKE UP Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 38 20ms 2.82V 20ms 90ms BAT > 3.1V WAKE Up <90ms BAT <2.82V (3.1V–0.28V) When VIN <3.15V (3.75V0.24V) Disable WAKE Up Suddenly is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 CDP/DCP WAKE go low as VIN go low VIN VIN > 3.75V 3.75V 3.51V BAT > 3.1V 3.1V BAT > 3.1V 3.1V 3.1V BAT 300ms 20ms 20ms 20ms 20ms 2.82V 20ms < 90ms WAKE 90ms 90ms 90ms 90ms BAT > 3.1V WAKE Up VIN > 3.75V when BAT >3.1V WAKE UP BAT > 3.1V WAKE Up RT5072 needs 300mSec to do charging type detection after VIN plug in and larger than threshold. BAT <2.82V (3.1V–0.28V) When VIN <3.15V (3.75V-0.24V) Disable WAKE Up Suddenly When external EN pin go high, WAKE UP impulse would be masked off. WAKE impulse width 90ms can not be cut by EN = H 90ms WAKE BAT exists VIN plug in BAT plug in EN No WAKE impulse 90ms BAT/VIN plug in Suspend Mode When USUS = 1, the charger will enter Suspend Mode. In Suspend Mode, the CHG pin is high impedance and IUSUS(MAX) < 300μA. Charging Current Decision The charge current can be set according to the I2C register A8.ISETA [3:0] setting : RT5072 allows user to set the battery charge current level and the list as below. The default value is 0.5A. BAT Charge BAT Charge BAT Charge BAT Charge Code Code Code Code Current Current Current Current ISETA [3:0] 0000 0.1A 0001 0.2A 0010 0.3A 0011 0.4A 0100 0.5A 0101 0.6A 0110 0.7A 0111 0.8A 1000 0.9A 1001 1A 1010 1.1A 1011 1.2A 1100 1.2A 1101 1.2A 1110 1.2A 1111 1.2A Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 39 RT5072 Fault-Time During the fast charge phase, several events may increase the charging time. For example, the system load current may have activated the APPM loop which reduces the available charging current or the device has entered thermal regulation because the IC junction temperature has exceeded TREG. However, once the duration exceeds the fault-time, the CHG output pin will flash at approximately 4Hz to indicate a fault condition and the charge current will be reduced to about 1mA. There are four methods to release the Fault-time : Re-plug power Toggle EN Enter/exit suspend mode Remove Battery OVP The fault-time is inverse proportional to the charger current. 1 Fault-Time Icharge Example : If the sensing battery temperature is hot or cold, the charge current will reduce to half charge current. So, the fault-time will increase to be double. JEITA Battery Temperature Standard CV regulation voltage will be changed in the following battery temperature ranges : 0°C to 10°C and 45°C to 60°C. This function can be disabled by A9.VSETH and A9.VSETC. CC regulation current will be changed in the following battery temperature ranges : 0°C to 10°C and 45°C to 60°C. This function can be disabled by A9.ISETH and A9.ISETC. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 40 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 0°C JEITA = 0 VSETH = 0 VSETC = 0 ISETH = 0 ISETC = 0 10°C Cold 4.2V 45°C 60°C Hot VSETC = 0 VSETH = 0 0.5 x ICHG ISETC = 0 ISETH = 0 4.05V ICHG TS JEITA = 0 VSETH = 1 VSETC = 0 ISETH = 1 ISETC = 0 4.2V 4.05V VSETC = 0 VSETH = 1 ISETC = 0 ISETH = 1 ICHG 0.5 x ICHG TS JEITA = 0 VSETH = 1 VSETC = 1 ISETH = 1 ISETC = 1 4.2V 4.05V VSETC = 1 VSETH = 1 ISETC = 1 ISETH = 1 ICHG 0.5 x ICHG TS JEITA = 0 VSETH = 0 VSETC = 1 ISETH = 0 ISETC = 1 4.2V VSETH = 0 4.05V VSETC = 1 ICHG 0.5 x ICHG ISETH = 0 ISETC = 1 TS 0°C JEITA = 1 VSETH = 1 VSETC = x ISETH = 1 ISETC = x 10°C 45°C 60°C 4.2V 4.05V VSETH = 1 ICHG 0.5 x ICHG ISETH = 1 TS JEITA = 1 VSETH = 0 VSETC = x ISETH = 0 ISETC = x 4.2V 4.05V VSETH = 0 ICHG 0.5 x ICHG ISETH = 0 TS Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 41 RT5072 Battery Pack Temperature Monitoring The battery pack temperature monitoring function can be realized by connecting the TS pin to an external Negative Temperature Coefficient (NTC) thermal resistor to prevent over temperature condition. Charging is suspended when the voltage at the TS pin is out of normal operating range. The internal timer is then paused, but the value is maintained. When the TS pin voltage returns to normal operating range, charging will resume and the safe charge timer will continue to count down from the point where it was suspended. Note that although charging is suspended due to the battery pack temperature fault, the CHG pin will flash at 0.5Hz and indicate charging. The 3.3V at the VP pin is buffered by the RT5072 once it is in charging state or its PMU part is enabled. If a 100kΩ NTC thermal resistor is used, the A0.TSSEL bit should be set to “1”. If a 10kΩ NTC thermal resistor is used, the A0.TSSEL bit should be set to “0”. The TSSEL bit determines the TS threshold levels for 0°C and 60°C. It also defines the TS threshold levels used in JEITA operation. The choosing method of R1 and R2 to meet battery temperature monitoring shows as below. Case 1 : TSSEL = H (For 100kΩ NTC) : Case 2 : TSSEL = L (For 10kΩ NTC) : VP VP VP VP R1 TS 0.74 x VP + - R2 0.28 x VP + 0.6 x VP R1 Too Cold TS + - R2 Too Hot - + Too Cold Too Hot 0.28 x VP RNTC RNTC Figure 4 Figure 5 Too Cold Temperature Too Cold Temperature RCOLD = RNTC RCOLD = RNTC Too Hot Temperature Too Hot Temperature RHOT = RNTC RHOT = RNTC R2 RCOLD = 0.74 --------------------------------------- (1) RCOLD R1 R2 R2 + RCOLD = 0.6 ------------------------------------------ (1) RCOLD +R1+R2 R2 RHOT = 0.28 ----------------------------------------- (2) RHOT R1 R2 R2 + RHOT = 0.28 ------------------------------------------ (2) RHOT +R1+R2 Form (1), (2) Form (1), (2) R1 = RCOLD RHOT 2.457 R1 = 0.9 RCOLD RHOT R2 = 0.389 R1 RHOT R2 = 0.388 R1 RHOT If R2 < 0 If R2 < 0 RCOLD = 0.74 ---------------------------------------------- (3) RCOLD R1 RCOLD = 0.6 ------------------------------------------------- (3) RCOLD +R1 Form (3) R R1 = COLD RCOLD 0.74 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 42 Form (3) R1 = RCOLD RCOLD 0.6 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 The Control Temperature Used in JEITA Operation The above calculation gives R1 and R2. JEITA control thresholds for full charging current and 4.2V regulation voltage are at TS/VP ratio = 32% and 52% (for TSSEL = L), 35% and 64% (for TSSEL = H). With the ratio, the corresponding NTC thermistor resistances from the resistors in the voltage divider circuit can be obtained. According to the NTC resistances, the corresponding temperatures can be found. The two temperatures are the control temperatures used in JEITA operation. Operation State Diagram for TS Pin (TSSEL = H) Any State No 74% x VVP < VTS < 2.85V No VTS > 2.85V Or VTS < 28% x VVP Yes Yes TS fault State Battery Remove State ICHG = 0A ICHG = 0A CHG 4Hz flash rate CHG 4Hz flash rate Power Switch For the charger, there are three power scenarios : When a battery and an external power supply (USB or adapter) are connected simultaneously If the system required load exceeds the input current limit, the battery will be used to supplement the current to the load. However, if the system load is less than the input current limit, the excess power from the external power supply will be used to charge the battery. When only the battery is connected to the system The battery provides the power to the system. When only an external power supply is connected to the system The external power supply provides the power to the system. Input DPM Mode For the charger, the input voltage is monitored when USB100 or USB500 is selected. If the input voltage is lower than VDPM, the input current limit will be reduced to stop the input voltage from dropping further. This can prevent the IC from damaging improperly configured or inadequately designed USB sources. If VIN charger type is detected as SDP, the DPM function always is enabled. For other types, the DPM function always is disabled but user can set A0.ENDPM to turn on the DPM function. Enable the charger VIN DPM function. But if VIN charger type is detected as SDP (CHG_TYP [2:0] = 000), the DPM function always is enabled. ENDPM 0 : VIN DPM function disabled. 1 : VIN DPM function enabled. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 43 RT5072 APPM Mode Once the sum of the charging current and system load current is higher than the maximum input current limit, the SYS pin voltage will be reduced. When the SYS pin voltage is reduced to VAPPM, the RT5072 will automatically operate in APPM mode. In this mode, the charging current is reduced while the SYS current is increased to maintain system output. In APPM mode, the battery termination function is disabled. APPM Profile 1.5A Mode : 5V VIN VSYS 5V VAPPM 4.15V 4.2V VBAT 3A 2A 1A IBAT ISYS 0 IVIN -1A -2A -3A T1 T2 T3 T5 T4 T6 T7 ISYS V SYS IVIN IBAT T1, T7 0 SYS Regulation Voltage CHG_MAX CHG_MAX T2, T6 < IVIN_OC CHG_MAX SYS Regulation Voltage ISYS + CHG_MAX CHG_MAX VIN_OC VIN_OC ISYS VIN_OC ISYS IVIN_OC T3, T5 > IVIN_OC CHG_MAX < IVIN_OC Auto Charge Voltage Threshold T4 V BAT IBAT x RDS(ON) > IVIN_OC 500mA Mode : VUSB 5V VSYS 5V VAPPM 4.15V VBAT 4.2V 0.75A 0.5A IBAT 0.25A ISYS 0 IUSB -0.25A -0.5A -0.75A T1 T2 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 44 T3 T4 T5 T6 T7 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 ISYS VSYS IUSB IBAT T1, T7 0 SYS Regulation Voltage CHG_MAX CHG_MAX T2, T6 < IVIN_OC (USB) CHG_MAX SYS Regulation Voltage ISYS + CHG_MAX CHG_MAX Auto Charge Voltage Threshold IVIN_OC (USB) IVIN_OC (USB) ISYS VBAT IBAT x RDS(ON) IVIN_OC (USB) ISYS IVIN_OC (USB) T3, T5 T4 > IVIN_OC (USB) CHG_MAX < IVIN_OC (USB) > IVIN_OC (USB) Battery Supplement Mode Short Circuit Protect In APPM mode, the SYS voltage will continue to drop if the charge current is zero and the system load increases beyond the input current limit. When the SYS voltage decreases below the battery voltage, the battery will kick in to supplement the system load until the SYS voltage rises above the battery voltage. While in supplement mode, there is no battery supplement current regulation. However, a built-in short-circuit protection feature is available to prevent any abnormal current situation. While the battery is supplementing the load, if the difference between the battery and SYS voltage exceeds the short-circuit threshold voltage, SYS will be disabled. After a shortcircuit recovery time, tSHORT_R, the counter will be restarted. In supplement mode, the battery termination function is disabled. Note that the battery supply mode exiting condition is VBAT − VSYS < 0V. Thermal Regulation and Thermal Shutdown The charger provides a thermal regulation loop function to monitor the device temperature. If the die temperature rises above the regulation temperature, TREG, the charge current will automatically be reduced to lower the die temperature. However, in certain circumstances (such as high VIN, heavy system load, etc) even with the thermal loop in place, the die temperature may still continue to increase. In this case, if the temperature rises above the thermal shutdown threshold, TSD, the internal switch between VIN and SYS will be turned off. The switch between the battery and SYS will remain on however, to allow continuous battery power to the load. Once the die temperature decreases by ΔTSD, the internal switch between VIN and SYS will be turned on again and the device returns to normal thermal regulation. The internal thermal feedback circuitry regulates the die temperature to optimize the charge rate for all ambient temperatures. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 45 RT5072 I2C Interface RT5072 I2C slave address = 0010010 (7 bits). I2C interface supports fast mode (bit rate up to 400kb/s). The write or read bit stream (N 1) is shown below : Read N bytes from RT5072 Slave Address Register Address S 0 Slave Address A Sr A R/W 1 A Data for Address = m Data 2 LSB MSB Data N LSB A A Register Address S 0 MSB A Data 1 LSB A Assume Address = m R/W P Data for Address = m + N - 1 Data for Address = m + 1 Write N bytes to RT5072 Slave Address LSB A Assume Address = m MSB Data 1 MSB MSB Data 2 LSB A A Data for Address = m MSB Data for Address = m + 1 Data N LSB A P Data for Address = m + N - 1 Driven by Master, Driven by Slave (RT5072), P Stop, S Start, Sr Repeat Start I2C Waveform Information SDA tLOW tF tSU,DAT tR tF tHD,STA tSP tR tBUF SCL tHD,STA S tHD,DAT tHIGH Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 46 tSU,STA tSU,STO Sr P S is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 When the RT5072 and other I2C devices with 10-bit slave addressing (type I) or two-byte register addressing (type II) coexist in one I2C bus, the RT5072 needs one dummy I2C write frame to reset the RT5072 internal I2C operation state. The below shows a dummy write frame example, that is to write the RT5072 register A10 [7:0] = 00000000. Master should ignore the write operation (This operation is invalid). After the dummy frame, the master can read/write formal I2C frame for the RT5072 to get right operation. Write RT5072 register A10[7:0] = 00000000 data. Read 2 bytes Type I/Type II data. S A P S A P A P S S A P Write RT5072 register A10[7:0] = 00000000 data. A P Read RT5072 data. A P S A P S Write RT5072 register A10[7:0] = 00000000 data. Write 2 bytes Type I/Type II data. S A P Write RT5072 data. A P Write 2 bytes Type I/Type II data. S S Write RT5072 register A10[7:0] = 00000000 data. Read 2 bytes Type I/Type II data. S Read RT5072 data. A P S Write RT5072 data. A P S A P Normal I2C read/write frame Dummy I2C write frame. Type I : 10-bit slave address data format In 10-bit addressing, the slave address is sent in the first two bytes. The first byte begins with the special reserved address of 11110XX which indicates that 10-bit addressing is being used. S 1 1 1 Bit 9 Bit 8 Bit 7 MSB 1 0 x x R/W ACK x x 10-Bit Address x x x x x x x x x Bit 0 LSB x x ACK x x x x x Bit 9 MSB Bit 0 LSB Type II : 2-byte register address data format The register address is combined with 2-byte as below. 2-Byte Register Address Slave Address S Register Address 0 A A Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 Slave Address A Sr MSB Data 1 LSB 1 A A is a registered trademark of Richtek Technology Corporation. www.richtek.com 47 RT5072 I2C Register File Bit7 (MSB) Bit6 Bit5 Meaning RST_P RST_C OVP7 Default 1 0 0 X Read/Write R/W R/W R/W -- Address Register Address Name A0 0x00 Bit4 Bit2 Bit1 Bit0 (LSB) TSD MOD7 TSSEL 0 0 0 1 R/W R/W R R/W Bit3 Reserved ENDPM RT5072 would reset PMU-related registers under any one of the below two conditions : 1) VDDI 1.3V 2) (EN pin = low and A0.RST_P = 1) RST_P In the 2nd condition, RT5072 uses the register bit A0.RST_P to decide whether the PMU-related registers are reset or not when EN pin goes low. 0 : Don’t reset register (0x3 to 0x6) 1 : Reset register (0x3 to 0x6). RST_C RT5072 would reset Charge-related register under any one of the below three conditions : 1) VIN 4V 2) VDDI 1.3V 3) (BAT 3.1V) and (A0.RST_C = 1) In the 3rd condition, RT5072 uses the register bit A0.RST_C to decide whether the Charge-related registers are reset or not when BAT 3.1V. 0 : Don’t reset register (0x7 to 0x9). 1 : Reset register (0x7 to 0x9) OVP7 CH7 allow user to select the OVP level by I2C interface 0 : 16V OVP 1 : 25V OVP Enable the charger VIN DPM function. But if VIN charger type is detected as SDP (CHG_TYP [2:0] = 000), the DPM function always is enabled. ENDPM 0 : VIN DPM function disabled 1 : VIN DPM function enabled. Report whether thermal shutdown of PMU ever occurs. Reset it by writing 0 into the bit or (VDDI < 1.3V). TSD 0 : Thermal Shutdown has not occurred. 1 : Thermal Shutdown event ever occurs. Report the result of CH7 mode detection. MOD7 0 : Current Source. 1 : Boost. TS/VP ratio setting for battery temperature. TSSEL 0 : TS/VP = 60% (0°C), 28% (60°C) 1 : TS/VP = 74% (0°C), 28% (60°C) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 48 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Address Name A1 Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Meaning ERR1 ERR2 ERR3 ERR4 ERR5 ERR6 ERR7 ERR8 Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Register Address 0x01 Report whether the protection event of CH1 to CH8 ever occurs respectively. Reset it by writing 0 into the bit or (VRTC < 1.6V). ERR1 to ERR8 0 : No protection event occurs. 1 : Protection event ever occurs. Address Name A2 Bit7 (MSB) Bit6 Bit5 Meaning EN5 EN6 EN8 Default 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Register Address 0x02 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) EN7_DIM7 [4:0] Enable/disable CH5 EN5 0 : Disable 1 : Enable Enable/disable CH6 EN6 0 : Disable 1 : Enable Enable/disable CH8 EN8 0 : Disable 1 : Enable Enable CH7 and define FB7 regulation voltage EN7_DIM7 [4:0] 00000 : CH7 turn off 00001 to11111 : CH7 turn on and dimming ratio : VFB7 = EN7_DIM7 [4 : 0] / 31 x 0.25V Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 49 RT5072 Address Name Register Address Meaning A3 0x03 Default Read/Write PSM1 to PSM4 Bit7 (MSB) Bit6 Bit5 Bit4 PSM1 PSM2 PSM3 PSM4 Bit3 Bit2 Bit1 Bit0 (LSB) VOUT8 [3:0] 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W Define the CH1/2/3/4 CCM or PWM/PSM switching operation. 0 : Force PWM 1 : Automatic PWM/PSM switch operation 0 R/W 0 R/W CH8 regulation voltage can be selected by I2C interface. The default voltage is 2.8V. Code Voltage Code Voltage Code Voltage Code Voltage VOUT8 [3:0] Address Name Register Address 0000 0100 1000 1100 Switch 1.4V 1.8V 2.8V 0001 0101 1001 1101 1.1V 1.5V 2V 3.1V 0010 0110 1010 1110 1.2V 1.6V 2.2V 3.2V 0011 0111 1011 1111 1.3V 1.7V 2.5V 3.3V Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit0 (LSB) Meaning A4 0x04 VOUT1 [3:0] EN1 FB2 [2:0] Default 1 0 1 0 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 2 VOUT1 [3:0] EN1 CH1 regulation voltage can be selected by I C interface. The default voltage is 5V. Code Voltage Code Voltage Code Voltage Code Voltage 0000 3.6V 0001 3.7V 0010 3.8V 0011 3.9V 0100 4V 0101 4.5V 0110 4.6V 0111 4.7V 1000 4.8V 1001 4.9V 1010 5V 1011 5.1V 1100 5.2V 1101 5.3V 1110 5.4V 1111 5.5V Enable/Disable CH1 when sequence ID is SEO#0. In SEO#0, CH1 is not the power on/off sequence. In other sequence. CH1 is in sequence control and on/off by the pin EN, not by the register bit EN1. 0 : Disable 1 : Enable 2 FB2 [2:0] FB2 regulation voltage can be selected by I C interface. The default voltage is 0.8V. Code VREF If Target = 1.8V If Target = 1V If Target = 3.3V 000 0.72V 1.62V 0.9V 2.97V 001 0.74V 1.665V 0.925V 3.0525V 010 0.76V 1.71V 0.95V 3.135V 011 0.78V 1.755V 0.975V 3.2175V 100 0.8V 1.8V 1V 3.3V 101 110 111 0.82V 0.84V 0.86V Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 50 1.845V 1.89V 1.935V 1.025V 1.05V 1.075V 3.3825V 3.465V 3.5475V is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Address Name A5 Register Address Bit7 (MSB) Bit6 Bit5 Bit4 Bit2 FLST2 Bit0 (LSB) Bit1 Meaning FLST Default 1 1 0 0 1 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 0x05 FB3 [2:0] Bit3 FB4 [2:0] Used to control the CHG pin status when the register bit A9. CHGSTEN = 0. FLST 1 : CHG = High impedance. 0 : CHG = Low. 2 FB3 regulation voltage can be selected by I C interface. The default voltage is 0.8V. Code VREF If Target = 1.8V If Target = 1V If Target = 3.3V FB3 [2:0] 000 0.72V 1.62V 0.9V 2.97V 001 0.74V 1.665V 0.925V 3.0525V 010 0.76V 1.71V 0.95V 3.135V 011 0.78V 1.755V 0.975V 3.2175V 100 0.8V 1.8V 1V 3.3V 101 0.82V 1.845V 1.025V 3.3825V 110 0.84V 1.89V 1.05V 3.465V 111 0.86V 1.935V 1.075V 3.5475V Used to control the CHG2 pin status when the register bit A8. CHG2STEN = 0. FLST2 1 : CHG2 = High impedance. 0 : CHG2 = Low. 2 FB4 regulation voltage can be selected by I C interface. The default voltage is 0.8V. Code VREF If Target = 1.8V If Target = 1V If Target = 3.3V FB4 [2:0] 000 0.72V 1.62V 0.9V 2.97V 001 0.74V 1.665V 0.925V 3.0525V 010 0.76V 1.71V 0.95V 3.135V 011 0.78V 1.755V 0.975V 3.2175V 100 0.8V 1.8V 1V 3.3V 101 0.82V 1.845V 1.025V 3.3825V 110 0.84V 1.89V 1.05V 3.465V 111 0.86V 1.935V 1.075V 3.5475V Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 51 RT5072 Address Name Register Address Bit7 (MSB) Meaning A6 0x06 Bit6 Bit5 Bit4 Bit3 VOUT5 [3:0] Bit2 Bit1 Bit0 (LSB) VOUT6 [3:0] Default 1 0 0 0 0 0 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W 2 CH5 regulation voltage can be selected by I C interface. The default voltage is 1.8V. Code Voltage Code Voltage Code Voltage Code Voltage VOUT5 [3:0] 0000 REF 0001 1.1V 0010 1.2V 0011 1.3V 0100 1.4V 0101 1.5V 0110 1.6V 0111 1.7V 1000 1.8V 1001 2V 1010 2.2V 1011 2.3V 1100 2.5V 1101 2.6V 1110 2.7V 1111 2.8V Note : VOUT5 [3:0] = 0000 (REF) means using external feedback network and FB5 regulation target is 0.8V 1.5% 2 CH6 regulation voltage can be selected by I C interface. The default voltage is 1.3V. Code Voltage Code Voltage Code Voltage Code Voltage VOUT6 [3:0] 0000 Switch 0001 1.1V 0010 1.2V 0011 1.3V 0100 1.4V 0101 1.5V 0110 1.6V 0111 1.7V 1000 1.8V 1001 2V 1010 2.2V 1011 2.5V 1100 2.8V 1101 3.1V 1110 3.2V 1111 3.3V Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 52 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Address Register Address Name Bit7 (MSB) Meaning A7 0x07 Bit6 Bit5 Bit4 TIMER [3:0] Bit3 Bit2 Bit1 Bit0 (LSB) ENCH USUS ISETU ISETL Default 0 1 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W TIMER [3:0] Define fast charger safe charging time. Fast charging timeout time = (TIMER [3:0] + 1) hours. The default voltage is 5 hours. Note : pre-charge timeout time = fast charge time/8. Enable charger ENCH 0 : Enable charger 1 : Disable charger VIN Suspend control USUS 0 : No suspend 1 : Suspend VIN Current limit setting : ISETU and ISETL ISETL ISETU VIN Input Current Limit 0 0 85mA (default) 0 1 475mA 1 0 1A 1 1 1.5A Note: When Charger Type Detection finds the charger is Dedicated Charging Port (Sony or Apple Charger), ISETU/ISETL would set to be 475mA automatically. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 53 RT5072 Address Name Register Address Meaning A8 0x08 Bit7 (MSB) Bit6 TSHT[1:0] Bit5 Bit4 Bit3 Bit2 Mask_DPM CHG2STEN Bit1 Bit0 (LSB) ISETA [3:0] Default 0 0 0 1 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Set TS/VP threshold to monitor battery temperature for HOT boundary. TSHT [1:0] Code TS/VP ratio 00 Equivalent Battery Temperature 10k NTC 100k NTC 28% 60°C 60°C 01 28.5% 58°C 59°C 10 29% 56°C 57°C 11 29.5% 54°C 56°C Mask DPM function Mask_DPM 0 : When DPM event change, INT would be asserted. 1 : When DPM event change, INT would not be asserted. Used to control CHG2 pin status. 0 : See FLSH2 set. 1 : Base on charging status. CHG2STEN ISETA [3:0] Charging Status CHG2STEN = 1 (A8.bit4 = 1) No Charging/ Charging Finish High impedance (No flashing) Pre-Charge/ Fast Charge Low Abnormal (Fault timer timeout, in thermal regulation, battery too cold or too hot 4Hz (0.25s) FLST2 = 1 (A5.bit3 = 1) FLST2 = 0 (A5.bit3 = 0) High Impedance Low RT5072 allows user to set the battery charge current level and the list as below. The default value is 0.5A. BAT BAT BAT BAT Code Charge Code Charge Code Charge Code Charge Current Current Current Current 0000 0.1A 0001 0.2A 0010 0.3A 0011 0.4A 0100 0.5A 0101 0.6A 0110 0.7A 0111 0.8A 1000 0.9A 1001 1A 1010 1.1A 1011 1.2A 1100 1.2A 1101 1.2A 1110 1.2A 1111 1.2A Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 54 CHG2STEN = 0 (A8.bit4 = 0) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Address Name A9 Bit7 (MSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) Meaning JEITA VSETH VSETC ISETH ISETC CHGSTEN INT DPM Default 0 0 0 0 0 1 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R Register Address 0x09 BAT charge current and regulation voltage control scheme. JEITA, VSETH, VSETC, ISETH, ISETC JEITA = 0, it means the charger operation is automatic (JEITA rule). JEITA = 1, User can set the VSETH/VSETC to decide the BAT regulate voltage and set ISETH/ISETC to decide the BAT charge current level. The control scheme is listed as below. Used to control CHG pin status. 0 : See FLSH set. 1 : Base on charging status. CHGSTEN INT Charging Status CHGSTEN = 1 (A9.bit2 = 1) No Charging/ Charging Finish High impedance (No flashing) Pre-Charge/ Fast Charge 0.5Hz (2s) Abnormal (Fault timer timeout, in thermal regulation, battery too cold or too hot 4Hz (0.25s) CHGSTEN = 0 (A9.bit2 = 0) FLST = 1 (A5.bit7 = 1) FLST = 0 (A5.bit7 = 0) High Impedance Low Control the output of INT open drain port. The bit value is inverted of INT output. When interrupt events happen, INT port goes low and this bit A9. INT would be triggered to 1. Micro-processor must write this bit to be 0 for making INT go high. 0 : INT = High 1 : INT = Low The DPM bit is the charger VIN DPM status bit. It means the charger DPM (VIN falls and regulates at 4.35V) is activated or not. 0 : VIN DPM not activated. DPM 1 : VIN DPM activated (working). Note : when PMU turns on, it would check the bit DPM and compare to the value 0. If it is different, INT would be asserted. After PMU is on, once DPM bit toggles, INT also asserts again. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 55 RT5072 Address Register Address Name Bit7 (MSB) Meaning A10 0x0A Bit6 Bit5 TS_METER [2:0] Bit4 Bit3 Bit2 Bit1 Bit0 (LSB) NoBAT EOC PGOOD THR SAFE Default 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Reports the battery temperature and VP status by detecting the TS pin voltage. TS Meter [2:0] TS_METER [2:0] 60°C 0°C 10°C 45°C TS Meter TS Meter TS Meter TS Meter TS Meter [2:0] = 110 [2:0] = 100 [2:0] = 000 [2:0] = 001 [2:0] = 011 VP < 0.8V (VP UVLO) TS Meter [2:0] = 010 TS Note : when PMU turns on, it would check TS_Meter [2:0] and compare to the value 000. If it is different, INT would be asserted. After PMU is on, once any bits of TS_Meter [2:0] toggles, INT also asserts again. Means the battery installed or not. 0 : BAT Installed NoBAT 1 : No Battery Installed (TS > 90% of VP) Note : when PMU turns on, it would check the bit NoBAT and compare to the value 0. If it is different, INT would be asserted. After PMU is on, once NoBAT bit toggles, INT also asserts again. End of charge (EOC) bit show the charge status. If EOC = 1 means the charger is in EOC status. 0 : During Charging EOC 1 : Charging Done or Recharging after Termination Note: when PMU turns on, it would check the bit EOC and compare to the value 0. If it is different, INT would be asserted. After PMU is on, once EOC bit toggles, INT also asserts again. PGOOD bit means the VIN power status. PGOOD Input Status PGOOD Bit Status VIN < VUVLO 0 VUVLO < VIN < VBAT + 0 VOS_L VBAT + VOS_H < VIN < 1 VOVP VIN > VOVP 0 Note : when PMU turns on, it would check the bit PGOOD and compare to the value 0. If it is different, INT would be asserted. After PMU is on, once PGOOD bit toggles, INT also asserts again. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 56 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 THR bit can be let user to monitor the thermal regulation function is working or not. 0 : thermal Regulation is not working 1 : thermal Regulation is working Note : when PMU turn on, it would check the bit THR and compare to the value 0. If it is different, INT would be asserted. After PMU is on, once THR bit toggles, INT also asserts again. THR Charger safety timer status. SAFE 0 : charger in charging or suspended by thermal loop 1 : safety timer expired Note : when PMU turn on, it would check the bit SAFE and compare to the value 0. If it is different, INT would be asserted. After PMU is on, once SAFE bit toggles, INT also asserts again. Address Register Address Names Meaning A11 0x0B Bit7 (MSB) Bit6 Bit5 CHG_TYP [2:0] Bit4 Bit3 Bit2 Bit0 (LSB) Bit1 Reserved Reserved CHG_2DET CHG_1DET CHGRUN Default 0 0 0 x x 1 1 0 Read/Write R R R -- -- R/W R/W R The CHG_TYP [2:0] is used to recode the charger type. CHG_TYP [2:0] Code Charger Type Code Charger Type 000 Standard USB CHARGER (SDP) 100 APPLE CHARGER (1A) 001 Sony CHARGER -1 101 Nikon CHARGER 010 Sony CHARGER -2 110 Charging Downstream Port (CDP) (High current Host/Hub) APPLE CHARGER 111 DEDICATED CHARGER (DCP) (0.5A) The CHG_2DET bit is used to enable the secondary charger detection (to distinguish CDP and DCP). Default value is 0. Set this bit value to 1 in order to enable charger detection. 011 CHG_2DET 0 : Secondary CHARGER DETECTION DISABLED 1 : Secondary CHARGER DETECTION ENABLE. CHG_1DET The CHG_1DET bit is used to enable the primary charger detection. Default value is 1 (auto-detect charger type when VIN plug in). Toggle this bit value (set to 0 and then set 1) to re-enable charger detection. 0 : Primary CHARGER DETECTION DISABLED. 1 : Primary CHARGER DETECTION ENABLE. The CHGRUN bit is the charger detector status bit. It means the charger detection is running or not. 0 : CHARGER DETECTION NOT RUNING. CHGRUN 1 : CHARGER DETECTION RUNNING. Note : when PMU turn on, it would check the bit CHGRUN and compare to the value 1. If it is different, INT would be asserted. After PMU is on, once CHGRUN bit change from 1 to 0, INT also asserts again. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 57 RT5072 Address Name Register Address Meaning A0 A1 A2 A3 A4 Default 0x00 Read/Write Reset Condition Meaning Default 0x01 Read/Write Reset Condition Meaning Default 0x02 Read/Write Reset Condition Meaning Default 0x03 Read/Write Reset Condition Meaning Default 0x04 Read/Write Reset Condition Meaning Default A5 A6 A7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RST_P RST_C OVP7 Reserved ENDPM TSD MOD7 TSSEL 1 0 0 x 0 0 0 1 R/W R/W R/W -- R/W R/W R R/W A A A G A A H A ERR1 ERR2 ERR3 ERR4 ERR5 ERR6 ERR7 ERR8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W A A A A A A A A EN5 EN6 EN8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W B B B B B B B B PSM1 PSM2 PSM3 PSM4 1 1 1 1 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W C C C C C C C C EN7_DIM7 [4:0] VOUT1 [3:0] VOUT8 [3:0] EN1 FB2 [2:0] 1 0 1 0 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W C C C C B C C C FLST FB3[2:0] FLST2 FB4[2:0] 1 1 0 0 1 1 0 0 0x05 Read/Write Reset Condition Meaning R/W R/W R/W R/W R/W R/W R/W R/W C C C C C C C C Default 0x06 Read/Write Reset Condition Meaning 1 0 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W R/W C C C C C C C C ENCH USUS ISETU ISETL Default 0x07 Read/Write Reset Condition VOUT5 [3:0] TIMER [3:0] 0 1 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D D D D D D D D Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 58 VOUT6 [3:0] is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Address Name Register Address Meaning A8 A9 A10 Default 0x08 Read/Write Reset Condition Meaning Default 0x09 Read/Write Reset Condition Meaning Default 0x0A Read/Write Reset Condition Bit7 TSHT [1:0] 0x0B Bit5 Bit4 Bit3 Bit2 Mask_DPM CHG2STEN Bit1 Bit0 ISETA [3:0] 0 0 0 1 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W D D D D D D D D JEITA VSETH VSETC ISETH INT DPM 0 0 0 0 0 1 0 0 R/W R/W R/W R/W R/W R/W R/W R D D D D D D E D NoBAT EOC PGOOD THR SAFE TS_METER [2:0] ISETC CHGSTEN 0 0 0 0 0 0 0 0 R R R R R R R R I I I I J J J J Default 0 0 0 x x CHG_ 2DET 0 Read/Write Reset Condition R R R -- -- R/W R/W R K K K G G F F L Meaning A11 Bit6 CHG_TYP [2:0] Reserved Reserved CHG_ CHGRUN 1DET 1 0 I2C register reset condition : A. In addition to A0.bit 1 and A0.bit4, the bits of A0 and A1 (register 0x0, 0x1) reset only when (VRTC < 1.6V). B. The bits of A2 (register 0x2) and A4.bit3 reset when (EN pin = low) or (VDDI < 2.4V) or (BAT < 1.3V) or (Temperature > 125°C) C. In addition to A4.bit3, PMU settings (A3 to A6, register 0x3 to 0x6) reset when (EN pin = low and A0.RST_P = 1) or (VDDI < 1.3V) VDDI < 1.3V EN pin A0.RST_P bit TRUE x Low High Low High x (don’t care) 1 1 0 0 False (VDDI > 1.3V) ==> Reset PMU Setting Reset Reset Not reset Not reset Not reset D. In addition to A9.bit 1, charger settings (A7 to A9, registers (0x7 to 0x9) reset when (VIN < 4V) or (VDDI < 1.3V) or ((BAT < 3.1V) and (A0.RST_C = 1)) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 59 RT5072 VDDI < 1.3V VIN > 4V A0.RST_C bit (BAT < 3.1V) true (VDDI < 1.3V) false (VDDI > 1.3V) false (VDDI > 1.3V) false (VDDI > 1.3V) false (VDDI > 1.3V) false (VDDI > 1.3V) x False (VIN < 4V) True (VIN > 4V) True (VIN > 4V) True (VIN > 4V) True (VIN > 4V) x x 1 1 0 0 x x TRUE FALSE TRUE FALSE ==> Reset Charger Setting Reset Reset Reset Not reset Not reset Not reset E. (EN pin = low) or (VDDI < 1.3V) F. Charger type detection A11 (registers 0xB) reset when (VIN < 4V) or (VDDI < 1.3V) G. Always reset. H. A0.bit1 will be reset when (EN pin = low) or (VDDI < 2.4V) or (BAT < 1.3V) or (PMU protection occur) or (Temperature < 125°C). I. A0.bit1 will be reset when (EN pin = low) or (VDDI < 2.4V) or (BAT < 1.3V) or (In addition to CH7 OVP, PMU protection occur) or (Temperature < 125°C). J. Reference page-54 A10 explanation. K. A11.bit7 to bit5 will be rewritten after charging type detects finish. L. A11.bit0 keeps high during charging type detecting. CHG Signal Status Charging Status CHG CHG2 CHGSTEN = 0 CHG2STEN = 0 CHGSTEN = 1 CHG2STEN = 1 A5. bit7 = 1 A5. bit7 = 0 A5. bit3 = 1 A5. bit3 = 0 No High impedance Charging/Charging Finish (No flashing) Pre-Charge/Fast Charge Abnormal (Fault timer timeout, in thermal regulation, battery too cold or too hot) 0.5Hz (2s) High impedance (No flashing) High impedance 4Hz (0.25s) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 60 Low Low High impedance Low 4Hz(0.25s) is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 NTC Thermistor Order Detection PMU enabled (EN = H) or VIN plug-in (Charger start) VP buffer enabled Vref ready VP > 2.97V VP VP_Ready 10µs NTC Detection Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 Latch NTC detection result reset NTC detection result and issue next time to re-detect is a registered trademark of Richtek Technology Corporation. www.richtek.com 61 RT5072 USB Charger Detection Charger Type Detection : Detection Time 600ms Initial state USUS = 0 ENCH = 0 ISETL = 0 ISETU = 0 CHG_1DET = 1 CHG_2DET = 1 No UVLO < VIN < OVP & VIN - VBAT > 50mV & 30msec Deglitch time Yes Data Contact Detect No Data Contact OK No > 512ms Yes Yes Special Charger Yes Write DCD_T = 1 No CHG_TYP [2:0] = 111 D+ = VDP_SRC Dedicated Charger Detected (DCP) Yes No SONY/APPLE CHARGER DETECTION D- > VDAT_REF & D- <VLGC No CHG_TYP [2;0] = 110 High Current Host/Hub Detected (CDP) Yes Yes No NIKON DETECTION D+ < 0.3V Yes No PMU Turn On No Standard USB port Set 100mA mode USUS = 0 ENCH = 0 ISETL = 0 ISETU = 0 Dedicated or High current Host/Hub Set 0.5A mode USUS = 0 ENCH = 0 ISETL = 0 ISETU = 1 Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 62 Yes System is Wake-up then disable Wake-up function and set charging type. Set charger Condition by 2 I C is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 D+/D- impedance of Standard USB Host/Charging Downstream Port. Apple Charger, Sony Charger, and Dedicated Charger : Standard USB host charging downstream port 3.6V Apple Charger 5V 300k D+ 75k D+ 14.25k to 24.8k D- D+ 14.25k to 24.8k D+ Copyright © 2015 Richtek Technology Corporation. All rights reserved. 2M (MIN) Nikon D+ D+ 0.5A D- 5.1k D- 49.9k 1.554k 5V 43.2k (for 1A) 75k (for 0.5A) D- Dedicated Charger 5V 10k 5V 300k Sony Charger-2 5V 5.1k 49.9k 3.6V DS5072-00 March 2015 Sony Charger 5V D10k D2.155k 2M (MIN) is a registered trademark of Richtek Technology Corporation. www.richtek.com 63 RT5072 Thermal Considerations Layout Consideration For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : For the best performance of the RT5072, the following PCB layout guidelines must be strictly followed. Place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. Keep the main power traces as wide and short as possible. The switching node area connected to LX and inductor should be minimized for lower EMI. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-40L 5x5 package, the thermal resistance, θJA, is Place the feedback components as close as possible to the FB pin and keep these components away from the noisy devices. 27.5°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : Connect the GND and Exposed Pad to a strong ground plane for maximum thermal dissipation and noise protection. To make CH1 and whole chip stable, the power path from the PVD1 pin to its output capacitors must be as short (≤ 1mm is better) and wide as possible. To make CH4 and CH5 stable, the power path from the PVD45 pin to its input capacitors must be as short (≤ 1mm is better) and wide as possible. PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. PD(MAX) = (125°C − 25°C) / (27.5°C/W) = 3.63W for WQFN-40L 5x5 package Maximum Power Dissipation (W)1 The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 4.0 Four-Layer PCB 3.2 2.4 1.6 0.8 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 6. Derating Curve of Maximum Power Dissipation Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 64 is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 LX should be connected to Inductor by wide and short trace, and keep sensitive components away from this trace. GND VOUT_CH1 GND Place the feedback components as close as possible to the FB pin and keep away from noisy devices. VSYS Output capacitor must be placed as close as possible to the output pin. VOUT_CH3 C8 L3 C3 R16 R5 C25 C17 C14 C1 C9 C2 VRTC DN DP VIN SYS SYS BAT BAT PVD3 LX3 R6 C27 D7 D6 40 39 38 37 36 35 34 33 32 31 C4 D4 L1 D3 VSYS D2 VOUT_CH7 L7 C21 GND VOUT_CH6 C24 C22 VSYS WAKE PVD1 LX1 CHG2 FB7 PVD7 LX7 CHG VO6 PVD6 1 30 2 29 3 28 4 27 5 26 GND 6 25 7 24 8 23 41 9 22 10 21 11 12 13 14 15 16 17 18 19 20 R1 VP TS FB3 PVD2 LX2A LX2B VO2 FB2 VO8 SCL RNTC R2 C5 VSYS L2 R3 C7 VOUT_CH8 R4 C6 C19 FB4 SEQ LX4 EN PVD45 LX5 INT VO5/FB5 PVD8 SDA C23 R8 C26 L5 R7 L4 C28 C12 C11 C10 VSYS GND VOUT_CH4 C18 GND VOUT_CH5 D5 GND GND GND VOUT_CH2 Connect the Exposed Pad to a ground plane. Input/Output capacitors must be placed as close as possible to the Input/Output pins. Figure 7. PCB Layout Guide Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 65 RT5072 Protection Type SYS Threshold (Typical) Refer to Electrical Spec. PMU Shutdown Delay Time Reset Method No-delay EN1234 pin set to low or SYS > 2.1V 100ms VDDI power reset or EN1234 pin set to low No-delay VDDI power reset or EN1234 pin set to low 100ms VDDI power reset or EN1234 pin set to low No-delay VDDI power reset or EN1234 pin set to low 100ms VDDI power reset or EN1234 pin set to low N-MOSFET off, P-MOSFET off No-delay VDDI power reset or EN1234 pin set to low Protection Methods UVLO SYS < 1.5V PMU Shutdown. OVP VDDM > 6V Automatic reset at VDDM < 5.85V UVLO VDDM < 2.4V PMU Shutdown. Current Limit N-MOSFET peak current > 3A N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. PVD1 OVP PVDD1 > 6V N-MOSFET off, P-MOSFET off. VDDI PVDD1 < (VSYS 0.8V) or N-MOSFET off, PVD1 UVP --1 PVDD1 < 1.28V after P-MOSFET off. CH1 Step-Up soft-start end. After pre-charge (PVD1 PVD1 UVP --2 UVP-2 : FB1 < 0.4V after pre-charge) CH2 Step-Up/Down CH3 Step-Down PVD1 Over Load (OL) Target 0.6V Target Voltage is defined in A4.VOUT1 [3:0] PMU Shutdown when OL occur each cycle until 100ms. 100ms VDDI power reset or EN1234 pin set to low Current limit Both P-MOSFET (PVD2 LX2A) and N-MOSFET (LX2B GND) peak current > 2A N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. 100ms VDDI power reset or EN1234 pin set to low VO2 OVP PVDD1 > 6V N-MOSFET off, P-MOSFET off. No-delay VDDI power reset or EN1234 pin set to low FB2 UVP FB2 < 0.4V after soft-start end. No-delay VDDI power reset or EN1234 pin set to low FB2 Over Load Target 0.1V (Target voltage is the chosen one in A4.FB2 [2:0]) 100ms VDDI power reset or EN1234 pin set to low Current limit P-MOSFET peak current > 1.8A 100ms VDDI power reset or EN1234 pin set to low FB3 UVP FB3 < 0.4V after soft-start end. No-delay VDDI power reset or EN1234 pin set to low FB3 Over Load Target 0.1V (Target voltage is the chosen one in A5.FB3 [2:0]) 100ms VDDI power reset or EN1234 pin set to low Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 66 N-MOSFET off, P-MOSFET off. PMU Shutdown when OL occur each cycle until 100ms. N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. N-MOSFET off, P-MOSFET off. PMU Shutdown when OL occur each cycle until 100ms. is a registered trademark of Richtek Technology Corporation. DS5072-00 March 2015 RT5072 Protection Type Threshold (Typical) Refer to Electrical Spec. VDDI power reset or EN1234 pin set to low No-delay VDDI power reset or EN1234 pin set to low FB4 Over Load Target 0.1V (Target voltage is the chosen one in A5.FB4 [2:0]) PMU Shutdown when OL occur each cycle until 100ms. 100ms VDDI power reset or EN1234 pin set to low Current limit P-MOSFET peak current > 1.5A N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. 100ms VDDI power reset or EN1234 pin set to low No-delay VDDI power reset or EN1234 pin set to low PMU Shutdown when OL occur each cycle until 100ms. 100ms VDDI power reset or EN1234 pin set to low P-MOSFET off. 100ms VDDI power reset or EN1234 pin set to low N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. 100ms VDDI power reset or EN1234 pin set to low No-delay VDDI power reset and A2.EN7_DIM7 [4:0] reset or EN1234 pin set to low 100ms VDDI power reset or EN1234 pin set to low P-MOSFET peak current > 1.8A FB5 < 0.4V after soft-start end Target voltage is the chosen one in CH5 A6.VOUT5 [3:0] = 0000 Step-Down (FB5 = 0.8V) Target voltage is the VO5 Over chosen one in Load A6.VOUT5 [3:0] = 0001 to 0111 Target voltage is the chosen one in A6.VOUT5 [3:0] = 0111 to 1111 Max. output P-MOSFET current > 0.45A (PVD6 = 1.5V, CH6 LDO current (current limit) VO6 = 1.3V) VO5 UVP Current limit (Step-Up mode) CH7 WLED N-MOSFET current > 0.8A PVDD7 > 16V (A0.OVP7 = 0) PVDD7 OVP VIN 100ms FB4 < 0.4V after soft-start end. CH4 Step-Down FB4 UVP Thermal Reset Method N-MOSFET off, P-MOSFET off. Automatic reset at next clock cycle. N-MOSFET off, P-MOSFET off. Current limit CH8 LDO Protection Methods PMU Shutdown Delay Time Max. output current (current limit) Thermal shutdown VIN UVLO VIN OVP PVDD7 > 25V (A0.OVP7 = 1) N-MOSFET off, P-MOSFET off. Shutdown CH7 by self P-MOSFET current > 0.45A P-MOSFET off. (PVD6 = 3V, VO6 = 2.5V) All channels stop Temperature > 155C switching VIN < 3.3V No-charge VIN > 6.5V No-charge Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5072-00 March 2015 N-MOSFET off, P-MOSFET off. No-delay No-delay No-delay Temperature < (155 20)C No latch No latch is a registered trademark of Richtek Technology Corporation. www.richtek.com 67 RT5072 Outline Dimension D SEE DETAIL A D2 L 1 E2 E e b 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 D 4.950 5.050 0.195 0.199 D2 3.250 3.500 0.128 0.138 E 4.950 5.050 0.195 0.199 E2 3.250 3.500 0.128 0.138 e L 0.400 0.350 0.016 0.450 0.014 0.018 W-Type 40L QFN 5x5 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 68 DS5072-00 March 2015