RT9705B 80mΩ Ω, 1A Power Multiplexer General Description Features The RT9705B is a dual input single output power multiplexer specifically designed to provide seamless voltage transition between two independent power suppliers. Equipped with two low RDS(ON) N-Channel z MOSFETs driven by internal charge pump circuitry, the RT9705B is able to deliver 1A output current with only 80mV voltage drop. Manual or auto switching mode is easily selected by two digital inputs D1 and D0. When both D0 and D1 are selected high, the RT9705B enters shutdown mode and consumes minimum power making it ideal suitable for battery powered equipments. A STAT pin with open drain output is provided to indicate the switch status. A user-programmable up to 1.25A current limit function is available for maximum safety in various applications. z The RT9705B provides comprehensive protection functions, including adjustable current limit, over temperature protection, soft start function for minimum inrush current, cross-conduction protection, and reverse conduction protection. These features greatly simplify power multiplexer design. The RT9705B is available in TSSOP-8 package requiring minimum board area and smallest components. z z z z z z z z z Adjustable Current Limiting up to 1.25A Built-In (Typically 80mΩ Ω) N-Channel MOSFET Reverse Current Flow Blocking (no body diode) i.e. Output Can Be Forced Higher than Input (Off-State) Low Supply Current : `55μ μA Typical at Switch on State `Less than 0.5μ μA Typical at Switch Off State Guaranteed 1A Continuous Load Current Wide Input Voltage Ranges : 2.8V to 5.5V Open-Drain STAT Output Hot Plug-In Application (Soft-Start) Thermal Shutdown Protection Smallest TSSOP-8 Package Minimizes Board Space RoHS Compliant and 100% Lead (Pb)-Free Applications z z z z z z z LCD Monitor, LCD-TV Information Appliance and Set-Top Box Battery-Powered Equipment ACPI Power Distribution Motherboard & Notebook PCs Mini PCI & PCI-Express Cards PCMCIA & New Cards Ordering Information Marking Information RT9705B Package Type C : TSSOP-8 Lead Plating System P : Pb Free G : Green (Halogen Free and Pb Free) Note : Richtek products are : ` For marking information, contact our sales representative directly or through a Richtek distributor located in your area. Pin Configurations RoHS compliant and compatible with the current require- (TOP VIEW) ments of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. STAT D0 D1 ILIM 8 7 6 5 2 3 4 VIN1 VOUT VIN2 GND TSSOP-8 DS9705B-03 April 2011 www.richtek.com 1 RT9705B Typical Application Circuit VIN1 Switch Status 1 D0 D1 RILIM 2 VIN1 8 STAT 0.1uF 7 VOUT RT9705B 3 D1 VIN2 6 4 R1 D0 ILIM GND VOUT COUT 5 RLOAD VIN2 0.1uF Functional Pin Description Pin Name Pin Function VIN1 Power Input1 Voltage VIN2 Power Input2 Voltage VOUT Output Voltage GND Ground STAT STAT is an open-drain output that is Hi-Z if the VIN2 switch is ON. D0, D1 The truth table shown below illustrates the functionality of D0 and D1. ILIM A resistor RILIM from ILIM to GND sets the current limit ILIM to (500/RILIM). Table 1. Truth Table D1 D0 VIN2>VIN1 STAT VOUT 0 0 X Hi-Z VIN2 0 1 No 0 VIN1 0 1 Yes Hi-Z VIN2 1 0 X 0 VIN1 1 1 X 0 0 Notes for Table 1. 1. X : Don’ t care 2. Hi-Z: High impedance node 3. D0 and D1 cannot be floating which will lead to an unknown state. 4. An internal MOSFET with 2kΩ RDS(ON) turns on and softly discharges the output voltage when D0 = D1 = 1. www.richtek.com 2 DS9705B-03 April 2011 RT9705B Test Circuits 5V NC 1 STAT 2 0.1uF VIN1 8 7 VOUT RT9705B 3 D1 VIN2 6 f = 28Hz 78% Duty Cycle 400 D0 4 ILIM 1uF 5 GND 50 3.3V 0.1uF Test Circuit 1 5V NC 1 STAT 2 VIN1 8 0.1uF 7 VOUT RT9705B 3 D1 VIN2 6 f = 36Hz 78% Duty Cycle 400 D0 4 ILIM 1uF 5 GND 50 3.3V 0.1uF Test Circuit 2 5V NC 1 2 STAT VIN1 8 0.1uF 7 VOUT RT9705B 3 D1 VIN2 6 f = 580Hz 80% Duty Cycle 400 4 D0 ILIM COUT 5 GND 50 0.1uF Test Circuit 3 5V 1k 1 f = 220Hz 20% Duty Cycle 2 STAT VIN1 8 7 VOUT RT9705B 3 D1 VIN2 6 400 4 0.1uF D0 ILIM GND 5 VOUT 10uF 50 3.3V 0.1uF Test Circuit 4 DS9705B-03 April 2011 www.richtek.com 3 RT9705B Function Block Diagram VIN2 VOUT Q2 VIN1 Vf = 0 Vf = 0 Current Sence Q1 Internal VDD + - VTH - + ILIM + Charge Pump 0.5V + VDD UVLO Charge Pump + 0.1V EN2 EN1 Q2 is OFF Q1 is OFF VOUT>VIN + - VIN2 UVLO - Control Logic VIN1 UVLO + VIN1 - VIN2 STAT Thermal Sense Q2 is ON D0 D1 GND Timing Diagram 90% V OUT 90% 10% 0V D0-D1 tPLH1 Q1, Q2 Off 10% tr tPHL1 Q1, Q2 Enabled tf Q1, Q2 Off (a) 4.8V VOUT 5V 3.4V 3.3V D0-D1 tt Q1 Enabled Q2 Enabled (b) 5V VOUT 4.65V 3.4V 3.3V D0-D1 Q1Enabled tPHL2 tPLH2 Q2 Enabled Q1 Enabled (c) www.richtek.com 4 DS9705B-03 April 2011 RT9705B Absolute Maximum Ratings z z z z z z z z z (Note 1) Input Voltage, VIN1 & VIN2 ----------------------------------------------------------------------------------------- −0.3V to 6.0V Logic Inputs Voltage, D0 &D1 -------------------------------------------------------------------------------------- −0.3V to 6.0V Output Voltage, VOUT, STAT & ILIM ----------------------------------------------------------------------------- −0.3V to 6.0V Power Dissipation, PD @ TA = 25°C TSSOP-8 ---------------------------------------------------------------------------------------------------------------- 0.43W Package Thermal Resistance (Note 2) TSSOP-8, θJA ---------------------------------------------------------------------------------------------------------- 230°C/W Junction Temperature ------------------------------------------------------------------------------------------------- 125°C Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions z z z z (Note 4) Input Voltage VIN1 ( if VIN2 ≥ 2.8V) -------------------------------------------------------------------------------------------------- 2.3V to 5.5V VIN1 ( if VIN2 < 2.8V) -------------------------------------------------------------------------------------------------- 2.8V to 5.5V VIN2 ( if VIN1 ≥ 2.8V) -------------------------------------------------------------------------------------------------- 2.3V to 5.5V VIN2 ( if VIN1 < 2.8V) -------------------------------------------------------------------------------------------------- 2.8V to 5.5V Logic Inputs Voltage (D0 &D1) ------------------------------------------------------------------------------------- 0V to 5.5V Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN1 = VIN2 = 3.6V, CIN = COUT = 1μF, RILIM = 400Ω, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VIN1 = VIN2 = 3.6V, IOUT = 1A -- 80 95 VIN1 = VIN2 = 3.6V, IOUT = 1A −5°C ≤ T A ≤ 85°C (Note 5) -- -- 120 1.5 -- 2.1 V -- 500 -- mV Power Switch Switch On Resistance RDS(ON) mΩ Logic Inputs (D0 and D1) Logic Low to High Threshold Voltage VTH_LH Threshold Hysteresis Input Current at D0 or D1 VTH_HYS IIL D0 or D1 = High, Sink Current -- -- 1 IIH D0 or D1 = Low, Source Current -- -- 1 μA To be continued DS9705B-03 April 2011 www.richtek.com 5 RT9705B Parameter Symbol Test Conditions Min Typ Max Unit -- 55 200 -- 55 200 -- 0.5 3 μA -- 0.1 5 μA -- 0.1 5 μA -- 0.3 5 μA 0.95 0.47 0 1.25 0.71 -- 1.56 0.99 150 1.2 1.28 -- -2.2 -- 1.34 2.4 2.5 100 1.6 -2.8 -- μs 0.1 -- 0.25 V -- 75 -- μs -- 130 -- mV ---- 0.01 -150 1 0.4 -- μA V μs Supply and Leakage Currents Quiescent Current From (VIN1 + VIN2) (Operating) Shut Down Current From (VIN1 + VIN2) (Standby) IS1 IS2 ISHDN Forward Leakage Current From IFLKG_VIN1 VIN1 (Measured from VOUT to GND) Forward Leakage Current From I VIN2 (Measured from VOUT to GND) FLKG_VIN2 Reverse Leakage Current to VINx (Measured from VINx to GND) IRLKG_VINx D1 = High, D0 = Low (VIN1 Active), VIN1 = 3.6V, V IN2= 3.3V, IOUT = 0A D0 = D1 = Low (VIN2 Active), VIN1 = 3.3V, VIN2 = 3.6V, IOUT = 0A D0 = D1 = High (Inactive), VIN1 = V IN2 = 3.6V, IOUT = 0A D0 = D1 = High (inactive), VIN1 = 3.6V, VIN2 Open, V OUT = 0V (Shorted) D0 = D1 = High (inactive), VIN2 = 3.6V, VIN1 Open, V OUT = 0V (Shorted) D0 = D1 = High (inactive), V INX = 0V, VOUT = 3.6V μA Current Limit circuit Current Limit Accuracy Output Current at ILIM ILIM_400 ILIM_700 ILIM RILIM = 400Ω, VIN1 = VIN2 = 3.6V RILIM = 700Ω, VIN1 = VIN2 = 3.6V VILIM = 0V, IOUT = 0A A μA UVLO VIN1 and VIN2 UVLO VUVLO_FAL Falling Edge VUVLO_RSE Rising Edge Internal VDD UVLO (the higher of VUVLO_FAL Falling Edge VIN1 and VIN2) VUVLO_RSE Rising Edge UVLO Deglitch for VIN1 and VIN2 Rising Edge (Note 6) (Note7) VIN2 to VIN1 Comparators Hysteresis of VIN2 to VIN1 comparator Deglitch of VIN2 to VIN1 comparator (both Rising & Falling) Reverse Conduction Blocking (Note 6) ΔVO (I_Block) Minimum Output-toInput Voltage Difference to Block Switching D0 = D1 = High, VINX = 3.3V. Connect VOUT to a 5V supply through a series 100Ω resistor. Let D0 = Low. Slowly decrease the supply voltage until VOUT connects to V IN1. STAT Output Leakage Current Saturation Voltage Deglitch Time (falling edge only) ILEAKAGE VSAT VO(STAT) = 5.5V II(STAT) = 2mA, VIN1 Switch is On (Note 6) V V Thermal Shutdown Thermal Shutdown Protection T SD -- 135 -- °C Thermal Shutdown Hysteresis ΔTSD -- 10 -- °C To be continued www.richtek.com 6 DS9705B-03 April 2011 RT9705B Parameter Symbol Test Conditions Min Typ Max Unit Power Switch Timing (Note 6) Output Rise Time from tr an enable VIN1 = VIN2 = 3.3V, IOUT = 500mA See Timing Diagram (a) 1 1.72 3 ms Output Fall Time from a tf disable VIN1 = VIN2 = 3.3V, IOUT = 500mA See Timing Diagram (a) 0.1 0.26 1.5 ms -- 20 60 Transition Time VIN1 to V IN2 transition, IOUT = 500mA, (Measure VIN1 = 3.3V, V IN2 = 5V transition time as 10 to 90% rise time or from 3.4V to VIN2 to V IN1 transition, 4.8V on V OUT) See Timing VIN1 = 5V, VIN2 = 3.3V Diagram (b) tt μs -- 20 60 Turn-on Propagation Delay from Enable tPLH1 VIN1 = V IN2 = 3.3V, Measure from enable to 10% of V OUT, IOUT = 500mA See Timing Diagram (a) -- 1 -- ms Turn-off Propagation Delay from Disable tPHL1 VIN1 = VIN2 = 3.3V, Measure from disable to 90% of V OUT, IOUT = 500mA See Timing Diagram (a) -- 1 -- ms -- 20 100 μs 2 3.8 10 ms Switch-over Rising Propagation Delay Switch-over Falling Propagation Delay tPLH2 tPHL2 Logic 1 to Logic 0 transition VIN1 = 3.3V, on D1, Measure from D1 to VIN2 = 5V, 10% of VOUT VD0 = 0V, Logic 0 to Logic 1 transition IOUT = 500mA on D1, Measure from D1 to See Timing Diagram (c) 90% of VOUT Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. VOUT Response vs. UVLO Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. VIN1 (1V/Div) Note 2. θ JA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. VOUT (1V/Div) Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Performance at −5°C ≤ TA ≤ 85°C is assured by VIN2 = 2.2V, COUT = 10uF, RL = 180Ω Time (1ms/Div) design. Note 6. Not tested for production. Note 7. The UVLO is without latch. In VIN falling dege, the output voltage will depend on IOUT and COUT. Please see below curve as reference. DS9705B-03 April 2011 www.richtek.com 7 RT9705B Typical Operating Characteristics Quiescent Current vs. Input Voltage Current Limit vs. Junction Temperature 1.8 Current Limit (A) 1.6 60 D0 = 0, D1 = 1 VIN1 = 3.3V RILIM = 400Ω Quiescent Current (uA) 2 1.4 1.2 1 0.8 0.6 0.4 55 D0 = 0, D1 = 1 VIN1 = 2.8V→ 5.5V VIN2 = 0V, IOUT = 0A 50 45 40 35 0.2 30 0 -50 -25 0 25 50 75 100 2.5 125 3 3.5 90 D0 = 0, D1 = 1 VIN = 3.3V 100 85 90 80 RDS(ON) (mΩ) 5.5 6 80 70 60 5.5 6 D0 = 0, D1 = 1 VIN1 = 2.8V→ 5.5V 75 70 65 50 60 -25 0 25 50 125 2.5 3 3.5 4 4.5 5 Input Voltage (V) Output Switchover Response Output Turn-On Response (2V/Div) (2V/Div) (2V/Div) D0 = 0, D1 = 1 ↔ 0 VIN1 = 5V, VIN2 = 3.3V Time (1ms/Div) www.richtek.com 8 100 Temperature (°C) D0 D1 75 Refer to Test Circuits 1 -50 Refer to Test Circuits 2 RDS(ON) (mΩ) 5 RDS(ON) vs. Input Voltage RDS(ON) vs. Temperature VOUT 4.5 Input Voltage (V) Junction Temperature (°C) 110 4 (2V/Div) D1 (2V/Div) D0 (2V/Div) VOUT D0 = 1 ↔ 0, D1 = 1, VIN1 = 5V, VIN2 = 3.3V Time (1ms/Div) DS9705B-03 April 2011 RT9705B Output Switchover Voltage Droop (2V/Div), COUT = 1uF (2V/Div), COUT = open VOUT (2V/Div) VIN1 (2V/Div) VOUT D0 = 0, D1 = 1 ↔0, VIN1 = VIN2 = 5V, RL = 50Ω Refer to Test Circuits 4 D1 Refer to Test Circuits 3 (2V/Div) Auto Switchover Voltage Droop D0 = 1, D1 = 0, VIN1 = 5 ↔ 0V, VIN2 = 3.3V Time (250μs/Div) Time (50μs/Div) Output Switchover Voltage Droop (V)1 Output Switchover Voltage Droop vs. COUT 1.6 VIN1 =VIN2 = 3.3V 1.4 1.2 RL = 10Ω 1 0.8 0.6 RL = 50Ω 0.4 0.2 0 0.1 1 10 100 COUT (uF) DS9705B-03 April 2011 www.richtek.com 9 RT9705B Application Information Current Limiting The RT9705B is dual input single output power multiplexer specifically designed to provide seamless voltage transition between two independent power suppliers. Equipped with two low RDS(ON) N-Channel MOSFETs driven by internal charge pump circuitry, the RT9705B is able to deliver 1A output current with only 80mV voltage drop. The RT9705B provides comprehensive protection functions, including adjustable current limit, over temperature protection, soft start function for minimum inrush current, cross-conduction protection, and reverse conduction protection. These features greatly simplify power multiplexer design. The current limit circuitry prevents damage to the MOSFET switch and external load. A resistor RILIM from ILIM to GND sets the current limit to 500/R ILIM and the adjustable current limiting up to 1.25 A. A setting resistor RILIM equal to zero is not recommended as that disables current limiting. Manual Switching Mode The RT9705B provides two logic input D0 and D1 for switch selection as shown in Table 1. The RT9705B selects the manual-switching mode when the D0 is pulled low. In this mode VOUT connects to VIN1 if D1 pulled high, otherwise VOUT connects to VIN2. Auto Switching Mode RT9705B selects the auto-switching mode when the D0 is pulled high and D1 is pulled low. In this mode VOUT connects to the higher of VIN1 and VIN2. Thermal Considerations Thermal protection limits power dissipation in RT9705B. When the operation junction temperature exceeds 135°C, the OTP circuit starts the thermal shutdown function and turns the pass element off. The pass element turn on again after the junction temperature cools by 10°C. For continuous operation, do not exceed absolute maximum operation junction temperature 125°C. The power dissipation definition in device is : PD = (VIN-VOUT) x IOUT + VIN x IQ The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = ( TJ(MAX) - TA ) / θJA Shutdown Mode When both D0 and D1 are selected high, the RT9705B enters shutdown mode and consumes minimum power. An internal MOSFET with 2kΩ RDS(ON) turns on and softly discharges the output voltage in the shutdown mode. Since no body diode exists between VINX and VOUT, output voltage is allowed to be high than the input voltages in the shutdown mode. Switch Status Indication A STAT pin with open drain output is provided to indicate the switch status. STAT pin outputs high impedance if VIN2 is active, otherwise STAT pin outputs low. www.richtek.com 10 where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of RT9705B, where T J(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance (θJA is layout dependent) for TSSOP-8 package is 230°C/W on standard JEDEC 51-3 thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C -25°C) / 230°C/W = 430 mW (TSSOP-8) DS9705B-03 April 2011 RT9705B Layout Consideration In order to meet the voltage drop, droop, and EMI requirements, careful PCB layout is necessary. The following guidelines must be considered : z z z Keep all main current traces as short and wide as possible. Place a ground plane under all circuitry to lower both resistance and inductance and improve DC and transient performance (Use a separate ground and power plans if possible). Locate the ceramic input capacitors as close as possible to the VIN and GND pins of the device. Figure 1. Top Layer DS9705B-03 April 2011 Figure 2. Bottom Layer www.richtek.com 11 RT9705B Outline Dimension D L E1 E e A2 A A1 b Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 1.000 1.200 0.039 0.047 A1 0.050 0.150 0.002 0.006 A2 0.800 1.050 0.031 0.041 b 0.190 0.300 0.007 0.012 D 2.900 3.100 0.114 0.122 e 0.650 0.026 E 6.300 6.500 0.248 0.256 E1 4.300 4.500 0.169 0.177 L 0.450 0.750 0.018 0.030 8-Lead TSSOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 12 DS9705B-03 April 2011