® DAC650 FPO 70% 12-Bit 500MHz DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS ● 12-BIT RESOLUTION ● 500MHz UPDATE RATE ● GUARANTEED SPURIOUS PERFORMANCE ● LOW GLITCH ● FAST SETTLING ● INTERNAL EDGE-TRIGGERED LATCH ● LASER TRIMMED ACCURACY ● DIRECT DIGITAL SYNTHESIS ● ARBITRARY WAVEFORM GENERATION ● HIGH RESOLUTION GRAPHICS ● COMMUNICATIONS LOCAL OSCILLATORS Spread Spectrum Base Stations Digitally Tuned Receivers ● HIGH-SPEED MODEMS ● INTERNAL REFERENCE ● CLEAN LOW-NOISE OUTPUT CLK CLK Offset Trim Reference Adjust DESCRIPTION The DAC650 combines precision thin film and bipolar technology with high speed gallium arsenide to create a high performance, cost effective solution for modern waveform synthesis systems. Reference Input 12-Bit ECL Lines Edge Triggered Bit Latch The ECL compatibility provides for low digital noise at high update rates. The 50Ω output resistance and low output capacitance simplify transmission line design and filtering at the output. Complementary outputs are offered for increased performance while driving transformers or differential amplifiers. Reference Output +10V Ref The DAC650 is a high performance 12-bit digital to analog converter for high frequency waveform generation. It is complete with an internal low drift reference and edge-triggered data latch. The internal segmentation and latching provide for minimal output glitch energy. ±20mA VOUT VOUT 50Ω 50Ω VBBIN VBBEXT Tracking ECL Logic Threshold Reference ECL HI IN ECL LO IN ECL Logic Threshold Reference –1.3V VBBOUT International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1992 Burr-Brown Corporation PDS-1130B Printed in U.S.A. May, 1994 SPECIFICATIONS ELECTRICAL Over full specified temperature range, using the internal +10V reference and rated supplies, unless otherwise noted. DAC650JL PARAMETER TEMPERATURE RANGE Specification: DAC650JL, KL(1) θCA θJC DIGITAL INPUTS Logic Resolution ECL Logic Input Levels(2): VIL IIL VIH IIH Logic Threshold Voltage CONDITIONS MIN Ambient 0 TRANSFER CHARACTERISTICS Integral Linearity Error Differential Linearity Error Monotonicity Bipolar Gain Error Bipolar Offset Error TIME DOMAIN PERFORMANCE Glitch Energy Output Rise Time Output Fall Time Settling Time(3): ±0.1%FSR 12 Parallel Input Lines Logic “0” –1.475 Logic “1” –1.115 –1.2 DC 1.0 2.0 –500 RL = 0Ω RL = ∞ VOUT, VOUT to Ground POWER SUPPLIES Supply Voltages: +VCC –VCC +VDD1 –VDD2 Power Supply Rejection Supply Currents: +ICC –ICC +IDD1 –IDD2 Power Consumption 49 –1.8 1.0 –0.8 1.0 –1.3 MIN +70 * Output Voltage, RL = ∞ Output Voltage, RL = ∞ Major Carry 10% to 90% 90% to 10% Major Carry, 1LSB Change 20 300 350 2.0 –1.4 –1.4 –1.4 9.95 4.5 –1.3 –1.3 –1.3 10 4950 10.0 +25°C, Span = DC to fCLK/2 +25°C, Span = DC to fCLK/2 +25°C, Span = DC to fCLK/2 +25°C, Span = DC to fCLK/2 +25°C, Span = DC to 150MHz +25°C, Span = 50MHz to 150MHz Full Scale Sine Wave Output 65 59 50 47 49 51 68 63 52 50 55 56 1.0 Operating, TMIN to TMAX +14.25 –15.75 +4.75 –5.46 +15 –15 +5 –5.2 0.05 10 –47 53 –191 2.0 All Supplies, ±5% Change Operating Operating ECL Compatible 12 –2 * 10 –0.6 * 10 –1.4 * 1.8 –600 1.5 ±20 ±1.0 50 50 5 TYP MAX UNITS * °C °C/W °C/W * * * * * * Bits V µA V µA V * * * * MHz ns ns ps ns * * * * * mA V Ω ppm/°C pF * * 500 ±0.018 ±0.018 ±0.018 Typical ±0.5 ±0.5 Best Fit Straight Line +25°C Over Temperature REFERENCES VBB Input Range (Pin 1) VBB INT Reference (Pin 68) VBB EXT Tracking Reference (Pin 67) ECLHI IN = –0.8V, ECLLO IN = –1.8V Internal Reference Voltage (Ref Out) Ref in Resistance Ref in Operating Voltage Range DYNAMIC PERFORMANCE Spurious Free Dynamic Range(4) fO = 1MHz, fCLK = 100MHz fO = 10MHz, fCLK = 100MHz fO = 30MHz, fCLK = 200MHz fO = 80MHz, fCLK = 200MHz fO = 80MHz, fCLK = 500MHz fO = 100MHz, fCLK = 500MHz Output Noise DAC650KL MAX 27 13 DIGITAL TIMING Input Data Rate CLK Pulse Width Low Set-Up Time Hold Time (Referred to CLK) Propagation Delay ANALOG OUTPUT Bipolar Output Current Bipolar Output Voltage Output Resistance Output Resistance Drift Output Capacitance TYP 51 * * * * * ±0.036 ±0.036 ±0.036 * * * * * * ±0.012 ±0.024 ±0.08 ±0.024 ±0.012 ±0.024 Guaranteed ±0.5 ±1.0 ±0.25 ±0.5 ±1.0 ±1.0 * * * * –1.2 –1.2 –1.2 10.05 * * * * 11.0 * +15.75 –14.25 +5.25 –4.94 0.08 13 –50 57 –245 2.6 * * * * * * 68 62 53 50 52 54 70 65 56 52 58 59 * * * * * * * * * * * * * * * %FSR %FSR %FSR %FSR %FSR pV-s ps ps ns * * * * * V V V V Ω V dBc(5) dBc dBc dBc dBc dBc µV/ Hz * * * * * * * * * * V V V V %/% mA mA mA mA W NOTE: (1) Extended temperature range devices are available, inquire. (2) VBBIN (Pin 1) connected to VBB INT (Pin 68). (3) Settling time is influenced by load due to fast edge speeds. Use good transmission line techniques for best results. (4) Spurious Free Dynamic Range includes both harmonic and non-harmonic related spurs in the bandwidth indicated. (5) dBc is “dB referred to the fundamental amplitude.” ® DAC650 2 ORDERING INFORMATION MODEL PACKAGE INFORMATION TEMPERATURE RANGE (AMBIENT) DESCRIPTION DAC650JL, KL 68-Pin Ceramic, Gullwing Leads PACKAGE PACKAGE DRAWING NUMBER(1) 68-Pin Ceramic Gullwing 256 MODEL 0°C to +70°C DAC650JL, KL NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS ±VCC .................................................................................................. ±18V Logic Input ......................................................................... +0.5V to –5.5V Case Temperature .......................................................... –40°C to +125°C Junction Temperature .................................................................... +150°C Storage Temperature ...................................................... –55°C to +125°C Lead Temperature (soldering, 10s) ................................................ +300°C ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that this integrated circuit be handled and stored using appropriate ESD protection methods. Stresses above these ratings may permanently damage the device. PIN DEFINITIONS PIN NO DESIGNATION DESCRIPTION PIN NO DESIGNATION DESCRIPTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VBB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 VEE VEE CLK CLKNOT DNC VEE VEE VEE VEE VEE VEE VEE VEE DGND DGND DGND DGND DGND DGND DGND DGND Sets Logic Threshold for Bits 1-12 MSB 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 AGND AGND AGND AGND VOUT VOUT VOUT AGND AGND AGND VOUT VOUT VOUT AGND AGND AGND AGND –15V –15V PWR GND +5V +5V VOS ADJ PWR GND RefADJ RefOUT RefIN +15V PWR GND –5.2V Analog ECL LOIN ECL HIIN VBBEXT VBBINT Ground for Analog Output Current LSB Logic Power (–5.2V Nominal)(1) Clock Not Clock Do Not Connect Ground for Logic Complementary Output Voltage Output Voltage –15V Supply Ground for Analog Supplies +5V Supply +5V Supply Offset Adjust Ground for Analog Supplies Reference Out Adjust Reference Out (+10V, Buffered) Reference In (4.950kΩ) +15V Supply Ground for Analog Supplies Analog Power (–5.2V Nominal)(1) External ECL LOW input (optional) External ECL HI input (optional) The buffered mean of LOEXT and HIEXT Internally generated –1.3V reference NOTE: (1) Both the –5.2V Logic and –5.2V analog pins should be powered from a common supply. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® 3 DAC650 TYPICAL PERFORMANCE CURVES TA = +25°C unless otherwise noted. OUTPUT SPECTRUM OUTPUT SPECTRUM +5 +5 fO = 1.0MHz fCLK = 100MHz Amplitude = +3.6dBm Resolution BW = 150Hz –15 Amplitude (dBm) Amplitude (dBm) –15 fO = 1.0MHz fCLK = 100MHz Amplitude = +3.58dBm Resolution BW = 290Hz –35 –55 –75 –35 –55 –75 –95 –95 0.5 0.7 0.9 1.1 1.3 1.5 0 10 Frequency (MHz) OUTPUT SPECTRUM 40 50 +5 fO = 9.98MHz fCLK = 100MHz Amplitude = +3.4dBm Resolution BW = 580Hz fO = 9.96MHz fCLK = 100MHz Amplitude = +3.35dBm Resolution BW = 580Hz –15 Amplitude (dBm) –15 Amplitude (dBm) 30 OUTPUT SPECTRUM +5 –35 –55 –75 –35 –55 –75 –95 –95 5 7 9 11 13 15 0 10 Frequency (MHz) 20 30 40 50 Frequency (MHz) OUTPUT SPECTRUM OUTPUT SPECTRUM +5 +5 fO = 29.93MHz fCLK = 200MHz Amplitude = +3.13dBm Resolution BW = 290Hz fO = 29.32MHz fCLK = 200MHz Amplitude = +3.1dBm Resolution BW = 1.2kHz –15 Amplitude (dBm) –15 Amplitude (dBm) 20 Frequency (MHz) –35 –55 –75 –35 –55 –75 –95 –95 15 21 27 33 39 45 0 Frequency (MHz) 40 60 Frequency (MHz) ® DAC650 20 4 80 100 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C unless otherwise noted. OUTPUT SPECTRUM OUTPUT SPECTRUM +5 +5 fO = 49.88MHz fCLK = 500MHz Amplitude = +3.3dBm Resolution BW = 1.2kHz –15 Amplitude (dBm) Amplitude (dBm) –15 fO = 79.92MHz fCLK = 500MHz Amplitude = +3.0dBm Resolution BW = 4.6kHz –35 –55 –75 –35 –55 –75 –95 –95 25 35 45 55 65 75 0 30 Frequency (MHz) OUTPUT SPECTRUM 90 120 150 80 100 OUTPUT SPECTRUM +5 +5 fO = 79.88MHz fCLK = 200MHz Amplitude = +0.93dBm Resolution BW = 1.2kHz fO = 79.27MHz fCLK = 200MHz Amplitude = +0.93dBm Resolution BW = 9.1kHz –15 Amplitude (dBm) –15 –35 –55 –75 –35 –55 –75 –95 –95 50 60 70 80 90 100 0 20 Frequency (MHz) 40 60 Frequency (MHz) OUTPUT SPECTRUM +5 fO = 99.75MHz fCLK = 500MHz Amplitude = +2.7dBm Resolution BW = 2.3kHz –15 Amplitude (dBm) Amplitude (dBm) 60 Frequency (MHz) –35 –55 –75 –95 50 70 90 110 130 150 Frequency (MHz) ® 5 DAC650 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C unless otherwise noted. SPURIOUS FREE DYNAMIC RANGE vs CLOCK FREQUENCY (Span = DC to fCLK/2) SPURIOUS FREE DYNAMIC RANGE vs CLOCK FREQUENCY (Span = DC to 200MHz) Spurious Free Dynamic Range (dBc) Spurious Free Dynamic Range (dBc) 80 fOUT = 1MHz 70 fOUT = 10MHz 60 fOUT = 20MHz fOUT = 50MHz 50 40 55 fOUT = 100MHz 50 fOUT = 125MHz 45 40 0 100 200 300 400 500 300 400 450 Clock Frequency (MHz) SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY (Span = DC to fCLK/2) SPURIOUS FREE DYNAMIC RANGE vs OUTPUT FREQUENCY (Span = DC to 200MHz) 80 70 fCLK = 100MHz 60 350 Clock Frequency (MHz) Spurious Free Dynamic Range (dBc) Spurious Free Dynamic Range (dBc) 60 fCLK = 200MHz 50 fCLK = 300MHz 40 500 80 70 60 fCLK = 400MHz 50 fCLK = 500MHz 40 0 20 40 60 80 100 120 140 0 Output Frequency (MHz) 40 60 80 100 Output Frequency (MHz) ® DAC650 20 6 120 140 TECHNOLOGY OVERVIEW frequency performance and reliability due to higher current densities and operating temperature. Alternatively, lower full scale currents will affect operation because there is less current available to charge internal and external capacitances. The DAC650 uses a unique design approach to achieve very fast settling time and high resolution. This mixed-technology design uses two active chips: one gallium arsenide and the other silicon. It should be noted that the gain adjust techniques mentioned above affect the current output and thus the voltage output from the DAC650. The voltage output will also be affected by an external load acting in parallel with the 50Ω output impedance. The GaAs MESFET die is used for those circuits which determine speed. This includes the latches, data decoders, and current switches. A silicon die with thin film is used for those circuits which determine accuracy, such as the precision references and current sources. The precision R-2R resistor ladders are laser trimmed to further increase the accuracy of the DAC650. A block diagram of the DAC650 is shown in Figure 1. OFFSET ADJUST The offset may be adjusted by connecting a potentiometer between the +5V supply and ground with the wiper connected to the offset adjust pin. The voltage on this pin with no connection is about 2V, with an equivalent impedance of 1.6kΩ. A 10kΩ potentiometer will give the necessary adjustment range. The full scale range of the DAC output may be offset so it is not symmetrical around zero, but the full scale range must also be adjusted so that the output swing does not exceed ±1V. Connecting the offset adjust pin to ground gives a unipolar output of 0 to –2V (with no load) or 0 to –1V (with a 50Ω load). This also reduces the current requirements for the +5V supply by 20mA. THEORY OF OPERATION The DAC650 employs a familiar architecture where input bits switch on the appropriate current sources. Bits 1-3 are decoded into 7 segments before the first set of latches. A similar delay is given for the 9 least significant bits to minimize data skew. The edge triggered master-slave latches are driven by an internal clock buffer. This buffer placement has matched the clock lines to each of the 32 latches, thus minimizing output glitch energy. There are 7 current sources for bits 1 to 3. Current sources for bits 4-8 are scaled down in binary fashion. These current sources are switched directly to the output of the R-2R ladder. Bits 9-12 are fed to the laser trimmed R-2R ladder for proper scale-down. The segmentation further minimizes output glitch which can cause spectral degradation. DIGITAL INPUTS, LOGIC THRESHOLDS, and TERMINATION The input logic levels and clock levels are ECL compatible. The data inputs are single ended ECL and the clock input is differential. The internal impedance of the data and clock inputs is a high impedance (FET gate), and is clamped to the digital supply and ground to protect against ESD damage. ESD precautions should still be used when handling the DAC650. The output current sees 50Ω of output impedance from the equivalent resistance of a R-2R ladder (100Ω) in parallel with 100Ω (Figure 1). With all of the current sources off, the output voltage is at +1V. With all current sources on (–40mA), the output voltage is at –1V. There is also a complementary VOUT output that allows for a differential output signals. The full scale complementary outputs (VOUT and VOUT ) can be simply modeled as ±20mA in parallel with 50Ω. This gives an output swing of 1Vp-p with an external 50Ω load. The inputs will most likely be driven by high-speed ECL gate outputs. These outputs should be terminated using standard high-speed transmission line techniques. Consult an ECL handbook for proper methods of termination. Termination resistors should not be connected to the analog ground plane close to the DAC650. The fast changing digital bit currents will cause noise in the analog ground plane under this layout scheme. These fast changing digital currents should be steered away from the sensitive DAC650 analog ground plane. For speeds of up to 256MHz, series termination with 47Ω resistors will be adequate (Figure 3). This termination technique will greatly lessen the issue of termination currents coupling into the analog ground plane. Above 256MHz, parallel termination of the transmission line at the package pin may be required for clean digital input. REFERENCE/GAIN ADJUSTMENT A precision +10V reference is included in the DAC650. A 50Ω resistor should be connected between REFIN and REFOUT for the specified unadjusted gain. This internal reference has been laser trimmed to minimize offset and gain drift. Alternatively, an external reference may be used. Multiple DACs may be run from one master reference by connecting a 50Ω resistor from each REFIN to the master REFOUT. A 100Ω potentiometer may be used in place of the 50Ω resistor in order to provide a ±1% gain adjustment range (Figure 2). The input data threshold level is set by connecting the appropriate voltage (–1.2V to –1.4V) to pin 1. The actual level may be provided 3 ways: A wider adjustment range of ±20% may be achieved by connecting a 10kΩ potentiometer from REFOUT to ground, with the wiper connected to the REFADJ pin. Adjusting the output to more than 40mA full scale may degrade high (1) The user connects the DAC650’s internal –1.3V threshold reference directly to pin 1. This simple connection provides excellent noise margins for ECL levels. ® 7 DAC650 RefADJUST RefOUT RefIN Offset Adjust 3kΩ 3kΩ 3kΩ 8kΩ 4.95kΩ 5V Ref +2V 2kΩ 100Ω VBB 100Ω Current Sources Switch Drivers Latches Receivers MSB 2 3 4 5 6 7 8 9 10 11 LSB Latches +1V VOUT +1V Current Switches VOUT 100Ω 100Ω (Ladder Equivalent Resistance) VBBOUT (–1.3V) VBBEXT (Mid-point Out) ECL Logic Threshold Tracking ECL Logic Threshold ECL High In Clock Buffer ECL Low In CLK CLK FIGURE 1. Functional Block Diagram of the DAC650. ECL Drive Gates 100Ω 61 60 DAC650 DAC650 47Ω RefIN Bit Input RefOUT Recommended Pull Down Resistor –5.2V FIGURE 2. Using a Potentiometer for ±1% Gain Adjust. FIGURE 3. Series Bit Termination. ® DAC650 8 (2) An external VBB system reference is applied to pin 1. This technique may allow data threshold levels to track the system over supply and temperature variations. The DAC650 has a differential ECL clock input. This clock input can also be driven by a single-ended clock if desired by tying the CLK input to an external voltage of –1.3V. Using a true differential clock provides much improved digital feedthrough immunity, however. (3) The internal tracking ECL threshold reference (pin 67) is applied to pin 1. The output of the tracking ECL threshold reference is simply the average of two externally applied levels. These levels are a system logic low (pin 65) and system logic high (pin 66). This technique may provide increased noise margin for systems with levels slightly different from ECL. Leave pins 65-67 open if this option is not used. DATA IN/VOUT CORRESPONDENCE The each full scale output of the DAC650 may be modeled as either ±20mA current source in parallel with 50Ω or a ±1V voltage source in series with 50Ω. The nominal current and voltage bit weights are given in Table I and the input code vs output voltage relationships are given in Table II. Transmission line techniques at the output are also recommended to minimize ringing and glitching. Ideally, both of the outputs should see the same termination, including any delay between the DAC650 and the load. TIMING The DAC650 has an internal edge triggered latch. The output changes on the positive edge of CLK. This masterslave latching will assure that the 12 bits will arrive at the bit switches with a minimum of data skew. Data must have adequate setup and hold time for proper operation (refer to Figure 4). Note that the Hold time is negative. Therefore the data may change before the rising edge of clock and still be valid. Since the outputs VOUT and VOUT are equal in magnitude but opposite in sign, they are ideal for driving RF transformers (Figures 5). The primary may be connected between the two outputs. The secondary may be floating or referenced to ground. This results in a 2X signal power and some cancellation of clock feedthrough, glitching, and distortion. Figures 6 and 7 give recommended output amplifiers. tPWL CLK Data Clock 1 Clock 0 Data 1 Data 0 Data 2 VOUT 1 VOUT tP tH tSU SYMBOL tP tSU tH tPWL Clock 2 MIN DESCRIPTION Propagation delay. 50% of CLK to 50% of VOUT. Setup time DATA must remain stable before CLK. Hold time DATA must remain stable after CLK. CLK pulse width low (50% to 50%). 2.0 –500 1.0 TYP 1.5 1.8 –600 MAX UNITS ns ns ps ns FIGURE 4. Timing Diagram for the DAC650. ® 9 DAC650 If only one output is used, the unused output should be terminated identically. If the terminations cannot be identical and the unused output must be unterminated, the termination for the used output should be as close as possible to the DAC650. mended. A 10µF tantalum capacitor in parallel with a 0.01µF chip capacitor will be sufficient in most applications. Pin 64, Analog VEE, should be connected to the same supply as the digital VEE pins (–5.2V). MAXIMIZING PERFORMANCE The DAC650 has been designed to give a very clean analog output with minimal noise, overshoot, and ringing. In addition to optimizing the layout and ground of the DAC650, there are other important issues to consider when optimizing the performance of this DAC in various AC applications. LAYOUT AND POWER SUPPLIES A multilayer PC board with a solid ground and power planes is recommended. An example of a typical circuit configuration is given in Figures 8. The DAC650 has multiple ground pins to minimize pin impedances. All of the ground pins (analog and digital both) should be connected directly to the analog ground plane at the DAC650. The DAC650 includes an internal 50Ω output impedance to simplify output interfacing to a 50Ω load. Because some loads may be a complex impedance, care must be taken to match the output impedance with the load. Mismatching of impedances can cause reflections which will affect the measured AC performance parameters such as settling time, harmonic distortion, rise/fall times, etc. Often complex impedances can be matched by placing a variable 3 to 10pF capacitor at the output of the DAC to ground. Also, probing the output can present a complex impedance. Wide busses for the power paths are recommended as good general practice. There are several internal power supply bypass capacitors, but external bypassing is still recomBIT VOLTAGE (No External Load) CURRENT 1 2 3 4 5 6 7 8 9 10 11 12 (LSB) 1V .5V 0.25V 0.125V 62.5mV 31.25mV 15.625mV 7.8125mV 3.9063mV 1.9531mV 976µV 488µV 20mA 10mA 5mA 2.5mA 1.25mA 625µA 312.5µA 156.25µA 78.125µA 39.06µA 19.53µA 9.76µA The typical performance curves of Spurious Free Dynamic Range vs various combinations of clock rate and/or input frequency should give a general idea of the spectral performance of the DAC under system specific clock and output frequencies. We have defined Spurious Free Dynamic Range as any harmonic or non-harmonic spurs in the indicated bandwidth . In phase lock loop applications, the harmonics often fall outside the loop bandwidth of the PLL. In these cases, as well as cases where the output is filtered, Spurious TABLE I. Nominal Bit Weight Values. INPUT BITS 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • • • • 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 OUTPUT VOLTAGES VOUT NVOUT +1.000 +1 – 488µV +1 – 976µV RF –1 + 488µV –1 + 976µV –1 + 1.464mV 39 40 41 VOUT DAC650 0 0 1 0 0 1 0 0 1 0.50 0.000 –1 + 488µV –0.50 + 488µV +488µV +1.000 45 46 47 TABLE II. Input Code vs Output Voltage Relationships. VOUT OPA64X or OPA600 FIGURE 6. A High Speed Single Ended Amplifier at the Output. The Gain is –RF/50Ω. 39 40 41 VOUT 39 40 41 Load DAC650 45 46 47 VOUT DAC650 Mini Circuits TT5-1A 45 46 47 FIGURE 5. Using an RF Transformer at the Output of the DAC650. Filtering the Outputs Before the Transformer Improves the Performance in Some Applications. VOUT OPA64X or OPA600 FIGURE 7. A High Speed Differential Amplifier at the Output. ® DAC650 VOUT 10 EVALUATION BOARD The high frequency signals used in operating the DAC650 can cause difficult layout problems. It is especially difficult to build a high-performance prototype board using the DAC650. It is recommended that an evaluation fixture be used for prototyping. An evaluation fixture includes a DAC650 soldered to the PC board. Both grades are available for the evaluation fixture. Free Dynamic Range will generally be much better due to the harmonics falling outside the passband. Even with a bandpass filter, updating the DAC at greater than 4 times per cycle will (1) minimize the 2nd and 3rd harmonic magnitudes by having the output slew excessively between any successive clock and (2) will keep the (fCLK – 2fO) spur and other even order spurs from folding back close to the fundamental under the condition fOUT = 1/3fCLK and (3) will keep the (fCLK – 3fO) spur and other spurs from folding back close to the fundamental under the condition fOUT = 1/4fCLK. Making use of the high update rate of the DAC650 helps to lessen the problems of harmonics “folding back” into the passband. ORDERING INFORMATION MODEL DESCRIPTION DEM-DAC650J-E DEM-DAC650K-E DEM-DAC650 PDS C9 0.01µF DAC650 1 2 B1 3 B2 4 B3 5 B4 6 B5 7 B6 8 B7 9 B8 10 B9 11 B10 12 B11 13 B12 14 –5.2V 15 16 C10 0.01µF Evaluation Board with DAC650JL Attached Evaluation Board with DAC650KL Attached Data Sheet for DAC650 Evaluation Board 68 VBBIN VBBINT B1 (MSB) VBBEXT B2 ECL HIIN B3 ECL LOIN B4 –VEE B5 PWRGND B6 +15V B7 REFIN B8 REFOUT B9 REFADJ B10 REFGND B11 VOSADJ B12 +5V –VEE +5V 20 21 22 NOTE: Clock and data inputs must be terminated at source and/or package pin. 23 24 25 26 + C14 10µF C11 0.01µF 27 64 C5 0.01µF + C1 10µF –5.2V 63 +15V –VEE PWRGND CLK –15V CLK –15V DNC AGND –VEE AGND –VEE AGND –VEE AGND –VEE VOUT –VEE VOUT –VEE VOUT –VEE AGND –VEE AGND DGND AGND DGND VOUT DGND VOUT DGND VOUT DGND AGND DGND AGND DGND AGND DGND AGND 60 (50Ω Optional) C6 0.01µF + C2 10µF 59 58 57 56 C7 0.01µF + C3 10µF 55 +5V 54 53 –15V 52 51 19 CLK 65 61 18 –5.2V 66 62 17 CLK 67 50 C8 0.01µF + C4 10µF 49 48 47 46 DAC Out 45 44 43 42 28 41 29 30 31 32 40 DAC Out 39 38 37 33 36 34 35 FIGURE 8. Typical DAC650 Connection Diagram. ® 11 DAC650