M16C/6KA Group
REJ03B0100-0100Z
Rev.1.00
Jul 16, 2004
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M16C/6KA group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 144-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. To communicate with host CPU, the LPC bus interface is built in. In this way, this MCU can
work as slave controller in the personal computer system.
Features
• Memory capacity ........................................ ROM 128K bytes
RAM 5K bytes
• The Min. time of instruction execution ....... 62.5ns (f(XIN)=16MHz, with 0 wait, Vcc=3.3V)
• Supply voltage ........................................... 3.0 to 3.6V (f(XIN)=16MHZ with 0 wait)
• Supply voltage for Program/Erase ............. 3.0 to 3.6V
(CPU reprogram mode 0, Internal clock=8MHZ with 1 wait)
(CPU reprogram mode 1, Internal clock=4MHZ with 1 wait)
• Low power consumption ............................ 52.8mW ( f(XIN)=16MHZ, with 0 wait, VCC = 3.3V)
• Interrupts .................................................... 32 internal and 16 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Key input interrupts ...................................... 2 (8 inputs shared with 1 interrupt request X 1;
8 inputs (with event latch) shared with1 interrupt request X 1)
• Multifunction 16-bit timer ............................ 5 output timers + 6 input timers
• Serial I/O (Serial interface) ........................ 3 channels (1 for UART or clock synchronous, 2 for clock synchronous)
• Host interface ............................................. LPC bus interface X 4
• A-D converter (A/D converter) ................... 10 bits X 8 channels (Expandable up to 10 channels)
• PWM .......................................................... 8 bits X 6 channels
• Watchdog timer .......................................... 1
• I2C bus interface ........................................ 3 channels
• PS/2 interface ............................................ 3 channels
• Serial interrupt output ................................ 6 factors (2 fixed factors, 4 programmable factors)
• Programmable I/O ..................................... 129
_______
• Input port .................................................... 1 (P85 shared with NMI pin)
• Clock generating circuit ............................. 1 built-in clock generation circuit
(built-in feedback resistor, and external ceramic)
Applications
Notebook PC, others
Specifications written in this manual
are believed to be accurate, but are
not guaranteed to be entirely free of
error.
Specifications in this data sheet may
be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 1 of 266
M16C/6KA Group
Description
------Table of Contents-----Central Processing Unit (CPU) ..................... 13
Reset ............................................................. 16
Processor Mode ............................................ 26
Clock Generating Circuit ............................... 29
Protection ...................................................... 37
Interrupts ....................................................... 38
Watchdog Timer ............................................ 65
Timer ............................................................. 67
Serial I/O (Serial interface) ............................ 85
A-D Converter (A/D converter) .................... 111
PWM Output Circuit .................................... 121
LPC Bus Interface ....................................... 125
Serial interrupt output .................................. 143
I2C-BUS Interface ........................................ 154
PS2 Interface .............................................. 185
Programmable I/O Ports ............................. 200
Electrical Characteristics ............................. 221
Flash Memory Version ................................ 234
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REJ03B0100-0100Z
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M16C/6KA Group
Description
The differences in M16C/6K (144-pin) group
Type name
M306K7F8LRP(In mass production)
M306K9FCLRP
(In mass production)
M306KAFCLRP(Under development)
Pin numbers
144-pin
144-pin
144-pin
RAM
3K bytes
5K bytes
5K bytes
ROM
NEW DINOR
Flash memory 68K bytes
NEW DINOR
Flash memory 128K bytes
NEW DINOR
Flash memory 128K bytes
Built-in ROM area
User ROM area
Address 0EF00016 - 0FFFFF16
Boot ROM area
Address 0FF00016 - 0FFFFF16
User ROM area
Address 0E000016 - 0FFFFF16
Boot ROM area
Address 0FF00016 - 0FFFFF16
User ROM area
Address 0E000016 - 0FFFFF16
Boot ROM area
Address 0FF00016 - 0FFFFF16
Address 03B416
Flash memory recognition register
After reset 000000002
Flash memory recognition register
After reset XXXXXX102
Flash memory recognition register
After reset XXXXXX112
Address 03B716
Flash memory control register
After reset XX0000012
Flash memory control register
After reset 000000012
Flash memory control register
After reset 000000012
The power supply
for program/erase
Vcc
Vcc 3.0 - 3.6V
FVCC 3.0 - 3.6V
Vcc
FVCC pin
Not exist
The input pin of power supply
for program/erase
Not exist
PWM output circuit
14-bit X 4
8-bit X 6
8-bit X 6
I2C bus interface
2 channels
3 channels
3 channels (I2C bus interface pin of Channel
1 and 2 can changed.)
Key input interrupt
8 inputs shared with 1 interrupt
request X 1
8 inputs (with event latch) shared
with 1 interrupt request X 1
Detected only in the falling edge
Can not be selected with 1 bit unit
8 inputs shared with 1 interrupt
request X 1
8 inputs (with event latch) shared
with 1 interrupt request X 1
Detected in either of the edges by
the edge selection
Can be selected with 1 bit unit
8 inputs shared with 1 interrupt
request X 1
8 inputs (with event latch) shared
with 1 interrupt request X 1
Detected in either of the edges by
the edge selection
Can be selected with 1 bit unit
DMAC
Exist (2 channels)
Exist (2 channels)
Not exist
D/A converter
Exist (8-bit X 2 channels)
Exist (8-bit X 2 channels)
Not exist
Comparator Circuit
Exist (8 channels)
Exist (8 channels)
Not exist
Interrupts
31 vector
31 vector
45 vector (add OBE int.)
Serial I/O
• UART or clock
synchronous X 3
• clock
synchronous X 2
• UART or clock
synchronous X 3
• clock
synchronous X 2
• UART or clock
synchronous X 1
• clock
synchronous X 2
2 circuits
2 circuits
1 circuit
Clock generation
circuits
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
3.0 - 3.6V
page 3 of 266
3.0 - 3.6V
M16C/6KA Group
Description
Pin configuration
Fig. AA-1 shows the pin configuration (top view).
P10
P126
P125/INT111
P124/INT102
P123/INT92
P122/INT82
P121/INT72
P120/INT61
P07
P06
P05
P04
P03
P02
P01
P00
P117
P116
P115
P114
P113
P112
P111/F1OUT1
P110/F1OUT0
P107/AN7/INT110
P106/AN6/INT100
P105/AN5/INT90
P104/AN4/INT80
P103/AN3/INT70
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG/SIN40/INT60
82
81
80
79
78
77
76
75
74
73
84
83
95
94
93
92
91
90
89
88
87
86
85
108
107
106
105
104
103
102
101
100
99
98
97
96
P11
P12
P13
P14/INT71/CTS11/RTS11/CLKS11
P15/INT81/CLK11
P16/INT91/RXD11
P17/INT101/TXD11
P20
P21
P22
P23
P24
P25
P26
P27
VSS
P30/LAD0
VCC
P127
P31/LAD1
P32/LAD2
P33/LAD3
P34/LFRAME
P35/LRESET
P36/LCLK
P37
P130
P131
P132
P133
P134
P135
P136
P137
P40/ TA00OUT/OBF00/PWM41
P41/TA10OUT/PWM51
PIN CONFIGURATION (top view)
109
111
112
113
72
71
70
69
68
114
115
67
66
116
117
118
65
64
63
62
61
60
59
58
57
110
119
120
121
122
123
124
125
56
55
54
M306KAFCLRP
126
127
128
53
52
129
130
51
131
50
49
132
133
48
134
135
47
46
45
44
43
42
41
136
137
138
139
140
40
39
141
142
143
38
37
144
2 3 4 5
6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
P96/ANEX1/SOUT40/PWM30
P95/ANEX0/CLK40/PWM20
P94/TB40IN/PWM10
P93/TB30IN/PWM00
P92/SOUT30/INT5
P91/SIN30/INT4
P90/CLK30/INT3
P161/TB41IN/PWM50
P160/TB31IN/PWM40
P157/SIN41
P156/SOUT41
P155/CLK41
P154
P153
M1
M0
P87
P86
RESET
XOUT
VSS
XIN
VCC
P85/NMI
P84/TB2IN/SCL21
P83/TB1IN/SDA21
P82/TB0IN/SCL11
P81/TA4IN/SDA11
P80/ICCK
P77/TA3IN/SCL20
P76/SDA20
P75/TA2IN/INT2/PS2B2
P74/INT1/PS2B1
P73/TA1IN/INT0/PS2B0
P72/PS2A2
P71/TA0IN/TB5IN/PS2A1
1
P42/TA20OUT/GATEA20
P43/OBF01/SERIRQ
P44/PWM01/OBF1
P45/PWM11/OBF2/PRST
P46/PWM21/OBF3/CLKRUN
VCC
P47/PWM31
VSS
P140/KI10
P141/KI11
P142/KI12
P143/KI13
P144/KI14
P145/KI15
P146/KI16
P147/KI17
P50/KI00
P51/KI01
P52/KI02
P53/KI03
P54/KI04
P55/KI05
P56/KI06
P57 /CLKOUT/KI07
P150/TA01OUT/CLK31
P151/TA11OUT/SIN31
P152/TA21OUT/SOUT31
P60/SDA0
P61/SCL0
P62/SDA10
P63/SCL10
P64/CTS10/RTS10/CLKS10
P65/CLK10
P66/RXD10/TA3OUT
P67/TXD10/TA4OUT
P70/PS2A0
Package: 144PFB-A
Fig. AA-1 Pin configuration (top view)
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REJ03B0100-0100Z
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M16C/6KA Group
Description
Block Diagram
Fig.AA-2 is a block diagram of the M16C/6KA (144-pin version) group.
8
I/O ports
8
Port P0
Port P1
8
8
Port P2
8
Port P3
Port P4
Clock synchronous SI/O
(8 bits x 2channels)
Host interface
(LPC bus interface x 4 channels)
I C bus interface
(3 channels)
2
PWM output
(8 bits x 6channels)
PC
Stack pointer
ISP
USP
INTB
Flag register
FLG
Port P15
2
8
Port P14
8
Port P13
8
Note1 : ROM size depends on MCU type.
Note2 : RAM size depends on MCU type.
Fig.AA-2 Block diagram of M16C/6KA (144-pin version) group
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 5 of 266
AAAA
AAAA
Multiplier
Port P12
8
Port P11
8
8
Port P16
RAM
(Note2)
Vector table
SB
ROM
(Note1)
Port P10
R0H
R0
R0H
R0L
R1H
LR1
R1H
R1L
R L
R2
R
2
R3
A
3
A0
A
0
A1
F
B
1
FB
Serial interrupt output
(6 factors)
Memory
Program counter
Registers
8
M16C/60 series 16-bit CPU core
Port P9
Watchdog timer
(15 bits)
PS2 interface
(3 channels)
7
UART/clock synchronous SI/O
(8 bits x 1 channel)
8
XIN-XOUT
Port P85
Timer TA0(16 bits)
Timer TA1(16 bits)
Timer TA2(16 bits)
Timer TA3(16 bits)
Timer TA4(16 bits)
Timer TB0(16 bits)
Timer TB1(16 bits)
Timer TB2(16 bits)
Timer TB3(16 bits)
Timer TB4(16 bits)
Timer TB5(16 bits)
Port P6
Port P8
System clock generator
A-D converter
(10 bits x 8 channels
Expandable up to 10 channels)
Timer
Port P5
8
Port P7
Internal peripheral function
8
M16C/6KA Group
Description
Performance Outline
Table AA-1 is a performance outline of M16C/6KA (144-pin version) group.
Table AA-1 Performance outline of M16C/6KA (144-pin version) group
Item
Performance
Number of basic instructions
91 instructions
The Min. time of instruction execution
62.5ns (f(XIN)=16MHz, with 0 wait, Vcc=3.3V)
Memory
ROM
(See the figure of ROM Expansion)
capacity
RAM
5K bytes
I/O port
P0 to P10 (except P85)
8 bits x 10, 7 bits x 1
P11 to P16
8 bitsx5, 2 bitsx1
Input port
P85
1 bit x 1
Multifunction TA0, TA1, TA2, TA3, TA4
16 bits x 5
timer
TB0, TB1, TB2, TB3, TB4, TB5
16 bits x 6
Serial I/O
UART1
(UART or clock synchronous) x 1
SI/O3, SI/O4
A-D converter
Watchdog timer
Interrupt
Host interface
PWM
I2C bus interface
PS2 interface
Serial interrupt output
Clock generating circuit
(Clock synchronous) x 2
10 bits x (8 + 2) channels
15 bits x 1 (with prescaler)
32 internal and 16 external sources, 4 software
sources, 7 levels
4 channels (LPC bus interface)
8 bits x 6
3 channels
3 channels
6 factors (2 fixed factors, 4 programmable factors)
1 built-in clock generation circuit
(built-in feedback resistor, and external ceramic)
Power consumption
I/O
I/O withstand voltage
characteristics Output current
Device configuration
Package
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REJ03B0100-0100Z
page 6 of 266
52.8mW (3.3V, f(XIN)=16MHz, with 0 wait)
3.3V
5mA
CMOS high performance silicon gate
144-pin plastic mold QFP
M16C/6KA Group
Description
Renesas plans to release the following products in the M16C/6KA (144-pin version) group:
(1) Support for flash memory version
(2) ROM capacity
(3) Package
144PFB-A : Plastic molded QFP(flash memory version)
ROM Size
(Byte)
External
ROM
256K
M306KAFCLRP
128K
96K
80K
64K
32K
Mask ROM version
Flash version
Fig.AA-3 ROM expansion
Table AA-2 Product list
Type No.
M306KAFCLRP
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
From July 2004 up to now
ROM size RAM size
128 bytes
page 7 of 266
5K bytes
Package type
Host Interface
Remarks
144PFB-A
LPC
Flash memory (NEW
DINOR) version
M16C/6KA Group
Description
Type No. M30 6KA F C XXX RP
Package type
RP : 144PFB-A
ROM No.
ROM type
C : 128Kbytes
Memory type
F : Flash version
M16C/6KA Group
M16C Family
Fig.AA-4 Type No., memory size, and package
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REJ03B0100-0100Z
page 8 of 266
M16C/6KA Group
Pin Description
Pin Description
Pin name
Signal name
Vcc, Vss
I/O type
Power supply
input
Function
Apply 3.0 to 3.6 V to VCC . Apply 0V to VSS
____________
RESET
Reset input
Input
A “L” on this input resets the microcomputer.
XIN
XOUT
Clock input
Clock output
Input
Output
M0,M1
Chip mode
setting
Input
These pins are provided for the main clock generating circuit.
Connect a ceramic resonator between the XIN and the XOUT
pins. To use an externally derived clock, input it to the XIN pin
and leave the XOUT pin open.
Connect to VSS
AVCC
Analog power
supply input
This pin is a power supply input for the A-D converter.
Connect this pin to VCC.
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter.
Connect this pin to VSS.
VREF
Reference
voltage input
Input
P00 to P07
I/O port P0
Input/output This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or output individually. When set for input, the user can
specify in units of four bits via software whether or not they
are tied to a pull-up resistor.
This port supports CMOS input level. And output type supports CMOS 3 state or N channel open drain selectable.
P10 to P17
I/O port P1
Input/output This is an 8-bit I/O port equivalent to P0. Pins in this port also
function as external interrupt pins or UART1 I/O pin selected
by software.
P20 to P27
I/O port P2
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type just supports CMOS 3 state only). P20-P27 are available for directly driving LED's.
P30 to P37
I/O port P3
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type just supports CMOS 3 state only). The port can be
used for LPC bus interface I/O pins by software selection.
P40 to P47
I/O port P4
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type just supports CMOS 3 state only). By software selecting,
the port can also be used for LPC bus interface I/O pins,
Timer A0 to A2 output pins PWM output pins or serial interrupt
output I/O pins. P40 to P46 pins' level can be read regardless
the setting of input port or output port. If P40 or P43 are used
for output ports, the function that clears P40 or P43 to "0" after
the read of output data buffer from host CPU is available.
P50 to P57
I/O port P5
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output type
is CMOS 3 state only). Key on wake interrupt 0 input function
support. P57 in this port outputs a divide-by-8 or divide-by-32
clock of XIN selected by software.
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REJ03B0100-0100Z
page 9 of 266
This pin is a reference voltage input for the A-D converter.
M16C/6KA Group
Pin Description
Pin Description
Pin name
Signal name
I/O type
Function
P60 to P67
I/O port P6
Input/output This is an 8-bit I/O port equivalent to P0. (Except that P60 to
P63's output type is N channel open drain only; P64 to P67's
output type is CMOS 3 state only; P60 to P63 no internal
pull-up register support.) By software selecting, this port
can be used for I2C-BUS interface, UART1 input/output pin,
timerA3, A4 output pin. When P60 to P63 used as I2C-BUS
interface SDA, SCL, the input level of these pins are CMOS/
SMBUS selectable.
P70 to P77
I/O port P7
Input/output This is an 8-bit I/O port equivalent to P0. (Except that P70 to
P77 output type is N channel open drain only; no internal
pull-up register support.) By software selecting, this port
can be used for external interrupt input pin, timerA0 to A3
and timer B5 input pin, PS2 interface input/output pin, I2C
interface input/output pin. P70 to P75 pins' level can be read
regardless of the setting of input port or output port.
P80 to P84,
P86,
P87,
P85
I/O port P8
Input/output
Input/output
Input/output
Input
P90 to P97
I/O port P9
P100 to P107
I/O port P10
I/O port P85
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
P80 to P84, P86, and P87 are I/O ports with the same functions as P0. (Except that P86 to P87's output type is CMOS
3 state only; P80 to P84's output type is N channel open
drain only; P85 is input port only; the P80 to P84 and P85 are
no internal pull-up register support.)
By software selecting, this port can be used for timer A4, B0
to B2, I2C-BUS interface I/O pins. The input level of P81 to
P84 and SDA, SCL inputs can be switched to CMOS/SMBUS
when these pins function as I2C bus
interface.
P85 is an
______
______
input-only port that also functions for NMI. The NMI interrupt
is generated
when the input at this pin changes from “H” to
______
“L”. The NMI function cannot be cancelled using software.
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) By software selecting, the port
can be used for external interrupt, timer B3 to B4, A-D converter extended input pins, A-D trigger, SI/O3, SI/O4 I/O
pins, PWM, output pins.
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) If the ports are set to input
mode, the pull-up resistor can be set in bit unit. By software
selecting, the port can be used for A-D converter, external
interrupt input pins.
page 10 of 266
M16C/6KA Group
Pin Description
Pin Description
Pin name
Signal name
P110 to P117
I/O port P11
Input/output This is an 8-bit I/O port equivalent to P0. By software selecting, P110, P111 also function as clock output pins, which the
frequency is the same with XIN.
P120 to P127
I/O port P12
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) By software selecting, this port
can be used for external interrupt input pin.
P130 to P137
I/O port P13
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type is N channel open drain only; no internal pull-up register support.)
P140 to P147
I/O port P14
P150 to P157
I/O port P15
P160, P161
I/O port P16
Input/output This is an 8-bit I/O port equivalent to P0. The port can be
used for key on wake-up interrupt 1 input pins. P140 to P143
are available for directly driving LED's. In input mode, the
pull-up register can be set in one bit unit by software.
Input/output This is an 8-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) By software selecting, these
ports can be used for timer A0 to A2's output or SI/O3 and
SI/O4 I/O pins.
Input/output This is an 2-bit I/O port equivalent to P0. (Except that output
type is CMOS 3 state only.) By software selecting, this port
can be used for timer B3 and B4 input or PWM output pin.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
I/O type
page 11 of 266
Function
M16C/6KA Group
Memory
Operation of Functional Blocks
The M16C/6KA (144-pin version) group accommodates certain units in a single chip. These units include
ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/
logic operations. Also peripheral units such as timers, serial I/O, A-D converter, host bus interface, PWM
output, I2C BUS interface, PS2 interface and I/O ports are included.
The following explains each unit.
Memory
Fig.CA-1 is the memory map. The address space extends up to 1M bytes from address 0000016 to FFFFF16.
There is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped from FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal
register (INTB). See the section on interrupts for details.
From 0040016 to the address increasing direction RAM is allocated. For example, in the M306KAFCLRP, 5K
bytes of internal RAM is mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM
also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Fig.CA-2 to CA-5 are location of
peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped from FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can
be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
For details, see
Fig.CA-2 to Fig.CA-4
0040016
Internal RAM area
FFE0016
017FF16
Special page
vector table
FFFDC16
Inhibited
Undefined instruction
Overflow
BRK instruction
Address match
Single step
E000016
Internal ROM area
FFFFF16
Fig.CA-1 Memory map
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REJ03B0100-0100Z
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FFFFF16
Watchdog timer
DBC
NMI
Reset
M16C/6KA Group
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Fig.BA-1 Seven of these registers (R0, R1, R2, R3, A0, A1, and
FB) come in two sets; therefore, these have two register banks.
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
b15
R0(Note)
b8 b7
b15
R1(Note)
b8 b7
H
b15
R2(Note)
b15
R3(Note)
b15
A0(Note)
b15
A1(Note)
b15
FB(Note)
b0
L
H
b19
b0
L
b0
Program counter
Data
registers
b19
INTB
b0
Interrupt table
register
L
H
b15
b0
b0
User stack pointer
USP
b15
b0
b0
b0
PC
b0
Interrupt stack
pointer
ISP
Address
registers
b15
b0
Static base
register
SB
b15
b0
Frame base
register
b0
FLG
Flag register
AA
AAAAAA
AA
AA
AA
A
AA
A
AA
AA
AA
AAAAAAAAAAAAAAAAA
AAA
IPL
U
I O B S Z D C
Note: These registers consist of two register banks.
Fig.BA-1 Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and
low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be u2sed for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured
with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This
flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Fig.BA-2 shows the flag register
(FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to
“0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0”
when the interrupt is acknowledged.
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CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this
flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt No. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with the three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is
enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
AA
AAAAAAAAAA
AAA
AA
AAA
b15
b0
IPL
U
I
O B S Z D C
Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level (CPU)
Reserved area
Fig.BA-2 Flag register (FLG)
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M16C/6KA Group
RESET
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains the hardware reset.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Fig.VB-1 shows the example reset circuit. Fig.VB-2 shows the reset sequence.
3.3V
3.0V
VCC
RESET
0V
3.3V
VCC
RESET
0.6V
0V
Example when VCC = 3.3V
Fig.VB-1 Example reset circuit
XIN
More than 20 cycles are needed
RESET
BCLK
24cycles
Internal
clock Φ
Single chip
mode
Address
FFFFE16
Fig.VB-2 Reset sequence
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Content of reset vector
FFFFC16
page 16 of 266
M16C/6KA Group
RESET
____________
Table VB-1 shows the statuses of the other pins while the RESET pin level is “L”. Fig.VB-3 and VB-4 show
the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table VB-1 Pin status when RESET pin level is “L”
Status
Pin name
CNVSS = VSS
(M0)
P0
I/O port (floating)
P1
I/O port (floating)
P2, P3, P40 to P43
I/O port (floating)
P44
I/O port (floating)
P45 to P47
I/O port (floating)
P50
I/O port (floating)
P51
I/O port (floating)
P52
I/O port (floating)
P53
I/O port (floating)
P54
I/O port (floating)
P55
I/O port (floating)
P56
I/O port (floating)
P57
I/O port (floating)
P6, P7, P80 to P84,
P86, P87, P9, P10
I/O port (floating)
P11, P12, P13, P14
I/O port (floating)
P15, P16
I/O port (floating)
Rev.1.00 Jul 16, 2004
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RESET
0016
(26) Timer B5 interrupt control register
(005416)···
? 0 0 0
(27) OBE interrupt control register
(005516)···
? 0 0 0
(000616)··· 0 1 0 0 1 0 0 0
(28) PS20 interrupt control register
(005616)···
? 0 0 0
(000716)··· 0 0 1 0 0 0 0 0
(29) PS21 interrupt control register
(005716)···
? 0 0 0
0 0
(30) PS22 interrupt control register
(1) Processor mode register 0
(000416)···
(2) Processor mode register 1
(000516)··· 0 0 0 0 0
(3) System clock control register 0
(4) System clock control register 1
(5) Address match interrupt enable register
(000916)···
0
0 0 0
(6) Protect register
(000A16)···
(7) Watchdog timer control register
(000F16)··· 0 0 0 ? ? ? ? ?
(8) Address match interrupt register 0
? 0 0 0
(005B16)···
? 0 0 0
(32) UART1 transmit interrupt control register
(005C16)···
? 0 0 0
(001016)···
0016
(33) Key input 0 interrupt control register
(005F16)···
? 0 0 0
(001116)···
0016
(34) Key input 1 interrupt control register
(006016)···
? 0 0 0
(35) SI/O3 interrupt control register
(006116)···
? 0 0 0
(001216)···
(9) Address match interrupt register 1
(005816)···
(31) UART1 receive interrupt control register
0 0 0 0
(001416)···
0016
(36) SI/O4 interrupt control register
(006216)···
? 0 0 0
(001516)···
0016
(37) I2C0 interrupt control register
(006316)···
? 0 0 0
(001616)···
0 0 0 0
(38) SCL0, SDA0 interrupt control register
(006416)···
? 0 0 0
(006516)···
? 0 0 0
? 0 0 0
(10) LRESET interrupt control register
(004116)···
? 0 0 0
(39) I2C1 interrupt control register
(11) A-D interrupt control register
(004416)···
? 0 0 0
(40) SCL1, SDA1 interrupt control register
(006616)···
(12) IBF0 interrupt control register
(004516)···
? 0 0 0
(41) I2C2 interrupt control register
(006716)···
? 0 0 0
(13) IBF1 interrupt control register
(004616)···
? 0 0 0
(42) SCL2, SDA2 interrupt control register
(006816)···
? 0 0 0
(14) IBF2 interrupt control register
(004716)···
? 0 0 0
(43) INT0 interrupt control register
(006916)···
0 0 ? 0 0 0
(15) IBF3 interrupt control register
(004816)···
? 0 0 0
(44) INT1 interrupt control register
(006A16)···
0 0 ? 0 0 0
(16) Timer A0 interrupt control register
(004A16)···
? 0 0 0
(45) INT2 interrupt control register
(006B16)···
0 0 ? 0 0 0
(17) Timer A1 interrupt control register
(004B16)···
? 0 0 0
(46) INT3 interrupt control register
(006C16)···
0 0 ? 0 0 0
(18) Timer A2 interrupt control register
(004C16)···
? 0 0 0
(47) INT4 interrupt control register
(006D16)···
0 0 ? 0 0 0
(19) Timer A3 interrupt control register
(004D16)···
? 0 0 0
(48) INT5 interrupt control register
(006E16)···
0 0 ? 0 0 0
(20) Timer A4 interrupt control register
(004E16)···
? 0 0 0
(49) INT6 interrupt control register
(006F16)···
0 0 ? 0 0 0
(21) Timer B0 interrupt control register
(004F16)···
? 0 0 0
(50) INT7 interrupt control register
(007016)···
0 0 ? 0 0 0
(22) Timer B1 interrupt control register
(005016)···
? 0 0 0
(51) INT8 interrupt control register
(007116)···
0 0 ? 0 0 0
(23) Timer B2 interrupt control register
(005116)···
? 0 0 0
(52) INT9 interrupt control register
(007216)···
0 0 ? 0 0 0
(24) Timer B3 interrupt control register
(005216)···
? 0 0 0
(53) INT10 interrupt control register
(007316)···
0 0 ? 0 0 0
(25) Timer B4 interrupt control register
(005316)···
? 0 0 0
(54) INT11 interrupt control register
(007416)···
0 0 ? 0 0 0
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Fig.VB-3 Device's internal status after a reset is cleared (1)
Rev.1.00 Jul 16, 2004
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page 18 of 266
M16C/6KA Group
RESET
(55) PS20 shift register
(02A016)···
0016
(85) PWM control register 0
(030C16)···
0016
(56) PS20 status register
(02A116)···
0016
(86) PWM control register 1
(030D16)···
0016
(57) PS20 control register
(02A216)···
0016
(87) I2C2 address register
(031216)···
0016
(58) PS21 shift register
(02A416)···
0016
(88)
(031316)···
0016
(59) PS21 status register
(02A516)···
0016
(89) I2C2 clock control register
(031416)···
0016
(60) PS21 control register
I2C2
control register 0
I2C2
(02A616)···
0016
1A16
(02A816)···
0016
start/stop condition
control register
2
(91) I C2 control register 1
(031516)···
(61) PS22 shift register
(031616)···
3016
(62) PS22 status register
(02A916)···
0016
(92) I2C2 control register 2
(031716)···
0016
(90)
I2C2
(63) PS22 control register
(02AA16)···
0016
(93)
(64) PS2 mode register
(02AC16)···
0016
(94) I2C0 address register
(032216)···
0016
(65) Data bus buffer status register 0
(02C116)···
0016
2
(95) I C0 control register 0
(032316)···
0016
I2C0
status register
(66) Data bus buffer status register 1
(02C316)···
0016
(96)
(67) Data bus buffer status register 2
(02C516)···
0016
(68) Data bus buffer status register 3
(02C716)···
0016
(97) I2C0 start/stop condition
control register
(98) I2C0 control register 1
(69) Data bus buffer control register 1
(02C916)···
0016
(99)
(70) GateA20 control register
(02CA16)···
0016
2
(100) I C0 status register
I2C0
I2C1
clock control register
control register 2
(71) Port P11 direction register
(02E216)···
0016
(101)
(72) Port P12 direction register
(02E316)···
0016
(102) I2C1
(02E616)···
0016
(103)
I2C1
(74) Port P14 direction register
(02E716)···
0016
(75) Port P15 direction register
(02EA16)···
0016
(104) I2C1 start/stop condition
control register
(105) I2C1 control register 1
(73) Port P13 direction register
0 0
I2C1
(031816)··· 0 0 1 0 0 0 0
(032416)···
0016
(032516)···
1A16
(032616)···
3016
(032716)···
0016
(032816)··· 0 0 1 0 0 0 0
address register
(033216)···
0016
control register 0
(033316)···
0016
clock control register
(033416)···
0016
(033516)···
1A16
(033616)···
3016
(033716)···
0016
(76) Port P16 direction register
(02EB16)···
(77) Port function selection register 0
(02F816)···
0016
(107) I2C1 status register
(033816)··· 0 0 1 0 0 0 0
(78) Port function selection register 1
(02F916)···
0016
(108) TimerB3,4,5 count start flag
(034016)··· 0 0 0
(79) Port P4 input register
(02FA16)··· 0
(109) TimerB3 mode register
(035B16)··· 0 0 ?
0 0 0 0
(80) Port P7 input register
(02FB16)··· 0 0
(110) TimerB4 mode register
(035C16)··· 0 0 ?
0 0 0 0
(81) Pull-up control register 3
0 0 0 0
(106)
control register 2
(02FC16)···
0016
(111) TimerB5 mode register
(035D16)··· 0 0 ?
(82) Pull-up control register 4
(02FD16)···
0016
(112) Interrupt factor selection register 1
(035E16)···
0016
(83) Port control register 1
(02FE16)···
0016
(113) Interrupt factor selection register 0
(035F16)···
0016
(84) Port control register 2
(02FF16)···
0016
(114) SI/O3 control register
(036216)···
4016
(115) SI/O4 control register
(036616)···
4016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Fig.VB-4 Device's internal status after a reset is cleared (2)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 19 of 266
M16C/6KA Group
RESET
(116) Count start flag
(038016)···
0016
(138) Port P0 direction register
(03E216)···
0016
(03E316)···
0016
(117) One-shot start flag
(038216)··· 0 0
0 0 0 0 0
(139) Port P1 direction register
(118) Trigger select flag
(038316)···
0016
(140) Port P2 direction register
(03E616)···
0016
(119) Up-down flag
(038416)···
0016
(141) Port P3 direction register
(03E716)···
0016
(120) Timer A0 mode register
(039616)···
0016
(142) Port P4 direction register
(03EA16)···
0016
(121) Timer A1 mode register
(039716)···
0016
(143) Port P5 direction register
(03EB16)···
0016
0016
(039816)···
0016
(144) Port P6 direction register
(03EE16)···
(123) Timer A3 mode register
(039916)···
0016
(145) Port P7 direction register
(03EF16)···
0016
(124) Timer A4 mode register
(039A16)···
0016
(146) Port P8 direction register
(03F216)··· 0 0
0 0 0 0 0
0016
(122) Timer A2 mode register
(125) Timer B0 mode register
(039B16)··· 0 0 ?
0 0 0 0
(147) Port P9 direction register
(03F316)···
(126) Timer B1 mode register
(039C16)··· 0 0 ?
0 0 0 0
(148) Port P10 direction register
(03F616)···
0016
(127) Timer B2 mode register
(039D16)··· 0 0 ?
0 0 0 0
(149) Pull-up control register 0
(03FC16)···
0016
(128) UART1 transmit/receive mode register
(03A816)···
(150) Pull-up control register 1
(03FD16)···
0016
(129) UART1 transmit/receive control register 0
(03AC16)··· 0 0 0 0 1 0 0 0
(151) Pull-up control register 2
(03FE16)···
0016
(03AD16)··· 0 0 0 0 0 0 1 0
(152) Port control register 0
(03FF16)···
(130) UART1 transmit/receive control register 1
0016
0016
(153) Data registers (R0/R1/R2/R3)
000016
(131) UART transmit/receive control register 2
(03B016)···
0 0 0 0 0 0 0
(132) Flash memory recognition register (Note1)
(03B416)···
1 1
(154) Address registers (A0/A1)
000016
0
(155) Frame base register (FB)
000016
(133) Flash memory control register1 (Note1)
(03B516)··· 0 0 0
(134) Flash memory control register0 (Note1)
(03B716)··· 0 0 0 0 0 0 0 1
(156) Interrupt table register (INTB)
0000016
(135) A-D control register 2
(03D416)··· 0 0 0 1 0 0 0 0
(157) User stack pointer (USP)
000016
(136) A-D control register 0
(03D616)··· 0 0 0 0 0 ? ? ?
(158) Interrupt stack pointer (ISP)
000016
(137) A-D control register 1
(03D716)···
(159) Static base register (SB)
000016
(160) Flag register (FLG)
000016
0016
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
(Note1) This register exists only in the flash memory version.
Fig.VB-5 Device's internal status after a reset is cleared (3)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 20 of 266
M16C/6KA Group
RESET
(161) Serial interrupt control register 0
(02B016)···
0016
(162) Serial interrupt control register 1
(02B116)···
0016
(163) IRQ request register 0
(02B216)···
0016
(164) IRQ request register 1
(02B316)···
0016
(165) IRQ request register 2
(02B416)···
0016
(166) IRQ request register 3
(02B516)···
0016
(167) IRQ request register 4
(02B616)···
0016
(168) Serial interrupt control register 2
(02B716)···
1016
(169) LPC1 address register L
(02D016)···
0016
(170) LPC1 address register H
(02D116)···
0016
(171) LPC2 address register L
(02D216)···
0016
(172) LPC2 address register H
(02D316)···
0016
(173) LPC3 address register L
(02D416)···
0016
(174) LPC3 address register H
(02D516)···
0016
(175) LPC control register
(02D616)···
0016
(176) Port function selection register 2
(02F116)···
0016
(177) Pull-up resistor control register 5
(02F216)···
0016
(178) Pull-up resistor control register 6
(02F316)···
0016
(179) Key input interrupt 1 enable register
(02F416)···
0016
(180) Key input interrupt 1 edge selection register
(02F516)···
0016
(181) P14 event register
(02F616)···
0016
(182) Port control register 3
(02F716)···
0016
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must
therefore be set.
Fig.VB-6 Device's internal status after a reset is cleared (4)
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
SFR
000016
004016
000116
004116
000216
004216
004316
000316
000416
000516
000616
000716
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
000A16
004416
004516
004616
004716
004816
000816
000916
Address match interrupt enable register (AIER)
Protect register (PRCR)
004A16
004B16
000C16
004C16
004D16
000D16
000F16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
001116
004E16
004F16
005016
001016
Address match interrupt register 0 (RMAD0)
005116
001216
005216
001316
005316
005416
001416
001516
Address match interrupt register 1 (RMAD1)
A-D interrupt control register (A-DIC)
IBF0 interrupt control register (IBF0IC)
IBF1 interrupt control register (IBF1IC)
IBF2 interrupt control register (IBF2IC)
IBF3 interrupt control register (IBF3IC)
004916
000B16
000E16
LRESET interrupt control register (LRSTIC)
005516
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
Timer B3 interrupt control register (TB3IC)
Timer B4 interrupt control register (TB4IC)
Timer B5 interrupt control register (TB5IC)
OBE interrupt control register (OBEIC)
PS20 interrupt control register (PS20IC)
PS21 interrupt control register (PS21IC)
PS22 interrupt control register (PS22IC)
001616
005616
001716
005716
001816
005816
001916
005916
001A16
005A16
001B16
005B16
001C16
005C16
001D16
005D16
001E16
005E16
001F16
005F16
002016
006016
002116
006116
002216
006216
002316
006316
Key input interrupt 0 control register (KUP0IC)
Key input interrupt 1 control register (KUP1IC)
SI/O3 interrupt control register (S3IC)
SI/O4 interrupt control register (S4IC)
I2C0 interrupt control register (IIC0IC)
002416
006416
SCL0,SDA0 interrupt control register (SCLDA0IC)
002516
006516
I2C1 interrupt control register (IIC1IC)
002616
006616
SCL1,SDA1 interrupt control register (SCLDA1IC)
002716
006716
I2C2 interrupt control register (IIC2IC)
002816
006816
SCL2,SDA2 interrupt control register (SCLDA2IC)
002916
006916
002A16
006A16
002B16
006B16
002C16
006C16
002D16
006D16
002E16
006E16
002F16
006F16
003016
007016
003116
007116
003216
007216
003316
007316
003416
007416
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
INT3 interrupt control register (INT3IC)
INT4 interrupt control register (INT4IC)
INT5 interrupt control register (INT5IC)
INT6 interrupt control register (INT6IC)
INT7 interrupt control register (INT7IC)
INT8 interrupt control register (INT8IC)
INT9 interrupt control register (INT9IC)
INT10 interrupt control register (INT10IC)
INT11 interrupt control register (INT11IC)
UART1 receive interrupt control register (S1RIC)
UART1 transmit interrupt control register (S1TIC)
003516
003616
003716
027E16
003816
027F16
003916
003A16
003B16
003C16
003D16
003E16
003F16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-2 Location of peripheral unit control registers (1)
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M16C/6KA Group
SFR
028016
02C016
028116
02C116
028216
02C216
028316
02C316
028416
02C416
028516
02C516
028616
02C616
028716
02C716
028816
02C816
028916
02C916
028A16
02CA16
028B16
02CB16
028C16
02CC16
028D16
02CD16
028E16
02CE16
028F16
02CF16
029016
02D016
029116
02D116
029216
02D216
029316
02D316
029416
02D416
029516
02D516
029616
02D616
029716
02D716
029816
02D816
029916
02D916
029A16
02DA16
029B16
02DB16
029C16
02DC16
029D16
02DD16
029E16
02DE16
02A116
02A216
PS20 shift register (PS20SR)
PS20 status register (PS20STS)
PS20 control register (PS20CON)
02A516
02A616
PS21 shift register (PS21SR)
PS21 status register (PS21STS)
PS21 control register (PS21CON)
02A916
02AA16
PS22 shift register (PS22SR)
PS22 status register (PS22STS)
PS22 control register (PS22CON)
02E216
02E416
02E516
02E616
02E816
02E916
02EA16
02EB16
02AB16
02AC16
02E116
02E716
02A716
02A816
02E016
02E316
02A316
02A416
PS2 mode register (PS2MOD)
02ED16
02AE16
02EE16
02B216
02B316
02B416
02B516
02B616
02B716
Port P11 (P11)
Port P12 (P12)
Port P11 direction register (PD11)
Port P12 direction register (PD12)
Port P13 (P13)
Port P14 (P14)
Port P13 direction register (PD13)
Port P14 direction register (PD14)
Port P15 (P15)
Port P16 (P16)
Port P15 direction register (PD15)
Port P16 direction register (PD16)
02EF16
02AF16
02B116
LPC1 address registerL (LPC1ADL)
LPC1 address registerH (LPC1ADH)
LPC2 address registerL (LPC2ADL)
LPC2 address registerH (LPC2ADH)
LPC3 address registerL (LPC3ADL)
LPC3 address registerH (LPC3ADH)
LPC control register (LPCCON)
02EC16
02AD16
02B016
Data bus buffer control register1 (DBBCON1)
Gate A20 control register (GA20CON)
02DF16
029F16
02A016
Data bus buffer register0 (DBB0)
Data bus buffer status register0 (DBBSTS0)
Data bus buffer register1 (DBB1)
Data bus buffer status register1 (DBBSTS1)
Data bus buffer register2 (DBB2)
Data bus buffer status register2 (DBBSTS2)
Data bus buffer register3 (DBB3)
Data bus buffer status register3 (DBBSTS3)
Serial Interrupt control register 0 (SERCON0)
Serial Interrupt control register 1 (SERCON1)
IRQ request register 0 (IRQ0)
IRQ request register 1 (IRQ1)
IRQ request register 2 (IRQ2)
IRQ request register 3 (IRQ3)
IRQ request register 4 (IRQ4)
Serial Interrupt control register 2 (SERCON2)
02F016
02F416
Port function selection register 2 (PSL2)
Pull-up resistor control register 5 (PUR5)
Pull-up resistor control register 6 (PUR6)
Key input interrupt 1 enable register (KIN1EN)
02F516
Key input interrupt 1 edge selection regiter (KINSEL)
02F616
P14 event register (P14EV)
Port control register3 (PCR3)
Port function selection register0 (PSL0)
Port function selection register1 (PSL1)
Port P4 input register (P4PIN)
Port P7 input register (P7PIN)
Pull-up control register3 (PUR3)
Pull-up control register4 (PUR4)
Port control register1 (PCR1)
Port control register2 (PCR2)
02F116
02F216
02F316
02F716
02B816
02F816
02B916
02F916
02BA16
02FA16
02BB16
02FB16
02BC16
02FC16
02BD16
02FD16
02BE16
02FE16
02BF16
02FF16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-3 Location of peripheral unit control registers (2)
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M16C/6KA Group
030016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
SFR
PWM0 prescaler (PREPWM0)
PWM0 register (PWM0)
PWM1 prescaler (PREPWM1)
PWM1 register (PWM1)
PWM2 prescaler (PREPWM2)
PWM2 register (PWM2)
PWM3 prescaler (PREPWM3)
PWM3 register (PWM3)
PWM4 prescaler (PREPWM4)
PWM4 register (PWM4)
PWM5 prescaler (PREPWM5)
PWM5 register (PWM5)
PWM control register 0 (PWMCON0)
PWM control register 1 (PWMCON1)
I2C2 data shift register (S02)
031416
031516
031616
031716
031816
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
035016
035116
031116
031316
034216
034F16
030F16
031216
2C2
address register (S0D2)
I
I2C2 control register 0 (S1D2)
I2C2 clock control register (S22)
I2C2 start/stop condition control register (S2D2)
I2C2 control register 1 (S3D2)
I2C2 control register 2 (S4D2)
I2C2 status register (S12)
035216
035316
035416
035516
035A16
031B16
035B16
031C16
035C16
031D16
035D16
031E16
035E16
035F16
032316
032416
032516
032616
032716
032816
036016
I2C0 address register (S0D0)
I2C0 control register0 (S1D0)
I2C0 clock control register (S20)
I2C0 start/stop condition control register (S2D0)
I2C0 control register1 (S3D0)
I2C0 control register2 (S4D0)
I2C0 status register (S10)
036216
036316
036416
036616
036716
036916
036A16
032B16
036B16
032C16
036C16
032D16
036D16
032E16
036E16
036F16
032F16
I2C1 data shift register (S01)
033416
033516
033616
033716
033816
037016
037116
033116
033316
SI/O4 control register (S4C)
SI/O4 communication speed register (S4BRG)
036816
032A16
033216
SI/O3 control register (S3C)
SI/O3 communication speed register (S3BRG)
SI/O4 transmit/receive register (S4TRR)
036516
032916
033016
TimerB3 mode register (TB3MR)
TimerB4 mode register (TB4MR)
TimerB5 mode register (TB5MR)
Interrupt event select register 1 (IFSR1)
Interrupt event select register 0 (IFSR0)
SI/O3 transmit/receive register (S3TRR)
036116
032116
032216
TimerB5 register (TB5)
035816
035916
I2C0 data shift register (S00)
TimerB4 register (TB4)
035716
031A16
031F16
TimerB3 register (TB3)
035616
031916
032016
TimerB3,4,5 count start flag (TBSR)
034116
034E16
030E16
031016
034016
I2C1 address register (S0D1)
I2C1 control register0 (S1D1)
I2C1 clock control register (S21)
I2C1 start/stop condition control register (S2D1)
I2C1 control register1 (S3D1)
I2C1 control register2 (S4D1)
I2C1 status register (S11)
037216
037316
037416
037516
037616
037716
037816
033916
037916
033A16
037A16
033B16
037B16
033C16
037C16
033D16
037D16
033E16
037E16
033F16
037F16
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-4 Location of peripheral unit control registers (3)
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M16C/6KA Group
038016
SFR
Count start flag (TABSR)
038216
038316
038416
03C016
03C116
038116
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
03C216
03C316
03C416
038516
03C516
038616
TimerA0 (TA0)
03C616
TimerA1 (TA1)
03C816
TimerA2 (TA2)
03CA16
03C716
038716
038816
038916
038A16
038B16
03C916
03CB16
TimerA3 (TA3)
03CC16
038D16
03CD16
038E16
TimerA4 (TA4)
03CE16
TimerB0 (TB0)
03D016
TimerB1 (TB1)
03D216
TimerB2 (TB2)
03D416
TimerA0 mode register (TA0MR)
TimerA1 mode register (TA1MR)
TimerA2 mode register (TA2MR)
TimerA3 mode register (TA3MR)
TimerA4 mode register (TA4MR)
TimerB0 mode register (TB0MR)
TimerB1 mode register (TB1MR)
TimerB2 mode register (TB2MR)
03D616
038C16
03CF16
038F16
039016
039116
039216
039716
039816
039916
039A16
039B16
039C16
039D16
03D716
03E116
03A216
03E216
03A316
03E316
03A416
03E416
03A516
03E516
03A616
03E616
03E716
03A716
03AF16
03B016
UART1 transmit/receive mode register (U1MR)
UART1 communication speed register (U1BRG)
UART1 tranmit buffer register (U1TB)
UART1 transmit/receive control register0 (U1C0)
UART1 transmit/receive control register1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register2 (UCON)
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03B116
03F116
03B216
03F216
03F316
03B316
03B416
03B516
Flash memory identification register (FTR)
Flash memory control register1 (FMR1)
03B716
03F416
Flash memory control register0 (FMR0)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (P0D)
Port P1 direction register (P1D)
Port P2 (P2)
Port P3 (P3)
Port P2 direction register (P2D)
Port P3 direction register (P3D)
Port P4 (P4)
Port P5 (P5)
Port P4 direction register (P4D)
Port P5 direction register (P5D)
Port P6 (P6)
Port P7 (P7)
Port P6 direction register (P6D)
Port P7 direction register (P7D)
Port P8 (P8)
Port P9 (P9)
Port P8 direction register (P8D)
Port P9 direction register (P9D)
Port P10 (P10)
03F516
03F616
03B616
A-D control register0 (ADCON0)
A-D control register1 (ADCON1)
03DD16
03E016
03AE16
A-D control register2 (ADCON2)
03DC16
03A116
03AD16
A-D register7 (AD7)
03DB16
03DF16
03AC16
A-D register6 (AD6)
03DA16
03A016
03AB16
A-D register5 (AD5)
03D916
03DE16
03AA16
A-D register4 (AD4)
03D816
039F16
03A916
A-D register3 (AD3)
03D516
039E16
03A816
A-D register2 (AD2)
03D316
039516
039616
A-D register1 (AD1)
03D116
039316
039416
A-D register0 (AD0)
Port P10 direction register (P10D)
03F716
03B816
03F816
03B916
03F916
03BA16
03FA16
03BB16
03FB16
03BC16
03FC16
03BD16
03FD16
03BE16
03FE16
03BF16
03FF16
Pull-up control register0 (PUR0)
Pull-up control register1 (PUR1)
Pull-up control register2 (PUR2)
Port control register0 (PCR0)
Note 1: The areas that nothing are allocated in SFR are reserved. Read and Write to the areas are inhibited.
Fig.CA-5 Location of peripheral unit control registers (4)
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REJ03B0100-0100Z
page 25 of 266
Software Reset
M16C/6KA Group
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are retained.
Processor Mode
(1) Types of Processor Mode
The single-chip mode is supported in processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed.
Ports P0 to P16 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions.
Fig. BG-1 shows the structure of processor mode register 0 and processor mode register 1.
Processor mode register 0 (Note 1)
b7
b6
b5
b4
b3
0 0 0 0
b2
b1
Symbol
PM0
b0
0
Address
000416
Bit symbol
PM00
Bit name
Processor mode bit
PM01
Reserved bit
PM03
When reset
0016 (Note 2)
Function
b1 b0
0 0: Single-chip mode
0 1: Inhibited
1 0: Inhibited
1 1: Inhibited
Must always be set to “0”
Software reset bit
Reserved bit
AA
AA
A
AA
A
R W
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
Must always be set to “0”
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note 1)
b7
b6
b5
b4
0 0 0
b3
0
b2
b1
Symbol
PM1
b0
0
Address
000516
Bit symbol
Bit name
When reset
00000XX02
Function
Must always be set to “0”
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out
to be indeterminate.
Must always be set to “0”
Reserved bit
PM17
Wait bit
0 : No wait state
1 : Wait state inserted
A
A
AA
A
AA
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Fig.BG-1 Processor mode register 0 and 1
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R W
Bus control
M16C/6KA Group
Bus control
(1) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) .
A software wait is inserted in the internal ROM/RAM area by setting the wait bit of the processor mode
register 1. When set to “0”, each bus cycle is executed in one BCLK cycle. When set to “1”, each bus cycle
is executed in 2 BCLK cycles. After the microcomputer has been reset, this bit defaults to “0”.
Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency)
of the electric characteristics.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Table.EF-1 shows the software wait and bus cycles. Fig.EF-1 shows example bus timing when using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table.EF-1 Software waits and bus cycles
Bus cycle
Area
Wait bit
SFR
Invalid
2 BCLK cycles
0
1 BCLK cycle
1
2 BCLK cycles
Internal
ROM/RAM
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Bus control
M16C/6KA Group
No wait
Bus cycle
Bus cycle
(Note 1)
(Note 1)
BCLK
Write signal
Read signal
Output
Data bus
Address bus
Address
Input
Address
Chip select
With wait
Bus cycle
Bus cycle
(Note 1)
(Note 1)
BCLK
Write signal
Read signal
Data bus
Address bus
Input
Output
Address
Address
Chip select
Note 1: This timing sample shows the lenth of bus cycle. It is possible that the read cyles, write cycle
comes after this cycle in succession.
Fig.EF-1 Typical bus timings using software wait
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M16C/6KA Group
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table.WA-1 Main clock generating circuits
Use of clock
Usable oscillator
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Main clock generating circuit
• CPU’s operating clock source
• Internal peripheral units’
operating clock source
Ceramic oscillator
XIN, XOUT
Available
Oscillating
Externally derived clock can be input
Example of oscillator circuit
Fig.WA-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Circuit constants in Fig.WA-1 vary with oscillator used. Use the values recommended by the manufacturer of your oscillator.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
COUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Apply the feedback register between XIN and XOUT if required by oscillator maker.
Fig.WA-1 Examples of main clock
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M16C/6KA Group
Clock Generating Circuit
Clock Control
Fig.WA-2 shows the block diagram of the clock generating circuit.
f1
f1SIO2
fAD
f8
f8SIO2
f32SIO2
CM10 “1”
Write signal
f32
S Q
AAAA
AAAA
XOUT
XIN
b
R
a
RESET
Software reset
Main clock
CM02
NMI
Interrupt request
level judgment
output
c
d
Divider
BCLK
S Q
WAIT instruction
R
c
b
a
1/2
1/2
1/2
1/2
1/2
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
Fig.WA-2 Clock generating circuit
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Details of divider
M16C/6KA Group
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616).
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit defaults to “1” when shifting from high speed mode or mid-speed mode to stop mode and after a reset.
(2) BCLK
The BCLK is the clock that drives the CPU, and is either the main clock or is derived by dividing the main
clock by 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
When shifting from high speed mode or mid-speed mode to stop mode, the main clock division select bit (bit
6 at 000616) is set to “1”.
(3) Peripheral function clock
f1, f8, f32, f1SIO2, f8SIO2, f32SIO2, fAD
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral
function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit
(bit 2 at 000616) to “1” and then executing a WAIT instruction.
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M16C/6KA Group
Clock Generating Circuit
Fig.WA-3 shows the system clock control registers 0 and 1.
System clock control register 0
b7
b6
0
b5
b4
b3
0
0
1
b2
b1
(Note 1)
b0
Symbol
CM0
Address
000616
Bit symbol
Bit name
Function
Clock output function
select bit
WAIT peripheral function
clock stop bit
0 :Do not stop peripheral clock in wait mode
1 :Stop peripheral clock in wait mode
CM01
0 0 : I/O port P57
0 1 : Inhibited
1 0 : f8 output
1 1 : f32 output
Reserved bit
Always set to “1”
Reserved bit
Always set to “0”
CM06
Main clock division select
bit 0 (Note 2)
Reserved bit
0 : CM16 and CM17 valid
1 : Division by 8 mode
Always set to “0”
A
A
A
A
A
A
A
A
A
RW
b1 b0
CM00
CM02
When reset
4816
Note 1 : Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2 : The bit is set to "1" when shifting from high speed mode or mid speed mode to stop mode and
after reset.
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0
0
0
0
b0
Symbol
CM1
Address
000716
Bit symbol
CM10
When reset
2016
Bit name
All clock stop control bit
(Note 4)
Function
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
Reserved bit
Always set to “0”
CM15
CM16
XIN-XOUT drive capacity
select bit (Note 2)
Main clock division
select bit 1 (Note 3)
CM17
0 : LOW
1 : HIGH
b7 b6
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
RW
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: The bit is set to "1" when shifting from high speed mode or mid speed mode to stop mode and
after reset.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0".
If "1", division mode is fixed at 8.
Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor turns null.
Fig.WA-3 System clock control registers 0 and 1
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M16C/6KA Group
Clock Generating Circuit
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32 to be
output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address 000616)
is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
By setting the f1 output function selection bits (bits 0 and 1 at address 02F116), the same frequency clock
with f(XIN) can be output from P110 and P111.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains
above 2V.
The oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, and fAD stop in stop mode, peripheral functions such as the
A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the
event counter mode is set to an external pulse, and UART1, SIO3,4 functions provided an external clock is
selected. Table.WA-2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or interrupt. If an interrupt is to be used to cancel stop mode, that
interrupt must first have been enabled. After the restoration by interrupt, the corresponding interrupt routine
will be processed. When shifting from high speed mode or mid-speed mode to stop mode, the main clock
division select bit 0 (bit 6 at 000616) is set to “1”.
Table.WA-2 Port status during stop mode
Pin
Port
CLKOUT
When f8, f32 selected
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Single-chip mode
Retains status before stop mode
Retains status before stop mode
M16C/6KA Group
Wait Mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. Table.WA-3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table.WA-3 Port status during wait mode
Pin
Single-chip mode
CLKOUT
When f8, f32 selected Does not stop when the WAIT peripheral function clock stop
bit is “0”.
When the WAIT peripheral function clock stop bit is “1”, the
status immediately prior to entering wait mode is maintained.
maintained the status immediately prior to entering wait mode
Port
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M16C/6KA Group
Status Transition Of BCLK
Status Transition Of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table.WA-4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1.
After a reset, operation defaults to division by 8 mode. When shifting from high speed mode or mid-speed
mode to stop mode, and after a reset main clock division select bit 0 (bit 6 at address 000616) is set to “1”.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. After reset, it works in this mode. Note that oscillation of
the main clock must have stabilized before transferring from this mode to No-division, Division by 2 and
Division by 4 mode.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is used as the BCLK.
Table.WA-4 Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM06
Operating mode of BCLK
0
1
Invalid
1
0
1
0
Invalid
1
0
0
0
1
0
0
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
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M16C/6KA Group
Power control
Power control
The following is a description of the power control modes:
Modes
Power control is available in three modes.
(1) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock
selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The
CPU operates according to the internal clock selected. Each peripheral function operates according to its
assigned clock.
(2) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(3) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes
listed here, is the most effective in decreasing power consumption.
Fig.WA-4 is the state transition diagram of (1) to (3).
Transition of stop mode, wait mode
Reset
All oscillators stop
Stop mode
Interrupt
All oscillators stop
WAIT
command
CM10 = “1”
Medium-speed mode
(Divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
CM10 = “1”
WAIT
command
High-speed/mediumspeed mode
Normal mode
Fig.WA-4 State transition diagram of Power control mode
page 36 of 266
CPU operation stop
Wait mode
Interrupt
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CPU operation stop
M16C/6KA Group
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Fig.WA-5 shows the protect register. The values in the processor mode
register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0
(address 000616), system clock control register 1 (address 000716), can only be changed when the respective bit in the protect register is set to “1”.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
PRCR
Address
000A16
Bit symbol
Bit name
When reset
XXXXX0002
Function
PRC0
Enables writing to system clock
0 : Write-inhibited
control registers 0 and 1 (addresses
1 : Write-enabled
000616 and 000716)
PRC1
Enables writing to processor mode
0 : Write-inhibited
registers 0 and 1 (addresses 000416
1 : Write-enabled
and 000516)
Reserved bit
Must be "0"
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Fig.WA-5 Protect register
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AAA
AAA
AAA
R W
M16C/6KA Group
Interrupt
Overview of Interrupt
Type of Interrupts
Fig.DD-1 lists the types of interrupts.
Hardware
Special
Peripheral I/O (Note)
Interrupt
Software
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Reset
NMI
________
DBC
Watchdog timer
Single step
Address matched
_______
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Fig.DD-1 Classification of interrupts
• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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M16C/6KA Group
Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”.
The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the
INT instruction. Software interrupt numbers 0 through 52 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer
assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the
interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt
routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as
software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
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M16C/6KA Group
Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______
_______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D
flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by the
address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set, no
address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are
dependent on classes of products, so the interrupt factors are also dependent on classes of products. The
interrupt vector table is the same as the one for software interrupt numbers 0 through 52 the INT instruction
uses. Peripheral I/O interrupts are maskable interrupts.
1)Key-input interrupt 0
___
A key-input interrupt occurs if an “L” is input to the KI pin.
2)Key-input interrupt 1
___
A key-input interrupt occurs if an “L” or “H” is input to the KI pin.
3)A-D conversion interrupt
This is an interrupt that the A-D converter generates.
4)UART1, SI/O3 and SI/O4 transmission interrupt
These are interrupts that the serial I/O transmission generates.
5)UART1, SI/O3 and SI/O4 reception interrupt
These are interrupts that the serial I/O reception generates.
6)Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
7)Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
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M16C/6KA Group
________
Interrupt
__________
8)INT0 interrupt through INT11 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge or both edges are input to the INT pin.
9)IBF0 to IBF3, OBE interrupt
These are interrupts that host bus interface generates.
______________
10) LRESET interrupt
______________
______________
LRESET interrupt occurs if an “L” is input to LRESET pin.
11)I2C0, I2C1, I2C2, SCL0, SDA0, SCL1, SDA1, SCL2, SDA2 interrupt
These are interrupts that I2C bus interface generates.
12)PS20 to PS22 interrupt
These are interrupt that PS2 interface generates.
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M16C/6KA Group
Interrupt
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Fig.DD-2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
AAAAAAAA
LSB
MSB
Vector address + 0
Low address
Mid address
Vector address + 1
Vector address + 2
0000
High address
0000
0000
Fig.DD-2 Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table.DD-1 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
Table.DD-1 Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Undefined instruction
Overflow
BRK instruction
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
Single step (Note)
FFFEC16 to FFFEF16
Watchdog timer
FFFF016 to FFFF316
________
DBC (Note)
FFFF416 to FFFF716
Do not use
_______
_______
NMI
FFFF816 to FFFFB16
External interrupt by input to NMI pin
Reset
FFFFC16 to FFFFF16
Note: Interrupts used for debugging purposes only.
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M16C/6KA Group
Interrupt
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. The start
address of vector table is set to the interrupt table register (INTB). The 256-byte area subsequent that the
start address is indicated by the INTB becomes the area for the variable vector tables. One vector table
comprises 4 bytes. Set the first address of the interrupt routine in each vector table. Table.DD-2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
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M16C/6KA Group
Interrupt
Table.DD-2 Interrupts assigned to the variable vector tables and addresses of vector
Software interrupt number
Vector table address
Interrupt source
Address (L) to address (H)
Software interrupt number 0
+0 to +3 (Note 1)
BRK instruction
Software interrupt number 1
+4 to +7 (Note 1)
LRESET
Software interrupt number 4
+16 to +19 (Note 1)
A-D
Software interrupt number 5
+20 to +23 (Note 1)
IBF0
Software interrupt number 6
+24 to +27 (Note 1)
IBF1
Software interrupt number 7
+28 to +31 (Note 1)
IBF2
Software interrupt number 8
+32 to +35 (Note 1)
IBF3
Software interrupt number 10
+40 to +43 (Note 1)
Timer A0
Software interrupt number 11
+44 to +47 (Note 1)
Timer A1
Software interrupt number 12
+48 to +51 (Note 1)
Timer A2
Software interrupt number 13
+52 to +55 (Note 1)
Timer A3
Software interrupt number 14
+56 to +59 (Note 1)
Timer A4
Software interrupt number 15
+60 to +63 (Note 1)
Timer B0
Software interrupt number 16
+64 to +67 (Note 1)
Timer B1
Software interrupt number 17
+68 to +71 (Note 1)
Timer B2
Software interrupt number 18
+72 to +75 (Note 1)
Timer B3
Software interrupt number 19
+76 to +79 (Note 1)
Timer B4
Software interrupt number 20
+80 to +83 (Note 1)
Timer B5
Software interrupt number 21
+84 to +87 (Note 1)
OBE
Software interrupt number 22
+88 to +91 (Note 1)
PS20
Software interrupt number 23
+92 to +95 (Note 1)
PS21
Software interrupt number 24
+96 to +99 (Note 1)
PS22
Software interrupt number 27
+108 to +111 (Note 1)
UART1 receive
Software interrupt number 28
+112 to +115 (Note 1)
UART1 transmit
Software interrupt number 31
+124 to +127 (Note 1)
Key input interrupt 0
Note 1: Address relative to address in interrupt table register (INTB).
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Remarks
Cannot be masked by I flag
M16C/6KA Group
Interrupt
Table.DD-3 Interrupts assigned to the variable vector tables and addresses of vector
Software interrupt number
Vector table address
Interrupt source
Address (L) to address (H)
Software interrupt number 32
+128 to +131(Note 1)
Key input interrupt 1
Software interrupt number 33
+132 to +135 (Note 1)
SIO3
Software interrupt number 34
+136 to +139 (Note 1)
SIO4
Software interrupt number 35
+140to +143 (Note 1)
I2C0
Software interrupt number 36
+144 to +149 (Note 1)
SCL0, SDA0
Software interrupt number 37
+148 to +151 (Note 1)
I2C1
Software interrupt number 38
+152 to +155 (Note 1)
SCL1, SDA1
Software interrupt number 39
+156 to +159 (Note 1)
I2C2
Software interrupt number 40
+160 to +163(Note 1)
SCL2, SDA2
Software interrupt number 41
+164 to +167 (Note 1)
INT0
Software interrupt number 42
+168 to +171 (Note 1)
INT1
Software interrupt number 43
+172 to +175 (Note 1)
INT2
Software interrupt number 44
+176 to +179 (Note 1)
INT3
Software interrupt number 45
+180 to +183(Note 1)
INT4
Software interrupt number 46
+184 to +187 (Note 1)
INT5
Software interrupt number 47
+188 to +191 (Note 1)
INT6
Software interrupt number 48
+192 to +195 (Note 1)
INT7
Software interrupt number 49
+196 to +199 (Note 1)
INT8
Software interrupt number 50
+200 to +203 (Note 1)
INT9
Software interrupt number 51
+204 to +207 (Note 1)
INT10
Software interrupt number 52
+208 to +211 (Note 1)
INT11
Software interrupt number 53
+212 to +215 (Note 1)
to
Software interrupt number 63
to
+252 to +255 (Note 1)
Software interrupt
Note 1: Address relative to address in interrupt table register (INTB).
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Remarks
Cannot be masked by I flag
M16C/6KA Group
Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection
bits and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated
by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bits are located
in the interrupt control register of each interrupt. The interrupt enable flag (I flag) and the IPL are located in
the flag register (FLG).
Fig.DD-3 and DD-4 shows the memory map of the interrupt control registers.
Interrupt control register
AAA
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
LRSTIC
ADIC
IBFiIC(i=0 to 3)
TAiIC(i=0 to 4)
TBiIC(i=0 to 5)
OBEIC
PS2iIC(i=0 to 2)
S1RIC
S1TIC
KUPiIC(i=0,1)
SiIC(i=3,4)
IICiIC(i=0 to 2)
SCLDAiIC(i=0 to 2)
Bit symbol
ILVL0
Address
004116
004416
004516 to 004816
004A16 to 004E16
004F16 to 005416
005516
005616 to 005816
005B16
005C16
005F16,006016
006116,006216
006316,006516,006716
006416,006616,006816
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
Interrupt request bit
When reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Function
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
0 : Interrupt not requested
1 : Interrupt requested
Note 1: Can only be writing by “0” (Please do not write “1” to this bit)
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W
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Nothing is assigned.
Fig.DD-3 Interrupt control registers(1)
AA
AA
AA
A
A
AA
A
A
AA
AA
AA
AA
R
(Note 1)
M16C/6KA Group
AA
A
A
AA
b7
b6
b5
b4
Interrupt
b3
b2
b1
b0
Symbol
INTiIC(i=0 to 11)
0
Bit name
Bit symbol
ILVL0
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
Address
006916 to 007416
Interrupt request bit
Polarity select bit
Reserved bit
Function
b2 b1 b0
0: Interrupt not requested
1: Interrupt requested
0 : Selects falling edge
1 : Selects rising edge
Always set to “0”
Note 1: Can only be written by "0" (Please do not write "1" to this bit)
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AA
AA
AA
AA
AAAA
AA
AA
AA
AA
AA
A
A
AA
A
A
AA
AA
AAAA
R
W
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Nothing is assigned.
Fig.DD-4 Interrupt control registers (2)
When reset
XX00X0002
(Note 1)
M16C/6KA Group
Interrupt
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag
to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0”
after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bits and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bits in the interrupt control register.
When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt
priority level to “0” disables the interrupt.
Table.DD-3 shows the settings of interrupt priority levels and Table.DD-4 shows the interrupt levels enabled,
according to the consist of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > processor interrupt priority level (IPL)
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bits, and the IPL are
independent, and they are not affected each other.
Table.DD-5 Interrupt levels enabled according
Table.DD-4 Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
to the contents of the IPL
Priority
order
b2 b1 b0
IPL
Enabled interrupt priority levels
IPL2 IPL1 IPL0
0
0
0
Level 0 (interrupt disabled)
0
0
1
Level 1
0
1
0
0
1
1
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Interrupt levels 2 and above are enabled
Level 2
0
1
0
Interrupt levels 3 and above are enabled
1
Level 3
0
1
1
Interrupt levels 4 and above are enabled
0
0
Level 4
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Level 5
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Level 6
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
Level 7
1
1
1
All maskable interrupts are disabled
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Low
High
M16C/6KA Group
Interrupt
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. If there is possibility of the interrupt request occurrence, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This
will depend on the instruction. If this creates problems, use the below instructions to change the register.
Instructions : AND, OR, BCLR, BSET
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M16C/6KA Group
Interrupt
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an
interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor
temporarily suspends the instruction being executed, and transfers control to the interrupt sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address
0000016.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to “0” .
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the procession of interrupt sequence the processor executes instructions from the first address of the
interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of
an interrupt to the completion of the instruction under execution at that moment (a) and the time required for
executing the interrupt sequence (b). Fig.DD-5 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Fig.DD-5 Interrupt response time
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Instruction in
interrupt routine
M16C/6KA Group
Interrupt
Time (a) is dependent on the instruction under execution. 30 cycles is the maximum required for the DIVX
instruction (without wait).
Time (b) is as shown in Table.DD-6
Table.DD-6 Time required for executing the interrupt sequence
Interrupt vector address
Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
18 cycles (Note 1)
20 cycles (Note 1)
Even
Odd
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Even
19 cycles (Note 1)
20 cycles (Note 1)
Odd (Note 2)
Odd
20 cycles (Note 1)
20 cycles (Note 1)
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address bus
Address
0000
Interrupt
information
Data bus
R
Indeterminate
Indeterminate
SP-2
SP-2
contents
SP-4
SP-4
contents
vec
vec+2
vec
contents
PC
vec+2
contents
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Fig.DD-6 Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in
Table.DD-7 is set in the IPL.
Table.DD-7 Relationship between interrupts without interrupt priority levels and IPL
Interrupt sources without priority levels
Value set in the IPL
_______
Watchdog timer, NMI
7
Reset
0
Not changed
Other
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 51 of 266
M16C/6KA Group
Interrupt
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC)
are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Fig.DD-7 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM
instruction alone can save all the registers except the stack pointer (SP).
Address
MSB
Stack area
Address
MSB
LSB
Stack area
LSB
m–4
m–4
Program counter (PCL)
m–3
m–3
Program counter (PCM)
m–2
m–2
Flag register (FLGL)
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
[SP]
Stack pointer
value before
interrupt occurs
Stack status before interrupt request
is acknowledged
Flag register
(FLGH)
[SP]
New stack
pointer value
Program
counter (PCH)
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Fig.DD-7 State of stack before and after acceptance of interrupt request
The operation of saving registers carried out in the interrupt sequence is dependent on whether the content
of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the
stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter
(PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Fig.DD-8
shows the operation of the saving registers.
(1) Stack pointer (SP) contains even number
Address
Stack area
[SP] – 3 (Odd)
Program counter (PCL)
Program counter (PCM)
[SP] – 2 (Even) Flag register (FLGL)
[SP] – 1 (Odd)
[SP]
Address
Stack area
Flag register Program
(FLGH) counter (PCH)
(2) Saved simultaneously,
all 16 bits
(1) Saved simultaneously,
all 16 bits
[SP] – 4 (Odd)
Program counter (PCL)
[SP] – 3 (Even)
Program counter (PCM)
(4)
[SP] – 2 (Odd)
Flag register (FLGL)
(1)
[SP] – 1 (Even) Flag register
(FLGH)
[SP]
(Even)
Program
counter (PCH)
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Fig.DD-8 Operation of saving registers
page 52 of 266
(3)
Saved
simultaneously,
all 8 bits
(2)
(Odd)
Finished saving registers
in two operations.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 5 (Odd)
[SP] – 4 (Even)
(2) Stack pointer (SP) contains odd number
Sequence in which order
registers are saved
Finished saving registers
in four operations.
M16C/6KA Group
Interrupt
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG)
as it was immediately before the start of interrupt sequence and the contents of the program counter (PC),
both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bits. If the same interrupt priority level is assigned, however, the interrupt with higher hardware priority
is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Fig.DD-9 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine
Interrupt priority level judgement circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Fig.DD-10 shows the circuit that judges the interrupt priority level.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 53 of 266
M16C/6KA Group
_______
Interrupt
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Fig.DD-9 Hardware interrupts priorities
Priority level of each interrupt
INT11
Level 0 (initial value)
High
INT9
INT7
Priority level of each interrupt
Timer B5
INT10
Timer B3
INT8
Timer B1
INT5
Key input interrupt 0
INT3
INT1
UART1 reception
SCL2, SDA2
PS21
SCL1, SDA1
OBE
SCL0, SDA0
Timer B4
S/IO4
Timer B2
Key input interrupt 1
Timer A4
INT6
Timer A2
INT4
Timer A0
INT2
IBF3
INT0
IBF1
I2C2
A-D conversion
I2C1
Timer B0
2
I C0
Timer A3
SI/O3
Timer A1
UART1 transmission
IBF2
PS22
IBF0
PS20
LRESET
Processor interrupt priority level(IPL)
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
NMI
RESET
Fig.DD-10 Interrupt priority judgement circuit
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 54 of 266
Priority of peripheral I/O interrupts
(if priority levels are same)
Low
To interrupt request level judgment output
clock generation circuit (Fig. WA-2)
Interrupt request
accepted
M16C/6KA Group
Interrupt
______
INT Interrupt
________
__________
INT0 to INT11 are triggered by the edges of external inputs. The edge polarity can be selected using the
polarity select bit.
As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by
________
setting “1” in the INTi interrupt polarity switching bit of the interrupt factor selection register0,1 (035F16,
035E16). To select both edges, set the polarity switching bit of the corresponding interrupt control register to
‘falling edge’ (“0”). After the selection of interrupt edge, the corresponding interrupt request bit should be
cleared to "0" before enabling the interrupt.
Fig.DD-11, Fig.DD-12 show the Interrupt factor selection register 0, 1.
AA
A
AA
A
AAAA
AA
Interrupt factor selection register 0
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
IFSR0
Address
035F16
Bit name
Bit symbol
Function
IFSR00
INT0 interrupt polarity
switching bit
0 : One edge
1 : Two edges
IFSR01
INT1 interrupt polarity
switching bit
0 : One edge
1 : Two edges
IFSR02
INT2 interrupt polarity
switching bit
0 : One edge
1 : Two edges
IFSR03
INT3 interrupt polarity
switching bit
0 : One edge
1 : Two edges
IFSR04
INT4 interrupt polarity
switching bit
0 : One edge
1 : Two edges
IFSR05
INT5 interrupt polarity
switching bit
0 : One edge
1 : Two edges
Reserved bits
Fig.DD-11 Interrupt factor selection register(1)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
When reset
0016
page 55 of 266
Must be "0"
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
R W
M16C/6KA Group
Interrupt
AA
A
AA
A
AAAA
AA
Interrupt factor selection register 1
b7
b6
b5
b4
b3
0 0
b2
b1
b0
Symbol
IFSR 5
Address
035E16
Bit symbol
Bit name
IFSR10
INT6 interrupt polarity switching bit
0 : One edge
1 : Two edge
IFSR11
INT7 interrupt polarity switching bit
0 : One edge
1 : Two edge
IFSR12
INT8 interrupt polarity switching bit
0 : One edge
1 : Two edge
IFSR13
INT9 interrupt polarity switching bit
0 : One edge
1 : Two edge
IFSR14
INT10 interrupt polarity switching bit
0 : One edge
1 : Two edge
IFSR15
INT11 interrupt polarity switching bit
0 : One edge
1 : Two edge
Reserved bits
Fig. DD-12 Interrupt factor selection register(4)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
When reset
0016
page 56 of 266
Function
Must be "0"
AA
AA
A
AA
A
AA
A
A
A
A
AA
R W
M16C/6KA Group
Interrupt
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt 0
If the direction register of any of P50 to P57 is set for input and a falling edge is input to that port, a key input
interrupt 0 is generated. A key input interrupt 0 can also be used as a key-on wakeup function for cancelling
the wait mode or stop mode. Fig.DD-13 shows the block diagram of the key input interrupt 0. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Pull-up select bit
Pull-up
transistor
Key input interrupt 0 control register
(address 004D16)
Port P57 direction register
Port P57 direction register
P57/KI07
Pull-up
transistor
Port P56 direction
register
P56/KI06
Interrupt control circuit
Pull-up
transistor
Port P55 direction
register
P55/KI05
Pull-up
transistor
Port P54 direction
register
P54/KI04
Pull-up
transistor
Port P53 direction
register
P53/KI03
Pull-up
transistor
Port P52 direction
register
P52/KI02
Pull-up
transistor
Port P51 direction
register
P51/KI01
Pull-up
transistor
Port P50 direction
register
P50/KI00
Fig.DD-13 Block diagram of key input interrupt 0
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 57 of 266
Key input interrupt 0
request
M16C/6KA Group
Interrupt
Key Input Interrupt 1
If any of the bits of key input interrupt 1 enable register (Address: 02F416) are set to “1”, the key input
interrupt 1 request occurs when a falling or a rising edge is input to one of the corresponding pins.
The effective input edge of key input interrupt 1 is determined by the edge selection bit of key input
interrupt 1 edge selection register (Address: 02F516). When the bit is set to “0”, at the falling edge,
when the bit is set to “1”, at the rising edge of the input signal to the corresponding pin, the interrupt
request occurs respectively.
When an effective rising edge or falling edge is input, “1” is set to the corresponding bit of P14 event
register (Address: 02F616). By reading the register after the interrupt occurs, the pin, which the effective edge is input, can be confirmed even if the status of that pin has been changed.
At the completion of the reading of P14 event register, the bits, whose value is “1” in reading, will be
cleared automatically. A dummy write clears the register too.
The registers, the block diagram and the timing of key input interrupt 1 are shown in Fig. DD-15, Fig.
DD-16 and Fig. DD-17 respectively.
After changing the enable/disable setting of key input interrupt1 register or changing the effective edge
by modifying key input interrupt 1 edge selection register, the value of P14 event register and interrupt
request bit may become “1”. A dummy write to the P14 event register and a clear to the interrupt
request bit should be done after changing the effective edge.
P14 event register
AAA
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
KIN1EV
Bit symbol
Bit name
When reset
0016
Function
KIN1EV0
P14 event bit 0
0 : Factor
1 : No factor
KIN1EV1
P14 event bit 1
0 : Factor
1 : No factor
KIN1EV2
P14 event bit 2
0 : Factor
1 : No factor
KIN1EV3
P14 event bit 3
0 : Factor
1 : No factor
KIN1EV4
P14 event bit 4
0 : Factor
1 : No factor
KIN1EV5
P14 event bit 5
0 : Factor
1 : No factor
KIN1EV6
P14 event bit 6
0 : Factor
1 : No factor
KIN1EV7
P14 event bit 7
0 : Factor
1 : No factor
Fig.DD-14 P14 event register
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Address
02F616
page 58 of 266
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
R W
M16C/6KA Group
Interrupt
AA
A
AA
AA
AAAA
AAA
Key input interrupt 1 enable register
b7
b6
b5
b4
b3
b2
AA
A
AA
AA
AAAA
AAA
b1
b0
Symbol
KIN1EN
Address
02F416
Bit Symbol
When reset
0016
Bit name
Function
KIN1EN0
0 : Disable
Key input interrupt 1 enable bit 0 1 : Enable
KIN1EN1
0 : Disable
Key input interrupt 1 enable bit 1 1 : Enable
KIN1EN2
0 : Disable
Key input interrupt 1 enable bit 2 1 : Enable
KIN1EN3
0 : Disable
Key input interrupt 1 enable bit 3 1 : Enable
KIN1EN4
0 : Disable
Key input interrupt 1 enable bit 4 1 : Enable
KIN1EN5
0 : Disable
Key input interrupt 1 enable bit 5 1 : Enable
KIN1EN6
Key input interrupt 1 enable bit 6 0 : Disable
1 : Enable
KIN1EN7
Key input interrupt 1 enable bit 7 0 : Disable
1 : Enable
AAAA
AA
AAAA
AAA
A
AAA
AAA
A
R W
Key input interrupt 1 edge selection register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
KIN1SEL
Address
02F516
Bit Symbol
Bit name
Function
KIN1SEL0
Key input interrupt 1 edge
selection bit 0
0 : Falling edge
1 : Rising edge
KIN1SEL1
Key input interrupt 1 edge
selection bit 1
0 : Falling edge
1 : Rising edge
KIN1SEL2
Key input interrupt 1 edge
selection bit 2
0 : Falling edge
1 : Rising edge
KIN1SEL3
Key input interrupt 1 edge
selection bit 3
0 : Falling edge
1 : Rising edge
KIN1SEL4
Key input interrupt 1 edge
selection bit 4
0 : Falling edge
1 : Rising edge
KIN1SEL5
Key input interrupt 1 edge
selection bit 5
0 : Falling edge
1 : Rising edge
KIN1SEL6
Key input interrupt 1 edge
selection bit 6
0 : Falling edge
1 : Rising edge
KIN1SEL7
Key input interrupt 1 edge
selection bit 7
0 : Falling edge
1 : Rising edge
Fig.DD-15 Key input interrupt 1 registers
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
When reset
0016
page 59 of 266
AAA
AAA
AA
AA
AAAA
AA
AAAA
R W
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 60 of 266
Fig.DD-16 The block diagram of key input interrupt 1
P140/KI10
P141/KI11
P142/KI12
P143/KI13
P144/KI14
P145/KI15
P146/KI16
P147/KI17
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Pull-up
transistor
Key input interrupt 1 enable bit 0
Key input interrupt 1 enable bit 1
Key input interrupt 1 enable bit 2
Key input interrupt 1 enable bit 3
Key input interrupt 1 enable bit 4
Key input interrupt 1 enable bit 5
Key input interrupt 1 enable bit 6
Key input interrupt 1 enable bit 7
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit0
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit1
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit2
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit3
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit4
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit5
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit6
Edge selection one-shot
generation circuit
Key input interrupt 1
edge selection bit7
P147 direction register
Pull-up selection bit
Q
R
D
The write to address 02F616
The read from address 02F616
P140 event latch circuit
The write to address 02F616
The read from address 02F616
P141 event latch circuit
The write to address 02F616
The read from address 02F616
P142 event latch circuit
The write to address 02F616
The read from address 02F616
P143 event latch circuit
The write to address 02F616
The read from address 02F616
P144 event latch circuit
The write to address 02F616
The read from address 02F616
P145 event latch circuit
The write to address 02F616
The read from address 02F616
P146 event latch circuit
Delay circuit
RESET
The read from
address 02F616
P147 event latch circuit
Interrupt control circuit
D
R
DB0
The read from address 02F616
DB1
The read from address 02F616
DB2
The read from address 02F616
DB3
The read from address 02F616
DB4
The read from address 02F616
DB5
The read from address 02F616
DB6
The read from address 02F616
Q
Event register
The read from
address 02F616
Q
The read from
address 02F616
R
S
Event data
Key input interrupt 1 request
Key input interrupt 1 control register (Address 005C16)
The read from
address 02F616
DB7
M16C/6KA Group
Interrupt
M16C/6KA Group
Interrupt
P140
P141
(Note 1)
P140 request
P141 request
Interrupt request bit
P140 event data
(Note 2)
P141 event data
P14 event register
0016
0116
0316
0016
The read signal from 02F616
The read from 02F616
0116
Interrupt
procession
0316
Interrupt
procession
0016
Interrupt
procession
Note 1: If there are several effective edge inputs, the input sequential order can not be confirmed.
Note 2: If another interrupt request occurs between the setting of prior key input interrupt 1 request bit and the read of
P14 event register, the interrupt request bit will be set again same as P14 event register. After the read of P14
event register, both the bits, which were set to “1”, will be automatically cleared. However, the interrupt processing
will be executed twice because of the re-setting of interrupt request bit (the value of P14 event register in the 2nd
reading will be “0”).
Fig.DD-17 The timing of key input interrupt 1
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 61 of 266
M16C/6KA Group
Address match interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt
enable flag (I flag) and processor interrupt priority level (IPL). The stacked value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Fig.DD-18 shows the address match interrupt-related registers.
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Address
000916
When reset
XXXXXX002
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAA
AA
A
AAAAAAAAAAAAAA
AAAAAAAAAAAAAA
Bit symbol
Bit name
Function
AIER0
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
RW
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Address match interrupt register i (i = 0, 1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
Function
Address setting register for address match interrupt
When reset
X0000016
X0000016
AA
A
AAA
Values that can be set R W
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Fig.DD-18 Address match interrupt-related registers
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 62 of 266
M16C/6KA Group
Precautions for interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets the request bit, which the interrupt source is enabled with the
highest priority, to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Hence do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer is initialized to 000016 right after the reset. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
_______
stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at the
beginning of a program. Concerning the first instruction immediately after reset, generating any interrupts
_______
including the NMI interrupt is prohibited.
_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pullup) if unused. Be sure to work on it.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
• Do not reset the CPU with the input to the NMI pin being in the “L” state.
_______
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to the
_______
NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned down.
_______
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to the
_______
NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved. In this
instance, the CPU is returned to the normal state by a later interrupt.
_______
• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
________
• Either an “L” level or an “H” level of at least 380 ns width is necessary for the signal input to pins INT0
_________
through INT11 regardless of the CPU operation clock.
________
_________
• When the polarity of the INT0 to INT11 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Fig.DD-19 shows the procedure for changing
______
the INT interrupt generate factor.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 63 of 266
M16C/6KA Group
Precautions for interrupts
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Fig.DD-19 Switching condition of INT interrupt request
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. If there is possibility of the interrupt request occurs, rewrite the interrupt control register after the
interrupt is disabled. The program examples are described as follow:
• When a instruction to rewrite the interrupt control register is executed when the interrupt is disabled, the
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated.
This will depend on the instruction. If this creates problems, use the below instructions to change the register.
Instructions : AND, OR, BCLR, BSET
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. Bit 7 of the watchdog timer
control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). Thus the watchdog
timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error
due to the prescaler.
With XIN chosen for BCLK
Watchdog timer period =
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.7 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a
watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16).
Fig.DG-1 shows the block diagram of the watchdog timer. Fig.DG-2 shows the watchdog timer-related registers.
Prescaler
1/16
BCLK
1/128
“WDC7 = 0”
“WDC7 = 1”
Watchdog timer
HOLD
Write to the watchdog timer
start register
(address 000E16)
RESET
Fig.DG-1 Block diagram of watchdog timer
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 65 of 266
Set to
“7FFF16”
Watchdog timer
interrupt request
M16C/6KA Group
Watchdog Timer
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
WDC
0 0
Bit symbol
Address
000F16
When reset
000XXXXX2
Bit name
Function
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Reserved bit
Must always be set to “0”
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
AA
AA
A
AA
A
AA
A
R W
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Fig.DG-2 Watchdog timer control and start registers
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 66 of 266
A
RW
M16C/6KA Group
Timer
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Fig.FB-1 and FB-2 show the block diagram of timers.
f1
XIN
f8
1/8
1/4
f32
f1 f8 f32
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
TA0IN
Timer A0
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
TA1IN
Timer A1 interrupt
Timer A1
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
TA2IN
Timer A2 interrupt
Timer A2
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Noise
filter
TA3IN
Timer A0 interrupt
Timer A3 interrupt
Timer A3
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A4 interrupt
Noise
filter
TA4IN
Timer A4
• Event counter mode
Timer B2 overflow
Note 1: The TA0IN pin (P71) is shared with TB5IN pin, so be careful.
Fig.FB-1 Timer A block diagram
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
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M16C/6KA Group
Timer
f1
XIN
f8
1/8
1/4
f32
f1 f8 f32
Timer A
• Timer mode
• Pulse width measuring mode
Noise
filter
TB0IN
Timer B0 interrupt
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB1IN
Timer B1 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB2IN
Timer B2 interrupt
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB3IN
Timer B3 interrupt
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB4IN
Timer B4 interrupt
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB5IN
Timer B5
• Event counter mode
Note 1: The TB5IN pin (P71) is shared with TA0IN pin, so be careful.
Fig.FB-2 Timer B block diagram
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
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Timer B5 interrupt
M16C/6KA Group
Timer A
Timer A
Fig.FB-3 shows the block diagram of timer A. Fig.FB-4 to FB-6 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer continually outputs pulse with arbitrary width.
Data bus high-order bits
Clock source
selection
f1
f8
f32
AAA
A
AAA
A
Data bus low-order bits
• Timer
• One shot
• PWM
Low-order
8 bits
• Timer
(gate function)
High-order
8 bits
Reload register (16)
• Event counter
Counter (16)
Polarity
selection
Up count/down count
Clock selection
TAiIN
(i = 0 to 4)
Always down count except
in event counter mode
Count start flag
(Address 038016)
Down count
TB2 overflow
External
trigger
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Up/down flag
(Address 038416)
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Addresses
038716 038616
038916 038816
038B16 038A16
038D16 038C16
038F16 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Fig.FB-3 Block diagram of timer A
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
MR0
MR1
Address
When reset
039616 to 039A16
0016
Bit name
Function
b1 b0
Operation mode selection bits 0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
Function varies with each operation mode
MR2
MR3
TCK0
TCK1
Fig.FB-4 Timer A-related registers (1)
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REJ03B0100-0100Z
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Count source selection bits
(Function varies with each operation mode)
A
A
A
A
AA
A
AA
A
A
AA
A
AA
AA
R W
M16C/6KA Group
Timer A
Timer Ai register (Note)
(b15)
b7
(b8)
b0 b7
Symbol
TA0
TA1
TA2
TA3
TA4
b0
Address
038716,038616
038916,038816
038B16,038A16
038D16,038C16
038F16,038E16
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
AA
AAA
AA
AAA
AA
AA
AA
Values that can be set
• Timer mode
Count the internal count source
000016 to FFFF16
• Event counter mode
Count pulses from external input or the overflow of timer
000016 to FFFF16
• One-shot timer mode
Count one shot width
000016 to FFFF16
• Pulse width modulation mode (16-bit PWM)
Function as a 16-bit pulse width modulator
000016 to FFFE16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FE16
(Both high-order
and low-order
addresses)
RW
Note: Read and write data in 16-bit units.
Count start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
TABSR
b0
Address
038016
When reset
0016
AA
AAA
A
AA
A
AA
A
AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAAA
AA
Bit symbol
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
RW
0 : Stop count
1 : Start count
Up/down flag
b7
b6
b5
b4
b3
b2
b1
Symbol
UDF
b0
Bit symbol
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
TA2P
TA3P
TA4P
Fig.FB-5 Timer A-related registers (2)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Address
038416
page 70 of 266
When reset
0016
Function
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
factor
Timer A2 two-phase pulse 0 : two-phase pulse signal
processing disabled
signal processing select bit
1 : two-phase pulse signal
Timer A3 two-phase pulse
processing enabled
signal processing select bit
When not using the two-phase
Timer A4 two-phase pulse pulse signal processing function,
signal processing select bit set the select bit to “0”
AA
AAAAAA
AA
AA
AA
AA
AA
AA
R W
M16C/6KA Group
Timer A
One-shot start flag
b7
b6
b5
b4
b3
b2
b1
Symbol
ONSF
b0
Address
038216
Bit symbol
When reset
00X000002
Bit name
TA0OS
Timer A0 one-shot start flag
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
Function
1 : Timer start
When read, the value is “0”
AA
AA
AAA
A
AA
AA
AA
AA
R W
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
TA0TGL
Timer A0 event/trigger
selection bits
TA0TGH
b7 b6
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
Trigger selection register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TRGSR
Address
038316
Bit symbol
TA1TGL
Bit name
Timer A1 event/trigger
selection bits
TA1TGH
TA2TGL
Timer A2 event/trigger
selection bits
TA2TGH
TA3TGL
Function
b1 b0
b3 b2
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
b5 b4
Timer A4 event/trigger
selection bits
b7 b6
TA4TGH
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”.
Fig.FB-6 Timer A-related registers (3)
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page 71 of 266
AA
AA
A
A
A
A
AA
AA
AA
A
A
AA
AA
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
Timer A3 event/trigger
selection bits
TA3TGH
TA4TGL
When reset
0016
R W
M16C/6KA Group
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table.FB-1) Fig.FB-7 shows the
timer Ai mode register in timer mode.
Table.FB-1 Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32
• Down count
• When the timer underflows, it reloads the reload register contents and then continuing counting
1/(n+1) n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
When the timer underflows
Programmable I/O port or gate input
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or pulse output
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Select function
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
0 0
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode
selection bits
Function
b1 b0
0 0 : Timer mode
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR0
Pulse output function
selection bit
MR1
Gate function selection bits 0 X (Note 2): Gate function not available
b4 b3
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR2
MR3
TCK0
0 (Must always be fixed to “0” in timer mode)
Count source selection bits
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Inhibited
AA
AA
A
AA
A
RW
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Fig.FB-7 Timer Ai mode register in timer mode
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M16C/6KA Group
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can count
a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase external
signals. Table.FB-2 lists timer specifications and Fig. FB-8 shows the timer Ai mode register in event count
mode when counting a single-phase external signal.
Table.FB-3 lists timer specifications and Fig. FB-8 shows the timer Ai mode register in event count mode
when counting a two-phase external signals.
Table.FB-2 Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
• External signal input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents and then continuing counting (Note)
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
Programmable I/O port or count source input
TAiOUT pin function
Programmable I/O port, pulse output, or up/down count select input
Read from timer
Count value can be read out by reading timer Ai register
Write to timer
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
TAiMR(i = 0, 1)
0 1
Address
039616, 039716
Bit symbol
Bit name
TMOD0
Operation mode selection
bits
TMOD1
When reset
0016
Function
b1 b0
0 1 : Event counter mode (Note 1)
MR0
Pulse output function
selection bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
Count polarity
selection bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
MR2
Up/down switching factor
selection bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
MR3
0 (Must always be fixed to “0” in event counter mode)
TCK0
Count operation type
selection bit
TCK1
Invalid in event counter mode
Can be “0” or “1”
0 : Reload type
1 : Free-run type
A
AA
AA
A
AA
R
W
RW
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Fig.FB-8 Timer Ai mode register in event counter mode
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REJ03B0100-0100Z
page 73 of 266
M16C/6KA Group
Timer A
Table.FB-3 Timer specifications in event counter mode (when processing two-phase pulse signals with timers A2, A3, and A4)
Item
Count source
Count operation
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
Specification
• Two-phase pulse signals input to TAiIN and TAiOUT pin
• Up count or down count can be selected by two-phase pulse signals
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start flag is set (= 1)
Count start flag is reset (= 0)
Timer overflows or underflows
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
• Normal processing operation
The timer up-counts by the rising edge of TAiIN pin and down-counts by the
falling edge fo TAiIN pin during the "H" level period of input signal in TAiOUT
pin.
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
count
Down
count
Down
count
Down
count
• Multiply-by-4 processing operation
If the phase relationship is such that the TAiIN pin goes “H” when the input
signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges
Count down all edges
Count up all edges
Count down all edges
TAiIN
(i=3,4)
Note: This does not apply when the free-run function is selected.
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
Timer A
Timer Ai mode register
(When not using two-phase pulse signals' processing)
b7
b6
b5
b4
b3
b2
0
b1
b0
0 1
Symbol
Address
When reset
TAiMR(i = 2 to 4) 039816 to 039A16
0016
Bit symbol
Bit name
TMOD0
Operation mode selection
bits
TMOD1
Function
b1 b0
0 1 : Event counter mode
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR0
Pulse output function
selection bit
MR1
Count polarity selection bit 0 : Counts external signal's falling edges
1 : Counts external signal's rising edges
(Note 2)
MR2
Up/down switching
factor selection bit
MR3
0 : (Must always be “0” in event counter mode)
TCK0
Count operation type
selection bit
0 : Reload type
1 : Free-run type
TCK1
Two-phase pulse signals'
processing operation
selection bit
(Note 4)(Note 5)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
A
A
A
A
A
A
A
A
A
R W
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0”.
Note 4: This bit is valid for the timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0 ”or “1”.
Note 5: When performing two-phase signal processing, make sure the two-phase pulse signals'
processing operation selection bit (address 038416) is set to “1”. Also, always be sure
to set the event/trigger selection bit (addresses 038216 and 038316) to “00”.
Timer Ai mode register
(When using two-phase pulse signals' processing)
b7
b6
b5
b4
b3
b2
b1
b0
0 1 0 0 0 1
Symbol
Address
When reset
TAiMR(i = 2 to 4) 039816 to 039A16
0016
Bit symbol
TMOD0
TMOD1
Bit name
Operation mode selection
bits
Function
b1 b0
0 1 : Event counter mode
MR0
0 (Must always be “0” when using two-phase pulse signal
processing)
MR1
0 (Must always be “0” when using two-phase pulse signal
processing)
MR2
1 (Must always be “1” when using two-phase pulse signal
processing)
MR3
0 (Must always be “0” when using two-phase pulse signal
processing)
TCK0
TCK1
Count operation type
selection bit
0 : Reload type
1 : Free-run type
Two-phase pulse processing 0 : Normal processing operation
operation selection bit
1 : Multiply-by-4 processing operation
(Note 1)(Note 2)
A
A
A
A
A
A
A
A
RW
Note 1: This bit is valid for timer A3 mode register.
For timer A2 and A4 mode registers, this bit can be “0” or “1”.
Note 2: When performing two-phase pulse signals' processing, make sure the two-phase pulse
signals' processing operation selection bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger selection bit (addresses 038216 and 038316) to “00”.
Fig.FB-9 Timer Ai mode register in event counter mode
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page 75 of 266
M16C/6KA Group
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table.FB-4) When a trigger occurs, the timer starts to
operate for a given period. Fig.FB-10 shows the timer Ai mode register in one-shot timer mode.
Table.FB-4 Timer specifications in one-shot timer mode
Item
Specification
Count source
Count operation
f1, f8, f32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : Set value
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
• The count start flag is reset (= 0)
The count reaches 000016
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
Address
When reset
TAiMR(i = 0 to 4) 039616 to 039A16
0016
1 0
Bit symbol
TMOD0
Bit name
Function
AA
A
AA
A
AAA
AA
A
AAA
AA
A
AA
A
AAA
Operation mode
selection bits
b1 b0
MR0
Pulse output function
selection bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
External trigger selection 0 : Falling edge of TAiIN pin's input signal (Note 3)
bit (Note 2)
1 : Rising edge of TAiIN pin's input signal (Note 3)
MR2
Trigger selection bit
MR3
0 (Must always be “0” in one-shot timer mode)
TMOD1
TCK0
TCK1
Count source selection
bits
1 0 : One-shot timer mode
RW
0 : One-shot start flag is valid
1 : Selected by event/trigger selection register
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Inhibited
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger selection bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Fig.FB-10 Timer Ai mode register in one-shot timer mode
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table.FB-5) In this mode, the
counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Fig.FB-11
shows the timer Ai mode register in pulse width modulation mode. Fig.FB-12 shows the example of how a
16-bit pulse width modulator operates. Fig.FB-13 shows the example of how an 8-bit pulse width modulator
operates.
Table.FB-5 Timer specifications in pulse width modulation mode
Item
Specification
Count source
Count operation
f1, f8, f32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• High level width
n / fi n : Set value
• Cycle time
(216-1) / fi fixed
• High level width n (m+1) / fi
n : values set to timer Ai register’s high-order address
8
• Cycle time
(2 -1) (m+1) / fi
m : values set to timer Ai register’s low-order address
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
The falling edge of PWM pulse
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Timer Ai mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 1
1
Symbol
TAiMR(i=0 to 4)
Bit symbol
TMOD0
TMOD1
Address
When reset
039616 to 039A16
0016
Bit name
Operation mode
selection bits
Function
b1 b0
1 1 : PWM mode
MR0
1 (Must always be “1” in PWM mode)
MR1
External trigger selection 0: Falling edge of TAiIN pin's input signal (Note 2)
bit (Note 1)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
Trigger selection bit
0: Count start flag is valid
1: Selected by event/trigger selection register
MR3
16/8-bit PWM mode
selection bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
TCK0
TCK1
Count source selection
bits
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Inhibited
AA
A
AA
AA
A
RW
Note 1: Valid only when the TAiIN pin is selected by the event/trigger selection bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0”.
Fig.FB-11 Timer Ai mode register in pulse width modulation mode
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M16C/6KA Group
Timer A
Condition : Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X (2 16 – 1)
Count source
“H”
TAiIN pin
input signal
“L”
Trigger is not generated by this signal
1 / fi X n
“H”
PWM pulse output
from TAiOUT pin
“L”
“1”
Timer Ai interrupt
request bit
“0”
fi : Frequency of count source
Cleared to “0” when interrupt request is accepted, or cleared by software
(f1, f8, f32)
Note: n = 000016 to FFFE16.
Fig.FB-12 Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (2 8 – 1)
Count source (Note1)
TAiIN pin input signal
“H”
“L”
AAAAAAAAAAAAAAA
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fi X (m + 1) X n
PWM pulse output
from TAiOUT pin
“H”
Timer Ai interrupt
request bit
“1”
“L”
“0”
fi : Frequency of count source
(f1, f8, f32)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16.
Fig.FB-13 Example of how an 8-bit pulse width modulator operates
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M16C/6KA Group
Timer B
Timer B
Fig.FB-14 shows the block diagram of timer B. Fig.FB-15 and FB-16 show the timer B-related registers.
Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f1
• Timer
• Pulse period/pulse width measurement
f8
f32
Reload register (16)
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
(address 038016)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
TBj overflow
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Address
039116 039016
039316 039216
039516 039416
035116 035016
035316 035216
035516 035416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Fig.FB-14 Block diagram of timer B
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
TBiMR(i = 0 to 5) 039B16 to 039D16
035B16 to 035D16
Bit symbol
Bit name
TMOD0
Operation mode selection
bits
Function
b1 b0
TMOD1
MR0
When reset
00XX00002
00XX00002
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
Function varies with each operation mode
MR1
MR2
A
A
A
A
A
A
AA
AA
A
A
AA
AA
R
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source selection bits
(Function varies with each operation mode)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Fig.FB-15 Timer B-related registers (1)
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M16C/6KA Group
Timer B
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
039116, 039016
039316, 039216
039516, 039416
035116, 035016
035316, 035216
035516, 035416
Function
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Values that can be set
• Timer mode
Counts the timer's period
000016 to FFFF16
• Event counter mode
Counts external pulses input or a timer overflow
000016 to FFFF16
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
AA
A
A
AA
A
A
A
RW
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Address
038016
When reset
0016
AAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAA
A
AA
A
AAAAAAAAAAAAAAA
AA
A
A
AA
AAAAAAAAAAAAAAA
A
A
AAAAAAAAAAAAAAA
AA
A
A
AAAAAAAAAAAAAAA
AA
Bit symbol
Bit name
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
TA3S
Timer A3 count start flag
TA4S
Timer A4 count start flag
TB0S
Timer B0 count start flag
TB1S
Timer B1 count start flag
TB2S
Timer B2 count start flag
Function
RW
0 : Stops counting
1 : Starts counting
Timer B3, 4, 5 count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Address
034016
When reset
000XXXXX2
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA
AA
AA
AAAAAAAAAAAAAAA
AAA
A
Bit symbol
Bit name
Function
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
TB3S
Timer B3 count start flag
TB4S
Timer B4 count start flag
TB5S
Timer B5 count start flag
Fig.FB-16 Timer B-related registers (2)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
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0 : Stops counting
1 : Starts counting
RW
M16C/6KA Group
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table.FB-6.) Fig.FB-17 shows the
timer Bi mode register in timer mode.
Table.FB-6 Timer specifications in timer mode
Item
Specification
Count source
f1, f8, f32
Count operation
•Counts down
•When the timer underflows, it reloads the reload register contents and
then continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
AAA
A
AA
Programmable I/O port
Count value is read out by reading timer Bi register
•When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
TBiMR(i=0 to 5)
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039D16
035B16 to 035D16
When reset
00XX00002
00XX00002
Bit name
Operation mode selection
bits
Function
b1 b0
0 0 : Timer mode
MR1
Invalid in timer mode
Can be “0” or “1”
MR2
0 (Set to “0” in timer mode ; i = 0, 3)
AA
A
AA
A
AA
AAA
A
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be indeterminate.
MR3
Invalid in timer mode.
In an attempt to write to this bit, write “0”. The value, if read in
timer mode, turns out to be indeterminate.
TCK0
Count source selection bits
TCK1
b7 b6
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Inhibited
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Fig.FB-17 Timer Bi mode register in timer mode
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REJ03B0100-0100Z
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R
(Note 1)
(Note 2)
W
M16C/6KA Group
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table.FB-7) Fig.FB-18
shows the timer Bi mode register in event counter mode.
Table.FB-7 Timer specifications in event counter mode
Item
Specification
Count source
•External signals input to TBiIN pin
•Effective edge of count source can be a rising edge, a falling edge, or both
edges as selected by software
Count operation
•Counts down
•When the timer underflows, it reloads the reload register contents and
then continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count start flag is set (= 1)
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Count source input
Read from timer
Count value can be read out by reading timer Bi register
Write to timer
•When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
•When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7
AA
b6
b5
b4
b3
b2
b1
Symbol
TBiMR(i=0 to 5)
b0
0 1
Address
039B16 to 039D16
035B16 to 035D16
Bit symbol
Bit name
TMOD0
Operation mode selection
bits
TMOD1
MR0
Count polarity selection
bits (Note 1)
MR1
MR2
When reset
00XX00002
00XX00002
Function
b1 b0
0 1 : Event counter mode
b3 b2
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
0 (Fixed to “0” in event counter mode; i = 0, 3)
Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read,
turns out to be indeterminate.
MR3
Invalid in event counter mode.
In an attempt to write to this bit, write “0”. The value, if read in
event counter mode, turns out to be indeterminate.
TCK0
Invalid in event counter mode.
Can be “0” or “1”.
TCK1
Event clock selection
0 : Input from TBiIN pin (Note 4)
1 : TBj overflow
(j = i – 1; however, j = 2 when i = 0,
j = 5 when i = 3)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding port direction register to “0”.
Fig.FB-18 Timer Bi mode register in event counter mode
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AA
AA
AA
AAAA
AA
A
AA
AAAA
R
(Note 2)
(Note 3)
W
M16C/6KA Group
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table.FB-8)
Fig.FB-19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Fig.FB-20
shows the operation timing when measuring a pulse period. Fig.FB-21 shows the operation timing when
measuring a pulse width.
Table.FB-8 Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32
•Up count
•At measurement pulse's effective edge, after the count value is transferred
to reload register, it is cleared to "000016" and then continues counting.
Count start flag is set (= 1)
Count start flag is reset (= 0)
•When measurement pulse's effective edge is input (Note 1)
•When an overflow occurs. (Simultaneously, the timer Bi overflow flag becomes
“1”. The timer Bi overflow flag becomes “0” when the count start flag is “1”
and a value is written to the timer Bi mode register.)
Count start condition
Count stop condition
Interrupt request generation timing
TBiIN pin function
Read from timer
Measurement pulse input
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1 : An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2 : After count starts, the value read out from the timer Bi register is indeterminate until the second effective edge
is input .
Timer Bi mode register
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
TBiMR(i=0 to 5)
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode
selection bits
Measurement mode
selection bits
MR1
MR2
When reset
00XX00002
00XX00002
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
b3 b2
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
0 (Fixed to “0” in pulse period/pulse width measurement mode; i = 0, 3)
Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
MR3
Timer Bi overflow
flag ( Note 1)
0 : Timer did not overflow
1 : Timer has overflowed
TCK0
Count source
selection bits
b7 b6
TCK1
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : Inhibited
AA
AAAA
AA
AA
AA
AAA
AA
AA
R
W
(Note 2)
(Note 3)
Note 1: The timer Bi overflow flag becomes “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Fig.FB-19 Timer Bi mode register in pulse period/pulse width measurement mode
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M16C/6KA Group
Timer B
When measuring a pulse time interval from falling edge to falling edge
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
Count start flag
“0”
“1”
Timer Bi interrupt
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Fig.FB-20 Operation timing when measuring a pulse period
Count source
Measurement pulse
Reload register
transfer timing
“H”
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
Count start flag
“0”
“1”
Timer Bi interrupt
request bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software.
Timer Bi overflow flag
“1”
“0”
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Fig.FB-21 Operation timing when measuring a pulse width
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M16C/6KA Group
Serial I/O
Serial I/O
Serial I/O is configured as three channels: UART1, S I/O3 and S I/O4.
UART1
Fig.GA-1 shows the block diagram of UART1. Fig.GA-2 shows the block diagram of the transmit/receive
unit.
UART1 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O
mode (UART mode). The contents of the serial I/O mode selection bits (bits 0 to 2 at address 03A816) determine whether UART1 is used as a clock synchronous serial I/O or as a UART. Although a few functions are
different, UART1 has almost the same functions.
Table.GA-1 shows the functions of UART1, and Fig.GA-3 to GA-7 show the registers related to UART1.
Table.GA-1 Functions of UART1
Function
UART1
CLK polarity selection
Possible
(Note 1)
LSB first / MSB first selection
Possible
(Note 1)
Continuous receive mode selection
Possible
(Note 1)
Transfer clock output from multiple
pins selection
Possible
(Note 1)
Serial data logic switch
Possible
TxD, RxD I/O polarity switch
Possible
TxD, RxD port output format
CMOS output
Note 1: Only in clock synchronous serial I/O mode.
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M16C/6KA Group
Serial I/O
(UART1)
RxD polarity
switching circuit
RxD1
1/16
Clock source selection
Bit rate generator
Internal (address 03A916)
f1
f8
f32
UART reception
1 / (n1+1)
External
Reception
control circuit
Clock synchronous type
UART transmission
1/16
Clock synchronous type
Clock synchronous type
Transmission
control circuit
Receive
clock
Transmit/
receive
unit
Transmit
clock
(when internal clock is selected)
1/2
CLK1
CTS1 / RTS1
/ CLKS1
CLK
polarity
switching
circuit
Clock synchronous type
(when external clock is
selected)
Clock synchronous type
(when internal clock is selected)
CTS/RTS disabled
RTS1
Clock output pin
select switch
VCC
CTS/RTS disabled
CTS1
n1 : Values set to UART1 bit rate generator (BRG1)
Fig.GA-1 Block diagram of UART1
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TxD
polarity
switching
circuit
TxD1
M16C/6KA Group
Serial I/O
No reverse
RxD data
reverse circuit
RXD1
Reverse
Clock
synchronous type
PAR
disabled
1SP
SP
UART1 receive register
UART(7 bits)
PAR
SP
2SP
PAR
enabled
0
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
0
0
0
UART
0
Clock
synchronous type
UART
(9 bits)
0
0
UART
(8 bits)
UART
(9 bits)
D8
D7
D6
D5
D4
D3
D2
D1
D0
Logic reverse circuit + MSB/LSB conversion circuit
UART1 receive
buffer register
Address 03AE16
Address 03AF16
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D7
D8
D6
D5
D4
D3
D2
D1
D0
UART
(8 bits)
UART
(9 bits)
PAR
enabled
2SP
SP
SP
UART
(9 bits)
Clock
synchronous type
UART
PAR
1SP
PAR
disabled
“0”
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART1 transmit register
Clock
synchronous type
Not reverse
TxD data
reverse circuit
TXD1
Reverse
SP: Stop bit
PAR: Parity bit
Fig.GA-2 Block diagram of UART1 transmit/receive unit
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 87 of 266
UART1 transmit
buffer register
Address 03AA16
Address 03AB16
M16C/6KA Group
Serial I/O
UART1 transmit buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U1TB
Address
03AB16, 03AA16
When reset
Indeterminate
A
Function
R W
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turn out to be indeterminate.
UART1 receive buffer register
(b15)
b7
(b8)
b0 b7
b0
Symbol
U1RB
Bit
symbol
Address
03AF16, 03AE16
When reset
Indeterminate
Function
(During clock synchronous
serial I/O mode)
Bit name
Receive data
Function
(During UART mode)
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
OER
Overrun error flag (Note 1) 0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
PER
Parity error flag (Note 1)
Invalid
0 : No parity error
1 : Parity error found
SUM
Error sum flag (Note 1)
Invalid
0 : No error
1 : Error found
AA
AA
AA
AA
AA
AA
R W
Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode selection bits (bits 2 to 0 at address
03A816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UART1 receive buffer register (address 03AE16) is read out.
UART1 bit rate generator
b7
b0
Symbol
U1BRG
Address
03A916
When reset
Indeterminate
Function
Assuming that set value = n, BRG1 divides the count source by
n+1
Fig.GA-3 Serial I/O-related registers (1)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 88 of 266
Values that can be set
0016 to FF16
A
R W
M16C/6KA Group
Serial I/O
UART1 transmit/receive mode register
b7
b6
b5
b4
b3
b2
b1
Symbol
U1MR
b0
Address
03A816
Bit
symbol
Bit name
SMD0
Serial I/O mode selection
bits
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
b2 b1 b0
0 : Internal clock
1 : External clock (Note 1)
Must always be "0"
STPS
Stop bit length selection
bit
Invalid
0 : One stop bit
1 : Two stop bits
PRY
Odd/even parity selection Invalid
bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
Invalid
0 : Parity disabled
1 : Parity enabled
SLEP
Sleep selection bit
Must always be “0”
0 : Sleep mode deselected
1 : Sleep mode selected
0 : Not reverse
1 : Reverse
Usually set to “0”
Note 1: Set the corresponding port direction register to "0".
Fig.GA-4 Serial I/O-related registers (2)
page 89 of 266
A
A
A
A
AA
AA
AA
AA
AA
A
A
A
A
A
A
AA
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR Internal/external clock
selection bit
IOPOL TxD, RxD I/O polarity
switching bit
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Function
(During UART mode)
0 : Not reverse
1 : Reverse
Usually set to “0”
R W
M16C/6KA Group
Serial I/O
UART1 transmit/receive control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U1C0
Bit
symbol
CLK0
Address
03AC16
CLK1
CRS
Function
(During clock synchronous
serial I/O mode)
Bit name
BRG count source
selection bits
CTS/RTS function
selection bit
TXEPT Transmit register empty
flag
When reset
0816
Function
(During UART mode)
b1 b0
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Inhibited
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(Pins function as
programmable I/O port)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(Pins function as programmable
I/O port)
NCH
Data output selection bit
0 : TXD1 pin is CMOS output
1 : TXD1 pin is N-channel opendrain output
0: TXD1 pin is CMOS output
1: TXD1 pin is N-channel open-drain
output
CKPOL CLK polarity selection bit 0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
Must always be “0”
UFORM Transfer format selection 0 : LSB first
1 : MSB first
bit (Note 3)
0 : LSB first
1 : MSB first
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Fig.GA-5 Serial I/O-related registers (3)
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REJ03B0100-0100Z
page 90 of 266
R W
AA
AA
AA
AA
AA
A
A
M16C/6KA Group
Serial I/O
UART1 transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U1C1
Bit
symbol
Address
03AD16
Bit name
When reset
0216
Function
(During clock synchronous
serial I/O mode)
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer empty flag
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
RI
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
U1LCH
Data logic selection bit
0 : Not reverse
1 : Reverse
0 : Not reverse
1 : Reverse
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Fig.GA-6 Serial I/O-related registers (4)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
AA
A
AA
A
AA
AA
A
AA
A
AA
AA
A
Function
(During UART mode)
page 91 of 266
R W
M16C/6KA Group
Serial I/O
UART transmit/receive control register 2
b7
b6
0
b5
b4
b3
b2
b1
0
b0
Symbol
UCON
0
Bit
symbol
Address
03B016
Bit name
Reserved bit
U1IRS
UART1 transmit interrupt
factor selection bit
Reserved bit
U1RRM
UART1 continuous
receive mode enable bit
CLKMD0 CLK/CLKS selection bit 0
CLKMD1
CLK/CLKS selection bit 1
(Note)
Reserved bit
When reset
X00000002
Function
(During clock synchronous
serial I/O mode)
Function
(During UART mode)
Must always be “0”
Must always be “0”
0 : Continuous receive mode
disabled
1 : Continuous receive mode
enabled
Invalid
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
Must always be “0”
0 : Normal mode
(CLK output is CLK1 only)
1 : Transfer clock output from
multiple pins function selected
Must always be “0”
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock selection bit (bit 3 at address 03A816) = “0”.
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page 92 of 266
A
A
0 : Transmit buffer empty (Tl = 1) 0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
1 : Transmission completed
(TXEPT = 1)
(TXEPT = 1)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Fig.GA-7 Serial I/O-related registers (5)
R W
AA
AA
A
M16C/6KA Group
Clock synchronous serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables.GA-2 and
GA-3 list the specifications of the clock synchronous serial I/O mode. Fig.GA-8 shows the UART1 transmit/
receive mode register.
Table.GA-2 Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• When internal clock is selected (bit 3 at address 03A816 = “0” ) :
fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at address 03A816 = “1” ) :
Input from CLK1 pin
_______
_______
_______ _______
Transmission/reception control • Selecting from CTS function/RTS function/Disable CTS, RTS function
Transmission start condition • To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at address 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at address 03AD16) = “0”
_______
_______
_ When CTS function selected, CTS input level = “L”
• Furthermore, if external clock is selected, the following requirements must also be met:
_ CLK1 polarity select bit (bit 6 at address 03AC16) = “0”:
CLK1 input level = “H”
_ CLK1 polarity select bit (bit 6 at address 03AC16) = “1”:
CLK1 input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at address 03AD16) = “1”
_ Transmit enable bit (bit 0 at address 03AD16) = “1”
_ Transmit buffer empty flag (bit 1 at address 03AD16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ CLK1 polarity select bit (bit 6 at address 03AC16) = “0”:
CLK1 input level = “H”
_ CLK1 polarity select bit (bit 6 at address 03AC16) = “1”:
CLK1 input level = “L”
• When transmitting
_ Transmit interrupt factor selection bit (bit 1 at address 03B016) = “0”:
Interrupt request
At the completion of data transmission from UART1 transfer buffer register
generation timing
to UART1 transmit register
_ Transmit interrupt factor selection bit (bit 1 at address 03B016) = “1”:
At the completion of data transmission from UART1 transfer register is
completed
• When receiving
_ At the completion of data transferring from UART1 receive register to
UART1 receive buffer register
Error detection
• Overrun error (Note 2)
This error occurs when bit 7 of next data is received before the contents of
UART1 receive buffer register are read out.
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UART1 receive buffer will have the next data written in. Note also that
the UART1 receive interrupt request bit is not set to “1”.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
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M16C/6KA Group
Clock synchronous serial I/O mode
Table.GA-3 Specifications of clock synchronous serial I/O mode (2)
Item
Function selection
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Specification
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the
transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
page 94 of 266
M16C/6KA Group
Clock synchronous serial I/O mode
UART1 transmit/receive mode registers
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U1MR
0 0 1
Address
03A816
When reset
0016
Bit symbol
Bit name
SMD0
Serial I/O mode selection bits
b2 b1 b0
Internal/external clock
selection bit
0 : Internal clock
1 : External clock (Note 1)
SMD1
SMD2
CKDIR
Function
0 0 1 : Clock synchronous serial
I/O mode
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note 1)
0 : No reverse
1 : Reverse
Note 1: Usually sent to "0".
Note 2: The corresponding port direction register should be "0".
Fig.GA-8 UART1 transmit/receive mode register in clock synchronous serial I/O mode
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 95 of 266
A
A
A
A
A
A
A
RW
M16C/6KA Group
Clock synchronous serial I/O mode
Table.GA-4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table
shows the pin functions that the transfer clock output from multiple pins are not selected. Note that for a
period from when the UART1 operation mode is selected to when transfer starts, the TxD1 pin outputs a “H”.
(If the N-channel open-drain is selected, this pin is in floating state.)
Table.GA-4 Input/output pin functions in clock synchronous serial I/O mode
(The function that the transfer clock output from multiple pin is not selected.)
Pin name
Function
Method of selection
TxD1
Serial data output
(Outputs dummy data when performing reception only)
RxD1
Serial data input
The corresponding bit of port direction register = “0”
(Can be used as an input port when performing transmission only)
CLK1
Transfer clock output
Internal/external clock select bit (bit 3 at address 03A816) = “0”
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A816) = “1”
The corresponding bit of port direction register = “0”
CTS input
CTS/RTS disable bit (bit 4 at address 03AC16) =“0”
CTS/RTS function selection bit (bit 2 at address 03AC16) = “0”
The corresponding port direction bit = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03AC16) = “0”
CTS/RTS function selection bit (bit 2 at address 03AC16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03AC16) = “1”
CTS1/RTS1
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M16C/6KA Group
Clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
“1”
“0”
Data is set in UART1 transmit buffer register
“1”
“0”
Transferred from UART1 transmit buffer register to UART1 transmit register
“H”
CTS1
TCLK
“L”
Stopped because CTS = “H”
Stopped because transfer enable bit = “0”
CLK1
TxD1
D0 D1 D2 D 3 D 4 D 5 D 6 D 7
Transmit
register empty
flag (TXEPT)
D0 D1 D2 D 3 D 4 D5 D 6 D7
D0 D1 D2 D 3 D 4 D 5 D 6 D 7
“1”
“0”
Transmit interrupt “1”
request bit (IR)
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity selection bit = “0”.
• Transmit interrupt factor selection bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRG1 count source (f1, f8, f32)
n: value set to BRG1
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
Transmit enable
bit (TE)
“0”
Transmit buffer
empty flag (Tl)
“1”
“0”
“H”
RTS1
Dummy data is set in UART1 transmit buffer register
“1”
Transferred from UART1 transmit buffer register to UART1 transmit register
“L”
1 / fEXT
CLK1
Receive data is taken in
D0 D1 D 2 D 3 D4 D5 D 6 D7
RxD1
“1”
Receive complete
“0”
flag (Rl)
Receive interrupt
request bit (IR)
Transferred from UART1 receive register
to UART1 receive buffer register
D 0 D1 D 2 D3 D4 D5
Read out from UART1 receive buffer register
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity selection bit = “0”.
The following conditions should be matched when the input level of
CLK1 pin is "H" before the data reception.
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UART1 transmit buffer register
fEXT: frequency of external clock
Fig.GA-9 Typical transmit/receive timings in clock synchronous serial I/O mode
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M16C/6KA Group
Clock synchronous serial I/O mode
(a) Polarity selection function
As shown in Fig.GA-10, the CLK polarity selection bit (bit 6 at address 03AC16) allows to select the polarity
of the transfer clock.
• When CLK polarity selection bit = “0”
CLK1
TXD1
D0
D1
D2
D3
D4
D5
D6
D7
RXD1
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: The CLK pin level is "H" when
there is no transferring.
• When CLK polarity select bit = “1”
CLK1
TXD1
D0
D1
D2
D3
D4
D5
D6
D7
RXD1
D0
D1
D2
D3
D4
D5
D6
D7
Note 2: The CLK pin level is "L" when
there is no transferring.
Fig.GA-10 Polarity of transfer clock
(b) LSB first/MSB first selection function
As shown in Fig.GA-11, when the transfer format selection bit (bit 7 at address 03AC16) = “0”, the transfer
format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format selection bit = “0”
CLK1
TXD1
D0
D1
D2
D3
D4
D5
D6
D7
LSB first
RXD1
D0
D1
D2
D3
D4
D5
D6
D7
D2
D1
D0
• When transfer format selection bit = “1”
CLK1
TXD1
D7
D6
D5
D4
D3
MSB first
RXD1
D7
D6
D5
D4
D3
D2
D1
D0
Note: This applies when the CLK polarity selection bit = “0”.
Fig.GA-11 Transfer format
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M16C/6KA Group
Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function (UART1)
This function allows to set two transfer clock output pins and chooses one to output a clock by the setting of
CLK and CLKS selection bits (bits 4 and 5 at address 03B016). (See Fig.GA-12) The function is valid only
_______ _______
when the UART1 internal clock is selected. Note that when this function is selected, CTS/RTS function
cannot be used.
Microcomputer
TXD1
CLKS1
CLK1
IN
IN
CLK
CLK
Fig.GA-12 The sample of transfer clock output from the multiple pins function
(d) Continuous receive mode
If the continuous receive mode enable bit (bit 3 at address 03B016) are set to “1”, the unit is placed in
continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously
goes to a receive enable state without having to set dummy data to the transmit buffer register back again.
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables.GA-5 and GA-6 list the specifications of the UART mode. Fig.GA-13 shows the UART1
transmit/receive mode register.
Table.GA-5 Specifications of UART Mode (1)
Item
Specification
Transfer data format
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
• When internal clock is selected (bit 3 at address 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at address 03A816 =“1”) :
fEXT/16(n+1)(Note 1) (Note 2)
_______ _______
Transmission/reception control • Selecting from Disable CTS, RTS function
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at address 03AD16) = “1”
- Transmit
buffer empty flag (bit 1_______
at address 03AD16) = “0”
_______
- When CTS function is selected CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at address 03AD16) = “1”
- Start bit detection
Interrupt request
• When transmitting
generation timing
- Transmit interrupt factor selection bit (bit 1 at address 03B016) = “0”:
At the completion of data transferring from UART1 transfer buffer register to
UART1 transmit register
- Transmit interrupt factor selection bit (bit 1 at address 03B016) = “1”:
At the completion of data transmission from UART1 transfer register
• When receiving
- At the completion of data transferring from UART1 receive register to
UART1 receive buffer register
Error detection
• Overrun error (Note 3)
This error occurs when the bit prior to the stop bit of next data is received
before the contents of UART1 receive buffer register are read out.
• Framing error
This error occurs when the number set for stop bits is not detected
• Parity error
This error occurs in the case that parity is enabled and the number of "1" in
parity bit and character bits does not match the number of "1" in parity odd/
even setting.
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART1 bit rate register.
Note 2: fEXT is input from the CLK1 pin.
Note 3: If an overrun error occurs, the UART1 receive buffer will have the next data written in. Also note
that the UART1 receive interrupt request bit is not set to “1”.
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
Table.GA-6 Specifications of UART Mode (2)
Item
Function selection
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Specification
• Serial data logic switch
This function is reversing logic value of transferring data. Start bit, and stop
bit are not reversed.
• TXD, RXD I/O polarity switch
This function is reversing TXD port output and RXD port input. All I/O data
level are reversed.
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M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
UART1 transmit / receive mode registers
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U1MR
Bit symbol
SMD0
Address
03A816
When reset
0016
Bit name
Function
Serial I/O mode selection bits
b2 b1 b0
CKDIR
Internal / external clock
selection bit
0 : Internal clock
1 : External clock (Note 1)
STPS
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
PRY
Odd / even parity select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
switching bit (Note 2)
0 : No reverse
1 : Reverse
SMD1
SMD2
Note 1: The corresponding port direction register should be "0".
Note 2: Usually set to “0”.
Fig.GA-13 UARTi transmit/receive mode register in UART mode
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page 102 of 266
AA
A
AA
A
AAA
AA
A
AA
A
AAA
AA
A
AA
A
AAA
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
R W
M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
Table.GA-7 lists the functions of the input/output pins during UART mode. Note that for a period from when
the UART1 operation mode is selected to when transfer starts, the TxD1 pin outputs a “H”. (If the N-channel
open-drain is selected, this pin is in floating state.)
Table.GA-7 Input/output pin functions in UART mode
Pin name
Function
Method of selection
TXD1
Serial data output
RXD1
Serial data input
Corresponding port direction register bit = "0".
(Can be used as an input port when performing transmission only)
CLK1
Programmable I/O port
Internal/external clock selection bit (bit 3 at address 03A816) = “0”
Transfer clock input
Internal/external clock selection bit (bit 3 at address 03A816) = “1”
Corresponding port direction register bit = “0”
CTS input
CTS/RTS disable bit (bit 4 at address 03AC16) =“0”
CTS/RTS function selection bit (bit 2 at address 03AC16) = “0”
Corresponding port direction register bit = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03AC16) = “0”
CTS/RTS function selection bit (bit 2 at address 03AC16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03AC16) = “1”
CTS1/RTS1
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M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data are 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UART1 transmit buffer register.
“0”
Transferred from UART1 transmit buffer register to UART1 transmit register
“H”
CTS1
“L”
Start
bit
TxD1
Parity
bit
ST D0 D1 D2 D3 D4 D5 D6 D7
Stopped because transmit enable bit = “0”
Stop
bit
SP
P
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1
P SP
“1”
Transmit register
empty flag (TXEPT)
“0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
• CTS function is selected.
• Transmit interrupt factor selection bit = “1”.
Tc = 16 (n +1) / fi or 16 (n +1) / fEXT
fi : frequency of BRG1 count source (f1, f8, f32)
fEXT : frequency of BRG1 count source (external clock)
n : value set to BRG1
• Example of transmit timing when transfer data are 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
Transmit enable
bit(TE)
“1”
Transmit buffer
empty flag(TI)
“1”
“0”
Data is set in UART1 transmit buffer register
“0”
Transferred from UART1 transmit buffer register to UART1 transmit register
Start
bit
TxD1
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Stop
bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“1”
Transmit register
empty flag (TXEPT) “0”
Transmit interrupt
request bit (IR)
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
• CTS function is disabled.
• Transmit interrupt factor selection bit = “0”.
Fig.GA-14 Typical transmit timings in UART mode
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Tc = 16 (n +1) / fi or 16 (n +1) / fEXT
fi : frequency of BRG1 count source (f1, f8, f32)
fEXT : frequency of BRG1 count source (external clock)
n : value set to BRG1
M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data are 8 bits long (parity disabled, one stop bit)
BRG1 count
source
Receive enable bit
RxD1
“1”
“0”
Stop bit
Start bit
D0
D1
D7
Sampled “L”
Receive data taken in
Transfer clock
Receive
complete flag
RTS1
Receive interrupt
request bit
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
“0”
“H”
“L”
“1”
“0”
Transferred from UART1 receive register to
UART1 receive buffer register
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Fig.GA-15 Typical receive timing in UART mode
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M16C/6KA Group
Clock asynchronous serial I/O (UART) mode
(a) Function for switching serial data logic
When the data logic selection bit is assigned 1, data is inverted in writing to the transmission buffer register
or reading the reception buffer register. Fig.GA-16 shows the example of timing for switching serial data
logic.
• When LSB first, parity enabled, one stop bit
Transfer clock
“H”
“L”
TxD1
“H”
(no reverse)
“L”
TxD1
“H”
(reverse)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“L”
ST : Start bit
P : Even parity
SP : Stop bit
Fig.GA-16 Timing for switching serial data logic
(b) TxD, RxD I/O polarity switching function
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for usual
use.
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M16C/6KA Group
SI/O3,4
S I/O3, 4
S I/O 3 and S I/O 4 are exclusive clock-synchronous serial I/Os.
Fig.GA-17 shows the S I/O 3, 4 block diagram, and Fig.GA-18 shows the S I/O 3, 4 control register.
Table.GA-8 shows the specifications of S I/O 3, 4.
f1
Data bus
SMi1
SMi0
f8
f32
Synchronous
circuit
1/2
1/(ni+1)
Transfer rate register (8)
SMi3
SMi6
SMi6
S I/O counter i (3)
CLKi
SMi2
SMi3
SMi5 LSB
MSB
SOUTi
S I/Oi transmission/reception register (8)
SINi
8
Note: i = 3, 4.
ni = A value set in the S I/O transfer rate register i (036316, 036716).
Fig.GA-17 S I/O3, 4 block diagram
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S I/Oi
interrupt request
M16C/6KA Group
SI/O3,4
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SiC
0
Bit
symbol
SMi0
Address
036216, 036616
When reset
4016
Description
Bit name
Internal synchronous
clock selection bits
R W
b1 b0
0 0 : Selecting f1
0 1 : Selecting f8
1 0 : Selecting f32
1 1 : Not to be used
SMi1
SMi2
SOUTi output disable bit
0 : SOUTi output
1 : SOUTi output disable (high impedance)
SMi3
S I/Oi port selection bit
(Note 2)
0 : Input-output port
1 : SOUTi output, CLK function
Reserved bit
Must be "0"
SMi5
Transfer direction
selection bit
0 : LSB first
1 : MSB first
SMi6
Synchronous clock
selection bit (Note 2)
0 : External clock
1 : Internal clock
SMi7
SOUTi initial value
set bit
Effective when SMi3 = 0
0 : L output
1 : H output
Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the
S I/Oi control register (i = 3, 4).
Note 2: When SI/Oi port selection bit (i= 3, 4) is set to "0" as for I/O port, set the
synchronous clock selection bit to "1".
SI/Oi bit rate generator
b7
Symbol
S3BRG
S4BRG
b0
Address
036316
036716
When reset
Indeterminate
Indeterminate
Indeterminate
Values that can be set
Assuming that set value = n, BRGi divides the count
source by n + 1
R W
0016 to FF16
SI/Oi transmission/reception register
b7
Symbol
S3TRR
S4TRR
b0
Address
036016
036416
When reset
Indeterminate
Indeterminate
Indeterminate
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
Fig.GA-18 S I/O3, 4 control registers
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R W
M16C/6KA Group
SI/O3,4
Table.GA-8 Specifications of S I/O3, 4
Specifications
Item
Transfer data format • Transfer data length: 8 bits
• With the internal clock selected (bit 6 of 036216, 036616 = “1”): f1/2(ni+1),
Transfer clock
f8/2(ni+1), f32/2(ni+1) (Note 1)
• With the external clock selected (bit 6 of 036216, 036616 = 0):Input from the CLKi
terminal (Note 2)
• To start transmit/reception, the following requirements must be met:
Conditions for
- Select the synchronous clock (use bit 6 of 036216, 036616).
transmission/
Select a frequency dividing ratio if the internal clock has been selected (use bits
reception start
0 and 1 of 036216, 036616).
- SOUTi initial value set bit (use bit 7 of 036216, 036616)= 1.
- S I/Oi port select bit (bit 3 of 036216, 036616) = 1.
- Select the transfer direction (use bit 5 of 036216, 036616)
- Write transfer data to SI/Oi transmission/reception register(036016, 036416)
• To use S I/Oi interrupts, the following requirements must be met:
- S I/Oi interrupt request bit (bit 3 of 004916, 004816) = 0.
Interrupt request • At the rising edge of the last transfer clock (Note3)
generation timing
Select function
Precaution
• LSB first or MSB first selection
Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be
selected.
• The SOUTi default value setting function
If the transfer clock is selected to external clock, the output level of SOUTi pin
can be selected when it is not in transferring please refer to Fig.GA-30.
• The SI/Oi (i=3,4) is different from UART0 to 2 that the register and buffer can not
be separated, so don't write the next transfer data to the transmission/reception
register(036016, 036416) during transferring.
• If the transfer clock is selected to internal clock, at the end of transferring, the
SOUTi holds the last data during the last 1/2 transfer clock, and then to high impedance.
If the transmission/reception register(036016, 036416) is written during the period,
the SOUTi becomes the high impedance right the writing, the data hold time will be
shortened.
Note 1: n is a value from 0016 through FF16 set in the S I/Oi transfer rate register (i = 3, 4).
Note 2: With the external clock selected:
• Please write to the SI/Oi transmission/reception register(036016, 036416) under the status that the
CLKi pin is input to "H" level. Also please write to the bit 7(SOUTi default value setting bit) under
the status that the CLKi pin is input to "H" level.
• The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it,
so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,
automatically stops.
Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the “H” state.
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M16C/6KA Group
SI/O3,4
Functions for setting an SOUTi initial value
In carrying out transmission, the output level of the SOUTi pin as it is before transmitting 1-bit data can be set
either to “H” or to “L”. Fig.GA-19 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) With "H" selected for SOUTi
Signal written to the SI/Oi
transmission /reception
register
SI/Oi port selection bit SMi3 = 0
SOUTi initial value selection bit
SMi7 = 1
"H" level)
(SOUTi: Internal
SOUTi's initial value
set bit (SMi7)
SI/Oi port selection bit
(SMi3)
SI/Oi port selection bit
SMi3 = 0 1
(Port selection: Normal port SOUTi)
D0
SOUTi (internal)
SOUTi pin = "H" output
D0
Port output
SOUTi pin output
Initial value = "H"(Note)
(i = 3, 4)
Setting the SOUTi initial
value to H
Signal written to the SI/Oi register
="L" "H"
"L"
(Falling edge )
Port selection
(normal port SOUTi)
Note: The set value is output only when the external clock has been selected. Please
set the SOUTi default under the status that the CLKi is input to "H" level.
If the internal clock has been selected or if SOUTi output inhibition has been set,
this output goes to the high-impedance state.
SOUTi pin = Outputting
stored data in the SI/Oi transmission/
reception register
Fig.GA-19 Timing chart for setting SOUTi’s initial value and how to set it
S I/Oi operation timing
Fig.GA-20 shows the S I/Oi operation timing
MAX:1.5 cycle
SI/Oi internal clock
Transfer clock
(Note 1)
Signal written to the
SI/Oi register
(Note 2)
Hiz
S I/Oi output SOUTi
(i= 3, 4)
D0
D1
D2
D3
D4
D5
D6
D7
Hiz
SI/Oi input SINi
(i= 3, 4)
SI/Oi interrupt "1"
request bit (i=3,4)
"0"
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the
SI/Oi control register (i = 3,4). (No frequency division, 8-division frequency, 32-division frequency.)
Note 2: With the internal clock selected for the transfer clock, the SOUTi (i = 3,4) pin becomes to the high-impedance state after the
transfer finishes.
Note 3: The figure shows when the port selection bit of SOUTi (i = 3,4) is set to "1".
Fig.GA-20 S I/Oi operation timing chart
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M16C/6KA Group
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P100 to P107, P95, and P96 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5
at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table.JA-1 shows the performance of the A-D converter. Fig.JA-1 shows the block diagram of the A-D
converter, and Fig.JA-2 and JA-3 show the A-D converter-related registers.
Table.JA-1 Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage
0V to AVCC (VCC)
Operating clockφAD (Note1) fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
• 8-bit resolution
±2LSB
• 10-bit resolution
±6LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition
• Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
___________
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin
• Without sample and hold function
8-bit resolution : 49 φAD cycles
10-bit resolution : 59 φAD cycles
• With sample and hold function
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
Note 1: The frequency φAD should be set to 250kHz min and 8MHz max.
Without sample and hold function,set the φAD frequency to 250kHz min.
With the sample and hold fucntion, set the φAD frequency to 1MHz min.
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M16C/6KA Group
A-D Converter
A-D conversion rate selection
CKS1=1
φAD
CKS0=1
fAD
1/2
1/2
CKS1=0
CKS0=0
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016)
A-D register 0(16)
(03C316, 03C216)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
(03C516, 03C416)
(03C716, 03C616)
(03C916, 03C816)
(03CB16, 03CA16)
(03CD16, 03CC16)
(03CF16, 03CE16)
Vref
Decoder
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
A-D register 7(16)
VIN
Comparator
Data bus high-order
Data bus low-order
AN0
CH2,CH1,CH0=000
AN1
CH2,CH1,CH0=001
AN2
CH2,CH1,CH0=010
AN3
CH2,CH1,CH0=011
AN4
CH2,CH1,CH0=100
AN5
CH2,CH1,CH0=101
AN6
CH2,CH1,CH0=110
AN7
CH2,CH1,CH0=111
OPA1,OPA0=0,0
OPA1, OPA0
OPA1,OPA0=0,1
ANEX0
ANEX1
OPA1,OPA0=1,0
Fig.JA-1 Block diagram of A-D converter
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0
0
1
1
0 : AN0-AN7
1 : ANEX0
0 : ANEX1
1 : Inhibited
M16C/6KA Group
A-D Converter
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
CH0
Analog input pin selection
bits
CH1
CH2
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
TRG
Trigger selection bit
0 : Software trigger
1 : ADTRG trigger
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
MD0
MD1
(Note 2)
b4 b3
A-D operation mode
selection bits 0
AA
A
A
AA
A
AA
AA
A
AA
A
A
AA
A
AA
A
AA
A
AA
RW
Function
b2 b1 b0
(Note 2)
0 : FAD/4 selected
1 : FAD/2 selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
CKS0
Frequency selection bit 0
A-D control register 1 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin selection bits When single sweep and repeat sweep
mode 0 are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
When repeat sweep mode 1 is selected
SCAN1
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
MD2
A-D operation mode
selection bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
BITS
8/10-bit mode selection bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency selection bit 1
0 : FAD/2 or FAD/4 selected
1 : FAD selected
VCUT
Vref connect bit
0 : Vref not connected
1 : Vref connected
b7 b6
OPA0
ANEX0,1 selection bits
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : Inhibited
RW
AA
A
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
A
AA
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Fig.JA-2 A-D converter-related registers (1)
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M16C/6KA Group
A-D Converter
A-D control register 2 (Note)
b7
b6
b5
b4
b3
b2
b1
Symbol
ADCON2
b0
0 0 0 0
Address
03D416
Bit symbol
SMP
When reset
000100002
Bit name
A-D conversion method
select bit
Function
0 : Without sample and hold
1 : With sample and hold
Must be “0”.
Reserved bits
Nothing is assigned.
AAA
AA
A
AAA
R W
In an attempt to write to this bit, write “0”. The value, if read, turn out to be “0”.
Symbol
A-D register i
(b15)
b7
(b8)
b0 b7
ADi(i=0 to 7)
Address
When reset
03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
Fig.JA-3 A-D converter-related registers (2)
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AA
AA
AA
R W
M16C/6KA Group
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin selection bits is used for one-shot A-D conversion. Table.JA-2 shows the specifications of one-shot mode. Fig.JA-4 shows the A-D control register in oneshot mode.
Table.JA-2 One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin selection bits is used for one A-D conversion
Start condition
Writing “1” to A-D conversion start flag
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
Symbol
ADCON0
b0
0 0
Address
03D616
Bit symbol
Bit name
CH0
Analog input pin selection
bits
When reset
00000XXX2
Function
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
CH1
CH2
MD0
MD1
TRG
ADST
A-D conversion start flag
CKS0
Frequency selection bit 0
(Note 2)
b4 b3
A-D operation mode
selection bits 0
Trigger selection bit
0 0 : One-shot mode
AAAA
AA
AAA
AA
A
AAA
AAA
A
RW
b2 b1 b0
(Note 2)
0 : Software trigger
1 : ADTRG trigger
0 : A-D conversion disabled
1 : A-D conversion started
0 : FAD/4 selected
1 : FAD/2 selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
b1
b0
Symbol
ADCON1
0
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
A-D sweep pin selection Invalid in one-shot mode
bits
SCAN1
0 : Any mode other than repeat sweep
mode 1
MD2
A-D operation mode
selection bit 1
BITS
0 : 8-bit mode
1 : 10-bit mode
0 : FAD/2 or FAD/4 selected
Frequency selection bit 1
1 : FAD selected
CKS1
VCUT
8/10-bit mode select bit
Vref connect bit
1 : Vref connected
b7 b6
OPA0
ANEX0,1 selection bis
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : Inhibited
AAA
AAA
AA
AAA
A
AAA
AA
AAA
AAA
A
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Fig.JA-4 A-D conversion register in one-shot mode
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 115 of 266
M16C/6KA Group
A-D Converter
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin selection bits is used for repeated A-D conversion. Table.JA-3 shows the specifications of repeat mode. Fig.JA-5 shows the A-D control register in repeat
mode.
Table.JA-3 Repeat mode specifications
Item
Specification
The pin selected by the analog input pin selection bits is used for repeated A-D conversion
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Not generated
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Function
Star condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
CH0
CH1
CH2
MD0
(Note 2)
b4 b3
MD1
A-D operation mode
selection bits 0
TRG
Trigger selection bit
0 : Software trigger
1 : ADTRG trigger
ADST
A-D conversion start flag
CKS0
Frequency selection bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : FAD/4 selected
1 : FAD/2 selected
0 1 : Repeat mode
A
A
A
A
A
A
A
A
A
RW
b2 b1 b0
Analog input pin selection
0 0 0 : AN0 is selected
bits
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
(Note 2)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Address
03D716
When reset
0016
Bit symbol
Bit name
SCAN0
A-D sweep pin selection
bits
Invalid in repeat mode
Function
MD2
A-D operation mode
selection bit 1
Should be “0” in this mode
BITS
8/10-bit mode selection
bit
SCAN1
CKS1
VCUT
0 : 8-bit mode
1 : 10-bit mode
0 : FAD/2 or FAD/4 selected
Frequency selection bit 1
1 : FAD selected
Vref connect bit
1 : Vref connected
b7 b6
OPA0
ANEX0,1 selection bis
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : Inhibited
A
A
A
A
A
A
A
A
A
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Fig.JA-5 A-D conversion register in repeat mode
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 116 of 266
RW
M16C/6KA Group
A-D Converter
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin selection bits are used for one-by-one AD conversion. Table.JA-4 shows the specifications of single sweep mode. Fig.JA-6 shows the A-D control
register in single sweep mode.
Table.JA-4 Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin selection bits are used for one-by-one A-D conversion
Start condition
Writing “1” to A-D converter start flag
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D converter Read A-D registers corresponding to selected pins
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
ADCON0
Bit symbol
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin selection bits
Invalid in single sweep mode
A-D operation mode selection
bits 0
b4 b3
TRG
Trigger selection bit
0 : Software trigger
1 : ADTRG trigger
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
Frequency selection bit 0
0 : FAD/4 selected
1 : FAD/2 selected
CH0
CH1
CH2
MD0
1 0 : Single sweep mode
MD1
CKS0
A
AA
A
AA
A
AA
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
b4
1
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
A-D sweep pin select bit
Function
When single sweep and repeat sweep mode 0
are selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
A-D operation mode
select bit 1
Should be "0" in this mode
BITS
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
CKS1
Frequency selection bit 1 0 : FAD/2 or FAD/4 selected
1 : FAD selected
VCUT
Vref connect bit
OPA0
ANEX0,1 selection bis
1 : Vref connected
b7 b6
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : Inhibited
A
AA
AA
AA
AA
R W
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Fig.JA-6 A-D conversion register in single sweep mode
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 117 of 266
M16C/6KA Group
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin selection bits are used for repeat sweep
A-D conversion. Table.JA-5 shows the specifications of repeat sweep mode 0. Fig.JA-7 shows the A-D
control register in repeat sweep mode 0.
Table.JA-5 Repeat sweep mode 0 specifications
Item
Specification
The pins selected by the A-D sweep pin selection bits are used for repeat sweep A-D conversion
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Not generated
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Read A-D registers corresponding to selected pins (at any time)
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin selection bits Invalid in repeat sweep mode 0
CH1
CH2
MD0
b4 b3
A-D operation mode selection 1 1 : Repeat sweep mode 0
bits 0
MD1
TRG
Trigger selection bit
0 : Software trigger
1 : ADTRG trigger
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency selection bit 0
0 : FAD/4 selected
1 : FAD/2 selected
AAA
AAA
AAA
A
AA
AAA
AA
AAA
A
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
b4
1
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
When reset
0016
Bit name
Function
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
SCAN1
MD2
A-D operation mode
selection bits 1
Should be "0" in this mode
BITS
8/10-bit mode selection bit
CKS1
Frequency selection bit 1
0 : 8-bit mode
1 : 10-bit mode
0 : FAD/2 or FAD/4 selected
1 : FAD selected
VCUT
Vref connect bit
1 : Vref connected
b7 b6
OPA0
ANEX0,1 selection bis
OPA1
AAA
AAA
AAA
AAA
AA
A
AAAA
AA
AAA
AAA
R W
A-D sweep pin selection bits When single sweep and repeat sweep mode 0
are selected
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : Inhibited
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Fig.JA-7 A-D conversion register in repeat sweep mode 0
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REJ03B0100-0100Z
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M16C/6KA Group
A-D Converter
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using
the A-D sweep pin selection bits. Table.JA-6 shows the specifications of repeat sweep mode 1. Fig.JA-8
shows the A-D control register in repeat sweep mode 1.
Table.JA-6 Repeat sweep mode 1 specifications
Item
Specification
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin selection bits
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Not generated
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Read A-D registers corresponding to selected pins (at any time)
Function
Start condition
Stop condition
Interrupt request generation timing
Input pin
Reading of result of A-D converter
A-D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
When reset
00000XXX2
Bit name
Function
Analog input pin selection bits Invalid in repeat sweep mode 1
CH1
CH2
MD0
b4 b3
A-D operation mode selection 1 1 : Repeat sweep mode 1
bits 0
MD1
TRG
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
CKS0
Frequency selection bit 0
0 : FAD/4 selected
1 : FAD/2 selected
AA
AA
AA
AA
A
RW
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
A-D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
1
b1
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
Bit name
A-D sweep pin selection bits
BITS
Function
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
SCAN1
MD2
When reset
0016
A-D operation mode selection 1 : Repeat sweep mode 1
bit 1
0 : 8-bit mode
8/10-bit mode selection bit
1 : 10-bit mode
CKS1
Frequency selection bit 1
0 : FAD/2 or FAD/4 selected
1 : FAD selected
VCUT
Vref connect bit
1 : Vref connected
b7 b6
OPA0
ANEX0,1 selection bis
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : Inhibited
AA
AA
A
AA
AA
R W
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
Fig.JA-8 A-D conversion register in repeat sweep mode 1
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
A-D Converter
(a) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is converted
from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is converted
from analog to digital. The result of conversion is stored in A-D register 1.
(b) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rage of conversion of each pin increases. As a result, a 28 φAD cycle is
achieved with 8-bit resolution and 33φAD cycle with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is
to be used.
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
PWM
PWM output circuit (PWM : Pulse Width Modulation)
There are 6 PWM output circuits, PWM0 to PWM5, with 8-bit resolution and operating independently. The
input clock f(PC) for PWM is based on XIN, 2 division of XIN or 4 division of XIN.
Data bus
PWM0 prescaler pre-latch
PWM0 register pre-latch
Transmission control circuit
PWM0 prescaler latch
"00"
f(XIN)
PWM0 register latch
Count source
selection bits
P44 latch
P44/PWM01
1/2
1/4
"01"
f(PC)
PWM0 prescaler
PWM0 register
PWM0
"10"
PWM0 output pin selection bit
PWM0 output enable bit
P44 direction register
P93 latch
P93/DA1/PWM00
PWM0 output pin selection bit
PWM0 output enable bit
Note: Refer to page 24 for the addresses of PWM prescaler and PWM register.
Fig.LA-1 PWM circuit (PWM0)
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REJ03B0100-0100Z
page 121 of 266
P93 direction register
M16C/6KA Group
PWM
Data Setup (PWM0)
PWM0 output pin shares with P93 or P44. PWM0 output pin is selected from either P93/PWM00 or P44/
PWM01 by bit 0 of PWM control register 0 (address 030C16). PWM0 output is enabled and starts to operate
by setting bit 0 of PWM control register 1 (address 030D16) to "1".
The period of PWM is set by PWM0 prescaler (address 030016), The "H" width of output pulse is set by
PWM0 register (address 030116).
The following are the calculations if the prescaler value is n and PWM0 register value is m.
(n = 0 to 255, m = 0 to 255)
PWM period = 255 ✕ (n+1) = 31.875 ✕ (n+1) µs
f(XIN)
(In the case of f(XIN)=8MHz, PWM counter source selection bits="002")
"H" width of output pulse = PWM period ✕ m = 0.125 ✕ (n+1) ✕ mµs
255
(In the case of f(XIN)=8MHz, PWM counter source selection bits="002")
The setting of PWM1 to PWM5 are the same.
PWM Operation
By setting bit 0 ( PWM0 output enable bit) of PWM control register 1 to "1", the PWM output circuit starts to
operate from default state with "H" pulse output.
If the values of PWM0 register and PWM0 prescaler are modified during the PWM output operation, the
corresponding pulse will be output from the next period after the modification.
31.875 ✕ m ✕ (n+1)
µs
255
<
>
PWM0 output
< T = [31.875 ✕ (n+1)] µs
>
m : The content of PWM0 register
n : The content of PWM0 prescaler
T : PWM Period ( in the case of f(XIN) = 8MHz)
Fig.LA-2 The timing of PWM period (PWM0)
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REJ03B0100-0100Z
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M16C/6KA Group
PWM
A
B
C
B
C
=
T T2
PWM0 output
T
The write signal to
PWM0 register
The write signal to
PWM0 prescaler
T
T2
( The modification of "H" width from "A" to "B")
( The modification of PWM period from "T" to "T2")
In the case that values of PWM0 register and PWM0 prescaler are modified,
the PWM0 output will be changed from the next period after the modification.
Fig.LA-3 The PWM output timing in the case of modification of PWM register and PWM prescaler
(PWM0)
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
PWM
AAA
AA
A
AAA
AA
A
PWM control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PWMCON0
Bit symbol
Address
030C16
When reset
0016
Bit name
Function
PWMSEL0
PWM0 output pin selection bit
0 : P93/PWM00
1 : P44/PWM01
PWMSEL1
PWM1 output pin selection bit
0 : P94/PWM10
1 : P45/PWM11
PWMSEL2
PWM2 output pin selection bit
0 : P95/PWM20
1 : P46/PWM21
PWMSEL3
PWM3 output pin selection bit
0 : P96/PWM30
1 : P47/PWM31
PWMSEL4
PWM4 output pin selection bit
0 : P160/PWM40
1 : P40/PWM41
PWMSEL5 PWM5 output pin selection bit
0 : P161/PWM50
1 : P41/PWM51
R W
b7 b6
PWMCLK0 PWM count source selection bits 0 0 : f(XIN)
0 1 : f(XIN)/2
1 0 : f(XIN)/4
PWMCLK1
1 1 : Inhibit
AAA
AA
A
AAA
AA
A
PWM control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PWMCON1
Bit symbol
Address
030D16
Bit name
Function
PWMEN0
PWM0 output enable bit
0 : Inhibit
1 : Enable
PWMEN1
PWM1 output enable bit
0 : Inhibit
1 : Enable
PWMEN2
PWM2 output enable bit
0 : Inhibit
1 : Enable
PWMEN3
PWM3 output enable bit
0 : Inhibit
1 : Enable
PWMEN4
PWM4 output enable bit
0 : Inhibit
1 : Enable
PWMEN5
PWM5 output enable bit
0 : Inhibit
1 : Enable
Nothing is assigned.
Can not be written. The value is “0” in reading.
Fig.LA-4 PWM control registers
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
When reset
0016
page 124 of 266
R W
M16C/6KA Group
LPC Bus Interface
LPC Bus Interface
LPC bus interface is based on Intel Low Pin Count (LPC) Interface Specification, Revision 1.0. It is I/O cycle
data transfer format of serial communication. 4 channels are built in. The function of data bus buffer and data
bus buffer status are almost the same as that of MELPS8-41 series. It can be written in or read out (as slave
mode) by the control signals from host CPU side. The LPC bus interface functionality block diagram is shown
in Figure GF-2. LPC data bus buffer functional Input / Output ports (P30-P36 ) are shared with GPIO port.
The setting of bit3 (LPC bus buffer enable bit) of LPC control register ( address 02D616 ) is as below:
0: General purpose Input / Output port
1: LPC bus buffer functional Input / Output port
The enabling of channel of LPC bus buffer is controlled by bits 4-7 (LPC bus buffer 0-3 enable bits) of LPC
control register (address 02D616 ). The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h,
0064h. The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC 1-3 address register H, L (address 02D016 to 02D516 ). The setting value of bit2 of LPC1-3 address register (A2) L
will not be decoded. The bit is “0” when read from slave CPU. The A2 status of slave address is latched to
XA2 flag when written by host CPU. The input buffer full interrupt is generated when written in the data by
host CPU. The Output buffer empty interrupt is generated when read out the data by host CPU.
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
LPC Bus Interface
Output buffer full flag0 OBF0
Input buffer full flag0
IBF0
Rising edge
detection circuit
One shot pulse
generator
Input Buffer Full0 interrupt requestsignal
(IBF0 interrupt request)
Input buffer full flag1
IBF1
Rising edge
detection circuit
One shot pulse
generator
Input Buffer Full1 interrupt request signal
(IBF1 interrupt request)
Input buffer full flag2
IBF2
Rising edge
detection circuit
One shot pulse
generator
Input Buffer Full2 interrupt request signal
(IBF2 interrupt request)
Input buffer full flag3
IBF3
Rising edge
detection circuit
One shot pulse
generator
Input Buffer Full3 interrupt request signal
(IBF3 interrupt request)
OBE0
Rising edge
detection circuit
One shot pulse
generator
OBE1
Rising edge
detection circuit
One shot pulse
generator
OBE2
Rising edge
detection circuit
One shot pulse
generator
OBE3
Rising edge
detection circuit
One shot pulse
generator
Output buffer full flag1 OBF1
Output buffer full flag2 OBF2
Output buffer full flag3 OBF3
IBF0
IBF0 interrupt request
IBF1
IBF1 interrupt request
IBF2
IBF2 interrupt request
IBF3
IBF3 interrupt request
OBF0(OBE0)
OBF1(OBE1)
OBF2(OBE2)
OBF3(OBE3)
OBE interrupt request
Fig.GF-1 Interrupt, request, circuit of Data Bus Buffer
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REJ03B0100-0100Z
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Output Buffer empty interrupt request signal
(OBE interrupt request)
M16C/6KA Group
LPC Bus Interface
P33/LAD3
Address register LL (Note1)
Address register LH (Note1)
Address register HL (Note1)
Address register HH (Note1)
RD/WR register
Start register
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Internal Data Bus
Input Data Buffer [7:4] Input Data Buffer [3:0]
Output Data Buffer [7:4]Output Data Buffer [3:0]
Data bus buffer status register
U7
U6
U5
U4
XA2
U2
IBF
OBF
Output Control Circuit
TAR register
P32/LAD2
Input Control Circuit
SYNC register
P31/LAD1
System Bus
P30/LAD0
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
Input Data Comparator
P34/LFRAME
P35/LRESET
P36/LCLK
Interrupt signal
IBF, OBE
Interrupt generate
Circuit
b7
b6
b5
b4
b3
b2
LPC control register (address 02D616)
0
0
Note1 : LPC bus interface channel 0 is fixed on slave address “0060h”, “0064h”.
Fig.GF-2 LPC bus interface function block diagram (LPC1)
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M16C/6KA Group
LPC Bus Interface
Figure GF-3: Data bus buffer control registers
Figure GF-4: Data bus buffer status register
Figure GF-5, 6: LPC related registers
Data bus buffer status register (DBBSTS0-DBBSTS3)
This is 8-bit register.
The bit 0, 1, 3 are read only bits and indicate the status of data bus buffer.
Bit 2, 4, 5, 6, 7 are user definable and flags which can be read and written by software. The data bus buffer
status register can be read out by host CPU when the slave address (16 bit) bit2 (A2) is high.
• Output buffer full flag (OBF)
The bit will be set to "1" when a data is written into output data bus buffer and will be cleared to "0" when host
CPU read out the data from output data bus buffer.
• Input buffer full flag (IBF)
The bit will be set to "1" while a data is written into input data bus buffer by host CPU and will be cleared to
"0" when the data is read out from input data bus buffer by slave CPU.
• XA2 flag (XA2)
The bit 2 of slave address (16 bits) is latched while a data is written into data bus buffer.
Input data bus buffer register (DBBIN0-DBBIN3)
When there is a write request from host CPU, the data on the data bus will be latched to DBBIN0-3. The data
of DBBIN0-3 can be read out from data bus buffer registers (Address:02C016, 02C216 , 02C416 , 02C616 ) in
SFR field.
Output data bus buffer register (DBBOUT0-DBBOUT3)
When writing data to data bus buffer registers (Address: 02C016 , 02C216 , 02C416 , 02C616 ), the data will
be transferred to DBBOUT0-3 automatically. The data of DBBOUT0-3 will be output to the data bus when
there is a read request from host CPU and the status of bit2 (A2) of slave address (16 bits) is low.
LPCi address register H/L (LPC1ADH-LPC3ADH / LPC1ADL-LPC3ADL)
The slave address (16 bits) of LPC bus buffer channel 0 is fixed on 0060h, 0064h.
The slave addresses (16 bits) of LPC bus buffer channel 1-3 are definable by setting LPC1-3 address registers H/L (02D016 to 02D516 ). The settings are for slave address upper 8 bits and lower 8 bits. And these
registers can be set and cleared in any time.
The bit 2 of LPC 1-3 address L is not decoded regardless of the setting value. When slave CPU reads LPC13 address registers, the bit2 (A2) of address low byte will be fixed to "0". The bit2 (A2) status of slave address
is latched to XA2 flag when written by host CPU. The slave addresses that are already set in these registers
will be used for comparing with the addresses to be received.
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M16C/6KA Group
LPC Bus Interface
Data bus buffer control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DBBCON1
Bit symbol
Address
02C916
Bit name
Function
OBF0SEL
OBF0 output selection bit
0 : OBF00 enable
1 : OBF01 enable
OBF00EN
OBF00 output enable bit
0 : P40 as GPIO
1 : P40 as OBF00 output
OBF01EN
OBF01 output enable bit
0 : P43 as GPIO
1 : P43 as OBF01 output
OBF1EN
OBF1 output enable bit
0 : P44 as GPIO
1 : P44 as OBF1 output
OBF2EN
OBF2 output enable bit
0 : P45 as GPIO
1 : P45 as OBF2 output
OBF3EN
OBF3 output enable bit
0 : P46 as GPIO
1 : P46 as OBF3 output
Nothing is assigned.
Cannot be written. The value is "0" in reading.
Fig.GF-3 Data bus buffer control registers
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
When reset
000000002
page 129 of 266
R W
M16C/6KA Group
LPC Bus Interface
Data bus buffer status register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DBBSTS0
DBBSTS1
DBBSTS2
DBBSTS3
Bit name
Bit symbol
When reset
000000002
000000002
000000002
000000002
Function
OBF
Output buffer full flag
0 : Buffer empty
1 : Buffer full
IBF
Input buffer full flag
0 : Buffer empty
1 : Buffer full
U2
User definable flag
This flag can be freely defined
by user
XA2
XA2 flag
This flag is indication the A2
status of the 16 bit slave address
when IBF flag is set
U4
User definable flag
This flag can be freely defined
by user
U5
U6
U7
Fig.GF-4 Data bus buffer status register
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Address
02C116
02C316
02C516
02C716
page 130 of 266
R W
M16C/6KA Group
LPC Bus Interface
LPCi address register L (i=1,2,3)
b7
b6
b5
b4
b3
b2
b1
(Note2)
Symbol
LPC1ADL
LPC2ADL
LPC3ADL
b0
Bit symbol
Address
02D016
02D216
02D416
When reset
000000002
000000002
000000002
Bit name
LPCSAD0
Slave address0
LPCSAD1
Slave address1
LPCSAD2
Slave address2 (Note1)
LPCSAD3
Slave address3
LPCSAD4
Slave address4
LPCSAD5
Slave address5
LPCSAD6
Slave address6
LPCSAD7
Slave address7
R W
Note1: Always returns “0” when read, even if writing “1” to this bit.
Note2: Do not set the same 16 bits slave address in each channel.
LPCi address register H (i=1,2,3)
b7
b6
b5
b4
b3
b2
b1
Symbol
LPC1ADH
LPC2ADH
LPC3ADH
b0
Bit symbol
Fig.GF-5 LPC related registers
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Address
02D116
02D316
02D516
Bit name
LPCSAD8
Slave address8
LPCSAD9
Slave address9
LPCSAD10
Slave address10
LPCSAD11
Slave address11
LPCSAD12
Slave address12
LPCSAD13
Slave address13
LPCSAD14
Slave address14
LPCSAD15
Slave address15
When reset
000000002
000000002
000000002
R W
M16C/6KA Group
LPC Bus Interface
LPC control register (LPCCON)
• LPC bus interface enable bit (LPCBEN)
"0": P30 -P36 use as GPIO
"1": P30 -P36 use as LPC bus interface
• LPC bus buffer 0 enable bit (LPCEN0)
"0": LPC bus buffer0 disable
"1": LPC bus buffer0 enable
• LPC bus buffer 1 enable bit (LPCEN1)
"0": LPC bus buffer1 disable
"1": LPC bus buffer1 enable
• LPC bus buffer 2 enable bit (LPCEN2)
"0": LPC bus buffer2 disable
"1": LPC bus buffer2 enable
• LPC bus buffer 3 enable bit (LPCEN3)
"0": LPC bus buffer3 disable
"1": LPC bus buffer3 enable
• LPC software reset bit (LPCSR)
______________
By setting the bit to "1", LPC interface is reset by the same status as LRESET="L". After 1.5 cycles of
BCLK at writing "1", reset is released and the bit becomes "0".
Nothing happens if "0" is set.
• SYNC output selection bits (SYNCSEL0,SYNCSEL1)
The content of SYNC output can be selected by bit 0,1 (SYNC output selection bits) of LPC control register.
Fig.GF-6 shows the configuration of LPC control register, Table.GF-1 shows the content of SYNC output
selected by SYNC output selection bits.
Table GF-1 SYNC output
SYNCSEL1
SYNCSEL0
SYNC cycle
0
0
1
1
0
1
0
1
1
4
1
4
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1st cycle
00002
01102
10102
01102
SYNC output
2nd cycle
3rd cycle
4th cycle
01102
01102
00002
01102
01102
10102
M16C/6KA Group
AA
AA
A
AA
AAAAAA
A
LPC Bus Interface
LPC control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
LPCCON
Bit symbol
Address
02D616
When reset
000000002
Bit name
Function
b1 b0
SYNCSEL0
SYNC output selection bits
0 0: OK
0 1: Long & OK
1 0: Err
1 1: Long & Err
LPCSR
LPC software reset bit
0 : The release of reset (Note)
1 : Reset
LPCBEN
LPC interface enable bit
0 : P30 - P36 as GPIO
1 : LPC bus buffer enable
LPCEN0
LPC bus buffer 0 enable bit
0 : LPC bus buffer 0 disable
1 : LPC bus buffer 0 enable
LPCEN1
LPC bus buffer 1 enable bit
0 : LPC bus buffer 1 disable
1 : LPC bus buffer 1 enable
LPCEN2
LPC bus buffer 2 enable bit
0 : LPC bus buffer 2 disable
1 : LPC bus buffer 2 enable
LPCEN3
LPC bus buffer 3 enable bit
0 : LPC bus buffer 3 disable
1 : LPC bus buffer 3 enable
SYNCSEL1
Note: For LPC software reset, the bit will automatically return to “0” after writing “1”.
Fig.GF-6 LPC control register
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R W
M16C/6KA Group
LPC Bus Interface
Basic operation of LPC bus interface
The status transition of LPC bus interface is shown in Figure GF-7.
Setting steps for using LPC bus interface is explained below.
• Setting bit3 (LPC interface enable bit) of LPC control register ( address 02D616 ) to "1"
• Choosing which LPC bus buffer channel will be used
• Setting "1" to bits 4-7 (LPC bus buffer 0-3 enable bit) of LPC control register ( address 02D616 ).
• The 16-bit slave address of LPC bus buffer channel is defined by writing 16-bit slave address to LPC 1-3
address registers ( address 02D016 to 02D516 ). If channel 1-3 LPC bus buffer is chosen, set the address to
the corresponding address register.
• Selecting IBF/ OBE interrupt in data bus buffer control register0 ( address 02C816 )
• Selecting OBF output port in data bus buffer control register1 ( address 02C916 )
<1> Example of I/O writing cycle from HOST
Writing timing is shown in Figure GF-8.
The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the
_______________
rising edge of LCLK. Communication will start from LFRAME falling edge.
______________
• 1st cycle : When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start frame detecting.
_______________
• 2nd cycle : When LFRAME is "High", sending "001X2 " to LAD[3:0] for write frame detecting.
• From 3rd cycle to 6th cycle: These four cycles are detecting for 16 bits slave address.
3rd cycle: The slave address which is from host is written to slave address register [15:12] through LAD[3:0]
4th cycle: The slave address which is from host is written to slave address register [11:8] through LAD[3:0]
5th cycle: The slave address which is from host is written to slave address register [7:4] through LAD[3:0]
6th cycle: The slave address which is from host is written to slave address register [3:0] through LAD[3:0]
• 7th and 8th cycles are used for one data byte transfer.
7th cycle: The data which is from host is written to input data buffer[3:0] through LAD[3:0]
8th cycle: The data which is from host is written to input data buffer[7:4] through LAD[3:0]
• 9th and 10thcycles are for changing the communication direction from host→slave to slave→host
9th cycle: Host outputs "11112 " to LAD[3:0]
10thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction.
• 11th cycle: The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge.
• 12th cycle: The "11112 " is output to LAD[3:0]. The XA2 and IBF flag are set. IBF interrupt signal is generated.
• 13th cycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction.
During the host write period, the bit2 (A2) status of 16 bits slave address will be latched to XA2 flag. When 8
bits data from input data buffer are read out by slave CPU, the IBF flag will be cleared simultaneously.
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M16C/6KA Group
LPC Bus Interface
<2> Example for I/O reading cycle from HOST
Reading timing is shown in Figure GF-9.
The basic communication cycles of LPC I/O protocol are 13 cycles. The data of LAD[3:0] will be read by the
_______________
rising edge of LCLK. Communication will start from LFRAME falling edge.
_______________
• 1st cycle: When LFRAME is "Low", sending "00002 " to LAD[3:0] for communication start detecting.
_______________
• 2ndcycle: When LFRAME is "High", the host send "000X2 " on LAD[3:0] to inform the cycle type as I/O read.
• From 3rd cycle to 6thcycle: These four cycles are detecting for 16 bits slave address.
3rdcycle: The slave address which is from host is written to slave address register [15:12] throughLAD[3:0]
4thcycle: The slave address which is from host is written to slave address register [11:8] throughLAD[3:0]
5thcycle: The slave address which is from host is written to slave address register [7:4] throughLAD[3:0]
6thcycle: The slave address which is from host is written to slave address register [3:0] throughLAD[3:0]
• 7th and 8thcycles are used for changing the communication direction from host→slave to slave→host
7thcycle: Host is output "11112 " to LAD[3:0]
8thcycle: The LAD[3:0] will be set to Hi-Z by HOST to switch the communication direction.
• 9thcycle : The "00002 " (SYNC OK) is output to LAD[3:0] for acknowledge.
• 10th and 11thcycles are for output 8 bits data from output data buffer or output 8 bits data from status register.
10thcycle: Sending output data buffer [3:0] to LAD[3:0] or sending data of status register [3:0] to LAD[3:0]
11thcycle: Sending output data buffer [7:4] to LAD[3:0] or sending data of status register [7:4] to LAD[3:0].
• 12thcycle: The "11112 " is output to LAD[3:0]. The OBF flag is cleared and OBE interrupt signal is generated.
• 13thcycle: The LAD[3:0] will be set to Hi-Z by slave to switch the communication direction. OBF flag will be
set when 8 bits data are written to output data buffer by slave CPU.
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M16C/6KA Group
LPC Bus Interface
Data WR (I/O write cycle)
START
WR
16 BIT ADDRESS
DATA
TAR
SYNC
TAR
LCLK
LFRAME
(Note1)
LAD [3:0]
Input buffer
XA2 flag
IBF flag
Driven by the HOST
Driven by the SLAVE
Command WR (I/O write cycle)
START
WR
16 BIT ADDRESS
DATA
TAR
SYNC
TAR
LCLK
LFRAME
(Note1)
LAD [3:0]
Input buffer
XA2 flag
IBF flag
Driven by the HOST
Driven by the SLAVE
Note1 : LAD0 to LAD3 pins remain Hi-Z after transfer completion
Fig.GF-7 Data and Command write timing figure
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M16C/6KA Group
LPC Bus Interface
Data RD (I/O read cycle)
START
RD
16 BIT ADDRESS
TAR
SYNC
DATA
TAR
LCLK
LFRAME
(Note1)
LAD [3:0]
OBF flag
Driven by the HOST
Driven by the SLAVE
Status RD (I/O read cycle)
START
RD
16 BIT ADDRESS
TAR
SYNC
DATA
TAR
LCLK
LFRAME
(Note1)
LAD [3:0]
(Note2)
OBF flag
Driven by the HOST
Driven by the SLAVE
Note1 : LAD0 to LAD3 pins become Hi-Z after transfer completion.
Note2 : OBF flag does not change.
Fig.GF-8 Data and Status read timing figure
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page 138 of 266
1
1
OBF1
OBF2
OBF3
P45/OBF2
P46/OBF3
1
P44/OBF1
0
1
OBF01
P43/OBF01
O
O
O
O
O
OBF00
P40/OBF00
1
I
1
LCLK
P36/LCLK
0
I
1
LRESET
I
I/O
I/O
1
02C916
Bit 6
I/O
1
02C916
Bit 5
1
0
02C916
Bit 4
Input/
Output
P35/LRESET
LAD3
P33/LAD3
02C916
Bit 3
HOSTEN
control bit
1
LAD2
P32/LAD2
02C916
Bit 2
OBF3
output
enable bit
I/O
02C916
Bit 1
OBF1
OBF2
output
output
enable bit enable bit
1
1
02C916
Bit 0
02D616
Bit 3
OBF00
OBF01
output
output
enable bit enable bit
P34/LFRAME LFRAME
LAD1
LAD0
Name
P31/LAD1
P30/LAD0
Pin name
OBF0
output
enable bit
LPC
interface
enable bit
Table GF-2 Function explanation of the control input and output pins in LPC bus interface function
Status output signal.
OBF3 output.
Status output signal.
OBF2 output.
Status output signal.
OBF1 output.
Status output signal.
OBF01 output.
Status output signal.
OBF00 output.
LPC synchronous clock signal.
LPC reset signal.
LPC bus interface function is reset.
It is used for indicating the start of LPC cycle and
termination of abnormal communication cycle.
LPC bus used for transmitting and receiving address,
command and data between Host CPU and peripheral
devices.
Function
M16C/6KA Group
LPC Bus Interface
M16C/6KA Group
LPC Bus Interface
______________
Table GF-3 Conditions of LPC bus interface function induced by LRESET input
Pin name / Internal register
______________
______________
LRESET=“H”
LRESET=“L”
P30/LAD0
P31/LAD1
LPC bus interface
function(function is
P32/LAD2
P33/LAD3
select)
Note
I/O port
Pin
_________________
P34/LFRAME
_______________
P35/LRESET
I/O port
LPC bus interface function
P36/LCLK
P40/OBF00
I/O port
P43/OBF01
P44/OBF1
Internal register
P45/OBF2
P46/OBF3
OBF output is enable until
LRESET="L". A spike pulse may
be output to the port when the port
is already set to L output port and
OBF signal______________
is output to the port
just before LRESET is set to L.
______________
P42/GateA20
Input data bus buffer
unstable
Output data bus buffer
U flag 7,6,5,4,2
It can't be written by slave side.
It can be written and read by Initialization to "0" only for
DBBSTS0.
XA2 flag
slave side.
Initialization to "0"
IBF flag
Initialization to "0"
There is possibility to generate
IBF interrupt request.
OBF flag
Initialization to "0"
There is possibility to generate
OBE interrupt request.
LPCADH/L
It can be written and read by
slave side.
LPCCON
It can be written and read by
slave side.
GA20 circuit
Initialization
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M16C/6KA Group
LPC Bus Interface
GateA20 output function
The GateA20 pin (port P42) can be controlled by LPC interface function channel 0 in hardware.
Hardware GateA20 is sharing with P42 pin. Setting "1" to bit 0 of GateA20 control register enables the hardware GateA20 function. The default value of hardware GateA20 is "1".
The GateA20 control register is shown in Fig.GF-9.
When the host CPU writes "D1" command to address 006416, and then writes data to address 006016 in
succession, the value of bit 1 of the data will be output to GateA20 pin. The timing is shown in Fig.GF-10.
The GateA20 operation sequences are shown in Fig.GF-11, Fig.GF-12. As shown in the figures, there is no
change in input buffer full flag(IBF0) and no input buffer full(IBF) interrupt request, but the input data bus
buffer and XA2 flag are changed in these sequences.
The value of the GateA20 output pin will be held till the data next to D1 command is written in. P42 becomes
_____________
I/O port and the the value of GateA20 becomes "0" when LRESET input is "L". GateA20 will be initialized even
if the sequence is executed. However, the GateA20 enable bit will not be changed and GateA20 output pin
_____________
will be resumed after the LRESET input becomes "H".
GateA20 control register
AA
A
A
AA
AAA
AA
A
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
GA20CON
Address
002CA16
Reset
0016
Bit name
Bit Symbol
Function
GateA20 enable bit
GA20EN
R W
0 : P42 as GPIO
1 : Hardware GateA20 function enable
Reserved bit
Must be set to "0"
Nothing is assigned.
Meaningless in writing. "0" in reading.
Fig.GF-9 GateA20 control register
START
WRITE
16-bit address
DATA
TAR
SYNC
TAR
LCLK
LFRAME
LAD (3:0)
Previous value
GateA20 pin
Fig.GF-10 GateA20 output timing
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The value of bit 1 of the data
M16C/6KA Group
LPC Bus Interface
Sequence 1 (basic operation 1)
LPC communication
GateA20 pin
Write data
to 006016
Write D1
to 006416
Write FF
to 006416
Previous value
Bit 1 value of the data
IBF0 flag refresh
No
No
No
IBF interrupt request
No
No
No
Sequence 2 (basic operation 2)
LPC communication
GateA20 pin
Write data other
than FF and D1
to 006416
Write data
to 006016
Write D1
to 006416
Previous value
Bit 1 value of the data
IBF0 flag refresh
No
No
Yes
IBF interrupt request
No
No
Yes
Sequence 3 (basic operation 3)
LPC communication
GateA20 pin
Write data
to 006016
Write D1
to 006416
Write data
to 006016
Previous value
Bit 1 value of the data
IBF0 flag refresh
No
No
Yes
IBF interrupt request
No
No
Yes
Fig.GF-11 GateA20 operation sequence (1)
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M16C/6KA Group
LPC Bus Interface
Sequence 4 (re-trigger)
Write D1
to 006416
LPC communication
Write D1
to 006416
GateA20 pin
Write data
to 006016
Previous value
Bit 1 value of the data
IBF0 flag refresh
No
No
No
IBF interrupt request
No
No
No
Sequence 5 (cancel operation)
LPC communication
Write D1
to 006416
GateA20 pin
Previous value
Write data
other than
D1 to 006416
IBF0 flag refresh
No
Yes
IBF interrupt request
No
Yes
Sequence 6 (continuance operation)
LPC communication
GateA20 pin
Write data1
to 006016
Write D1
to 006416
Previous value
Write D1
to 006416
Write data2
to 006016
Bit 1 value of the data
The value of bit 1 of data 2
IBF0 flag refresh
No
No
No
No
IBF interrupt request
No
No
No
No
Fig.GF-12 GateA20 operation sequence (2)
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M16C/6KA Group
Serial Interrupt Output
Serial Interrupt Output
The serial interrupt output is the circuit that outputs the interrupt request to the host with serial interrupt
data format.
Tab.SI-1 shows the specification of serial interrupt output.
Table.SI-1 Specifications of serial interrupt output
Item
The factors of serial interrupt
The number of frame
Operation clock
Clock restart
Clock stop inhibition
OBF sync enable
Specification
The numbers of serial interrupt requests (numbers of channels) that can output simultaneously are 5 factors. Each interrupt factor of each channel is explained as
follows.
• Channel 0
(1) By setting “1” to IRQi request bit (bit 5, 6 i=1,12) of IRQ request register 0, the
interrupt request can be generated.
(2) Synchronized with OBF00 and OBF01 that are the host bus interface internal
signals, the serial interrupt request can be generated.
• Channel 1-3
(1) By setting “1” to IRQ request bit (bit 5) of IRQ request register 1-3, the interrupt
request can be generated.
(2) Synchronized with OBF1-3 that are the host bus interface internal signals, the
serial interrupt request can be generated.
• Channel 4
By setting “1” to IRQ request bit (bit 5) of IRQ request register 4, the interrupt request can be generated.
• Channel 0
(1) Setting the IRQ1 request bit (bit 5) of IRQ request register0 to “1” or detecting
OBF00, which is the host bus interface internal signal, selects Frame 1.
(2) Setting the IRQ12 request bit (bit 6) of IRQ request register0 to “1” or detecting
OBF01, which is the host bus interface internal signal, selects Frame 12.
• Channel 1-4
Selecting the frame select bit (bit 0-4) of IRQ request register1-4 selects Frame 1-15
or extend Frame 0-10.
The operation synchronized with LCLK (Max. 33MHz). (Note)
Setting the clock restart enable bit (bit 6) of serial interrupt control register0 to “1”
requests the clock restart if the clock has stopped or slowed down in serial interrupt
output.
Setting the clock stop inhibition bit (bit 5) of serial interrupt control register0 to “1”
requests the inhibition of clock stop if the clock tends to stop or slow down in serial
interrupt output.
Setting the OBF00, OBF01, OBF1-3 sync enable bit (bit 0-4) of serial interrupt control register0 to “1” enables the OBF synchronization.
Note: To enable LCLK, it is necessary to enable the LPC bus interface function.
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M16C/6KA Group
Serial Interrupt Output
internal data bus
Serial interrupt control register0
(address:02B016 )
b7 b6 b5 b4 b3 b2 b1 b0
Clock stop inhibiting enable
IRQ request register1 - 4
(address:02B316 , 02B416,
02B516 ,02B616)
IRQ request register0
(address:02B216 )
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
IRQ request 00,01
IRQ request 1 - 4
Clock restart enable
OBF sync enable
IRQ request 0 - 4
Serial interrupt enable
Internal signals
OBF00,OBF01,
OBF1 - OBF3
IRQ frame number 1 - 4
Serial interrupt request
Control circuit
IRQ request
0-4
Port control section
IRQ request
clear
Frame number
(CH0 - CH4)
SERIRQ
Serial interrupt output
Control circuit
Clock operation
Status & finish
acknowledge
Clock restart
request & start frame
start request
Clock monitor/
Control circuit
CLKRUN
LCLK
Reset selection
LRESET
b7 b6 b5 b4 b3 b2 b1 b0
PRST
Serial interrupt control register1(address:
02B116 )
f1
Internal data bus
Fig.SI-1 Serial interrupt block chart
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 144 of 266
M16C/6KA Group
Serial Interrupt Output
(1) Register explanation
Fig.SI-2 shows the configuration of IRQ request register0, Fig.SI-3 shows the configuration of
IRQ request register1-4, Fig.SI-4, SI-5 show the configurations of serial interrupt control register0,1 respectively.
● IRQ request register0 IRQR0
The serial interrupt request of Channel 0 is set by software.
•IRQ1 request bit IR0
Setting the bit to “1” generates the serial interrupt request (Frame 1).
By setting the OBF00 sync enable bit (bit 0) of the serial interrupt control register0 to “1”, the value
of IR0 is the same as that of OBF00, which is the host bus interface internal signal. When the
internal signal OBF00 is “1”, the serial interrupt is generated.
IR0 is cleared to “0” by writing “0” in software.
IR0 can not be cleared to “0” by software when the internal signal OBF00 is “1” if OBF00 sync
enable bit is set to “1”.
•IRQ12 request bit IR1
Setting the bit to “1” generates the serial interrupt request (Frame 12).
By setting the OBF01 sync enable bit (bit 1) of the serial interrupt control register0 to “1”, the value
of IR1 is the same with that of OBF01, which is the host bus interface internal signal. When the
internal signal OBF01 is “1”, the serial interrupt is generated.
IR1 is cleared to “0” by writing “0” in software.
IR1 can not be cleared to “0” by software when the internal signal OBF01 is “1” if OBF01 sync
enable bit is set to “1”.
AAAAAA
A
AAAAAA
A
IRQ request register0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol: IRQR0
Address: 02B216
Bit symbol
Bit name
Nothing is assigned.
Meaningless in writing, “0” in reading.
Function
IR0
IRQ1 request bit
0: No IRQ1 request
1: IRQ1 request
IR1
IRQ12 request bit
0: No IRQ12 request
1: IRQ12 request
Nothing is assigned.
Meaningless in writing, “0” in reading.
Fig.SI-2 Configuration of IRQ request register0
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
When reset: 0016
page 145 of 266
R W
M16C/6KA Group
Serial Interrupt Output
● IRQ request register i IRQRi (i=1-4)
The serial interrupt request of Channel 1-4 is set by software, or asserting frame is selected.
•IRQ request bit IR
Setting the bit to “1” generates the serial interrupt request.
By setting the OBFj sync enable bit (bit2-4, j=1-3) of the serial interrupt control register0 to “1”, the
value of IR is the same as that of OBFj, which is the host bus interface internal signal. When the
internal signal OBFj is “1”, the serial interrupt is generated.
IR is cleared to “0” by writing “0” in software.
IR can not be cleared to “0” by software when the internal signal OBFj is “1” if OBFj sync enable
bit is set to “1”.
● IRQ select bit IS0-4
The asserting frame is selected.
AA
A
A
AA
AAA
AA
A
IRQ request register1-4
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IRQR1
IRQR2
IRQR3
IRQR4
Bit symbol
IS0
Address
02B316
02B416
02B516
02B616
When reset
0016
0016
0016
0016
Bit name
IRQ Frame
0 0 0 0 0 : No SERIRQ output
0 0 0 0 1 : Frame 1
0 0 0 1 0 : Frame 2
0 0 0 1 1 : Frame 3
0 0 1 0 0 : Frame 4
0 0 1 0 1 : Frame 5
0 0 1 1 0 : Frame 6
0 0 1 1 1 : Frame 7
0 1 0 0 0 : Frame 8
0 1 0 0 1 : Frame 9
0 1 0 1 0 : Frame 10
0 1 0 1 1 : Frame 11
0 1 1 0 0 : Frame 12
0 1 1 0 1 : Frame 13
0 1 1 1 0 : Frame 14
0 1 1 1 1 : Frame 15
1 0 0 0 0 : Can’t select
1 0 0 0 1 : Can’t select
1 0 0 1 0 : Can’t select
1 0 0 1 1 : Can’t select
1 0 1 0 0 : Can’t select
1 0 1 0 1 : Extend Frame 0
1 0 1 1 0 : Extend Frame 1
1 0 1 1 1 : Extend Frame 2
1 1 0 0 0 : Extend Frame 3
1 1 0 0 1 : Extend Frame 4
1 1 0 1 0 : Extend Frame 5
1 1 0 1 1 : Extend Frame 6
1 1 1 0 0 : Extend Frame 7
1 1 1 0 1 : Extend Frame 8
1 1 1 1 0 : Extend Frame 9
1 1 1 1 1 : Extend Frame 10
IRQ request bit
0: No IRQ request
1: IRQ request
IS1
IS2
IS3
IS4
IR
Nothing is assigned.
Meaningless in writing, “0” in reading.
Fig.SI-3 Configuration of IRQ request register1-4
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REJ03B0100-0100Z
page 146 of 266
Function
Frame select bit
b4b3b2b1b0
R W
M16C/6KA Group
Serial Interrupt Output
● Serial interrupt control register0 SERCON0
The operation condition of serial interrupt is set.
•OBFi sync enable bit SENi (i=00,01,1-3)
By setting the bit to "1", sync with the OBFi of host interface, the serialized interrupt can be
generated.
•Clock stop inhibition bit SUPEN
Setting the bit to “1” will request the inhibition of clock if the clock tends to stop or slow down in
serial interrupt request.
•Clock restart enable bit RUNEN
Setting the bit to “1” requests the clock restart during the clock stop or clock slow down in serial
interrupt request.
•Serial interrupt enable bit IRQEN
__________ _______________
0: SERIRQ, PRST, CLKRUN are I/O ports.
__________ _______________
1: SERIRQ, PRST, CLKRUN are serial interrupt function ports.
Serial interrupt control register0
AA
AAA
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
SERCON0
Bit symbol
Address
02B016
When reset
0016
Bit name
Function
SEN00
OBF00 sync enable bit
0: Sync inhibition
1: Sync enable
SEN01
OBF01 sync enable bit
0: Sync inhibition
1: Sync enable
SEN1
OBF1 sync enable bit
0: Sync inhibition
1: Sync enable
SEN2
OBF2 sync enable bit
0: Sync inhibition
1: Sync enable
SEN3
OBF3 sync enable bit
0: Sync inhibition
1: Sync enable
Clock stop inhibition bit
0: Stop control operation
1: No stop control operation
Clock restart enable bit
0: No clock restart
1: Clock restart
Serial interrupt enable bit
0: Serial interrupt inhibition
1: Serial interrupt enable
SUPEN
(Note 1)
RUNEN
(Note 1)
IRQEN
(Note 2)
R W
_______________
Note 1 : When IRQEN is set to "1", if either SUPEN or RUNEN is set to "1", P46 will function as CLKRUN I/O and the output type
is N channel open drain.
__________
__________
Note 2 : When the bit is set to "1", P43, P45 function as SERIRQ, PRST respectively. Even the bit is set to "1", P45/PRST can
function as GPIO if bit 1 of serial interrupt control register 1 (address 02B116) is set to "1".
Fig.SI-4 Configuration of serial interrupt control register0
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REJ03B0100-0100Z
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M16C/6KA Group
Serial Interrupt Output
● Serial interrupt control register1 SERCON1
The register is for setting the pins of serial interrupt.
•Reset selection bit RSEL
__________
0: The input of PRST is the reset signal.
______________
1: The input of LRESET is the reset signal. (Note1)
__________
Note 1: The PRST pin becomes I/O port if setting the bit to “1”.
AAA
AA
A
AAAA
AA
Serial interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
0
0
Symbol
SERCON1
Bit symbol
Address
02B116
Bit name
Reset selection bit
0 : Select PRST pin.
1 : Select LRESET pin.
Must be “0”.
Reserved bit
OBF0MRG
OBF0 mergence bit
0 : OBF00 and OBF01 are
independent.
1 : OBF00 and OBF01 are merged
(logical OR).
OBF0CLR
OBF0 cut sync bit
0: Normal operation
1: SEN00, SEN01 is cleared
when OBF0 is cleared.
Reserved bit
Fig.SI-5 Configuration of serial interrupt control register1
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Function
Must be “0”.
Reserved bit
RSEL
When reset
0016
page 148 of 266
Must be “0”.
R W
M16C/6KA Group
Serial Interrupt Output
•OBF0 mergence function
By setting the bit to “1”, the signal, which is logically OR by OBF00 and OBF01 signals from LPC
bus interface, will output to IRQ1 and IRQ12 of serial interrupt circuit.
With the function, the IRQ1 and IRQ12 request bits can be cleared simultaneously by H/W at the
read of output data buffer from system if both IRQ1 and IRQ12 request bits are set in the case
that IRQ1 request bit (or IRQ12 request bit) is set after that of IRQ12 (or IRQ1) because of the
overwrite to the output data buffer.
•OBF0 sync inhibitant function
By setting bit 4 of serial interrupt control register 1 (OBF cut sync bit), simultaneously after the
read of OBF0, the OBF0 sync function can be inhibited.
If the bit is set to “1”, simultaneously after the clear of OBF00 or OBF01, SEN00 (OBF00 sync
enable bit) and SEN01 (OBF01 sync enable bit) bits are cleared (sync inhibitation) by H/W.
The configuration of serial interrupt control register 1 and the switching circuit controlled by
OBF0MRG, OBF0CLR are shown in Fig. SI-5, Fig. SI-6 respectively.
OBF0CLR
OBF0MRG
OBF0
RD
OBF0
“0”
RD/WR
OBF0001
SEN00
To IRQ1 request bit of
serial interrupt circuit
WR
IR0
“1”
OBF0 clear signal
(Triggered by host read)
“0”
OBF0SEL
OBF0001
“1”
SEN01
RD/WR
To IRQ12 request bit of
serial interrupt circuit
WR
IR0
RD
Fig.SI-6 The switching circuit controlled by OBF0MRG, OBF0CLR
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
Serial Interrupt Output
● Serial interrupt control register2 SERCON2
The polarity of serial interrupt output can be selected by bit 0 to bit 5 of serial interrupt control register 2.
When the bit is set to “0”:
If there is a request, Hiz-Hiz-Hiz
If there is no request, L-H-Hiz
When the bit is set to “1”:
If there is a request, L-H-Hiz
If there is no request, Hiz-Hiz-Hiz
Only the default value of bit 4 (serial interrupt polarity bit 3) of serial interrupt control register 2
after reset is “1”.
Fig.SI-7 shows the configuration of serial interrupt control register 2.
AA
A
AA
A
AAAA
AA
Serial interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SERCON2
Bit symbol
Address
02B716
When reset
1016
Bit name
Function
SERSEL00
Serial interrupt polarity selection
bit 00
SERSEL01
Serial interrupt polarity selection
bit 01
SERSEL1
Serial interrupt polarity selection
bit 1
SERSEL2
Serial interrupt polarity selection
bit 2
SERSEL3
Serial interrupt polarity selection
bit 3
SERSEL4
Serial interrupt polarity selection
bit 4
Nothing is assigned.
Meaningless in writing. “0” in reading.
Note: “0”
“1”
: If there is a request
If there is no request
: If there is a request
If there is no request
Hiz-Hiz-Hiz
L-H-Hiz
L-H-Hiz
Hiz-Hiz-Hiz
Fig.SI-7 The configuration of serial interrupt control register 2
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 150 of 266
Select serial interrupt
output polarity of IRQ1 in
channel 0. (Note)
Select serial interrupt
output polarity of IRQ12
in channel 0. (Note)
Select serial interrupt
output polarity of IRQ in
channel 1. (Note)
Select serial interrupt
output polarity of IRQ in
channel 2. (Note)
Select serial interrupt
output polarity of IRQ in
channel 3. (Note)
Select serial interrupt
output polarity of IRQ in
channel 4. (Note)
R W
M16C/6KA Group
Serial Interrupt Output
(2) The operation of serial interrupt
A cycle operation of serial interrupt starts with start frame and finishes with stop frame. There are
2 kinds of operation mode: continuous mode and quiet mode. The next operation mode is judged
by monitoring the length of stop frame sent from host side.
● The timing of serial interrupt cycle
Fig.SI-8 shows an example of basic timing of serial interrupt cycle.
➀ Start frame
The start frame will be detected if the SERIRQ remains “L” in 4-8 clock cycles.
➁IRQ data frame
Each IRQ data frame is 3 clock cycles.
•Channel 0-2,4:If the IRQ request bit is “0”, then the SERIRQ is driven to “L” during the 1st clock
cycle of the corresponding data frame, to “H” during the 2nd clock cycle, to high impedance during
the 3rd clock cycle. If the IRQ request bit is “1”, then the SERIRQ is high impedance during all of
the 3 clock cycles.
•Channel 3:If the IRQ request bit is “0”, then the SERIRQ is high impedance during all of the 3
clock cycles. If the IRQ request bit is “1”, then the SERIRQ is driven to “L” during the 1st clock
cycle of the corresponding data frame, to “H” during the 2nd clock cycle, to high impedance during
the 3rd clock cycle.
Serial Interrupt output polarity of each channel can changed by Serial Interrupt polarity selection
bit i (i=00, 01, 1, 2, 3, 4) of Serial Interrupt control register 2.
③Stop frame
The stop frame will be detected if the SERIRQ remains “L” in 2 or 3 clock cycles. The next operation mode is quiet mode if the length of “L” is 2 clock cycles, the continuous mode if the length is
3 clock cycles.
Start frame
frame 0
frame 1
frame 15
IOCHK
Stop frame
Clock
SERIRQ
Driver source
System side
Device side
Fig.SI-8 Basic timing of serial interrupt cycle
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 151 of 266
Device side
System side
to the next cycle
M16C/6KA Group
Serial Interrupt Output
● Operation mode
Fig.SI-9 shows an example of timing of continuous mode, Fig.SI-10 shows that of quiet mode.
➀Continuous mode
__________
_______________
After reset, at the rising edge of PRST (or LRESET) or the length of the last stop frame of serial
interrupt cycle being 3 clock cycles, it will be the continuous mode.
After receiving the start frame (Note 1), the Frame 1, Frame 12 or frames selected in each channel will be asserted.
Note 1: If the length of “L” is less than 4 clock cycles or more than 9 clock cycles, the start frame
will not be detected and the next start (the falling edge of SERIRQ) is waited.
Start frame (Note1)
IRQ0 frame
IRQ1 frame
IRQ2 frame
IRQ3 frame
Clock
SERIRQ line
System•SERIRQ output
Device•SERIRQ output
Driver source
System side
Device side
Note1 . The start frame is set to 4 clock as setting exemple
Fig.SI-9 Timing diagram of continuous mode
➁Quiet mode
At clock stop or clock slow down, or the length of the last stop frame of serial interrupt cycle being
2 clock cycles, it will be the quiet mode.
In this mode the SERIRQ is driven to “L” in the 1st clock cycle by device and after the receiving of
the rest start frame (Note 1) from host, the IRQ1 Frame , IRQ12 Frame or frames selected in each
channel will be asserted.
Note 1: If the sum of length of “L” that is driven by the device in the 1st clock cycle and by the host
in the rest clock cycles is within 4-8 clock cycles, the start frame will be detected.
If the sum of length of “L” is less than 4 clock cycles or more than 9 clock cycles, the start
frame will not be detected and the next start (the falling edge of SERIRQ) is waited.
Start frame (Note1)
IRQ0 frame
IRQ1 frame
LCLK
SERIRQ line
System•SERIRQ output
Device•SERIRQ output
Driver source
Device side
Device side
System side
Note1 . The start frame is set to 4 clock as setting example
Fig.SI-10 Timing diagram of quiet mode
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 152 of 266
IRQ2 frame
IRQ3 frame
M16C/6KA Group
Serial Interrupt Output
(3) Clock restart/ stop inhibition request
_______________
Asserting the CLKRUN signal can request to restart or maintain the clock which stops or slows
down or request the host to tend to stop or slow down.
Fig.SI-11 shows an example of timing of clock restart request, Fig.SI-12 shows an example of
timing of clock stop inhibition request.
➀Clock restart operation
Setting the clock restart bit of serial interrupt control register0 to “1” will request the clock restart if
the clock has slowed down or stopped at serial interrupt request.
LCLK
CLKRUN line
System•CLKRUN
Restart frame
Device•CLKRUN
Start frame
SERIRQ line
System•SERIRQ
Device•SERIRQ
f1
Serial interrupt request
Internal Interrupt restart
request signal
Fig.SI-11 Timing diagram of clock restart request
➁Clock stop inhibition request
Setting the clock stop inhibition bit of serial interrupt control register0 to “1” will request the inhibition of clock stop if the clock tends to stop or slow down during all the period of serial interrupt
output.
Clock
CLKRUN line
System•CLKRUN
Inhibition
request
Device•CLKRUN
A cycle of serial interrupt
SERIRQ line
Serial interrupt request
Internal Interrupt Inhibition
request signal
Fig.SI-12 Example of timing of clock stop inhibition request
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communication circuit based on Philips I2C-BUS data transfer
format. 3 independent channels, with both arbitration lost detection and a synchronous functions, are built in
for the multi-master serial communication. Fig.GC-1 shows a block diagram of the multi-master I2C-BUS
interface and Table.GC-1 lists the multi-master I2C-BUS interface functions. The multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C
control register 1, I2C control register 2, the I2C status register, the I2C start/stop condition control register
and other control circuits.
Table.GC-1 Multi-master I2C-BUS interface functions
Item
Format
Communication mode
SCL clock frequency
*VIIC=I2C
Function
Based on Philips I2C-BUS standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Based on Philips I2C-BUS standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1kHz to 400kHz (at VIIC = 4MHz)
system clock
✽ : Purchase of Renesas Technology Corporation's I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev.1.00 Jul 16, 2004
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page 154 of 266
S3D
ICK1
b7
Rev.1.00 Jul 16, 2004
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b0
Fig.GC-1 Block diagram of multi-master I2C-BUS interface
2
clock
(SCL)
Serial
Noise
elimination
circuit
I C start/stop condition
control register
Clock
control
circuit
circuit
BB
circuit
b0
TOE
I2C system clock
(VIIC)
Clock division
ICK1,ICK0=1,1
ICK1,ICK0=0,0
ICK1,ICK0=0,1
ICK1,ICK0=1,0
1/2
1/2
1/2
1/2
f1
10BIT ALS
SAD
Bit count
ES0 BC2 BC1 BC0
b0
I 2 C status register
I C control register 0
S1D
2
b0
Interrupt request signal
(I2CIRQ)
AL AAS AD0 LRB
ICCK(External clock)
b7
S1
TISS
2 S2
I C clock control register
Interrupt
generating
circuit
MST TRX BB PIN
b7
b0
System clock select circuit
Timeout detection
circuit
TOSEL TOF
Internal data bud
b0
FAST
ACK MODE
CCR4 CCR3 CCR2 CCR1 CCR0
BIT
S4D
2
I C control register 2
I2C data shift register
Address comparator
SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
I2C address register
b7
S0
b7
S0D
SAD6
b7
ACK
Data
control
circuit
Noise
elimination
circuit
AL
Interrupt request signal
(SCLSDAIRQ)
SIM
Interrupt
generating
circuit
WIT
STSP
SIS SIP SSC4 SSC3 SSC2 SSC1 SSC0
SEL
S2D
(SDA)
Serial data
ICK0 SCLM SDAM
I2C Control register 1
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
I2C Data Shift Register
The I2C data shift register (address 032016, 033016, 031016) is an 8-bit shift register to store receiving data
and write transmission data. When transmit data is written into this register, it is transferred to the outside
from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register
are shifted by one bit to the left. When data is received, it is input to this register from bit 0 in synchronization
with the SCL clock, and each time one-bit data is input, the data of this register are shifted by one bit to the
left. The timing of storing received data to this register is shown in figure GC-3.The I2C data shift register is
in a write enable status only when the I2C-BUS interface enable bit (ES0 bit : bit 3 of address 032316,
033316, 031316) of the I2C control register 0 is “1”. The bit counter is reset by a write instruction to the I2C
data shift register. When both the ES0 bit and the MST bit of the I2C status register (address 032816, 033816,
031816) are “1”, the SCL is output by a write instruction to the I2C data shift register. Reading data from the
I2C data shift register is always enabled regardless of the value of ES0 bit.
AAAAAA
AAAAAA
2
I C data shift register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S0i(i=0,1,2)
Address
032016,033016,031016
When reset
--
R W
Function
Transmission data /receiving data are stored.
In the master transmission mode, the start condition/ stop condition are
triggered by writing data to the register (refer to the section on the method to
generate the start/stop condition). The transmission/receiving are started
synchronized with SCL.
Note
Note The write is only enabled when bus interface enable bit (ES0 bit) is "1".
Because the register is used both for storing transmission data/receiving data, the
transmission data should be written after the receiving data are read out before
writing transmission data to this register.
Fig.GC-2 I2C data shift register
SCL
SDA
tdfil
tdfil : Noise elimination circuit delay time
Internal SCL
1 to 2 VIIC cycle
Internal SDA
tdfil
tdsf : Shift clock delay time
1 VIIC cycle
tdsft
Shift clock
Storing data at shift clock rising edge.
Fig.GC-3 The timing of receiving data stored to I2C data shift register
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page 156 of 266
MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
I2C Address Register
The I2C address register (address 032216, 033216, 031216) consists of a 7-bit slave address and a read/
write bit. In the addressing mode, the slave address written in this register is compared with the address
data to be received immediately after the START condition is detected.
•Bit 0: Read/write bit (RBW)
This is not used in the 7-bit addressing mode. In the 10-bit addressing mode, the first byte address data to
be received are compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
•Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode or the 10-bit addressing
mode, the address data transmitted from the master is compared with the contents of these bits.
AA
A
AA
A
AAAA
AA
2
I C address register
b7
b6
b5
b4
b3
b2
b1
Symbol
S0Di(i=0,1,2)
b0
Bit Symbol
Address
032216,033216,031216
Bit name
When reset
000000002
Function
RBW
Read/Write bit
This bit is using for comparing
with receiving address data in the
10-bit address mode. (Note)
SAD0
Slave address
For comparing with received
address data
SAD1
SAD2
SAD3
SAD4
SAD5
SAD6
Note.The RBW bit is cleared to "0" automatically when stop condition is detected
Fig.GC-4 I2C address register
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page 157 of 266
R
W
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
I2C Clock Control Register
The I2C clock control register 0,1 (address 032416, 033416, 031416) is used to set ACK control, SCL mode
and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table GC-2.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0”, the standard clock mode is selected. When the bit
is set to “1” , the high-speed clock mode is selected. When connecting to the bus with the high-speed mode
I2C-BUS standard (maximum 400 kbits/s), set 4 MHz or more to I2C system clock(VIIC).
•Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock is generated. When this bit is set to “0”, the ACK return mode
is selected and SDA goes to “L” at the occurrence of an ACK clock. When the bit is set to “1”, the ACK
nonreturn mode is selected. The SDA is held in the “H” status at the occurrence of an ACK clock. However,
when the slave address agrees with the address data in the reception of address data at ACK BIT = “0”, the
SDA is automatically made “L” (ACK is returned). If there is a disagreement between the slave address and
the address data, the SDA is automatically made “H” (ACK is not returned).
*ACK clock: Clock for acknowledgment
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which responses to the data transferring. When this bit is set
to “0”, the no ACK clock mode is selected. In this case, no ACK clock occurs after data transmission. When
the bit is set to “1”, the ACK clock mode is selected and the master generates an ACK clock at the completion of each 1-byte data transfer. The device for transmitting address data and control data releases the SDA
at the occurrence of an ACK clock (makes SDA “H”) and receives the ACK bit generated by the data receiving
device.
Note: Except for ACK bit (ACKBIT), do not write data into the I2C clock control register during transfer.
If data is written during transfer, the I2C clock generator is reset, so that data cannot be transferred
normally.
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MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
AAA
AA
A
AAAA
AA
2
I C clock control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S2i(i=0,1,2)
Bit Symbol
CCR0
Address
032416,033416,031416
Bit name
When reset
000000002
Function
SCL frequency control bits
Refer to table.GC-2
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock mode
ACK bit
0 : ACK is returned
1 : ACK is not returned
ACK clock bit
0 : No ACK clock
1 : ACK clock
CCR1
CCR2
CCR3
CCR4
FAST
MODE
ACK BIT
ACK
Fig.GC-5 I2C clock register
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R W
MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
Table.GC-2 Set values of I2C clock control register and SCL frequency
Setting value of CCR4 to CCR0
CCR4 CCR3 CCR2 CCR1 CCR0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
→
→
→
→
→
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
SCL frequency (at VIIC=4MHz, unit : kHz) (Note1)
Standard clock mode
High-speed clock mode
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
- (Note2)
333
- (Note2)
250
100
400 (Note3)
83.3
166
500 / CCR value
1000 / CCR value
(Note3)
(Note3)
17.2
34.5
16.6
33.3
16.1
32.3
Notes 1:Duty of SCL clock output is 50 %. The duty becomes 35 to 45 % only when the high-speed clock
mode is selected and CCR value = 5 (400 kHz, at V IIC = 4 MHz). “H” duration of the clock
fluctuates from –4 to +2 machine cycles in the standard clock mode, and fluctuates from –2 to +2
machine cycles in the high-speed clock mode. In the case of negative fluctuation, the frequency
does not increase because “L” duration is extended instead of “H” duration reduction. These are
value when SCL clock synchronization by the synchronous function is not performed. CCR value
is the decimal notation value of the SCL frequency control bits CCR4 to CCR0.
2:Each value of SCL frequency exceeds the limit at VIIC = 4 MHz or more. When using these
setting value, use VIIC = 4 MHz or less. Refer to I2 C system clock selection bits (bit 6, 7 of
I 2C control register 1) on VIIC.
3:The data formula of SCL frequency is described below:
VIIC/(8 X CCR value) Standard clock mode
VIIC/(4 X CCR value) High-speed clock mode (CCR value ≠ 5)
VIIC/(2 X CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of VIIC frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed clock
mode to the SCL frequency by setting the SCL frequency control bits CCR4 to CCR0.
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
I2C Control Register 0
The I2C control register 0 (address 032316, 033316, 031316) of channel 0, 1 controls data communication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. The I2C interrupt request
signal occurs immediately after the number of count specified with these bits (ACK clock is added to the
number of count when ACK clock is selected by ACK bit (bit 7 of address 032416, 033416, 031416)) have
been transferred, and BC0 to BC2 are returned to “0002”.
Also when a START condition is detected, these bits become “0002” and the address data is always transmitted and received in 8 bits.
•Bit 3: I2C interface enable bit (ES0)
This bit enables to use the multi-master I2C-BUS interface. When this bit is set to “0”, the interface is disabled
and the SDA and the SCL become high-impedance. When the bit is set to “1”, the interface is enabled.
When ES0 = “0”, the following is performed.
1)Set MST = “0”, TRX = “0”, PIN = “1”, BB =“0”, AL = “0”, AAS = “0”, and AD0 = “0”, of I 2C status
register (Address : 032816, 033816, 031816)
2)Writing data to I2C data shift register (Address : 032016, 033016, 031016) is inhibited.
3)The TOF bit of I2C control register (Address : 032716, 033716, 031716) is cleared to “0”
4)I2C system clock (VIIC) is stopped and the interval counter, flags are initialized.
•Bit 4: Data format selection bit (ALS)
This bit decides if the recognition of slave address should be processed. When this bit is set to “0”, the
addressing format is selected, so that address data will be recognized. The transfer will be processed only
when a comparison is matched between the salve address and the address data or a general call is received
(refer to the item of bit 1 of I2C status register: general call detection flag). When this bit is set to “1”, the free
data format is selected, so that slave address will not be not recognized.
•Bit 5: Addressing format selection bit (DBIT SAD)
This bit selects a slave address specification format. When this bit is set to “0”, the 7-bit addressing format
is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address
032216, 033216, 031216) are compared with address data. When this bit is set to “1”, the 10-bit addressing format is selected, and all the bits of the I2C address register are compared with address data.
•Bit 6: I2C-BUS interface reset bit (IHR)
The bit is used to reset I2C-BUS interface circuit in the case that the abnormal communication occurs.
When the ES0 bit is“1” (I2C-BUS interface is enabled), writing“1” to the IHR bit makes a H/W reset.
Flags are processed as follows:
1)Set MST = “0”, TRX = “0”, PIN = “1”, BB =“0”, AL = “0”, AAS = “0”, and AD0 = “0”, of I 2 C status
register (Address : 032816, 033816, 031816)
2)The TOF bit of I2C control register (Address : 032716, 033716, 031716) is cleared to “0”
3)The interval counter, flags are initialized.
After writing“1” to IHR bit, the circuit reset processing will be finished in Max. 2.5 VIIC cycles and IHR bit will
be automatically cleared to “0”. Fig.GC-6 shows the reset timing.
•Bit 7: I2C-BUS interface pin input level selection bit
This bit selects the input level of the SCL and SDA pins of the multi-master I2C-BUS interface. When this bit is
set to“1” the P60, P61/P62, P63/P76, P77 will become SMBus input level.
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MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
The signal of writing "1" to IHR bit
IHR bit
The reset signal to I2 C-BUS interface circuit
2.5 VIIC cycles
Fig.GC-6 The timing of reset to the I2C-BUS interface circuit
I 2 C control register 0
AAA
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S1Di(i=0,1,2)
Address
032316,033316,031316
Bit Symbol
Bit name
b2
0
0
0
0
1
1
1
1
ES0
I 2C-BUS interface
enable bit
0 : Disable
1 : Enable
ALS
Data format selection bit
0 : Addressing format
1 : Free data format
DBIT
SAD
Addressing format
selection bit
0 : 7-bit addressing format
1 : 10-bit addressing format
IHR
I2 C-BUS interface reset bit
0 : Release of reset (auto)
1 : Reset
BC1
BC2
TISS
Note
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Function
Bit counter
(Number of transmitting/
receiving bits)
BC0
Fig.GC-7 I2C control register
When reset
000000002
2
I C-BUS interface pin
input level selection bit
b1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
(Note)
:
:
:
:
:
:
:
:
8
7
6
5
4
3
2
1
0 : I 2 C-BUS input
1 : SMBUS input
In the following status, the bit counter will be cleared automatically
•Start condition/stop condition is detected
•Right after the completion of 1 byte data transmission
•Right after the completion of 1 byte data receiving
R W
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
I2C Status Register
The I2C status register (address 032816, 033816, 031816) controls the I2C-BUS interface status. The loworder 6 bits are read-only if it is used for status check. The high-order 2 bits can be both read and written.
Regarding to the function of writing to the low-order 6 bits, refer to the method of start condition/stop condition generation described later.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK
is returned when an ACK clock occurs, the LRB bit is set to “0”. If ACK is not returned, this bit is set to “1”.
Except in the ACK mode, the last bit value of received data is input. The bit will be “0” by executing a
write instruction to the I2C data shift register (address 032016, 033016, 031016).
•Bit 1: General call detecting flag (AD0)
When the ALS bit is “0”, this bit is set to “1” when a general call* whose address data is all “0” is received in
the slave mode. By a general call of the master device, every slave device receives control data after the
general call. The AD0 bit is set to “0” by detecting the STOP condition, START condition, or ES0 is“0”, or
reset.
*General call: The master transmits the general call address “0016” to all slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the ALS bit is “0”.
1)In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the
following conditions:
• The address data, which following the start conduction, is same with upper bits data of I 2C address
register(Address 032216, 033216, 031216)
• A general call is received.
2)In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the
following condition:
• When the address data is compared with the I2C address register (8 bits consisting of slave address and
RBW bit), the first bytes agree.
3)This bit is set to “0” by executing a write instruction to the I2C data shift register (address 032016, 033016,
031016) when ES0 is set to “1”. The bit is also set to “0” when ES0 is set to “0” or when reset.
•Bit 3: Arbitration lost* detecting flag (AL)
In the master transmission mode, when the SDA is made “L” by any other device, arbitration is judged to have
been lost, so that this bit is set to “1”. At the same time, the TRX bit is set to “0”. Immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0”. The arbitration lost can be
detected only in the master transmission mode. When arbitration is lost during slave address transmission,
the TRX bit is set to “0” and the reception mode is set. Consequently, it becomes possible to detect the
agreement between its own slave address and address data transmitted by another master device. The bit is
cleared to “0” if writing to I2C data shift register (address 032016, 033016, 031016) when ES0 is “1”.
The bit is also cleared to “0” when ES0 is set to “0” or when reset.
*Arbitration lost: The status in which communication as a master is disabled.
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
•Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. After each byte data is transmitted, the PIN bit changes from
“1” to “0”. At the same time, an I2C interrupt request signal occurs to the CPU. The PIN bit is set to “0”
synchronized with the falling edge of the last internal transmitting clock (including the ACK clock) and an
interrupt request signal occurs synchronized with the falling edge of the PIN bit. When the PIN bit is “0”, the
SCL is kept in the “0” state and clock generation is disabled. In the ACK clock enable mode, if WIT bit (bit 1
of I2C control register 1) is set to “1”, synchronized with the falling edge of last bit clock and ACK clock, PIN
bit becomes to “0” and I2C interrupt request is generated (Refer to the description on bit 1 of I2C control
register 1: the data reception completion interrupt enable bit). Fig.GC-9 shows the timing of I2C interrupt
request generation. The bit is read-only, the value should be “0” in writing.
The PIN bit is set to “0” in one of the following condition:
•Executing a write instruction to the I2C data shift register (address 032016, 033016, 031016).
•Executing a write instruction to the I2C clock control register (Address : 032416, 033416, 031416)
(only when WIT is “1” and internal WAIT flag is “1”)
•When the ES0 bit is “0”
•At reset
The PIN bit is set to “0” in one of the following condition:
•Immediately after the completion of 1-byte data transmission (including arbitration lost is detected)
•Immediately after the completion of 1-byte data reception
•In the slave reception mode, with ALS = “0” and immediately after the completion of slave address agreement
or general call address reception
•In the slave reception mode, with ALS = “1” and immediately after the completion of address data reception
•Bit 5: Bus busy flag (BB)
This bit indicates the in-use status the bus system. When this bit is set to “0”, bus system is not busy and a
START condition can be generated. The BB flag is set/reset by the SCL, SDA pins input signal regardless of
master/slave. This flag is set to “1” by detecting the start condition, and is set to “0” by detecting the stop
condition. The condition of the detecting is set by the start/stop condition setting bits (SSC4–SSC0) of the
I2C start/stop condition control register (address 032516, 033516, 031516). When the ES0 bit (bit 3) of the I2C
control register (address 032316, 033316, 031316) is “0” or reset, the BB flag is set to “0”. For the writing
function to the BB flag, refer to the sections “START Condition Generating Method” and “STOP Condition
Generating Method” described later.
•Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides a direction of transfer for data communication. When this bit is “0”, the reception mode is
selected and the data from a transmitting device is received. When the bit is “1”, the transmission mode is
selected and address data and control data are output onto the SDA synchronized with the clock generated on the SCL. This bit can be set/reset by software or hardware. This bit is set to “1” by hardware in the
following condition:
In slave mode with ALS = “0”, if the AAS flag is set to “1” after the address data reception and the received
___
R/W bit is “1”.
This bit is set to “0” by hardware in one of the following conditions:
•When arbitration lost is detected.
•When a STOP condition is detected.
•When a start condition is prevented by the start condition duplication preventing function (Note).
•When a start condition is detected with MST = “0”.
•When ACK non-return is detected with MST = “0”.
•When ES0 = “0”.
•At reset
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MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
•Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0”, the slave is
specified, so that a START condition and a STOP condition generated by the master are received. The data
communication is performed synchronized with the clock generated by the master. When this bit is “1”, the
master is specified and a START condition and a STOP condition are generated.
Additionally, the clocks required for data communication are generated on the SCL.
This bit is set to “0” by hardware in one of the following conditions.
•Immediately after the completion of 1-byte data transfer when arbitration lost is detected.
•When a STOP condition is detected.
•Writing a start condition is prevented by the start condition duplication preventing function (Note).
•At reset
Note: START condition duplication preventing function The MST, TRX, and BB bits is set to “1” at the same
time after confirming that the BB flag is “0” in the procedure of a START condition occurrence.
However, when a START condition by an other master device occurs and the BB flag is set to “1”
immediately after the contents of the BB flag is confirmed, the START condition duplication preventing function makes the writing to the MST and TRX bits invalid. The duplication preventing function
becomes valid from the rising of the BB flag to reception completion of slave address. Refer to the
method on the start condition generation in detail.
2
AAAA
I C status register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S1i(i=0,1,2)
Bit symbol
LRB
Address
032816,033816,031816
When reset
0001000X2
Bit name
Last receive bit
Function
R W
0 : Last bit = "0"
1 : Last bit = "1"
(Note1)
AD0
General call detecting flag
0 : No general call detected
1 : General call detected
(Note1)
AAS
Slave address comparison flag
0 : Address disagreement
1 : Address agreement
(Note1)
AL
Arbitration lost detection flag
0 : Not detected
1 : Detected
(Note1)
PIN
I 2 C-BUS interface interrupt
request bit
BB
TRX
MST
Bus busy flag
Communication mode
specification bits
0 : Interrupt request issued
1 : No interrupt request issued
0 : Bus free
1 : Bus busy
b7
0
0
1
1
b6
0 : Slave receive mode
1 : Slave transmit mode
0 : Master receive mode
1 : Master transmit mode
Note1.This bit is read only if it is used for the status check.
How to write this bit, please refer to start condition/stop condition generating
method.
Note2.The bit can be read and only can be written with "0" by software.
Note3.Refer to the method of start condition generation on how to write these bits.
How to write this bit, please refer to start condition/stop condition generating
method.
Fig.GC-8 I2C status register
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(Note2)
(Note1)
(Note3)
(Note3)
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
SCL
PIN flag
I2CIRQ
Fig.GC-9 Interrupt request signal generating timing
Rev.1.00 Jul 16, 2004
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
I2C0, I2C1 control register 1
I2C control register 10, 11, 12 (address 032616, 033616, 031616) controls I2C-BUS interface circuit.
•Bit 0 : Interrupt enable bit by STOP condition (SIM )
It is possible for I2C-BUS interface to request an interrupt by detecting a STOP condition. If the bit set to “1”,
an interrupt from I2C-BUS interface occurs by detecting a STOP condition ( There is no change for PIN flag)
•Bit 1: Interrupt enable bit at the completion of data receiving (WIT)
When with-ACK mode (ACK bit = “1”) is specified, by enabling the interrupt at the completion of data
receiving (WIT bit = “1”), the I2C interrupt request occurs and PIN bit becomes “0” synchronized with the
falling edge of last data bit clock. SCL is fixed “L” and the generation of ACK clock is suppressed.
Table GC-3 and Fig.GC-10 show the I2C interrupt request timing and the method of communication restart.
After the communication restart, synchronized with the falling edge of ACK clock, PIN bit becomes to “0”
and I2C interrupt request occurs.
Table.GC-3 Timing of interrupt generation in data receiving
The timing of I2C interrupt generation
(1) Synchronized with the falling edge of the
last data bit clock
(2) Synchronized with the falling edge of the
ACK clock
The method of communication restart
The execution of writing to ACKBIT of I2C clock control
register. (Do not write to I2C data shift register.
The processing of ACK clock would be incorrect.)
The execution of writing to I2C data shift register
The state of internal WAIT flag can be read out by reading the WIT bit. The internal WAIT flag is set after
writing to I2C data shift register, and it is reset after writing to I2C clock control register. Consequently, which
of the timing 1) and 2) of interrupt request occurring can be understood. (See Fig.GC-10)In the cases of
transmission and address data reception immediately after the START condition, the interrupt request only
occurs at the falling edge of ACK clock regardless of the value of WIT bit and the WAIT flag remains the reset
state. Write “0” to WIT bit when in NACK is specified. (ACK bit = “0”)
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MULTI-MASTER I2C-BUS Interface
•Bits 2, 3 : Port function selection bits PED, PEC
When ES0 bit of I2C control register 0 is set to “1”, P61/P63/P77 and P60/P62/P76 function as SCL and SDA
respectively. However, if PED is set to “1”, SDA functions as output port so as to SCL if PEC is set to “1”. In this
case, if “0” or “1” is written to the port register, the data can be output on to the I2C-BUS regardless of the
internal SCL/SDA output signals. The functions of SCL/SDA are returned back by setting PED/PEC to “1”
again.
If the ports are set in input mode, the values on the I2C-BUS can be known by reading the port register
regardless of the values of PED and PEC.Table GC-4 shows the port specification.
Table.GC-4 Ports specifications
Pin name
ES0 bit
PED bit
P6/P7 port
direction register
P60/P62/P76
0
1
1
0
1
0/1
-
P61/P63/P77
ES0 bit
PEC bit
P6/P7 port
direction register
0
1
0
0/1
-
1
1
-
Function
Port I/O function
SDA I/O function
SDA input function, port output function
Function
Port I/O function
SCL I/O function
SCL input function, port output function
•Bits 4, 5 : SDA/SCL logic output value monitor bits SDAM /SCLM
It is possible to monitor the logic value of the SDA and SCL output signals from I2C-BUS interface circuit.
SDAM can monitor the output logic value of SDA. SCLM can monitor the output logic value of SCL. The bits are
read-only. Write “0” if in writing (Writing “1” is reserved)
•Bits 6, 7 : I2C system clock selection bits ICK0, ICK1
These bits select the basic operation clock of I2C-BUS interface circuit. It is possible to select I2C system
clock VIIC among 1/2,1/4 and 1/8 of main clock f(XIN) and 1/2 of external I2C clock (ICCK)
Table.GC-5 I2C system clock selecting bits
ICK1
ICK0
I2C system clock
0
0
VIIC = 1 / 2f1
0
1
VIIC = 1 / 4f1
1
0
VIIC = 1 / 8f1
1
1
VIIC = 1 / 2ICCK
Note: f1 = f(XIN)
ICCK = External I2C clock
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MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
•The address reception in STOP mode /WAIT mode
It is possible for I2C-BUS interface to receive address data even in STOP mode or in WAIT mode. However
the I2C system clock VIIC should be supplied. Table.GC-6 shows the setting list.
Table.GC-6 Clock setting to the I2C system in different operation mode.
Mode
STOP mode
The setting content
The external clock is selected as the I2C system clock ( ICK1 = 1, ICK0 = 1) and
the external I2C clock is supplied by ICCK.
The external clock is selected as the I2C system clock ( ICK1 = 1, ICK0 = 1) and
the external I2C clock is supplied by ICCK.
Select the peripheral function clock stop bit CMO2 (bit 2 of the system clock
control register 0, address : 000616) to the state of not stopping f1,f8,f32
(CMO2 = 0) when in WAIT mode, and then execute the WAIT command.
The external clock is selected as the I2C system clock ( ICK1 = 1, ICK0 = 1) and
WAIT mode
Low power
consumption mode
the external I2C clock is supplied by ICCK.
When in reception mode, ACK bit = "1" WIT bit = "0"
SCL
SDA
7 clock
7 bit
ACK
clock
8 clock
8 bit
1 clock
ACK bit
1 bit
ACKBIT
PIN flag
Internal WAIT flag
I2C interrupt request signal
The writing signal of I2C
data shift register
When in reception mode, ACK bit = "1" WIT bit = "1"
SCL
SDA
7 clock
7 bit
ACK
clock
8 clock
1 bit
8 bit
ACKBIT
PIN flag
Internal WAIT flag
(1)
I2C interrupt request signal
(2)
The writing signal of I2C
data shift register
The writing signal of I2C
clock control register
Note. Do not write to I2C clock control register except bit ACKBIT.
Fig.GC-10 The timing of the interrupt generation at the completion of data reception
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MULTI-MASTER I2C-BUS Interface
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2
AAA
AA
A
AAAA
AA
I C control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S3Di(i=0,1,2)
Bit Symbol
Address
032616,033616,031616
Bit name
When reset
001100002
Function
SIM
The interrupt enable bit of
STOP condition detection
0 : Disable the interrupt of STOP
condition detection
1 : Enable the interrupt of STOP
condition detection
WIT
The interrupt enable bit of
at the completion of data
reception
0 : Disable
1 : Enable
When in NACK setting
(ACK bit = "0") please write "0"
PED
SDAi/Port function switching
bit
0 : SDA I/O pin(enable ES0 = 1)
1 : GPIO(enable ES0 = 1)
PEC
SCLi/Port function switching
bit
0 : SCL I/O pin(enable ES0 = 1)
1 : GPIO(enable ES0 = 1)
SDAM
The logic value monitor
bit of SDA output
0 : SDA output logic value = "0"
1 : SDA output logic value = "1"
SCLM
The logic value monitor
bit of SCL output
0 : SCL output logic value = "0"
1 : SCL output logic value = "1"
ICK0
I 2 C system clock selection
bits
b7 b6
0 0 : VIIC=1/2f1
0 1 : VIIC=1/4f1 ✼ f1=f(XIN)
1 0 : VIIC=1/8f1
1 1 : VIIC=1/2ICCK
✼ ICCK=External I2C clock
ICK1
Fig.GC-11 I2C control register 1
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R W
MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
I2C control register 2
I2C0, 1 control register 2 (address: 032716, 033716, 031716) control the detection of communication abnormality. In I2C-BUS communication, the data transfer is controlled by the SCL clock signal. The devices will stop in
the communication state if SCL stops during transfer. So if the SCL clock stops in “H” state for a period of time,
the I2C-BUS interface circuit can detect the time out and request an I2C interrupt. Please see Fig.GC-12.
SCL clock stop (“H”)
1 clock
SCL
1 bit
SDA
2 clock
2 bit
3 clock
3 bit
BB flag
Internal counter start signal
Internal counter stop, reset signal
The time of timeout detection
Internal counter overflow signal
I2C interrupt request signal
Fig.GC-12 The timing of timeout detection
•Bit0: Time out detection function enable bit (TOE)
The bit enables timeout detection function. By setting this bit to “1”, the I2C interrupt request signal will be
generated if the SCL clock stops in “H” state for a period of time during bus busy (BB flag =“1”).
The time of time out detection which is selected by timeout detection time selection bit (TOSEL) with long
time mode or short time mode will be calculated by internal counter. When time out is detected, please set “0”
to I2C-BUS interface enable bit (ES0) and then process initialization.
•Bit1: Time out detection flag (TOF )
The bit is the flag showing timeout detection status. If the time which is calculated by the internal counter
overflows, the time out detection flag (TOF) becomes to “1”, and at the same time the I2C interrupt request
signal is generated.
•Bit2: timeout detection time selection bit (TOSEL)
The bit selects timeout detection time from long time and short time mode. If TOSEL = “0”, the long time
mode; TOSEL = “1”, the short mode is selected respectively. The long time is up counted by 16 bits counter
and the short time is up counted by 14 bits counter based on I2C system clock (VIIC). Table GC-7 shows
examples of the timeout detection time.
Table.GC-7 Examples of timeout detection time
VIIC(MHz)
4
2
1
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Long time mode
16.4
32.8
65.6
page 171 of 266
(Unit: ms)
Short time mode
4.1
8.2
16.4
MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
2
AAA
I C control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S4Di(i=0,1,2)
Bit symbol
Address
032716,033716,031716
Bit name
When reset
000000002
Function
TOE
Timeout detection function
enable bit
0 : Disable
1 : Enable
TOF
Timeout detection flag
0 : Not detected
1 : Detected
Timeout detection time selection bit
0 : Long time
1 : Short time
TOSEL
R
W
Nothing is assigned.
Can not be written in the value is "0"
SCPIN
STOP condition detection interrupt
request bit
0 : No interrupt request
1 : Interrupt request
Fig.GC-13 I2C control register 2
•Bit7: STOP condition detection interrupt request bit (SCPIN)
The bit monitors the stop condition detection interrupt. The bit becomes to “1” when I2C-BUS interface
interrupt is generated by the detecting of STOP condition. Writing “0” clears the bit and “1” can not be written.
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
I2C START/STOP condition control register
I2C START/STOP condition register(address 032516, 033516, 031516) controls the detection of START/STOP
condition.
•Bit0-Bit4: START/STOP condition setting bits (SSC4-SSC0)
Because the release time, set up time and hold time of SCL is calculated on the base of I2C system clock(VIIC).
The detecting condition changes depending on the oscillation frequency and I2C system clock selecting bits. It
is necessary to set the suitable value of START/STOP condition setting bits (SSC4-SSC0) so that obtain the
release time, set up time and hold time corresponding to the system clock frequency. Refer to Table GC-11. Do
not set odd number or “000002” to START/STOP condition setting bits. The recommended setting value to
START/STOP condition setting bits (SSC4-SSC0) at each oscillation frequency under standard clock mode is
shown in Table. GC-8. The detection of START/STOP condition starts immediately after the setting of ES0=1.
•Bit5: SCL/SDA interrupt pin polarity selection bit (SIP)
The interrupt can be generated by detecting the rising edge or the falling edge of SCL pin or SDA pin. SCL/SDA
interrupt pin polarity selection bit selects the polarity of SCL pin or SDA pin for interrupt.
•Bit6 : SCL/SDA interrupt pin selection bit (SIS)
SCL/SDA interrupt pin selection bit selects either SCL pin or SDA pin as SCL/SDA interrupt enable pin.
Note: The SCL/SDA interrupt request may be set when the setting of I2C-BUS interface enable bit ES0 changes.
Thus set the interrupt disable before the setting of SCL/SDA interrupt pin polarity selection bit (SIP) and
SCL/SDA interrupt selection bit(SIS). After that reset “0” to the interrupt request bit before enabling the
interrupt.
•Bit7: START/STOP condition generation selecting bit (STSPSEL)
The bit selects the length of set up/hold time when START/STOP condition occurs. The length of set up/hold
time is based on the I2C system clock cycles. Refer to Table GC-9. Set the bit to “1” if I2C system clock frequency
is over 4MHz.
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MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
2
AA
A
AA
A
AAA
AA
A
I C start/stop condition control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
S2Di(i=0,1,2)
Bit Symbol
SSC0
Address
032516,033516,031516
When reset
000110102
Bit name
Function
START/STOP condition setting
bits
R W
The setting of the detecting
condition of START/STOP
condition.Refer to Table GC-8.
SSC1
Note: Prohibit the setting of
"000002" and odd value
SSC2
SSC3
SSC4
SIP
SCL/SDA interrupt pin polarity
selection bit
0 : Active in falling edge
1 : Active in rising edge
SIS
SCL/SDA interrupt pin selection
bit
0 : SDA enable
1 : SCL enable
START/STOP condition
generation selection bit
0 : Setup/hold time short mode
1 : Setup/hold time long mode
STSP
SEL
Fig.GC-14 I2C start/stop condition control register
Table.GC-8 Recommended setting value (SSC4 - SSC0) start/stop condition at each oscillation frequency
Oscillation
f(XIN) (MHz)
10
8
I2C system
clock selection
1 / 2f1
1 / 2f1
8
4
1 / 8f1
1 / 2f1
2
1 / 2f1
I2C system SSC4-SSC0
clock(MHz)
5
XXX11110
4
XXX11010
XXX11000
1
XXX00100
2
XXX01100
XXX01010
1
XXX00100
SCL release
time(cycle)
6.2µs (31)
6.75µs(27)
6.25µs(25)
5.0µs (5)
6.5µs (13)
5.5µs (11)
5.0µs (5)
Setup time
(cycle)
3.2µs (16)
3.5µs (14)
3.25µs(13)
3.0µs (3)
3.5µs (7)
3.0µs (6)
3.0µs (3)
Note: Do not set odd value or “000002” to START/STOP condition setting bits.
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Hold time
(cycle)
3.0µs (15)
3.25µs(13)
3.0µs (12)
2.0µs (2)
3.0µs (6)
2.5µs (5)
2.0µs (2)
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
START Condition Generation Method
When ES0 bit of the I2C control register is “1” and the BB flag of I2C status register is “0”, writing “1” to the
MST, TRX, and BB bits and “0” to the PIN and low-order 4 bits of the I2C status register (address 032816,
033816, 031816) simultaneously enters the standby status to generate the start condition. The start condition
is generated after writing slave address data to the I2C data shift register. After that, the bit counter becomes
“0002” and 1 byte SCL are output. The START condition generation timing is different in the standard clock
mode and the high-speed clock mode. Refer to Fig.GC-17 the START condition generation timing diagram,
and Table GC-9 the START condition generation timing table.
Interrupt disable
No
BB=0?
Yes
S1i=E016
S0i=Data
Interrupt enable
Fig.GC-15 Start condition generation flow chart
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page 175 of 266
Start condition standby status setting
Start condition trigger occur.
✼ Data=Slave address data
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
Function of protection of duplicate START condition
It is necessary to verify that the bus is not in use via BB flag before setting up a START condition. However,
there is a possibility that right after the verification of BB flag, the BB flag becomes to “1” because a START
condition is generated by another master device .In this case, the function to interrupt the start condition is
built in. When the function starts, it works as follows:
•The prohibition of setting up START condition standby
If the START condition standby has been set up, releases it and resets the bits of MST and TRX.
•The prohibition of writing to the I2C data shift register (The prohibition of generating a START condition
trigger)
•If the generation of start condition is interrupted, sets the AL flag.
The function of protection of duplicate START condition is valid from the falling edge of SDA of START
condition to the completion of slave reception. Fig.GC-16 shows the valid period of the function of protection
of duplicate START condition.
1 clock
SCL
SDA
1 bit
2 clock
2 bit
3 clock
3 bit
8 clock
8 bit
ACK clock
ACK bit
BB flag
The valid period of protection of duplicate START condition
Fig.GC-16 The valid period of the function of protection of duplicate START condition
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page 176 of 266
MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
STOP Condition Generation Method
When the ES0 bit of the I2C control register is “1”, writing “1” to the MST and TRX bits, and “0” to the BB, PIN
and low-order bits of the I2C status register simultaneously enters the standby status to generate the stop
condition. The stop condition is generated after writing dummy data to the I2C data shift register. The STOP
condition generation timing is different in the standard clock mode and the high-speed clock mode. Refer to
Fig.GC-18, the STOP condition generation timing diagram, and Table GC-9, the STOP condition generation
timing table. Do not write data to I2C status register and I2C data shift register, before BB flag becomes to “0”
after the instruction to generate the stop condition to avoid the influence on generating STOP condition waveform.
I2C data shift register
write signal
SCL
Setup
time
SDA
AA
Hold
time
Fig.GC-17 Start condition generation timing diagram
I2C data shift register
write signal
SCL
SDA
AAAA
Setup
time
Hold
time
Fig.GC-18 Stop condition generation timing diagram
Table.GC-9 Start/Stop generation timing table
Item
Start/Stop condition generation
selection bit
Setup
“0”
time
“1”
hold
“0”
time
“1”
Note: VIIC = 4MHz
Standard clock mode
5.0µs (20 cycle)
13.0µs (52 cycle)
5.0µs (20 cycle)
13.0µs (52 cycle)
High-speed clock mode
2.5µs (10 cycle)
6.5µs (26 cycle)
2.5µs (10 cycle)
6.5µs (26 cycle)
As mentioned above, Writing “1” to MST and TRX bits.
Writing “1” or “0” to BB bit, writing “0” to PIN and low-order 4 bits, simultaneously sets up the START or STOP
condition standby. It releases SDA in START condition standby, makes SDA to “L” in STOP condition
standby. The signal of writing to data shift register triggers the generation of START/STOP condition. In the
case of setting MST, and TRX to “1” but do not want to generate a START/STOP condition. Write “1” to the
low-order 4 bits simultaneously. Fig.GC-10 illustrates the function of writing to status register.
Table.GC-10 The function of writing to status register
The value of the data writing to status register
MST TRX BB PIN AL AAS AS0 LRB
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0/1 0/1 0
1
1
1
1
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page 177 of 266
Function
Setting up the START condition stand by in master transmission mode
Setting up the STOP condition stand by in master transmission mode
Setting up the communication mode (refer to the description on I2C status register)
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in Fig.GC-19, GC-20 and Table.GC-11 The
START/STOP condition is set by the START/STOP condition set bit. The START/STOP condition can be detected only when the input signal of the SCL and SDA pins satisfy with three conditions: SCL release time, setup
time, and hold time (see Table.GC-11). The BB flag is set to “1” by detecting the START condition and is reset
to “0” by detecting the STOP condition. The BB flag set/reset timing is different in the standard clock mode and
the high-speed clock mode. Refer to Table GC-11, the BB flag set/reset time.
AA
AA
AA
SCL release time
SCL
SDA
Setup
time
Hold
time
BB flag
set time
BB flag
Fig.GC-19 Start condition detection timing diagram
AAA
AA
SCL release time
SCL
SDA
Setup
time
Hold
time
BB flag
reset time
BB flag
Fig.GC-20 Stop condition detection timing diagram
Table.GC-11 Start/Stop generation timing table
SCL release time
Setup time
Hold time
BB flag set/reset
time
Standard clock mode
SSC value + 1 cycle (6.25µs)
SSC value + 1 cycle < 4.0µs (3.25µs)
2
SSC value cycle < 4.0µs (3.0µs)
2
SSC value - 1 +2 cycle (3.375µs)
2
High-speed clock mode
4 cycle (1.0µs)
2 cycle (0.5µs)
2 cycle (0.5µs)
3.5 cycle (0.875µs)
Note: Unit : Cycle number of system clock VIIC
SSC value is the decimal notation value of the START/STOP condition set bits SSC4 to SSC0.
Do not set “0” or an odd number to SSC value. The value in parentheses is an example when the
I2C START/STOP condition control register is set to “1816” at VIIC = 4 MHz.
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing
format. The respective address communication formats are described below.
(1) 7-bit addressing format
To adapt the 7-bit addressing format, set the DBIT SAD bit of the I2C control register 0 (address 032316,
033316, 031316) to “0”. The first 7-bit address data transmitted from the master is compared with the highorder 7-bit slave address stored in the I2C address register (address 032216, 033216, 031216). At the time of
this comparison, address comparison of the RBW bit of the I2C address register (address 032216, 033216,
031216) is not performed. For the data transmission format when the 7-bit addressing format is selected,
refer to Fig.GC-21 (1) and (2).
(2) 10-bit addressing format
To adapt the 10-bit addressing format, set the DBIT SAD bit of the I2C control register 0 (address 032316,
033316, 031316) to “1”. Also set the WIT bit of I2C control register 1 to “1”. An address comparison is performed between the first-byte address data transmitted from the master and the 8-bit slave address stored in
the I2C address register (address 032216, 033216, 031216). At the time of this comparison, an address
____
comparison between the RBW bit of the I2C address register (address 032016, 033016, 031016) and the R/W
bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing
mode, the RBW bit which is the last bit of the address data not only specifies the direction of communication
for control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address, the AAS bit of the I2C status register (address
032816, 033816, 031816) is set to “1”. After the second-byte address data is stored into the I2C data shift
register (address 32016, 33016, 031016), perform an address comparison between the second-byte data and
the slave address by software. When the address data of the 2 bytes agree with the slave address, write “0”
to the ACKBIT to I2C clock control register, to return an ACK. When the address data of the 2 bytes do not
agree with the slave address, it does not return an ACK so that makes the finish of the communication by
writing “1” to the ACKBIT. If the address data agree with each other, set the RBW bit of the I2C address
register (address 032216, 033216, 031216) to “1” by software. This processing can make the 7-bit slave
___
address and R/W data agree, which are received after a RESTART condition is detected, with the value of
the I2C address register (address 032216, 033216, 031216). For the data transmission format when the 10-bit
addressing format is selected, refer to Fig.GC-21(3) and (4).
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address
R/W
7 bits
“0”
A
Data
A
1 - 8 bits
Data
A/A
P
A
P
1 - 8 bits
(2) A master-receiver receives data from slave-transmitter
S
Slave address
7 bits
R/W
A
“1”
Data
A
1 - 8 bits
Data
1 - 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1 st 7 bits
7 bits
R/W
A
“0”
Slave address
2nd byte
A
Data
1 - 8 bits
8 bits
Data
A
A/A
P
1 - 8 bits
(4) A master-receiver receives data from slave-transmitter with a 10-bit address
S
Slave address
1 st 7 bits
7 bits
S : START condition
A : ACK bit
Sr : Restart condition
R/W
“0”
A
Slave address
2nd byte
A
Sr
8 bits
P : STOP condition
R/W : Read/Write bit
Fig.GC-21 Address data communication format
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page 180 of 266
Slave address
1 st 7 bits
7 bits
R/W
“1”
A
Data
1 - 8 bits
A
Data
1 - 8 bits
A
P
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the
ACK return mode is shown below.
1)Set a slave address in the high-order 7 bits of the I2C address register and “0” into the RBW bit.
2)Set the ACK return mode and SCL = 100 kHz by setting “0016” in the I2C control register 1 and “8516” in the
I2C clock control register respectively. (f(XIN)=8MHz)
3)Set “0016” in the I2C status register so that transmission/reception mode is initialized.
4)Set a communication enable status by setting “0816” in the I2C control register 0.
5)Confirm the bus free condition by the BB flag of the I2C status register.
6)Set “E016” in the I2C status register to setup a standby of START condition.
7)Set the destination address data for transmission in high-order 7 bit of I2C data shift register and set “0” in
the least significant bit. And then a START condition occurs. At this time, SCL for 1 byte and an ACK clock
automatically generate.
8)Set transmission data in the I2C data shift register. At this time, an SCL and an ACK clock automatically
generate.
9)When transmitting control data of more than 1 byte, repeat step 8).
10)Set “C016” in the I2C status register to setup a STOP condition if ACK is not returned from slave reception
side or transmission ends.
11)A STOP condition occurs when writing dummy data to I2C data shift register.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK
return mode and using the addressing format is shown below.
1)Set a slave address in the high-order 7 bits of the I2C address register and “0” in the RBW bit.
2)Set the ACK clock mode and SCL = 400 kHz by setting “0016” in the I2C control register 1 and “A516” in the
I2C clock control register respectively. (f(XIN)=8MHz)
3)Set “0016” in the I2C status register so that transmission/reception mode is initialized.
4)Set a communication enable status by setting “0816” in the I2C control register 0.
5)When a START condition is received, an address comparison is performed.
6)•When all transmitted addresses are “0” (general call):
AD0 of the I2C status register is set to “1” and an interrupt request signal occurs.
•When the transmitted addresses agree with the address set in1):
ASS of the I2C status register is set to “1” and an interrupt request signal occurs.
•In the cases other than the above AD0 and AAS of the I2C status register are set to “0” and no interrupt
request signal occurs.
7)Set dummy data in the I2C data shift register.
8)After receiving 1 byte data, it returns an ACK automatically and an interrupt request signal occurs.
9)In the case of whether returning an ACK or not by the content of the received control data, set the WIT bit of
I2C control register 1 to “1”, and after writing dummy data to I2C data shift register, receives the control data.
10)After receiving 1 byte data, an interrupt request signal occurs, set the ACKBIT to “1” or “0” by reading the
content of the data shift register, and then returns or does not return an ACK.
11)When receiving control data of more than 1 byte, repeat step 7) 8) or 7) 10).
12)When a STOP condition is detected, the communication ends.
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M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
Usage precautions
(1) Access to the registers of I2C-BUS interface circuit
The precaution of read/write to the control registers of I2C-BUS circuit is as follows.
•I2C data shift register (S0i : 032016, 033016, 031016)
Do not write the register during transfer. The transfer bit counter will be reset and makes data communication
incorrect.
•I2C address register (S0Di : address 032216, 033216, 031216)
After the detection of a STOP condition, RBW is reset by H/W. Do not read/write the register at the time,
because data may become undetermined. Fig.GC-22 shows the RBW bit H/W reset timing.
2
•I C control register 0 (S1Di : address 032316, 033316, 031316).
After the detection of a START condition or the completion of 1 byte transfer, bit counter (bits BC0 - BC2)
is reset by H/W. Do not read/write the register at the time, because data may become undetermined.
Fig.GC-23, GC-24 show the bit counter H/W reset timing.
2
•I C clock control register (S2i : address 032416, 033416, 031416)
Do not write to this register except ACKBIT during transfer. The I2C clock generator will be reset and
makes transfer incorrect.
control register 1 (S3Di : address 032616, 033616, 031616)
Write I2C system clock selection bits when I2C-BUS interface enable bit (ES0)is in disable state. By reading the data reception completion interrupt enable bit (WIT), the internal WAIT flag will be read. Thus, do
not use bit manipulation (read-modify-write instruction) to access the register.
2
•I C status register (S1i : address 032816, 033816, 031816)
Do not use bit manipulation (read-modify-write instruction) to access the register because all bits of this
register are changed by H/W. Do not read/write during the timing when communication mode setting bits
MST and TRX are changed by H/W. Data may become undetermined. Fig.GC-22, GC-23, and GC-24
show the change timing of MST and TRX bits by H/W.
•I2C
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MULTI-MASTER I2C-BUS Interface
M16C/6KA Group
SCL
SDA
BB flag
Bit reset signal
AAAA
AAAA
Related bits
RBW
MST
TRX
AAAA
AAAA
1.5VIIC cycle
Fig.GC-22 The timing of bit reset (The detection of STOP condition)
SCL
SDA
AAAAAA
AAAAAA
BB flag
Bit reset signal
Related bits
BC0 - BC2
TRX(slave mode)
Fig.GC-23 The timing of bit reset (The detection of START condition)
SCL
PIN bit
AAA
AA
Bit reset signal
2VIIC cycle
Bit set signal
1VIIC cycle
AAAAA
AAAAA
AAAAA
AAAAA
The bits referring
to reset
The bits referring
to set
Fig.GC-24 Bit set/reset timing ( at the completion of data transfer)
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BC0 - BC2
MST(When in arbitration lost)
TRX(When in NACK reception in slave
transmission mode)
TRX(ALS="0" meanwhile the slave
reception R/W bit = "1"
M16C/6KA Group
MULTI-MASTER I2C-BUS Interface
(2) Generation of RESTART condition
After 1 byte data transfer, a RESTART condition standby can be set up by writing “E016” to I 2C
status register and the SDA pin will be released. Wait in software until SDA become “H” stable and then
owing to writing to I2C data shift register a START condition trigger will be generated. Fig.GC-25 shows
the restart condition generation timing.
SCL
ACK
clock
8 clock
SDA
S1i writing signal
( Set the standby of start condition)
S0i writing signal
(START condition trigger generation)
Fig.GC-25 The time of generation of RESTART condition
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page 184 of 266
Insert software wait
M16C/6KA Group
PS2 Interface
PS2 Interface
PS2 interface is supported by 3 channels of serial transmission/reception circuit which is based on PS2
standard specifications.
There are two signal lines, used by PS2 interface : PS2 data(DAT) and PS2 clock(CLK).
The DAT and CLK signal lines are bidirection and should be connected to positive power supply via external
pull-up resistors. These two pins are N-channel open drain output. While bus is released, the states of DAT
and CLK is “High”. Fig.GK-1 shows the system configuration.
Output
Output
DAT
DAT
Input
Output
Input
Output
CLK
CLK
Input
Control side
Fig.GK-1 System configuration
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Input
Device side
M16C/6KA Group
PS2 Interface
The PS2 interface performs 1 byte data transfer with the format shown in Fig.GK-2.
Table GK-1 shows the communication specification.
Table GK-1 Communication specification
Item
Data transfer format
*Start bit
*Data bit
*Parity bit
*Stop bit
Transfer clock
Reception start condition
Transmission start condition
Transfer abort
Interrupt request generation
timing
Error detection
Selection function
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Specification
: 1 bit
: 8 bits (LSB first)
: 1 bit (Odd)
: 1 bit
*Acknowledge
: 1 bit (Transmission only)
*Using the clock, which is synchronized with the sampling clock of PS2
clock (CLK)
*The following conditions should be met for reception start
1) Setting reception enable bit to “1”
2) The detection of “L” on both PS2 clock (CLK) and PS2 data (DAT) lines
*The following conditions should be met for transmission start
1) Setting transmission data to PS2i shift register
2) Setting transmission enable bit to “1”
*The following conditions should be met for transfer abort
1) Setting transfer interruption bit to “1”
2) The transfer completion flag becomes “1”
*In reception: At the completion of stop bit reception
*In transmission: At the completion of ACK bit reception.
*In transfer interruption: At the completion of transfer interruption
*Parity error (In reception)
It occurs when there is a parity error in data reception
*Framing error (In reception)
It occurs when the detection of stop bit of reception data fails.
*Abnormal acknowledge reception (In transmission)
It occurs when NAK is received from a device side after the data
transmission
*Sampling clock selection
Selecting the clock which samples the PS2 clock (CLK) and PS2 data (DAT)
M16C/6KA Group
PS2 Interface
In reception
Data
:8-bit
Parity
:Odd
Stop
:1 bit
START
D0
10-bit
D1
D2
D3
D4
D5
D6
D7
PARITY
STOP
D6
D7
PARITY
STOP ACK/NAK
1 byte data format
In Transmission
Data
Parity
Stop
Acknowledge
START
:8-bit
:Odd
:1 bit
:1 bit
D0
11-bit
D1
D2
D3
D4
D5
1 byte data format
Fig.GK-2 1 byte data format
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M16C/6KA Group
PS2 Interface
Fig.GK-3 shows the PS2 interface overall block diagram.
Fig.GK-4 shows the transmission/reception block diagram.
Internal data bus
PS2 mode register (02AC16)
Pin selection
Control stop
PS2Bi(i=0-2)
CLK output
DAT output
Ch0
Transmission/
reception
section
"1"
Interrupt request 0
"1"
CLK input
DAT input
PS2Ai(i=0-2)
Ch1
"1"
Transmission/
reception
section
"1"
Interrupt request 1
Port control section
1/4
f1
Divider
Sampling clock
selection
1/8
1/16
1/32
Fig.GK-3 PS2 interface block diagram
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page 188 of 266
Sampling clock
Ch2
Transmission/
reception
section
Interrupt request 2
M16C/6KA Group
PS2 Interface
Internal data bus
PS2i shift register
(02A016,02A416,02A816)
DAT output
Sampling clock
CLK output
CLK input
Synchronization
DAT input
Reception
start
detection
circuit
Transmission/reception
control circuit
Shift enable
Reception enable
Transfer abort
Reception completion
Reception process
section
• Completion detection
• Parity generation
PE & FE
Transmission process
section
Completion detection
• Parity generation
• Acknowledge reception
Transfer
completion
process circuit
Transmission completion
Acknowledge result
Transmission
enable
Communication status flags
Error flag refresh
Transfer completion
flag refresh
All bits clear
Interrupt request
PS2i control register
(02A216,02A616,02AA16)
PS2i status register
(02A116,02A516,02A916)
Internal data bus
Fig.GK-4 Transmission/reception section block diagram (One channel)
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M16C/6KA Group
PS2 Interface
(1) Register description
● PS2i shift register
• Transmission/reception data
(1) Data reception
The reception data are stored.
(2) Data transmission
By writing the transmitted data to the register, data transmission is ready to start. PS2 data (DAT) will
become “L” automatically (transmission start).
AAA
PS2i Shift register
b7
b6
b5
b4
b3
b2
b1
symbol
PS20SR
PS21SR
PS22SR
b0
Bit symbol
Fig.GK-5 PS2i shift register
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Address
02A016
02A416
02A816
Bit name
Reset value
0016
0016
0016
Function
Transmission/reception
data
R W
M16C/6KA Group
PS2 Interface
● PS2i Control register
• Reception enable bit (REN)
The data reception is allowed when this bit is set to “1”. The PS2 clock (CLK) will become to “H” (reception
enable status) automatically.
This bit will be cleared to “0” automatically after the completion of data reception and PS2 clock (CLK) will
become “L” (reception disable status) .
If this bit is needed wants to be cleared after setting it to “1” but before the transfer completion flag is
set, set reception enable bit = “0”, transfer abort request bit = “0” and process the transfer abort simultaneously.
• Transmission enable bit (TEN)
After writing transmission data to the PS2i shift register, setting the bit to “1” makes data transmission
enabled and PS2 clock (CLK) will become “H” automatically (transmission enable status).
This bit will be cleared to “0” automatically after the completion of data transmission and PS2 clock (CLK)
will become “L” (transmission disable status).
If this bit is needed to be cleared after setting it to “1” but before the transfer completion flag is set, set
reception enable bit = “0”, transfer abort request bit = “0” and process the transfer abort simultaneously.
• Transfer abort request bit (RSTOP)
This bit is used to abort the data transfer procession.
At the completion of transfer abort procession, the transfer completion flag and transfer abort flag of
PS2i status register are set to “1”, the bit is cleared to “0” automatically and PS2 clock (CLK) will become
“L” ( reception disable status).
After “L” is output to the PS2 clock (CLK), do not execute the following transmission/reception before the
device recognizes the transfer abort request.
PS2i control register
AAA
b7
b6
b5
b4
b3
b2
b1
Symbol
PS20CON
PS21CON
PS22CON
b0
Bit Symbol
Address
02A216
02A616
02AA16
Bit name
Function
REN
Reception enable bit
0 : Disable
1 : Enable
TEN
Transmission enable bit
0 : Disable
1 : Enable
RSTOP
Transfer abort request bit
0 : No transfer abort
1 : Transfer abort
Nothing is assigned.
Meaningless in writing, "0" in reading.
Fig.GK-6 PS2i control register
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Reset Value
0016
0016
0016
page 191 of 266
R W
M16C/6KA Group
PS2 Interface
●PS2i status register
• Transfer completion flag (TI)
The flag is set to “1” at the completion of transmission/reception and the completion of transfer abort.
The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from “0”
to “1”.
• Receiving flag (RF)
The flag is set to “1” during the data reception.
The flag is cleared automatically after the data reception or after the transfer abort.
• Reception abort incognizable flag (CD)
The flag is set in the case that device side can not recognize the abort even if the reception abort is requested.
(The flag is set in the period between the completion of data bit 6 reception and the completion of stop bit
reception.) The flag is cleared automatically after the completion of data reception or after the completion
of transfer abort.
✽ Note that during the period when the flag is set, the device side can not recognize the reception abort
request even if the transfer abort is executed. Thus the data that the transfer abort is requested will not be
resent from device side.
• Transfer status flag (TS)
The flag is set to “1” at the completion of data reception.
The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from “0”
to “1”.
• Parity error flag (PE)
This bit is set to “1” when parity error occurs in received data.
The flag is cleared at read out from PS2i shift register or when the reception enable bit is changed from
“0” to “1”.
• Framing error / NACK reception flag (FE)
At the completion of reception: The flag is set when the detection of stop bit of reception data fails.
At the completion of transmission: The flag is set when NAK is received from the device side.
The flag is cleared at read out from PS2i shift register, the reception enable bit or the transmission bit is
changed from “0” to “1”.
• Transfer abort completion flag (CC)
This bit is set to “1” when transfer abort procession is completed.
The flag is cleared at read out from PS2i shift register, or when the reception enable bit or the transmission
bit is changed from “0” to “1”.
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M16C/6KA Group
PS2 Interface
PS2i status register
AAA
b7
b6
b5
b4
b3
b2
b1
Symbol
PS20STS
PS21STS
PS22STS
b0
Bit Symbol
Address
02A116
02A516
02A916
Bit name
Function
TI
Transfer completion flag
0 : Waiting for transfer,
During transfer
1 : Communication complete
RF
Receiving flag
0 : Waiting for reception,
Reception complete
1 : During receiving
CD
Reception abort incognizable
flag
0 : Recognizable
1 : Incognizable
TS
Transfer status flag
0 : Transmission operation
1 : Reception operation
PE
Parity error flag
0 : No error
1 : Error
FE
Framing error /
NACK reception flag
0 : No error
1 : Error
CC
Transfer abort completion flag
0 : Not abort
1 : Abort
Nothing is assigned.
Meaningless in writing, "0" in reading.
Fig.GK-7 PS2i status register
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Reset Value
0016
0016
0016
page 193 of 266
R W
M16C/6KA Group
PS2 Interface
● PS2 mode register
• Sampling clock selection bits (SCK0,1)
These two bits select clock frequency for sampling PS2 clock (CLK) and PS2 data (DAT).
The relation between main clock (XIN) and sampling cycle is shown in table below.
8MHz
Setting value
1/4
0.5µ
1/8
1.0µ
1/16
2.0µ
1/32
4.0µ
5MHz
0.8µ
1.6µ
3.2µ
6.4µ
XIN
✽Sampling clock , which samples each line periodically, is used for avoiding the reflection from
each line. The sampling clock will be delayed by internal circuit around 1 cycle. Thus, set the
samplingclock as fast as possible.
• Pin selection bit (PSEL)
This bit is for selecting PS2 clock (CLK) or PS2 data (DAT) to connect to PS2Bi (i=0 to 2) .PS2Bi are external
interrupt input pins. The bit setting definition is shown in table below.
Pin selection bit
“0”
“1”
PS2Bi (i= 0 to 2)
PS2 clock (CLK)
PS2 data (DAT)
• PS2 interface enable bit (PSEN)
The PS2Ai (i= 0 to 2) and PS2Bi (i= 0 to 2) will be disconnected to hardware PS2 control section and become
GPIO port when the bit is “0”.
The PS2Ai and PS2Bi will be connected to hardware PS2 control section when this bit is “1”.
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M16C/6KA Group
PS2 Interface
PS2 mode register
AAA
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
PS2MOD
Bit Symbol
SCK0
Address
02AC16
Bit name
Sampling clock
selection bits
SCK1
PSEL
Pin selection bit
Reset Value
0016
Function
00 : Main clock /4
01 : Main clock /8
10 : Main clock /16
11 : Main clock /32
0 : PS2B connects to PS2 clock(CLK)
1 : PS2B connects to PS2 data(DAT)
Nothing is assigned.
Meaningless in writing, "0" in reading.
PSEN0
0 : P70,P73 as GPIO
1 : P70,P73 as PS2A0,PS2B0
PSEN1
0 : P71,P74 as GPIO
1 : P71,P74 as PS2A1,PS2B1
PSEN2
0 : P72,P75 as GPIO
1 : P72,P75 as PS2A2,PS2B2
Reserved bit
Must be set to "0".
Fig.GK-8 PS2 mode register
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PS2 interface enable bits
page 195 of 266
R W
M16C/6KA Group
PS2 Interface
(2) Operation description
● Basic setting
The following items should be set for PS2 mode register (address 02AC16) set when PS2 interface is used.
• PS2 interface enable bit
Set the PS2 interface enable bits (bit4 to 6 of PS2 mode register) to “1” to enable the PS2 channels to be
used. At this time PS2 clock goes “Low” (Receiving disable).
• Sampling clock selection bit
Sampling clock cycle (1/4,1/8,1/16,1/32 of main clock) is selected by setting sampling clock bit (bits 0,1).
• External interrupt function support pin (PS2B) selection
This bit is used to select PS2 clock (CLK) or PS2 data (DAT) for the external interrupt function support pin
(PS2B).
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M16C/6KA Group
PS2 Interface
● Reception operation
Fig.GK-9 shows the reception operation timing.
1
DAT
2
3
3
3
3
3
3
3
3
start
D0
D1
D2
D3
D4
D5
D6
D7
3
4
5
parity stop
CLK
(Device side CLK)
(Controller side CLK)
Reception enable bit
Data receiving flag
Reception abort incognizable flag
Transfer completion flag
Interrupt request
Fig.GK-9 Reception operation timing
(1) Reception enable
The reception operation is enabled by writing 0116 (reception enable bit = “1”) to PS2i control register
(address : 02A216, 02A616, 02AA16). The PS2 clock (CLK) will become “H”.
(2) Reception start
The reception operation starts when both PS2 clock (CLK) and PS2 data (DAT) are detected with “L”.
(3) Data reception (The reception of data and parity bits)
The content PS2 data (DAT) is read into PS2i shift register (address : 02A016, 02A416, 02A816) sequentially
by the falling edge of PS2 clock (CLK). The data transfer sequence is data bit (D0 -D7) then parity bit.
(4) Reception completion (Stop bit Reception completion)
By detecting the falling edge of PS2 clock (CLK), the transfer completion flag (bit 0 of PS2i status register)
is set to “1” after the update of error flag (bit 4 - 6 of PS2i status register) and the reception enable bit
(bit 0 of PS2i control register) is cleared to “0”. The PS2 clock (CLK) becomes “L” (reception disable
status) and interrupt request occurs.
(5) Data read out
Read out data from PS2i shift register (address : 02A016,02A416,02A816). At this time , the error flags
(Bit4 to 6) of and transfer completion flag (bit 0) of PS2i status register (address: 02A116, 02A516, 02A916)
will be cleared to “0”.
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M16C/6KA Group
PS2 Interface
● Transmission operation
Fig.GK-10 shows the transmission operation timing.
1
DAT
2
3
3
3
3
3
3
3
3
3
3
start
D0
D1
D2
D3
D4
D5
D6
D7
parity stop
start
D0
D1
D2
D3
D4
D5
D6
D7
parity stop
4
5
6
ack
(Device side DAT)
(Controller side DAT)
CLK
(Device side CLK)
(Controller side CLK)
Transmission enable flag
Transfer completion flag
Interrupt request
Fig.GK-10 Transmission operation timing
(1) Data writing
Write transmission data to PS2i shift register (address : 02A016, 02A416, 02A816). At this time,PS2 data
will become “L” (transmission start).
(2) Transmission enable
Set 0216 (Transmission enable bit = “1”) to PS2i control register (address : 02A216, 02A616, 02AA16) for
enabling transmission operation. At this time , PS2 clock (CLK) will become “H”.
(3) Data transmission (The transmission of data, parity and stop bits)
The content of PS2i shift register (address : 02A016, 02A416, 02A816) will be output to the PS2 data
(DAT) sequentially by the falling edge of PS2 clock (CLK). The sequence of data transfer is data bits (D0
to D7) , Parity bit, and stop bit.
(4) Acknowledge reception
The content of acknowledge bit will be read by the falling edge of PS2 clock (CLK).
(5) Communication completion
The communication operation is completed by detecting “H” on both PS2 clock (CLK) and PS2 data
(DAT). After the update of error flag (bit 4 - 6 of PS2i status register), the transfer completion flag (bit 0 of
PS2i status register) is set to “1” and the reception enable bit (bit 0 of PS2i control register) is cleared to
“0”. At this time, PS2 clock (CLK) becomes “L” (reception disable status) and the interrupt request occurs.
(6) Status clear
Read out the data from PS2i shift register (address : 02A016, 02A416, 02A816). At this time , the error flags
(bits 4 to 6) and transfer completion flag (Bit0) of PS2i status register (address : 02A116, 02A516, 02A916)
will be cleared to “0”.
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M16C/6KA Group
PS2 Interface
● Transfer abort operation
Fig.GK-11 shows the transfer abort operation timing.
1
DAT
2
3
3
3
3
start
D0
D1
D2
D3
4 5
6
D4
CLK
(Device side CLK)
(Controller side CLK)
Transfer abort request bit
Reception abort incognizable flag
Transfer abort completion flag
Transfer completion flag
Interrupt request
Fig.GK-11 Transfer abort operation timing ( reception)
(1) - (3) Data reception operation
(4) Transfer abort request
Set 0416 (transfer abort request bit = “1”) to PS2i control register (address : 02A216, 02A616,02AA16).
(5) Transfer abort completion
The transfer abort completion flag (bit 6) and transfer completion flag (bit 0) of PS2i status register
(address : 02A116, 02A516, 02A916) are set to “1”, transfer abort request bit (bit 2) of PS2i control register
(address : 02A216, 02A616, 02AA16) is cleared to “0”. At this time, PS2 clock (CLK) becomes “L” (reception disable status) and interrupt request occurs.
(6) Status clear
By a pseudo read of PS2i shift register (address : 02A016, 02A416, 02A816), the transfer abort completion
flag (bit 6) and transfer completion flag (bit 0) of PS2i status register (address : 02A116, 02A516, 02A916)
are cleared to “0”.
Note: Do not execute the following transmission/reception during the period between the “L” output from
PS2 clock (CLK) and the transfer abort request recognition of the device.
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page 199 of 266
M16C/6KA Group
Port
Programmable I/O Ports
There are 129 programmable I/O ports: P0 to P16 (excluding P85). Each port can be set independently for
input or output using the direction register. Pull-up resistances can be set in 4-port unit. (except for P10 and
P14). The N channel open drain ports P60 to P63, P70 to P77, P80 to P84, P130 to P137 and P85 (input only
port) do not build internal pull-up resistance.
Fig.UA-1 to UA-6 show the configurations of programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs
regardless of the contents of the direction registers. See the descriptions of the respective functions for how
to set up the built-in peripheral devices.
(1) Direction registers
Fig.UA-7 shows the configurations of direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers
corresponds one for one to each I/O pin.
Note: There is no direction register bit for P85.
(2) Port registers
Fig.UA-8 shows the configurations of port registers.
These registers are used to write and read data for input and output to and from exterior. A port register
consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers
corresponds one for one to each I/O pin.
(3) Pull-up control registers
Fig.UA-9 and UA-10, UA-11 shows the configurations of pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports (except for P10
and P14). When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the
direction register is set for input.
Pull-up resistance can be set to each pin of P10 and P14.
(4) Port control register
Fig.UA-12 shows the configurations of port control register 0, 1. Fig.UA-13 shows the configurations of port
control register 2, 3. The bit 0 of port control register 0 is used to read port P1 as follows:
0 : When port P1 is input port, port input level is read.
When port P1 is output port , the contents of port P1 register is read.
1 : The contents of port P1 register is read always. (neither input port nor output port)
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M16C/6KA Group
Port
The P0, P1, P40 to P46, P11 and P14 output type, CMOS or N channel open drain, are set by bit 0 to 6 of port
control register 1 and bit 0 to 2 of port control register 3.
0 : CMOS output
1 : N channel open drain output
Exception: P42 output type is N channel open drain if either bit 4 of port control register 1 or bit 2 of port
control register 3 is set to “1”.
Bit 7 of port control register1 functions as below
0 : P40/P43 output is cleared by software only
1 : P40/P43 output is cleared by software or when output buffer 0 is read by host side.
The driving ability of N channel output transistors for P140 to P143 can be selected by bit 6 of port control
register 2 controls as below:
0 : Driving ability of N channel open drain output transistor is LOW
1 : Driving ability of N channel open drain output transistor is HIGH
(5) Port P4/P7 input register
Fig.UA-14 shows the configurations of P4 and P7 input register.
By reading the registers, the input level of the corresponding pins can be known regardless the input/output
mode. These two registers can be read regardless port direction setting. And the ports level will be read out.
Port4 : Bit 0 to bit6's level will be read out. And bit7 is always “0”.
Port7 : Bit 0 to bit5's level will be read out. And bit6,7 is always “0”.
(6) Port function selection register 0,1,2
Fig.UA-15, UA-16 shows the configurations of port function selection register 0,1. The port functions of
________
__________
UART1 input/output, TimerA0 to TimerA2 output, TimerB3,B4 input, external interrupt INT6 to INT12 input or
I2C1,2 input/output can be switched by setting these two registers.
By setting bit0,1 of port function selection register 2, the same frequency clock with f(XIN) can be output from
P110 and P111.
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M16C/6KA Group
Port
Pull-up selection
Direction register
P00 to P07
P110 to P117
Output formality
selection bit
Data bus
Port latch
(Note)
Pull-up selection
Direction register
P12, P16
P140 to P147
Output formality
selection bit
Data bus
Port latch
(Note)
Input respective peripheral function
Pull-up selection
Direction register
P13, P43 to P46
"1"
Output formality
selection bit
Data bus
Output
Port latch
(Note)
Pull-up selection
Direction register
P10, P11, P14, P15, P17
P40 to P42
"1"
Output formality
selection bit
Data bus
Output
Port latch
(Note)
Input respective peripheral function
(Note)
Fig.UA-1 Programmable I/O ports (1)
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page 202 of 266
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc each port.
M16C/6KA Group
Port
Pull-up selection
Direction register
P126, P127
P153 to P157
Data bus
Port latch
(Note)
Pull-up selection
Direction register
P21, P24 to P27, P50 to P57
P91, P97
P120 to P125
P160, P161
Data bus
Port latch
(Note)
Input to respective peripheral function
Pull-up selection
Direction register
P47
"1"
Output
Data bus
Port latch
(Note)
Pull-up selection
P20, P22, P23, P30 to P37
P150 to P152, P64 to P67, P90, P92
Direction register
"1"
Output
Data bus
Port latch
(Note)
Input to respective peripheral function
Note.
Fig.UA-2 Programmable I/O ports (2)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 203 of 266
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
M16C/6KA Group
Port
Direction register
P130 to P137
Data bus
Port latch
(Note)
Direction register
P76 to P77, P80 to P84
Data bus
Port latch
(Note)
Input to respective peripheral function
Direction register
P60 to P63, P70 to P75
"1"
Output
Data bus
Port latch
(Note)
Input to respective peripheral function
Note.
Fig.UA-3 Programmable I/O ports (3)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 204 of 266
symbolizes a parasitic diode.
M16C/6KA Group
Port
Pull-up selection
Direction register
P100, P101 (Excepting the short dashes line section)
P102 to P107 (Including the short dashes line section)
Data bus
Port latch
(Note)
Analog input
Input to respective peripheral function
P102 to P107 only
Pull-up selection
Direction register
P93, P94
"1"
Output
Data bus
Port latch
(Note)
Input to respective peripheral function
Pull-up selection
Direction register
P95
"1"
Output
Data bus
Port latch
(Note)
Input to respective peripheral function
Analog input
Pull-up selection
Direction register
P96
"1"
Output
Data bus
Port latch
(Note)
Analog input
Note
Fig.UA-4 Programmable I/O ports (4)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 205 of 266
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
M16C/6KA Group
Port
Pull-up selection
Direction register
P87
Data bus
Port latch
(Note)
Input to respective peripheral function
Pull-up selection
Direction register
P86
"1"
Output
Data bus
Port latch
(Note)
Note
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Fig.UA-5 Programmable I/O ports (5)
M1
M1 signal input
(Note1)
M0
M0 signal input
(Note1)
RESET
RESET signal input
(Note1)
Note1.
Fig.UA-6 I/O pins
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 206 of 266
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each pin.
M16C/6KA Group
Port
Port Pi direction register
b7
b6
b5
b4
b3
b2
b1
Symbol
PDi(i=0-15, except 8)
b0
Bit symbol
Address
03E216,03E316,03E616,03E716,03EA16
03EB16,03EE16,03EF16,03F316,03F616
02E216,02E316,02E616,02E716,02EA16
Bit name
PDi_0
Port Pi0 direction register
PDi_1
Port Pi1 direction register
PDi_2
Port Pi2 direction register
PDi_3
Port Pi3 direction register
PDi_4
Port Pi4 direction register
PDi_5
Port Pi5 direction register
PDi_6
Port Pi6 direction register
PDi_7
Port Pi7 direction register
Function
When reset
0016
RW
0 : Input mode
(Function as an input port)
1 : Output mode
(Function as an output port)
(i=0-15, except 8)
Port P8 direction register
b7
b6
b5
b4
b3
b2
b1
Symbol
PD8
b0
Bit symbol
Address
03F216
Bit name
PD8_0
Port P80 direction register
PD8_1
Port P81 direction register
PD8_2
Port P82 direction register
PD8_3
Port P83 direction register
PD8_4
Port P84 direction register
When reset
00X000002
Function
RW
0 : Input mode
(Function as an input port)
1 : Output mode
(Function as an output port)
Nothing is assigned.
In an attempt to write to this bit, write "0".
The value, if read, turns out to be indeterminate.
PD8_6
Port P86 direction register
PD8_7
Port P87 direction register
0 : Input mode
(Function as an input port)
1 : Output mode
(Function as an output port)
Port P16 direction register
b7
b6
b5
b4
b3
b2
b1
Symbol
PD16
b0
Bit symbol
Address
02EB16
Bit name
PD16_0
Port P160 direction register
PD16_1
Port P161 direction register
Nothing is assigned.
In an attempt to write to this bit, write "0".
The value, if read, turns out to be indeterminate.
Fig.UA-7 Direction register
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 207 of 266
When reset
XXXXXX002
Function
0 : Input mode
(Function as an input port)
1 : Output mode
(Function as an output port)
RW
M16C/6KA Group
Port
Port Pi register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Pi(i=0 to15,
except 8)
Bit symbol
Address
03E016,03E116,03E416,03E516,03E816
03E916,03EC16,03ED16,03F116,03F416
02E016,02E116,02E416,02E516,02E816
Pi_0
Port Pi0 register
Port Pi1 register
Pi_2
Port Pi2 register
Pi_3
Port Pi3 register
Pi_4
Port Pi4 register
Pi_5
Port Pi5 register
Pi_6
Port Pi6 register
Pi_7
Port Pi7 register
RW
Function
Bit name
Pi_1
When reset
Indeterminate
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : "L" level data
1 : "H" level data
(i=0-15, except 8)
Port P8 register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P8
Bit symbol
Address
03F016
Bit name
P8_0
Port P80 register
P8_1
Port P81 register
P8_2
Port P82 register
P8_3
Port P83 register
P8_4
Port P84 register
P8_5
Port P85 register
P8_6
Port P86 register
P8_7
Port P87 register
When reset
Indeterminate
RW
Function
Data is input and output to and from
each pin by reading and writing to and
from each corresponding bit (except
for P85)
0 : "L" level data
1 : "H" level data
Port P16 register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P16
Bit symbol
Address
02E916
Bit name
PD16_0
Port P160 register
PD16_1
Port P161 register
Nothing is assigned.
In an attempt to write to this bit, write "0".
The value, if read, turns out to be indeterminate.
Fig.UA-8 Port register
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 208 of 266
When reset
Indeterminate
Function
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : "L" level data
1 : "H" level data
RW
M16C/6KA Group
Port
Pull-up control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Bit symbol
Address
03FC16
When reset
0016
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
PU04
P20 to P23 pull-up
PU05
P24 to P27 pull-up
PU06
P30 to P33 pull-up
PU07
P34 to P37 pull-up
Function
R W
The corresponding port is pulled
high with a pull-up resistor
0: Not pulled high
1: Pulled high
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit symbol
Address
03FD16
When reset
0016
Bit name
Function
PU10
P40 to P43 pull-up
PU11
P44 to P47 pull-up
PU12
P50 to P53 pull-up
PU13
P54 to P57 pull-up
R W
The corresponding port is pulled
high with a pull-up resistor
0: Not pulled high
1: Pulled high
Nothing is assigned. (Note)
Can't write to this bit. The value, if read, turns out to be “0”.
PU15
P64 to P67 pull-up
Nothing is assigned. (Note)
Can't write to this bit. The value, if read, turns out to be “0”.
Note.Since P60 to P63 and P70 to P77 are N-channel open drain ports, internal pull-up is not
available for them.
Pull-up control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR2
Bit symbol
Address
03FE16
When reset
0016
Bit name
Function
R W
Nothing is assigned. (Note)
Can't write to this bit. The value, if read, turns out to be “0”.
PU21
P86, P87 pull-up(Note)
PU22
P90 to P93 pull-up
PU23
P94 to P97 pull-up
The corresponding port is pulled
high with a pull-up resistor
0: Not pulled high
1: Pulled high
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Note.Since P80 to P84 are N-channel open drain ports, internal pull-up is not available for them.
And P85 is input port only , also no internal pull-up is available.
Fig.UA-9 Pull-up control register(1)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 209 of 266
M16C/6KA Group
Port
Pull-up control register 3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR3
Bit symbol
Address
02FC16
When reset
0016
Bit name
Function
PU30
P110 to P113 pull-up
PU31
P114 to P117 pull-up
PU32
P120 to P123 pull-up
PU33
P124 to P127 pull-up
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Pull-up control register 4
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR4
Bit symbol
Address
02FD16
When reset
0016
Bit name
Function
PU40
P150 to P153 pull-up
PU41
P154 to P157 pull-up
PU42
P160, P161 pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Fig.UA-10 Pull-up control register(2)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 210 of 266
R W
M16C/6KA Group
Port
Pull-up control register 5
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR5
Bit symbol
Address
02F216
When reset
0016
Bit name
Function
PU50
P100 pull-up
PU51
P101 pull-up
PU52
P102 pull-up
PU53
P103 pull-up
PU54
P104 pull-up
PU55
P105 pull-up
PU56
P106 pull-up
PU57
P107 pull-up
R W
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
Pull-up control register 6
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR6
Bit symbol
When reset
0016
Bit name
Function
PU60
P140 pull-up
PU61
P141 pull-up
PU62
P142 pull-up
PU63
P143 pull-up
PU64
P144 pull-up
PU65
P145 pull-up
PU66
P146 pull-up
PU67
P147 pull-up
Fig.UA-11 Pull-up control register(3)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Address
02F316
page 211 of 266
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high
R W
M16C/6KA Group
Port
Port control register 0
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PCR0
Bit Symbol
PCR00
Address
03FF16
When reset
0016
Bit name
Port P1 control register
RW
Function
0 : When input port, read port
input level. When output port,
read the contents of port P1 register
1 : Read the contents of port P1
register though input/output port.
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Port control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PCR1
Bit Symbol
Bit name
When reset
0016
Function
PCR10
Output type selection bit
(P00 to P03)
0 : CMOS
1 : N-channel open drain
PCR11
Output type selection bit
(P04 to P07)
0 : CMOS
1 : N-channel open drain
PCR12
Output type selection bit
(P10 to P13)
0 : CMOS
1 : N-channel open drain
PCR13
Output type selection bit
(P14 to P17)
0 : CMOS
1 : N-channel open drain
PCR14
Output type selection bit
(P40 to P46)
0 : CMOS
1 : N-channel open drain
PCR15
Output type selection bit
(P110 to P113)
0 : CMOS
1 : N-channel open drain
PCR16
Output type selection bit
(P114 to P117)
0 : CMOS
1 : N-channel open drain
PCR17
P40,P43 output
clear function selection bit
0 : Cleared by software only
1 : Cleared by software or when
output buffer is read by host side.
Fig.UA-12 Port control register 0, 1
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
Address
02FE16
page 212 of 266
R W
M16C/6KA Group
Port
Port control register 2
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
Symbol
PCR2
Address
02FF16
Bit symbol
Bit name
When reset
0016
Function
Reserved bit
Must be set to "0"
Reserved bit
Must be set to "0"
Reserved bit
Must be set to "0"
Reserved bit
Must be set to "0"
Reserved bit
Must be set to "0"
Reserved bit
Must be set to "0"
PCR26
Drive polarity selection bit
(P140 to P143)
R W
0 : Low side
1 : High side
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Port control register 3
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PCR3
Bit symbol
Address
02F716
When reset
0016
Bit name
Function
PCR30
Output type selection bit
(P140 to P143)
0 : CMOS
1 : N-channel open drain
PCR31
Output type selection bit
(P144 to P147)
0 : CMOS
1 : N-channel open drain
PCR32
Output type selection bit
(P42)
0 : CMOS
1 : N-channel open drain
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Fig.UA-13 Port control register 2, 3
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 213 of 266
R W
M16C/6KA Group
Port
Port P4 input register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P4PIN
Bit Symbol
Address
02FA16
When reset
0XXXXXXX2
Bit name
Function
P4PIN_0
Port P40 input register
For reading P40 pin level
P4PIN_1
Port P41 input register
For reading P41 pin level
P4PIN_2
Port P42 input register
For reading P42 pin level
P4PIN_3
Port P43 input register
For reading P43 pin level
P4PIN_4
Port P44 input register
For reading P44 pin level
P4PIN_5
Port P45 input register
For reading P45 pin level
P4PIN_6
Port P46 input register
For reading P46 pin level
R W
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Port P7 input register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P7PIN
Bit Symbol
Address
02FB16
When reset
00XXXXXX2
Bit name
Function
P7PIN_0
Port P70 input register
For reading P70 pin level
P7PIN_1
Port P71 input register
For reading P71 pin level
P7PIN_2
Port P72 input register
For reading P72 pin level
P7PIN_3
Port P73 input register
For reading P73 pin level
P7PIN_4
Port P74 input register
For reading P74 pin level
P7PIN_5
Port P75 input register
For reading P75 pin level
Nothing is assigned.
Can't write to this bit. The value, if read, turns out to be “0”.
Fig.UA-14 Port P4,P7 input register
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 214 of 266
R W
M16C/6KA Group
Port
Port function selection register 0
b7
b6
b5
b4
b3
0
b2
b1
0
b0
0
Symbol
PSL0
Address
02F816
Function
Bit name
Bit Symbol
R W
Must be set to "0" .
Reserved bit
PSL01
When reset
0016
UART1 I/O pin selection bit
0 : P64 to P67
1 : P14 to P17
Must be set to "0" .
Reserved bit
PSL03
INT7 input pin selection bit
0 : P103
1 : P14
PSL04
INT8 I/O pin selection bit
0 : P104
1 : P15
PSL05
INT9 I/O pin selection bit
0 : P105
1 : P16
PSL06
INT10 I/O pin selection bit
0 : P106
1 : P17
Must be set to "0" .
Reserved bit
Port function selection register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PSL1
Address
02F916
Bit Symbol
When reset
0016
Function
Bit name
PSL10
TA0 output pin selection bit
0 : P40
1 : P150
PSL11
TA1 output pin selection bit
0 : P41
1 : P151
PSL12
TA2 output pin selection bit
0 : P42
1 : P152
PSL13
TB3 output pin selection bit
0 : P93
1 : P160
PSL14
TB4 output pin selection bit
0 : P94
1 : P161
PSL15 (Note)
INT6-INT11 input pin
switching bit
0 : P97, P103 to P107
1 : P120, P121 to P125
R W
Nothing is assigned.
Meaningless in writing, "0" in reading.
Note. If this is set to "1" then port function selection register 0 (address 02F816) bit 3 to bit6
setting will be ignored.
Fig.UA-15 Port function selection register 0,1
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 215 of 266
M16C/6KA Group
Port
Port function selection register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PSL2
Address
02F116
Bit Symbol
Bit name
When reset
0016
Function
PSL20
P110 : f1 output function selection bit 0 : P110 as GPIO
1 : P110 as f1 output
PSL21
P111 : f1 output function selection bit 0 : P111 as GPIO
1 : P111 as f1 output
PSL22
S I/O3 I/O pin selection bit
0 : P90 to P92
1 : P150 to P152
PSL23
S I/O4 I/O pin selection bit
0 : P95 to P97
1 : P155 to P157
PSL24
I2C1 I/O pin selection bit
(Note 1)
0 : P62, P63
1 : P81, P82
PSL25
I2C2 I/O pin selection bit
(Note 1)
0 : P76, P77
1 : P83, P84
R W
Nothing is assigned.
Meaningless in writing, "0" in reading.
Note 1 When their pins will be changed, I2C1 or I2C2 is not active.
And after their pins were changed, the corresponding interrupt request bit should be
cleared to "0".
Fig.UA-16 Port function selection register 2
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 216 of 266
M16C/6KA Group
Port
Table.UA-1 Example connection of unused pins in single-chip mode
Pin name
Connection
Ports P0 to P10
(excluding P85)
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
Ports P11 to P16
After setting for input mode, connect every pin to VSS or VCC via a
resistor; or after setting for output mode, leave these pins open.
XOUT (Note)
Open
NMI
Connect via resistor to VCC (pull-up)
AVCC
Connect to VCC
AVSS, VREF, M1
Connect to VSS
Note: With external clock input to XIN pin.
Microcomputer
Port P0 to P16 (input mode)
(except for P85)
(input mode)
(output mode)
open
NMI
XOUT
open
VCC
AVCC
0.47 µF
M1
AVSS
VREF
M0
VSS
In single-chip mode
Fig.UA-17 Example connection of unused pins
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 217 of 266
M16C/6KA Group
Usage precaution
Usage Precaution
Timer A (timer mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of
the counter. But, reading the timer Ai register with the reload timing gets “FFFF16”. Reading the timer Ai
register after setting a value in the timer Ai register with a count halted but before the counter starts
counting gets a setting value to the timer.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of
the counter. But, reading the timer Ai register with the reload timing gets “FFFF16” by underflow or “000016”
by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted
but before the counter starts counting gets a setting value to the timer.
(2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TAiOUT pin outputs “L” level.
• The interrupt request generated and the timer Ai interrupt request bit goes to “1”.
(2) The timer Ai interrupt request bit goes to “1” if the timer's operation mode is set using any of the following
procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the
above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to “0” after the
above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop counting.
If the TAiOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and the timer Ai
interrupt request bit goes to “1”. If the TAiOUT pin is outputting an “L” level in this instance, the level does
not change, and the timer Ai interrupt request bit does not becomes “1”.
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value
of the counter. But, reading the timer Bi register with the reload timing gets “FFFF16”. Reading the timer
Bi register after setting a value in the timer Bi register with a count halted but before the counter starts
counting gets a setting value to the timer.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 218 of 266
M16C/6KA Group
Usage precaution
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request
bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the
reload register. At this time, timer Bi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0
of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an elapse
of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-D
conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT
instruction or from the instruction that sets the every-clock stop bit to “1” within the instruction queue are
prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT
instruction or to the instruction that sets the every-clock stop bit to “1”.
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
stack pointer before accepting an interrupt.
_______
When using the NMI interrupt, initialize the stack point at the beginning of a program. Concerning the first
_______
instruction immediately after reset, generating any interrupts including the NMI interrupt is prohibited.
_______
(3) The NMI interrupt
_______
• As for the NMI interrupt pin, an interrupt cannot be disabled. Connect it to the VCC pin via a resistor
(pull-up) if unused. Be sure to work on it.
_______
• Do not get into stop mode with the NMI pin set to “L”.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 219 of 266
M16C/6KA Group
Usage precaution
(4) External interrupt
_______
_________
• When the polarity of the INT0 to INT11 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0".
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP
NOP
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC FLG
; Push Flag register onto stack
; Disable interrupts.
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
• When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been generated.
This will depend on the instruction. If this creates problems, use the below instructions to change the
register.
Instructions : AND, OR, BCLR, BSET
Noise
(1) Insert the by-pass condenser to the Vcc-Vss line for preventing a noise and latch-up. Connect the by -pass
condencer (about 0.1µF) between Vcc pin and Vss pin. It is distance must be shortest rather sicker line.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 220 of 266
M16C/6KA Group
Electrical characteristics
Table.ZA-1 Absolute maximum ratings
Symbol
Parameter
Condition
Rated value
Unit
Vcc
Supply voltage
VCC=AVCC
-0.3 to 4.6
V
AVcc
Analog Supply voltage
VCC=AVCC
-0.3 to 4.6
V
Input
voltage
VI
RESET,M0,M1,VREF,XIN,
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P64 to P67,P86,P87,
P90 to P97,P100 to P107,P110 to P117,
P120 to P127,P140 to P147,P150 to P157,
P160,P161
-0.3 to Vcc+0.3
P60 to P63,P70 to P77,P80 to P84,P85,
P130 to P137
output
voltage
VO
P00 to P07,P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P64 to P67,P86,P87,
P90 to P97,P100 to P107,P110 to P117,
P120 to P127,P140 to P147,P150 to P157,
P160,P161,XOUT
P60 to P63,P70 to P77,P80 to P84,
P130 to P137
Pd
Power dissipation
Ta=25 C
V
-0.3 to 5.8
V
-0.3 to Vcc+0.3
V
-0.3 to 5.8
V
300
mW
Topr
Operating ambient temperature
-20 to 85
C
Tstg
Storage temperature
-40 to 125
C
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 221 of 266
M16C/6KA Group
Electrical characteristics
Table.ZA-2 Recommended operating conditions (referenced to Vcc=3.0V to 3.6V,Ta= -20 to 85oC)
Parameter
Symbol
Vcc
AVcc
Vss
AVss
Min.
3.0
Supply voltage
Analog Supply voltage
Supply voltage
Analog Supply voltage
"H" input
voltage
VIH
P00 to P07, P10 to P17,P20 to P27, P30 to P37,P40 to P47,
P50 to P57, P64 to P67,P86,P87,P90 to P97, P100 to P107,
P110 to P117, P120 to P127,P140 to P147, P150 to P157,
P160,P161,XIN, RESET, M0,M1
0
V
V
0
V
V
0.8Vcc
5.5
V
0.6Vcc
Vcc
V
0.7Vcc
1.4
5.5
5.5
V
V
P00 to P07, P10 to P17,P20 to P27, P30 to P37,P40 to P47,
P50 to P57, P64 to P67,P86,P87,P90 to P97, P100 to P107,
P110 to P117, P120 to P127,P140 to P147, P150 to P157,
P160,P161,XIN, RESET, M0,M1
0
0.2Vcc
V
P60 to P63, P70 to P77,P80 to P84,P85,P130 to P137,
PSA0 to PSA2, PSB0 to PSB2
0
0.2Vcc
V
0
0.2Vcc
V
0
0
0.3Vcc
0.6
V
I2C-BUS input level selected
SMBUS input level selected
LAD0 to LAD3,LFRAME,LCLK,SERIRQ,CLKRUN
SDA0,SCL0,SDA1,SCL1,SDA2,SCL2,
P60 to P63,P76,P77,P81 to P84
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
V
Vcc
SDA0,SCL0,SDA1,SCL1,SDA2,SCL2,
P60 to P63,P76,P77,P81 to P84
VIL
3.3
Vcc
Unit
Max.
3.6
0.8Vcc
P60 to P63, P70 to P77,P80 to P84,P85,P130 to P137,
PSA0 to PSA2, PSB0 to PSB2
LAD0 to LAD3,LFRAME,LCLK,SERIRQ,CLKRUN
"L" input
voltage
Standard
Typ.
page 222 of 266
I2C-BUS input level selected
SMBUS input level selected
V
M16C/6KA Group
Electrical characteristics
Table.ZA-3 Recommended operating conditions (referenced to Vcc=3.0V to 3.6V,Ta= -20 to 85oC)
Symbol
Parameter
IOH (peak) "H"peak output
current
IOL (peak)
"L"peak output
current
Min.
P00 to P07, P10 to P17,P20 to P27,P30 to P37,P40 to P47,
P50 to P57,P64 to P67,P86 to P87,P90 to P97,P100 to P107,
P110 to P117, P120 to P127,P140 to P147,P150 to P157,
P160,P161
P00 to P07, P10 to P17,P30 to P37,P40 to P47,
P50 to P57,P60 to P67,P76 to P77,P80 to P84, P86 to P87,
P90 to P97,P100 to P107, P110 to P117,P120 to P127,
P130 to P137,P144 to P147, P150 to P157,P160,P161
P20 to P27
IOL (peak)
IOH (avg)
IOL (avg)
"L"peak output
current
P140 to P143
Driven ability : High
Driven ability : Low
"H" average output P00 to P07, P10 to P17,P20 to P27,P30 to P37,
P40 to P47,P50 to P57,P60 to P67,P86 to P87,P90 to P97,
current
P100 to P107, P110 to P117, P120 to P127,P140 to P147,
P150 to P157,P160,P161
"L"average output P00 to P07, P10 to P17,P30 to P37, P40 to P47,
P50 to P57,P60 to P67,P76 to P77,P80 to P84, P86 to P87,
current
P90 to P97,P100 to P107,P110 to P117,P120 to P127,
P130 to P137,P140 to P147,P150 to P157,P160,P161
P20 to P27
IOL (avg)
"L"average output P140 to P143
current
f (XIN)
Main clock input
oscillation frequency
Driven ability : High
Driven ability : Low
0
Standard
Typ.
Max.
-10.0
mA
10.0
mA
20.0
20.0
10.0
mA
mA
mA
-5.0
mA
5.0
mA
15.0
15.0
5.0
mA
mA
mA
8
MHz
Note1 : The average output current is the average value during the 100ms period limited current.
Note2 : The value are as follow:
The sum of IOL (peak) of P0,P1,P2,P86 to P87,P9,P10,P11,P120 to P126,P153 to P157 P16 should be under 80mA.
The sum of IOH (peak) of P0,P1,P2,P86 to P87,P9,P10,P11,P120 to P126,P153 to P157 P16 should be under 80mA.
The sum of IOL (peak) of P3,P4,P5,P6,P7,P80 to P84,P13,P14,P150 to P152 should be under 80mA.
The sum of IOH (peak) of P3,P4,P5,P64 to P67,P14,P150 to P152 should be under 80mA.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 223 of 266
Unit
M16C/6KA Group
Electrical characteristics
Table.ZA-4 Electrical characteristics
(referenced to Vcc=3.0V, Vss=0V, Ta=25oC, f(XIN)=16MHz with 0 wait unless otherwise specified)
Symbol
Parameter
VOH
High output
voltage
VOH
High output
voltage
Low output
voltage
VOL
VOL
VOL
VT+VT-
VT+VTIIH
IIL
R PULLUP
Low output
voltage
Low output
voltage
Hysteresis
Hysteresis
HIGH input
current
Low input
current
Pull-up
resistance
R fXIN
Feedback resistance
V RAM
I CC
RAM retention voltage
Power supply current
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P64 to P67, P86, P87,
P90 to P97, P100 to P107, P110 to P117,
P120 to P127, P140 to P147, P150 to P157,
P160, P161
XOUT
HIGH POWER
LOWPOWER
P00 to P07, P10 to P17, P30 to P37,
P40 to P47,P50 to P57, P60 to P67, P70 to P77,
P80 to P84, P86, P87, P90 to P97, P100 to P107,
P110 to P117, P120 to P127, P130 to P137,
P140 to P147, P150 to P157, P160, P161
P20 to P27
P140 to P143
HIGH POWER
LOWPOWER
XOUT
HIGH POWER
LOWPOWER
_______
_________
TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT11,
__________
________
ADTRG, CTS1, CLK1, CLK3, CLK4, SIN3, SIN4,
_______
RXD1, ICCK, NMI, KI00 to KI07
____________
RESET
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67, P70 to P77,
P80 to P87, P90 to P97, P100 to P107,
P120 to P127, P130 to P137, P140 to P147,
____________
P150 to P157, P160, P161, XIN, RESET, M0, M1
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67, P70 to P77,
P80 to P87, P90 to P97, P100 to P107,
P110 to P117, P120 to P127, P130 to P137,
P140 to P147, P150 to P157, P160, P161,
____________
XIN, RESET, M0, M1
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P86, P87, P90 to P97,
P100 to P107, P110 to P117,
P120 to P127, P140 to P147,
P150 to P157, P160, P161
XIN
When reset, the output pins are opened , the
other pins are connected to Vss.
page 224 of 266
Standard
Measuring condition
IOH=-1mA
Min.
2.5
IOH= -0.1mA
IOH= -50µA
2.5
2.5
Typ.
Unit
Max.
V
V
IOL=1mA
0.5
V
VCC=3V, IOL=3mA
IOL=3mA
IOL=1mA
IOH=0.1mA
IOH=50µA
0.5
0.5
0.5
0.5
0.5
V
V
0.2
0.8
V
0.2
1.8
V
VI=3V
4.0
µA
VI=0V
-4.0
µA
250.0
kΩ
VI=0V
66.0
When clock is stopped
f(XIN)=16MHZ, Square wave
without division
Ta=25°C
When clock is stopped
Ta=85°C
When clock is stopped
2.0
120.0
3.0
16.0
V
MΩ
24.0
V
mA
100.0
µA
300.0
µA
M16C/6KA Group
Electrical characteristics
Table.ZA-5 A-D conversion characteristics
(referenced to Vcc=AVcc=VREF=3V,Vss=AVss=0V at Ta=25oC unless otherwise specified)
Symbol
Measuring condition
Parameter
RLADDER
Ladder resistance
tCONV
Conversion time
VREF
VIA
Reference voltage
Analog input voltage
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 225 of 266
Standard
Typ. Max.
Unit
10
±2
Bits
LSB
±6
LSB
VREF =VCC
Resolution
Absolute accuracy
Min.
8 bit
10 bit
VREF =VCC=3V, ØAD=fAD
VREF =VCC
8 bit
10 bit
10
40
kW
ms
ms
VCC
VREF
V
6.125
7.375
2.7
0
V
M16C/6KA Group
Electrical characteristics
Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified)
Table.ZA-6 External clock input
Parameter
Symbol
tc
tw(H)
tw(L)
tr
tf
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rising time
External clock falling time
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 226 of 266
Standard
Min.
Max.
Unit
62.5
ns
25
ns
25
ns
ns
ns
9
9
M16C/6KA Group
Electrical characteristics
Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified)
Table.ZA-7 Timer A input (The count input of event counter mode)
Parameter
Symbol
tc(TA)
TAiIN input cycle time
tw(TAH)
tw(TAL)
Standard
Min.
Max.
Unit
ns
TAiIN input "H" pulse width
150
60
TAiIN input "L" pulse width
60
ns
ns
Table.ZA-8 Timer A input (The gating input of timer mode)
Parameter
Symbol
Standard
Min.
tc(TA)
TAiIN input cycle time
600
tw(TAH)
tw(TAL)
TAiIN input "H" pulse width
TAiIN input "L" pulse width
300
300
Max.
Unit
ns
ns
ns
Table.ZA-9 Timer A input (The external trigger input of one shot timer mode)
Parameter
Symbol
Standard
Min.
tc(TA)
TAiIN input cycle time
300
tw(TAH)
tw(TAL)
TAiIN input "H" pulse width
TAiIN input "L" pulse width
150
150
Max.
Unit
ns
ns
ns
Table.ZA-10 Timer A input (The external trigger input of pulse width modulation mode)
Parameter
Symbol
Standard
tw(TAH)
TAiIN input "H" pulse width
Min.
150
tw(TAL)
TAiIN input "L" pulse width
150
Max.
Unit
ns
ns
Table.ZA-11 Timer A input (The up down input of event counter mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(UP)
TAiOUT input cycle time
3000
ns
tw(UPH)
tw(UPL)
TAiOUT input "H" pulse width
TAiOUT input "L" pulse width
1500
ns
ns
tsu(UP-TIN)
th(TIN-UP)
TAiOUT input setup time
TAiOUT input hold time
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 227 of 266
1500
200
200
ns
ns
M16C/6KA Group
Electrical characteristics
Timing requirements (referenced to Vcc=3V,Vss=0V at Ta=25oC unless otherwise specified)
Table.ZA-12 Timer B input (The count input of event counter mode)
Symbol
Parameter
tc(TB)
TBiIN input cycle time (single edge count)
tw(TBH)
tw(TBL)
TBiIN input "H" pulse width (single edge count)
TBiIN input "L" pulse width (single edge count)
tc(TB)
Standard
Min.
Max.
Unit
150
ns
60
60
ns
ns
TBiIN input cycle time (double edge count)
300
ns
tw(TBH)
TBiIN input "H" pulse width (double edge count)
160
ns
tw(TBL)
TBiIN input "L" pulse width (double edge count)
160
ns
Table.ZA-13 Timer B input (Pulse period measurement mode)
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
tw(TBL)
TBiIN input "H" pulse width
300
300
ns
TBiIN input "L" pulse width
ns
Table.ZA-14 Timer B input (Pulse width measurement mode)
Parameter
Symbol
Standard
Min.
Max.
Unit
tc(TB)
tw(TBH)
TBiIN input cycle time
TBiIN input "H" pulse width
600
300
ns
ns
tw(TBL)
TBiIN input "L" pulse width
300
ns
Table.ZA-15 A-D trigger input
Parameter
Symbol
tc(AD)
tw(ADL)
ADTRG input cycle time (The Min. of trigger)
ADTRG input "L" pulse width
Standard
Min.
Max.
Unit
1500
ns
200
ns
Table.ZA-16 Serial I/O
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
ns
tw(CKH)
tw(CKL)
td(C-Q)
CLKi input "H" pulse width
150
CLKi input "L" pulse width
TxDi output delay time
150
ns
ns
ns
th(C-Q)
tsu(D-C)
th(C-D)
TxDi hold time
RxDi input setup time
RxDi input hold time
160
ns
0
30
50
ns
ns
______
Table.ZA-17 External interrupt INTi input
Symbol
tw(INH)
tw(INL)
Parameter
Standard
Min.
INTi input "H" pulse width
380
INTi input "L" pulse width
380
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 228 of 266
Max.
Unit
ns
ns
M16C/6KA Group
Electrical characteristics
Timing requirements (referenced to Vcc = 3.0 to 3.6V, Vss = 0V, Ta =25 °C)
Table. ZA-18 Multi-master I2C-BUS line
Symbol
Standard clock mode
Min.
Max.
4.7
4.0
Parameter
tBUF
Bus free time
tHD;STA
tLOW
The hold time in start condition
The hold time in SCL clock "0" status
tR
tHD;DAT
SCL, SDA signals' rising time
Data hold time
tHIGH
tF
The hold time in SCL clock "1" status
SCL, SDA signals' falling time
tsu;DAT
tsu;STA
Data setup time
The setup time in restart condition
tsu;STO
Stop condition setup time
4.7
1000
High-speed clock mode
Min.
Max.
1.3
0.6
1.3
20+0.1Cb
µs
µs
µs
0
0.6
0.9
ns
µs
300
µs
ns
250
20+0.1Cb
100
4.7
4.0
0.6
0.6
0
4.0
300
300
Unit
ns
µs
µs
Table. ZA-19 PS2 interface (referenced to Vcc = 3.0 to 3.6V, Vss = 0V, Ta =25 °C)
Standard
Parameter
Symbol
Min.
30
30
twL
twH
PS2 clock "L" pulse width
PS2 clock "H" pulse width
tsu
th
PS2 data setup time
PS2 data hold time
5
0
td
tv
PS2 data delay time
PS2 data valid time
0
Typ.
Unit
Max.
50
50
µs
µs
µs
ns
twL-5
twL-5
µs
µs
Table. ZA-20 LPC bus interface/serial interrupt output
Standard
Parameter
Symbol
Min.
30
11
11
tC(CLK)
tWH(CLK)
tWL(CLK)
LCLK clock input cycle time
LCLK clock input "H" pulse width
LCLK clock input "L" pulse width
tsu(D-C)
LAD3-LAD0, SERIRQ, CLKRUN, LFRAME
Input setup time
th(C-D)
LAD3-LAD0, SERIRQ, CLKRUN , LFRAME
input hold time
tV(C-D)
LAD3-LAD0, SERIRQ, CLKRUN , LFRAME
valid delay time
toff(A-F)
LAD3-LAD0, SERIRQ, CLKRUN
floating output delay time
Typ.
Max.
∞
Unit
ns
ns
ns
_______________ _______________
_______________
_______________
7
ns
0
ns
_______________
_______________
2
11
ns
28
ns
_______________
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 229 of 266
M16C/6KA Group
Timing
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
Fig.ZA-1 The measuring circuit for port 0 to port 16
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 230 of 266
30pF
M16C/6KA Group
Timing
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up down input)
In event counter mode
TAiIN input
(when selecting the fulling edge count)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(when selecting the rising edge count)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TxDi
td(C-Q)
tsu(D-C)
RxDi
tw(INL)
INTi input
tw(INH)
Fig.ZA-2 Timing diagram (1)
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 231 of 266
th(C-D)
M16C/6KA Group
Timing
SDA
tHD:STA
tBUF
tLOW
SCL
tR
tF
S
p
tsu:STO
Sr
tHD:STA
tHD:DTA
tHIGH
tsu:DAT
p
tsu:STA
Fig.ZA-3 Timing diagram (2)
PS/2 interface timing diagram
In receiving
tWH
tWL
0.8VCC
0.8VCC
CLK
0.2VCC
0.2VCC
th
tsu
DATA
0.8VCC
0.8VCC
0.2VCC
0.2VCC
In transmitting
tWL
tWH
0.8VCC
CLK
0.2VCC
td
DATA
Fig.ZA-4 Timing diagram (3)
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0.2VCC
0.8VCC
0.2VCC
tv
0.8VCC
0.8VCC
0.2VCC
0.2VCC
M16C/6KA Group
Timing
LPC bus interface/serial interrupt output timing
tC(CLK)
tWH(CLK)
LCLK
tWL(CLK)
VIH
VIL
tsu(D-C)
LAD[3:0]
SERIRQ,CLKRUN,LFRAME
(Input)
tv(C-D)
LAD[3:0]
SERIRQ,CLKRUN,LFRAME
(Active output)
toff(A-F)
LAD[3:0]
SERIRQ,CLKRUN,LFRAME
(Floating output )
Fig.ZA-5 Timing diagram (4)
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th(C-D)
M16C/6KA Group
Flash memory version
Feature Outline
Table AB-1 shows the feature outline of M16C/6KA (build-in NEW DINOR flash memory version).
Table.AB-1 Feature outline of M16C/6KA (build-in NEW DINOR flash memory version)
Item
Feature
Power supply voltage
Power supply voltage for program/erase
3.0-3.6V (f(XIN)=16MHz, 0 wait)
3.0-3.6V
Flash memory operation mode
Erase block division
User ROM area
3 modes (parallel I/O, standard serial I/O, CPU reprogram)
6 division (32K+32K+32K+16K+8K+8K bytes)
Program method
Boot ROM area
1 division (4K bytes) (Note1)
2-byte unit
Erase method
Program/ erase control method
Block erase
Program/ erase controlled by s/w commands
Number of command
Program/ erase count
5 commands
100 times
User ROM area
Boot ROM area
ROM code protect
100 times
Support for parallel I/O and standard serial I/O modes
Note1: The control program for standard serial I/O mode is stored in boot ROM area when shipping from factory.
The area can only be erased or programmed by parallel I/O mode.
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M16C/6KA Group
Flash memory version
Flash Memory
The M16C/6KA (build-in flash memory version) contains the NEW DINOR type flash memory, which is
applied VCC=3.3V when using CPU reprogram or standard serial I/O mode. For the flash memory, 3 flash
memory modes are available in which to read, program and erase. They are parallel I/O mode, standard
serial I/O mode and CPU reprogram mode. For parallel I/O mode, a programmer is used. For standard serial
I/O and CPU reprogram modes, the flash memory is manipulated by CPU. Each mode is detailed in the
pages to follow.
Fig. AB-1 shows that flash memory is divided into several blocks. Erasing is in block unit.
In addition to the ordinary user ROM area there is a boot ROM area to store the control program for the CPU
reprogram and standard serial I/O modes. The control program for standard serial I/O mode is stored in boot
ROM area when shipping from factory. User can reprogram the program to suit its own application system.
The area can only be erased or programmed by parallel I/O mode.
0E000016
Block 5 : 32K bytes
0E800016
Block 4 : 32K bytes
0F000016
Block 3 : 32K bytes
0F800016
Block 2 : 16K bytesc
0FC00016
Block 1 : 8K bytes
0FE00016
0FF00016
Block 0 : 8K bytes
0FFFFF16
0FFFFF16
User ROM area
4K bytes
Boot ROM area (Note 1)
Note 1: Boot ROM area can be reprogrammed only in parallel
I/O mode. (Access to any other areas is inhibited.)
Note 2: To specify a block, use the maximum even address in
the block.
Fig.AB-1 Block diagram of flash memory version
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M16C/6KA Group
CPU Reprogram Mode
CPU reprogram mode
In CPU reprogram mode, the on-chip flash memory can be operated on (read, program or erase) under the
control of CPU.
In CPU reprogram mode, only the user ROM area shown in Fig.AB-1 can be reprogrammed. The boot ROM
area cannot be reprogrammed. Make sure the program and block erase commands are issued only for each
block of the user ROM area.
There are erase write mode 0 (EW0 mode) and erase write mode 1 (EW1 mode) in CPU reprogram mode.
Table BB-1 shows the difference between EW0 mode and EW1 mode.
EW0 mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register's FMR01 bit to "1" (CPU
reprogram mode enabled), ready to accept commands. In this case, because the FMR1 register's FMR11
bit=0, EW0 mode is selected. The FMR01 bit can be set to "1" by writing "0" and then "1" in succession. Use
software commands to control program and erase operations. Read the FMR0 register or status register to
check the status of program or erase operation completion.
EW1 mode
EW1 mode is selected by setting FMR11 bit to "1" (by writing "0" and then "1" in succession) after setting the
FMR01 bit to "1" (by writing "0" and then "1" in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status register
can not be read during EW1 mode.
Microcomputer mode and Boot mode
The control program for CPU reprogram mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/
O mode becomes disable.)
See Fig.AB-1 for details about the boot ROM area.
Normal microcomputer mode is entered when reset with pulling “L” of M0. In this case, the CPU starts
operating the control program in user ROM area.
If the microcomputer is reset with M0 being “H” and M1 being “L”, the CPU starts operating the control
program in boot ROM area. This mode is called as “boot” mode.
Block address
Block address refers to the maximum even address of each block. The address is used in block erase
command.
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M16C/6KA Group
CPU Reprogram Mode
Table BB-1 The list of software command (CPU reprogram mode)
Item
Operation mode
The area, which the reprogram
control program can be
allocated
The area, which the reprogram
control program can be
executed
Reprogramable area
EW0 mode
•Single chip mode
•Boot mode
•User ROM area
•Boot ROM area
EW1 mode
•Single chip mode
Should be transferred to RAM
and then executed
•Can be executed in User ROM area
•User ROM area
•User ROM area
However, the block, which the
reprogram control program is
allocated, is excluded.
•Program block area command
Inhibited to the block, which reprogram
control program is allocated
•Read status register command
Inhibited
Read array mode
Hold status (the status of I/O ports is
hold the same before executing the
command) (Note 1)
*Check FMR00, FMR06, FMR07 bits
of FMR0 register by S/W
The limitation of software
command
No
The mode after program erase
CPU status during auto
programming auto erasing
Read status register mode
Operate
The check of the status of flash
memory
*Check FMR00, FMR06, FMR07
bits of FMR0 register by S/W
*Execute the read status register
command, and then check SR7,
SR5 and SR4 bit of status register
_______
Note1:Do not use interrupts (exclude NMI and WDT).
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•User ROM area
M16C/6KA Group
CPU Reprogram Mode
Feature Outline (CPU reprogram mode)
In CPU reprogram mode, the writing and reading of the commands and data should be in even address ("0"
for byte address A0) in 16-bit unit, so the 8-bit unit S/W commands should be written in even address.
Commands are ignored with odd address.
Fig.BB-1 shows the flash recognition register, the flash control register 0 and the flash control register 1.
Bit 0 of flash control register 0 is the RY/BY status flag exclusively used to read the operating status of the
flash memory. During programming and erasing operation, it is "0", otherwise it is "1".
Bit 1 of flash control register 0 is EW0 mode selection bit. When setting the bit to "1", EW0 mode is selected
_______
and the receiving of software command is possible. Keep NMI pin to "H" for the setting. For setting the bit to
"1", it is necessary to set the bit to "0" and then to "1" in secession. For setting "0", only set the bit to "0".
Bit 3 of flash control register 0 is the flash memory reset bit used to reset the control circuit of the on-chip
flash memory. The bit is used when exiting EW0 mode and when flash memory access has failed. When
EW0 mode selection bit is "1", writing "1" to the bit resets the control circuit.
Bit 5 of the flash control register 0 is the user ROM selection bit. It is enabled only in boot mode. When the bit
is set to "1", the accessed area is switched from boot ROM to user ROM. When CPU reprogram mode is
entered in boot mode, set this bit to "1". The bit is disabled when program starts in user ROM. When in boot
mode, the function of the bit is enabled regardless the CPU rewrite mode. Write the bit with the program that
is not located in on-chip flash memory area.
Bit 6 of the flash control register 0 is a read only bit indicating the status of auto program operation. The bit is
set to "1" when a program error occurs. Otherwise, it is cleared to "0".
Bit 7 of the flash control register 0 is a read only bit indicating the status of auto erase operation. The bit is set
to "1" when a erase error occurs. Otherwise, it is cleared to "0".
Fig. BB-2 and Fig. BB-3 show the flow charts of the setting/resetting for EW0 mode and EW1 mode respectively.
The operation specified in the flow chart should be followed.
Bit 1 of flash control register 1 is EW1 mode selection bit. When setting the bit to "1", EW1 mode is selected
________
and the receiving of software command is possible. Keep NMI pin to "H" for the setting. For setting the bit to
"1", the EW0 mode selection bit should be "1" and it is necessary to set the bit to "0" and then to "1" in
succession. For setting to "0", only set the bit to "0". In the case that EW1 selection bit is set to "1" (both EW0
and EW1 mode selection bits are set to "1"), if writing "0" to EW0 mode selection bit, both EW0 and EW1
mode selection bits are cleared to "0".
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M16C/6KA Group
CPU Reprogram Mode
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
Address
When reset
FMR0
03B716
XX0000012
Bit name
Bit symbol
Function
FMR00
RY/BY signal status bit
FMR01
EW0 mode selection bit
(Note1)
0: Busy (be written and erased)
1: Ready
0: Normal mode
(S/W command disable)
1: EW0 mode
(S/W command enable)
Must be “0”.
Reserved bit
0: Normal operation
1: Reset
Flash memory reset bit
(Note 2)
FMR03
Must be “0”.
Reserved bit
FMR05
User ROM area selection bit 0: Access to boot ROM area
(Note 3)
1: Access to user ROM area
(Only enabled in boot mode)
FMR06
Program status flag
(Note 4)
0: Terminate normally
1: Terminate in error
FMR07
Erase status flag
(Note 4)
0: Terminate normally
1: Terminate in error
R W
R
AA
AAA
AAA
AA
A
AAA
AA
A
AA
AA
Note 1: To write “1” to the bit, it is necessary to write “0” and “1” in succession.
Otherwise the bit will not be “1”. Do not enter interrupt.
Note 2: It is enabled only EW0 mode selection bit is “1”. After setting to
“1”(reset), please write “0” in succession.
Note 3: Please write this bit with program that is not located in on-chip flash
memory area.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0
0
Symbol
Address
When reset
FMR1
03B516
000XXX0X2
Bit name
Bit symbol
Function
Reserved bit
FMR11
Uncertain in read.
EW1 mode selection
bit(Note1)
0: EW0mode
1: EW1 mode
Reserved bit
Uncertain in read.
Reserved bit
Must be “0”.
AA
AA
A
RW
W
R
Note 1: To write the bit to "1", the status of FMR01 should be "1" and it is
necessary to write "0" and then "1" in succession. Do not enter interrupt
before writing "1".
Keep NMI pin to "H" at setting of the bit.
If writing "0" to FMR01, both FMR01 and FMR11 are cleared to "0".
Flash memory identification register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
When reset
FTR
03B416
XXXXXX112
Function
The value after reset
XXXXXX112 : M16C/6KA Group
XXXXXX102 : M16C/6K9 Group
000000002
: M16C/6K7 Group
XXXX00012 : M16C/6K5 Group (Note)
AA
R W
Note: Address 03B416 of M16C/6K5 Group is the flash memory control register.
Fig.BB-1 The structure of flash memory control register and flash memory identification register
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M16C/6KA Group
CPU Reprogram Mode
EW0 mode procedure
Program located in ROM
Program located in RAM
*1
Start
Single-chip mode or boot mode
(Only for boot mode)
Set user ROM area selection bit to "1"
The setting of processor mode register (Note 1)
Set EW0 mode selection bit="1"
(write "0" and then write "1") (Note 2)
Transfer reprogram control program to
on-chip RAM
To erase and program with S/W command.
Jump to the reprogram control program,
which has been transferred to RAM.
(The subsequent processing is executed
by the reprogram control program in RAM.)
Reset with read array command or the
setting of flash memory reset bit (write "0"
and then write "1") (Note 3)
*1
Write "0" to EW0 mode selection bit.
(Only for boot mode)
Write user ROM area selection bit to "0".
(Note 4)
End
Note 1: Set the internal clock frequency as shown below using the main clock division ratio selection bits (bit 6 of address 000616, bit 6 and
bit 7 of address 000716):No exceeding 8MHz if wait bit (bit 7 of address 000516)="1". (with wait for internal accessing.)
Note 2: For writing "1" to the bit, it is necessary to write "0" and "1" in succession. Otherwise the bit will not be "1".
Do not enter interrupt. The write to the bit should be executed other than the flash memory area and MNI pin should be
in "H" state.
Note 3: Be sure to execute a read command or set flash memory reset bit before exiting the CPU reprogram mode after the completion of
earse or program operation.
Note 4: The bit can remain "1". In this case, user ROM area will be accessed.
Fig.BB-2 CPU reprogram mode 0 set/reset flowchart
EW1 mode procedure
Program located in ROM
Start
Single-chip mode (Note 1)
The setting of processor mode register (Note 2)
After setting EW0 mode selection bit ="1",
set EW1 mode selection bit = "1".
(Write "0" and then write "1") (Note 3)
To erase and program with S/W command.
Write "0" to EW0 mode selection bit.
End
Note 1: Do not set EW1 mode in boot mode.
Note 2: For CPU reporgram mode, set the internal clock frequency as shown below using the main clock
division ratio selection bits (bit6 of address 000616, bit 6 and bit 7 of address 000716)
Wait bit (bit 7 of address 000516) = "1" (with wait for internal accessing.) and not exceeding 4MHz.
Note 3: For writing "1" to EW0, EW1 mode selection bits, it is necessary to write "0" and "1" in succession.
Otherwise the bits will not be "1". Do not enter interrupt.
Fig.BB-3 CPU reprogram mode 1 set/reset flowchart
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M16C/6KA Group
CPU Reprogram Mode
Precautions on CPU reprogram mode
Described below are the precautions to be observed in programming the flash memory in CPU reprogram
mode.
(1) Operation speed
During CPU reprogram mode, set the internal clock frequency as shown below using the main clock divide
ratio select bits (bit 6 at address 000616 and bit 6 and 7 at address 000716):
• EW0 mode
Not exceeding 8MHz if wait bit (bit 7 of address 000516) = “1”. (with wait for internal accessing)
• EW1 mode
Not exceeding 4MHz if wait bit (bit 7 of address 000516) = “1”. (with wait for internal accessing)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU reprogram mode because they refer to the internal
data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction and BRK instruction
(3) Interrupts inhibited against use
_______
The NMI, address match and WDC interrupts cannot be used during CPU reprogram mode because they
refer to the internal data of the flash memory. If interrupts have their vectors in the variable vector table, they
can be used by transferring the vector into the RAM area.
(4) Reset
The reset is always receivable.
(5) The reprogram in user ROM area
When CPU reprogram mode is entered and the block that the flash reprogram control program is located is
being reprogramming, the block may not be reprogrammed correctly if the power supply is suddenly down. It
is possible that the flash reprogram cannot be executed again in this case. Thus, it is recommended to use
standard serial I/O mode and parallel I/O mode.
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M16C/6KA Group
CPU Reprogram Mode
Software commands
Table BB-2 lists the S/W commands available.
In CPU reprogram mode, the S/W commands can be used to specify the erase or program operation. Note
that when entering a S/W command, the upper byte (D15–D8) is ignored.
The content of each S/W command is explained below.
Table BB-2 List of software commands (CPU reprogram mode)
The 1st bus cycle
Cycle
Command
Data
Mode
Address
number
(D15–D0)
Read array
1
Write
X (Note 5)
FF16
Read status register
2
Write
X
7016
Clear status register
1
Write
X
5016
Program
2
Write
X
4016
Block erase
2
Write
X
2016
The 2nd bus cycle
Data
Mode
Address
(D15–D0)
Read
X
SRD(Note 2)
Write
Write
WA(Note 3)
BA(Note 4)
WD(Note 3)
D016
Note 1: When a S/W command is input, the high-order byte of the data(D15–D8) is ignored.
Note 2:
Note 3:
Note 4:
Note 5:
SRD = Status Register Data. The address should be even and within the user ROM area.
WA = Write Address, WD = Write Data
BA = Block Address (the maximum even address of the block)
“X” can be any even address in user ROM area.
Read Array Command (FF16)
Issuing the command code “FF16” in the 1st bus cycle enters the read array mode. When an even address is
issued in one of the bus cycle that follows, the content of the address is read out at the data bus (D15–D0), 16
bits at a time.
The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code “7016” is issued in the 1st bus cycle, the content of the status register is read out at
the data bus (D7–D0) by a read in the 2nd bus cycle. (The odd address in user ROM area should be specified.)
The status register is explained in the next section.
Clear Status Register Command (5016)
The command is used to clear the bits SR4 and SR5 of the status register after they have been set. These
bits indicate that operation has ended in error. To use this command, issue the command code “5016” in the
1st bus cycle.
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M16C/6KA Group
CPU Reprogram Mode
Program Command (4016)
Program operation starts when the command code “4016” is issued in the 1st bus cycle. If the address and
data are issued in the 2nd bus cycle, program operation (data programming and verification) will start.
_____
Whether the program operation is completed can be conformed by reading the status register or the RY/BY
status flag. When the program starts, the read status register mode is accessed automatically and the
content of the status register can be read on the date bus (D7–D0). The status register bit 7 (SR7) is set to
“0” at the same time when the program operation starts and is returned to “1” upon the completion of the
program operation. In this case, the read status register mode remains active until the Read Array Command
(FF16) is issued.
_____
The RY/BY status flag is “0” during program operation and “1” when the program operation is completed
same as the status register bit 7.
After the program, reading the status register can check the result. Refer to the section where the status
register is detailed.
Start
Write 4016
Write Write address
Write data
(The address for reading the status register
should be even and within the user ROM area.)
Status register read
SR7=1? or
RY/BY=1?
NO
YES
NO
SR4=0?
YES
Program completed
Fig.BB-4 Program flowchart
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Program error
M16C/6KA Group
CPU Reprogram Mode
Block Erase Command (2016/D016)
By issuing the command code “2016” in the 1st bus cycle and the conformation command code “D016” and
block address in the 2nd bus cycle, the erase operation specified by the block address starts (erase and
erase verification).
_____
Whether the block erase command is terminated can be conformed by reading the status register or the RY/BY
status flag. When the block erase operation starts, the read status register mode is accessed automatically
and the content of the status register can be read out. The status register bit 7 (SR7) is set to “0” at the same
time when the erase operation starts and is returned to “1” upon the completion of the erase operation. In this
case, the read status register mode remains active until the Read Array Command (FF16) is written.
_____
The RY/BY status flag is “0” during erase operation and “1” when the erase operation is completed the same
as the bit 7 of status register.
After the block erase, reading the status register can check the result. Refer to the section where the status
register is detailed.
Block Erase Command is inhibited to the block, which reprogram control program is allocated.
Start
Write 2016
Write D016
Block address
(The address for reading the status register
should be even and within the user ROM area.)
Status register read
SR7=1? or
RY/BY=1?
NO
YES
Full status check
(Note 1)
Error
Erase completed
Note 1: Refer to Fig. BB-6
Fig.BB-5 Erase flowchart
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Erase error
M16C/6KA Group
CPU Reprogram Mode
Status register
The status register shows the operation status of the flash memory and whether program and erase operations
end successfully or not. It can be read in the following conditions.
(1) By reading an arbitrary address from the user ROM area after issuing the read status register command
(7016).
(2) By reading an arbitrary address from the user ROM area in the period from the start of program or erase
operation to the execution of read array command (FF16).
Table BB-2 shows the status register.
The status register can be cleared in the following condition.
(1) By issuing the clear status register command (5016).
(2) After reset, the status register is set to “8016”.
Each bit of the register is shows below.
Sequencer status (SR7)
After power-on, the sequencer status is set to “1” (ready).
The bit is set to “0” (busy) during program and erase operations and is set to “1” upon the completion of these
operations.
Erase status (SR5)
Erase status indicates the status of erase operation. When erase error occurs, it is set to “1”.
The bit becomes “0” when it is cleared.
Program status (SR4)
Program status indicates the status of program operation. When program error occurs, it is set to “1”.
The bit becomes “0” when it is cleared.
If “1” is set to SR5 or SR4, the program and block erase operations are not accepted. Before execution of
these commands, it is necessary to execute the clear status register command (5016) to clear the status
register.
If any S/W commands are not correct, both the SR5 and SR4 are set to “1”.
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M16C/6KA Group
CPU Reprogram Mode
Table BB-3 Definition of each bit of status register
Each bit of
SRD
Status name
Definition
"1"
"0"
Ready
Busy
-
-
SR7 (bit7)
Sequencer status
SR6 (bit6)
Reserved
SR5 (bit5)
Erase status
Terminated in error
Terminated normally
SR4 (bit4)
Program status
Terminated in error
Terminated normally
SR3 (bit3)
Reserved
-
-
SR2 (bit2)
Reserved
-
-
SR1 (bit1)
Reserved
-
-
SR0 (bit0)
Reserved
-
-
Full status check
By performing full status check, the execution result of erase and program operations can be known.
Fig.BB-6 shows the full status check flowchart and the method to deal with the error.
Read status register
SR4=1 and
SR5=1?
YES
Command
sequence error
Execute the clear status register command (5016)
to clear the status register. Try to perform the
operation again after conforming that the command
is entered correctly.
NO
SR5=0?
NO
Block erase error
Should block erase error occur, the block cannot
be used.
Program error
Should program error occur, the block cannot be
used.
YES
SR4=0?
NO
YES
End (block erase, program)
Note: When SR5 or SR4 is set to “1”, neither of the program nor block erase
commands are accepted. Execute the clear status register command (5016)
before executing these commands.
Fig.BB-6 Full status check flowchart and the method to deal with errors
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M16C/6KA Group
Functions To Inhibit Rewriting Flash Memory
Functions to inhibit rewriting to the on-chip flash memory
To prevent flash memory from being miss-read or miss-written, ROM code protect function for parallel I/O
mode and ID code check function for standard serial mode are introduced.
ROM code protect function
ROM code protect function can inhibit readout from or modification to the flash memory by setting the content
in ROM code protect control address (0FFFFF16) for parallel I/O mode. Fig.BB-7 shows the content of ROM
code protect control address (0FFFFF16). (The address exists in user ROM area.)
If one of the pair of ROM code protect bits is set to “0”, ROM code protect is turned on, so that the flash
memory is protected against the readout or modification. ROM code protect is implemented in two levels. If
level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester,
etc. When both level 1 and level 2 are set, level 2 will be selected.
If both of the two ROM code protect reset bits are set to “00”, ROM code protect is turned off, so that the flash
memory can be read out or modified. Once ROM code protect is turned on, the ROM code protect reset bits
cannot be modified in parallel I/O mode. Use the serial mode or other to rewrite these two bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
1 1
ROMCP
0FFFFF16
FF16
Bit name
Bit symbol
Reserved bits
Function
Always set these bits to “1”
b3 b2
ROMCP2 ROM code protect level
2 set bits (Note 1,2)
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
b5 b4
ROMCR
0 0: Protect removed
ROM code protect reset 0 1: Protect set bits effective
bits (Note 3)
1 0: Protect set bits effective
1 1: Protect set bits effective
b7 b6
0 0: Protect enabled
ROMCP1 ROM code protect level 0 1: Protect enabled
1 0: Protect enabled
1 set bits (Note 1)
1 1: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is
protected against readout or modification in parallel I/O mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by
a shipment inspection LSI tester,etc. is also inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code
protect level 1 and level 2. However,Since these bits can not be
modified in parallel I/O mode, they should be rewritten in serial I/O
mode or other modes.
Fig.BB-7 ROM code protect control address
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 247 of 266
M16C/6KA Group
Functions To Inhibit Rewriting Flash Memory
ID code check function
The function is used in standard serial I/O mode. If the flash memory is not blank, the ID code sent from serial
burner is compared with that inside flash memory to check the agreement. It the ID codes do not match, the
commands from serial burner are not accepted. Each ID code consists of 8-bit data, the areas of which,
beginning from the 1 st byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,
0FFFFB16. Write a program with the ID code at these addresses to the flash memory.
Address
0FFFDC16 to 0FFFDF16
ID1
Undefined instruction vector
0FFFE016 to 0FFFE316
ID2
Overflow vector
0FFFE416 to 0FFFE716
BRK instruction vector
0FFFE816 to 0FFFEB16
ID3
Address match vector
0FFFEC16 to 0FFFEF16
ID4
Single step vector
0FFFF016 to 0FFFF316
ID5
Watchdog timer vector
0FFFF416 to 0FFFF716
ID6
DBC vector
0FFFF816 to 0FFFFB16
ID7
NMI vector
0FFFFC16 to 0FFFFF16
Reset vector
4 bytes
Fig.BB-8 ROM ID code addresses
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 248 of 266
M16C/6KA Group
Prallel I/O mode
Parallel I/O mode
Parallel I/O mode is to input and output the software command, address and data in parallel to access the
on-chip flash memory (read, program, erase etc.).
Please use the specific device (programmer) supported for M16C/6KA Group. Referring to the guideline etc.
of each device manufacture for the usage.
User ROM area and boot ROM area
In parallel I/O mode, both user ROM area and boot ROM area showed in Fig.AB-1 can be reprogrammed.
The access method to both areas is the same.
The size of boot ROM area is 4K bytes. The addresses are allocated in 0FF00016– 0FFFFF16. Make sure
program and block erase operations are always performed within this address range. (Access to any location
outside this address range is prohibited.)
In the boot ROM area, erase block operation is applied to only one 4K bytes block. The boot ROM area has
had a standard serial I/O mode control program stored in it when shipped from Renesas factory. Therefore,
if the standard serial I/O mode is used, the rewriting to the boot ROM area is not necessary.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 249 of 266
M16C/6KA Group
Standard Serial I/O Mode
Table EE-1 Pin function (Flash memory standard serial I/O mode)
Pin name
VCC, VSS
M0
____________
RESET
Name
Power supply
M0
Reset input
I/O
XIN
XOUT
Clock input
Clock output
I
O
M1
AVCC, AVSS
VREF
P00–P07
P10–P17
M1
Analog power supply
Reference voltage
Input port P0
Input port P1
I
I
I
I
Apply 3.3 ± 0.3V to VCC, apply 0V to VSS
Connect to VCC
Reset input pin. While reset is "L", 20 cycles or more
clocks input to XIN pin are needed.
Connect a ceramic resonator or crystal oscillator
between XIN and XOUT. If external clock is used, input
it to XIN pin and open the XOUT pin.
Connect to VSS
Connect AVSS to VSS, AVCC to VCC
The input pin of reference voltage of AD converter
Input "H", "L" or open
Input "H", "L" or open
P20–P27
P30–P37
P40–P47
P50–P57
P60–P63
P64
P65
P66
P67
P70–P77
P80–P84
P86,P87
P85
P90–P97
P100–P107
P110–P117
P120–P127
P130–P137
P140–P147
P150–P157
P160,P161
Input port P2
Input port P3
Input port P4
Input port P5
Input port P6
BUSY output
SCLK input
RXD input
TXD input
Input port P7
Input port P8
I
I
I
I
I
O
I
I
O
I
I
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
The output pin of BUSY signal
The input pin of serial clock
The input pin if serial data
The output pin of serial data
Input "H", "L" or open
Input "H", "L" or open
I
I
I
I
I
I
I
I
I
Connect to VCC
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Input "H", "L" or open
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
I
I
______
NMI input
Input port P9
Input port P10
Input port P11
Input port P12
Input port P13
Input port P14
Input port P15
Input port P16
page 250 of 266
Standard Serial I/O Mode
79
78
77
76
75
74
73
82
81
80
84
83
109
72
110
71
70
69
68
67
66
111
112
113
114
115
116
117
118
119
120
121
122
123
M306KAFCLRP
(144PFB)
124
125
65
64
63
62
61
60
59
58
57
129
56
55
54
53
52
130
51
131
132
50
49
133
134
135
48
126
127
128
47
46
45
44
43
42
41
136
137
138
139
140
141
142
40
39
38
37
143
144
2 3 4 5
6 7 8
SCLK
RXD
VSS
RESET
Connect to oscillation circuit
VCC
Mode setting method
Name of signal line
Value
M0
VCC
M1
VSS
RESET
Fig.EE-1 Pin connections for serial I/O mode
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
BUSY
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
M1
M0
P96/ANEX1/SOUT40/PWM30
P95/ANEX0/CLK40/PWM20
P94/TB40IN/PWM10
P93/TB30IN/PWM00
1
P42/TA20OUT/GATEA20
P43/OBF01
P44/PWM01/OBF1
P45/PWM11/OBF2
P46/PWM21/OBF3
VCC
P47/PWM31
VSS
P140/KI10
P141/KI11
P142/KI12
P143/KI13
P144/KI14
P145/KI15
P146/KI16
P147/KI17
P50/KI00
P51/KI01
P52/KI02
P53/KI03
P54/KI04
P55/KI05
P56/KI06
P57 /CLKOUT/KI07
P150 /TA01OUT
P151 /TA11OUT
P152 /TA21OUT
P60/SDA0
P61/SCL0
P62/SDA10
P63/SCL10
P64/CTS10/RTS10/CLKS10
P65/CLK10
P66/RXD10/TA3OUT
P67/TXD10/TA4OUT
P70/PS2A0
P92/SOUT30/INT5
P91/SIN30/INT4
P90/CLK30/INT3
P161/TB41IN/PWM50
P160/TB31IN/PWM40
P157/SIN41
P156/SOUT41
P155/CLK41
P154
P153
M1
M0
P87
P86
RESET
XOUT
VSS
XIN
VCC
P85/NMI
P84/TB2IN/SCL21
P83/TB1IN/SDA21
P82/TB0IN/SCL11
P81/TA4IN/SDA11
P80/ICCK
P77/TA3IN/SCL20
P76/SDA20
P75/TA2IN/INT2/PS2B2
P74/INT1/PS2B1
P73/TA1IN/INT0/PS2B0
P72/PS2A2
P71/TA0IN/TB5IN/PS2A1
P10
P126
P125/INT111
P124/INT102
P123/INT92
P122/INT82
P121/INT72
P120/INT61
P07
P06
P05
P04
P03
P02
P01
P00
P117
P116
P115
P114
P113
P112
P111/F1OUT1
P110/F1OUT0
P107/AN7/INT110
P106/AN6/INT100
P105/AN5/INT90
P104/AN4/INT80
P103/AN3/INT70
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVcc
P97/ADTRG/SIN40/INT60
98
97
96
95
94
93
92
91
90
89
88
87
86
85
108
107
106
105
104
103
102
101
100
99
P11
P12
P13
P14/INT71/CTS11/RTS11/CLKS11
P15/INT81/CLK11
P16/INT91/RXD11
P17/INT101/TXD11
P20/TXD21
P21/RXD21
P22/CLK21
P23/CTS21/RTS21
P24
P25
P26
P27
VSS
P30/LAD0
VCC
P127
P31/LAD1
P32/LAD2
P33/LAD3
P34/LFRAME
P35/LRESET
P36/LCLK
P37
P130
P131
P132
P133
P134
P135
P136
P137
P40/ TA00OUT/OBF00/PWM41
P41/TA10OUT/PWM51
M16C/6KA Group
page 251 of 266
VSS → VCC
TXD
M16C/6KA Group
Standard Serial I/O Mode
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the S/W commands, addresses and data needed to operate
(read, program, erase etc.) the on-chip flash memory with a dedicated serial programmer.
Different from parallel I/O mode, in standard serial mode, CPU controls the flash memory reprogramming
(uses the CPU reprogram mode) and the input of serial reprogram data etc. The standard serial I/O mode is
started by connecting M0 to “H”, M1 to “L” with the release of reset. (To connect M0 to “L” in normal
microcomputer mode.)
This control program is written in boot ROM area when the product is shipped from Renesas factory. Make
sure that the standard serial I/O mode cannot be used if boot ROM area is written in parallel I/O mode. Fig
EE-1 shows the pin connections for standard serial I/O mode. The input and output of serial data are processed
in CLK10, RxD10, TxD10, RTS10 (BUSY) 4 pins of the UART1.
The CLK10 is clock input pin, which clock is input externally. The TxD10 is CMOS output pin. The RTS10
(BUSY) pin outputs “L” when ready for reception and outputs “H” when reception starts. The serial data are
transferred in 8-bit unit.
In standard serial I/O mode, only the user ROM area shown in Fig.AB-1 can be reprogrammed. Boot ROM
area cannot be reprogrammed.
In the standard serial I/O mode, a 7-byte ID code is used. If the flash memory is not blank, commands sent
from programmer are not accepted unless the ID code matches.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 252 of 266
M16C/6KA Group
Standard Serial I/O Mode
Outline (standard serial I/O mode)
In standard serial I/O mode, S/W commands, addresses, and data etc. are input and output with the peripheral
device (serial programmer) using 4-wire clock-synchronized serial I/O (UART1). In reception, S/W commands,
addresses and program data are read from RxD10 pin synchronized with the rising edge of the transfer clock
that is input to the CLK10 pin. In transmission, the read data and status are output to TxD10 pin synchronized
with the falling edge of the transfer clock.
The TxD10 is CMOS output pin. Transfer is in 8-bit unit with LSB first.
During transmission, reception, erasing and programming, the RTS10 (BUSY) pin is “H”. Accordingly, always
start the next transfer after the RTS10 (BUSY) pin becomes “L”.
The read after the input of S/W commands can get memory data and status register. Reading the status
register can check the flash memory operation status, the normal/error end of erasing or programming operation.
The following are the explanation of S/W commands, status register etc.
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REJ03B0100-0100Z
page 253 of 266
M16C/6KA Group
Standard Serial I/O Mode
S/W commands
Table EE-2 lists the S/W commands. In standard serial I/O mode, the S/W commands, which transferred
from RxD pin, control of erase, program and read etc. The S/W commands in standard serial I/O mode are
similar with that in parallel I/O mode. ID check function, download function, version information output function,
boot ROM area output function and read check data, 5 commands are added.
Table EE-2 The list of S/W commands (standard serial I/O mode)
Control
1st byte
2nd byte
3rd byte
4th byte
5th byte
6th byte
–
If ID
1
command
Page read
transfer
FF16
Address
Address
Data
Data
Data
259th byte
unmatched
Not acceptable
2
Page program
4116
(middle)
Address
(high)
Address
output
Data
output
Data
output
Data
data output
259th byte
Not acceptable
(high)
Address
input
D016
input
input
data input
2016
(middle)
Address
7016
(middle)
SRD
(high)
SRD1
output
output
3
Block erase
Not acceptable
4
Read
5
status register
Clear
5016
6
status register
ID check
F516
Address
Address
Address
ID size
ID1
7
function
Download
FA16
(low)
Address
(middle)
Address
(high)
Check
Data
No. of
8
function
Version information
FB16
(low)
Version
(high)
Version
sum
Version
input
Version
times required
Version
–9th byte
Acceptable
9
output function
Boot ROM area
FC16
data output
Address
data output
Address
data output data output
Data
Data
data output
Data
Version data output
–259th byte
Not acceptable
(high)
Check data
output
output
data output
FD16
(middle)
Check data
(low)
(high)
output function
10 Read check
data
Acceptable
Not acceptable
output
–ID7
Acceptable
Not acceptable
Not acceptable
Note 1: Shading indicates transfer from flash memory on chip microcomputer to serial programmer.
The else indicates transfer from serial programmer to flash memory on chip microcomputer.
Note 2: SRD means status register data. SRD1 means status register 1 data.
Note 3: All commands are acceptable if the flash memory is blank.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 254 of 266
M16C/6KA Group
Standard Serial I/O Mode
The following are the descriptions of S/W commands
Page read command
The command reads the specified page (256 bytes) of the flash memory sequentially one byte at a time.
Execute the page read command as following:
(1) Transfer the “FF16” command code in the 1st byte.
(2) Transfer addresses A8– A15 and A16– A23 in the 2nd and 3rd byte respectively.
(3) From the 4th byte onward, data (D7–D0) of the page specified by the address (A23–A8) will be output
sequentially from the smallest address sync with the falling edge of the clock.
CLK10
RxD10
(M16C reception data)
FF16
A8 to
A15
A16 to
A23
Data255
Data0
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-2 Timing of page read
Read status register command
The command is for reading status information. When command code “7016” is sent in the 1st byte, the
contents of status register (SRD) and status register 1 (SRD1) will be output in the 2nd and 3rd byte respectively
sync with the falling edge of the clock.
CLK10
RxD10
(M16C reception data)
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-3 Timing of read status register
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 255 of 266
7016
SRD
output
SRD1
output
M16C/6KA Group
Standard Serial I/O Mode
Clear status register command
The command clears the bits (SR4–SR5), which are set when operation ended in error. When command
code “5016” is sent in the 1st byte, the aforementioned bits are cleared. When the clear status register
operation ends, the RTS10 (BUSY) signal changes from “H” to “L”.
CLK10
RxD10
(M16C reception data)
5016
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-4 Timing of clear status register
Page program command
The command programs the specified page (256 bytes) of flash memory sequentially one byte a time. Execute
the command as follows:
(1) Transfer the command code “4116” in the 1st byte.
(2) Transfer addresses A15–A8 and A23–A16 in the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, after inputting 256 bytes program data (A7–A0) from the smallest address of
the specified page, the page program operation will be executed automatically.
When the reception for the next 256 bytes is setup, the RTS10 (BUSY) signal changes from “H” to “L”.
The result of the page program can be known by reading the status register. For more detail, see the
section on the status register.
CLK10
RxD10
(M16C reception data)
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-5 Timing of page program
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 256 of 266
4116
A8 to
A15
A16 to
A23
Data0
Data255
M16C/6KA Group
Standard Serial I/O Mode
Block erase command
The command erases the data in the specified block. Execute the command as follows:
(1) Transfer the command code “2016” in the 1st byte.
(2) Transfer addresses A15–A8 and A23–A16 in the 2nd and 3rd bytes respectively.
(3) After transferring the verify command code“D016” in the 4th byte, the erase operation starts for the specified
block of the flash memory. Issue the biggest address of th2e specified block to A23–A8.
After the completion of block erase, the RTS10 (BUSY) signal changes from “H” to “L”. The result of the block
erase can be know by reading the status register. For more detail, see the section on the status register.
CLK10
RxD10
(M16C reception data)
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-6 Timing of block erase
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 257 of 266
2016
A8 to
A15
A16 to
A23
D016
M16C/6KA Group
Standard Serial I/O Mode
Download function
The command downloads an execution program to RAM. Execute the command as follows:
(1) Transfer the command code “FA16” in the 1st byte.
(2) Transfer the program size in the 2nd and 3rd bytes.
(3) Transfer the checksum in the 4th byte. Check sum is calculated from all transferred data from the 5th byte
onward.
(4) The execution program is transferred from 5th byte onward.
After the entire program data have been transferred, the downloaded execution program will be executed
if the checksum matches.
The program size allowed to transfer varies according to the size of on-chip RAM.
CLK10
RxD10
(M16C reception data)
FA16
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-7 Timing of download function
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REJ03B0100-0100Z
page 258 of 266
Data size Data size
(low)
(high)
Check
sum
Program
data
Program
data
M16C/6KA Group
Standard Serial I/O Mode
Version information output function
The version information of the control program stored in boot ROM area can be output by the function.
Execute the command as follows:
(1) Transfer the command code “FB16” in the 1st byte.
(2) From the 2nd byte onward, the version information will be output. The information is composed of 8 ASCII
character code.
CLK10
RxD10
(M16C reception data)
FB16
TxD10
(M16C transmit data)
'V'
'E'
'R'
'X'
RTS10(BUSY)
Fig.EE-8 Timing of version information output function
Boot ROM area output function
The control program stored in boot ROM area can be read out in page (256 bytes) unit by the function.
Execute the command as follows:
(1) Transfer the command code “FC16” in the 1st byte.
(2) Transfer addresses A15–A8 and A23–A16 in the 2nd and 3rd bytes respectively.
From the 4th byte onward, the data (D7–D0) specified in page (256 bytes) address A23–A8 will be output
sequentially from the smallest address in sync with the rising edge of the clock.
CLK10
RxD10
(M16C reception data)
FC16
A8 to
A15
A16 to
A23
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-9 Timing og boot ROM area output function
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REJ03B0100-0100Z
page 259 of 266
Data0
Data255
M16C/6KA Group
Standard Serial I/O Mode
ID check function
The command checks the ID code. Execute the command as follows:
(1) Transfer the command code “F516” in the 1st byte.
(2) Transfer addresses A 7–A0, A15–A8 and A23–A16 of 1st ID code (ID1) in the 2nd, 3rd and 4th bytes
respectively.
(3) Transfer the number of the ID code in the 5th byte.
(4) From the 6th byte onward, transfer the IDs from the 1st ID code (ID1).
CLK10
RxD10
(M16C reception data)
F516
DF16
FF16
0F16
IDsize
ID1
ID7
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-10 Timing of ID check function
ID code
If the flash memory is not blank, the input ID codes are compared with that written in flash memory. If they do
not match, the input commands will not be accepted. Each ID code contains 8 bits data. Beginning from the
1st ID byte, the address of each ID code is 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716
and 0FFFFB16 respectively. Write the program with the ID codes in these addresses to the flash memory.
Address
0FFFDC16 to 0FFFDF16
ID1
Undefined instruction vector
0FFFE016 to 0FFFE316
ID2
Overflow vector
0FFFE416 to 0FFFE716
BRK instruction vector
0FFFE816 to 0FFFEB16
ID3
Address match vector
0FFFEC16 to 0FFFEF16
ID4
Single step vector
0FFFF016 to 0FFFF316
ID5
Watchdog timer vector
0FFFF416 to 0FFFF716
ID6
DBC vector
0FFFF816 to 0FFFFB16
ID7
NMI vector
0FFFFC16 to 0FFFFF16
Reset vector
4 bytes
Fig.EE-11 ID code addressed
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REJ03B0100-0100Z
page 260 of 266
M16C/6KA Group
Standard Serial I/O Mode
Read check data
Read check date command is for conforming if the reprogram data sent after page program command have
been received correctly.
(1) Transfer the command code “FD16” in the 1st byte.
(2) Transfer check data (low) and check data (high) in the 2nd and 3rd bytes respectively.
When using read check data command, the command should be issued at first to initialize the check data.
The next is to issue the page program command and related reprogram data. After that, by issuing the read
check data command again, the check data for the reprogram data issued between the two read check data
command can be read out.
Adding the reprogram data in byte unit and then calculating the lower 2 bytes of the added data in two's
complement gives out the check data.
CLK10
RxD10
(M16C reception data)
TxD10
(M16C transmit data)
RTS10(BUSY)
Fig.EE-12 Timing of read check dt command
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 261 of 266
FD16
Check data
(low)
Check data
(high)
M16C/6KA Group
Standard Serial I/O Mode
Status register
Status register indicates if the operation to the flash memory ends successfully or in error. It can be read by
issuing the read status register command (7016). The status register can be cleared by issuing the clear
status register command (5016).
Table EE-3 shows the definition of each bit of the register.
After reset, status register outputs “8016”.
Table EE-3 Status register (SRD)
Definition
Symbol
Status
"1"
"0"
Ready
Busy
-
-
SR7 (D7)
Sequencer status
SR6 (D6)
Reserved
SR5 (D5)
Erase status
Terminated in error
Terminated normally
SR4 (D4)
Program status
Terminated in error
Terminated normally
SR3 (D3)
Reserved
-
-
SR2 (D2)
Reserved
-
-
SR1 (D1)
Reserved
-
-
SR0 (D0)
Reserved
-
-
Sequencer status (SR7)
After power-on, the sequencer status is set to “1” (ready).
The bit is set to “0” (busy) during program and erase operations and is set to “1” upon the completion of these
operations.
Erase status (SR5)
Erase status indicates the status of erase operation. When erase error occurs, it is set to “1”.
The bit becomes “0” when it is cleared.
Program status (SR4)
Program status indicates the status of program operation. When program error occurs, it is set to “1”.
The bit becomes “0” when it is cleared.
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M16C/6KA Group
Standard Serial I/O Mode
Status register 1 (SRD1)
Status register 1 indicates the status of serial communication, the result of ID codes comparison, the result of
checksum comparison etc. It can be read after SDR by issuing the read status register command (7016). The
register can be cleared by issuing the clear status register command (5016).
Table EE-4 shows the definition of each bit of the register.
After power on, status register 1 outputs “0016”.
Table EE-4 Status register (SRD1)
Definition
Each bit of
SRD
Status name
"1"
"0"
SR15 (bit7)
Boot update completed bit
SR14 (bit6)
Reserved
-
-
SR13 (bit5)
Reserved
-
-
SR12 (bit4)
Check sum match bit
Match
SR11 (bit3)
ID check completed bits
00
01
10
11
SR9 (bit1)
Timeout of data reception
Timeout
SR8 (bit0)
Reserved
SR10 (bit2)
Update completed
Not update
Mismatch
Not verified
Verified with mismatch
Reserved
Verified with match
Normal operation
-
-
Boot update completed bit (SR15)
The flag indicates that if the control program has been downloaded to RAM with download function.
Check sum match bit (SR12)
The flag indicates if the check sum is matched when downloading the control program with download function.
ID check completed bits (SR11, SR10)
These bits indicate the result of ID checks. Some commands cannot be accepted without the ID checks.
Timeout of data reception bit (SR9)
The flag indicates if timeout occurs during data reception. If the bit is set to “1” during data reception,
microcomputer will discard the received data and return to wait state.
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
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M16C/6KA Group
Standard Serial I/O Mode
Full status check
By performing full status check, the execution result of erase and program operations can be known. Fig.EE13 shows the full status check flowchart and the method to deal with the error.
Read status register
SR4=1 ? and YES
SR5=1 ?
Command
sequence error
NO
SR5=0?
NO
Execute the clear status register command (5016)
to clear the status register. Try to perform the
operation again after conforming that the
commands is entered correctly.
Block erase error
Should block erase error occur, the block can not
be used.
Program error
Should program error occur, the block can not be
used.
YES
SR4=0?
NO
YES
End (block erase, program)
Note: When SR5 or SR4 is set to "1", neither of the program nor block erase
commands are accepted. Execute the clear status register command (5016)
before executing these commands.
Fig.EE-13 Full status check flowchart and the method to deal with errors
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
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M16C/6KA Group
Standard Serial I/O Mode
Circuit applied for standard serial I/O mode (example)
The figure below shows a circuit applied for standard serial I/O mode. The control pins bary by different
programmer. Refer to programmer manual for the detail.
Clock input
CLK10
BUSY output
RTS10(BUSY)
Data input
RXD10
Clock output
TXD10
M16C/6KA (NEW DINOR type
flash memory)
M0
M1
NMI
The control pins and external circuitry vary by different programmer.
Refer to programmer manual for the detail.
Fig.EE-14 Example circuit applied for the standard serial I/O mode
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
page 265 of 266
M16C/6KA Group
Package
Package
MMP
144PFB-A
EIAJ Package Code
TQFP144-P-1616-0.40
Plastic 144pin 16 16mm body TQFP
Weight(g)
0.62
Lead Material
Cu Alloy
MD
ME
e
JEDEC Code
–
b2
HD
D
144
109
I2
Recommended Mount Pad
1
108
36
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
Lp
HE
E
Symbol
73
37
A
72
L1
F
A3
y
Rev.1.00 Jul 16, 2004
REJ03B0100-0100Z
b
x
M
page 266 of 266
L
Detail F
Lp
c
A1
A3
A2
e
x
y
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
–
–
1.2
0.05
0.1
0.15
–
1.0
–
0.13
0.18
0.23
0.105
0.125
0.175
15.9
16.0
16.1
15.9
16.0
16.1
0.4
–
–
17.8
18.0
18.2
17.8
18.0
18.2
0.4
0.5
0.6
1.0
–
–
0.45
0.6
0.75
–
0.25
–
–
–
0.07
0.08
–
–
0
8
–
0.225
–
–
1.0
–
–
–
16.4
–
–
16.4
–
M16C/6KA Group Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Jul 16, 2004
First edition issued
(1/1)
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