RENESAS M306H7FGFP

M306H7MG-XXXFP/MC-XXXFP/FGFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
with DATA ACQUISITION CONTROLLER
1.
REJ03B0152-0210
Rev.2.10
Oct 25, 2006
DESCRIPTION
The M306H7MG/MC-XXXFP and M306H7FGFP are single-chip microcomputers using the highperformance silicon gate CMOS process using M16C/62 Series CPU core and is packaged in a 100-pin
plastic molded QFP. This single-chip microcomputer operates using sophisticated instructions featuring a
high level of instruction efficiency. With 1M bytes of address space, this is capable of executing instructions
at high speed. This also features a built-in data slicer, making this correspondence to Global broadcasting
service.
1.1
Features
• Memory capacity ..............................ROM
Mask version : 256 K/128 K bytes
Flash memory version : 256 K bytes
RAM
Mask version : 8 K/5 K bytes
Flash memory version : 8 K bytes
• Shortest instruction execution time ..62.5 ns (f(XIN)=16 MHz)
• Supply voltage ..................................VCC1=3.00 V to VCC2, VCC2=4.5 V to 5.5 V(at f(XIN)=16 MHz)
VCC1=2.00 V to VCC2, VCC2=2.00 V to 5.5 V(at f(XCIN)=32 kHz)
*VCC2=2.0 V to 2.9 V: Operates only in the low power dissipation
mode
• Interrupts ..........................................25 internal and 8 external interrupt sources, 4 software
interrupt sources; 7 levels
• Multifunction 16-bit timer ..................5 output timers + 6 input timers
• Serial I/O ..........................................6 channels
UART/clock synchronous: 3
Clock synchronous: 2
Multi-master I2C: 1
• DMAC...............................................2 channels (trigger: 24 sources)
• A/D converter ...................................8 bits X 8 channels (Expandable up to 10 channels)
• CRC calculation circuit ....................1 circuit
• Watchdog timer ................................1 line
• Programmable I/O ............................79 lines (P6 to P7, P80 to P84: Can be used as 3.3 V interface)
• Input port ..........................................1 port (P85 shared with NMI pin)
• Clock generating circuit ....................2 built-in circuits
(built-in feedback resistor, external crystal oscillator is required)
• Data slicer ........................................For PDC, VPS, WSS, EPG-J, CC, CC2X, ID-1
1.2
Applications
DVD recorder, HDD recorder
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 1 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
1. DESCRIPTION
------Table of Contents------
1. DESCRIPTION.............................................................1
1.1 Features ..........................................................1
1.2 Applications.....................................................1
Table of Contents ......................................................2
1.3 Pin Configuration.............................................3
1.4 Performance Outline .......................................4
1.5 Block Diagram.................................................6
1.6 Memory .........................................................10
2. CENTRAL PROCESSING UNIT (CPU)..................... 11
2.1 Data Registers (R0, R1, R2 and R3)............. 11
2.2 Address Registers (A0 and A1)..................... 11
2.3 Frame Base Register (FB) ............................12
2.4 Interrupt Table Register (INTB) .....................12
2.5 Program Counter (PC) ..................................12
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ..12
2.7 Static Base Register (SB)..............................12
2.8 Flag Register (FLG) ......................................12
3. RESET ......................................................................13
3.1 Hardware Reset ............................................13
3.2 Software Reset..............................................14
3.3 Watchdog Timer Reset..................................14
3.4 SFR ...............................................................17
4. CLOCK GENERATION CIRCUIT ..............................25
4.1 Oscillator Circuit ............................................30
4.2 CPU Clock and Peripheral Function Clock ...33
4.3 Clock Output Function...................................33
4.4 Power Control ...............................................35
4.5 System Clock Protective Function ................41
5. PROTECTION............................................................42
6. INTERRUPTS ............................................................43
6.1 Type of Interrupts ..........................................43
6.2 Software Interrupts ........................................44
6.3 Hardware Interrupts ......................................45
6.4 Interrupts and Interrupt Vector ......................46
6.5 Interrupt Control ............................................48
6.6 I Flag .............................................................50
6.7 IR Bit .............................................................50
6.8 ILVL2 to ILVL0 Bits and IPL...........................50
6.9 Interrupt Sequence........................................51
6.10 Interrupt Response Time...............................52
6.11 Variation of IPL when Interrupt Request is Accepted ...... 52
6.12 Saving Registers ...........................................53
6.13 Returning from an Interrupt Routine..............55
6.14 Interrupt Priority.............................................55
6.15 Interrupt Priority Resolution Circuit ...............55
6.16 INT Interrupt ..................................................57
6.17 NMI Interrupt .................................................58
6.18 Address Match Interrupt................................58
7. WATCHDOG TIMER ..................................................60
8. DMAC ......................................................................62
8.1 Transfer Cycles .............................................67
8.2 Number of DMA Transfer Cycles ..................69
8.3 DMA Enable ..................................................70
8.4 DMA Request................................................70
8.5 Channel Priority and DMA Transfer Timing...71
9. TIMERS......................................................................72
9.1 Timer A..........................................................73
9.2 Timer B..........................................................87
10. SERIAL I/O ..............................................................93
10.1 UARTi (i=0 to 2).............................................93
10.2 Clock Synchronous serial I/O Mode............102
10.3 Clock Asynchronous Serial I/O (UART) Mode .... 109
10.4 Special Mode 1 (I2C mode)......................... 116
10.5 Special Mode 2............................................126
10.6 Special Mode 3 (IE mode)...........................131
10.7 Special Mode 4 (SIM Mode) (UART2).........133
10.8 SI/O3 and SI/O4..........................................138
11. MULTI-MASTER I2C BUS INTERFACE................143
12. A/D CONVERTER .................................................163
12.1 One-shot Mode ...........................................167
12.2 Repeat mode...............................................169
12.3 Single Sweep Mode ....................................171
12.4 Repeat Sweep Mode 0................................173
12.5 Repeat Sweep Mode 1................................175
12.6 Sample and Hold.........................................177
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12.7 Extended Analog Input Pins ....................... 177
12.8 External Operation Amp Connection Mode .... 177
12.9 Current Consumption Reducing Function....... 178
12.10 Analog Input Pin and External Sensor Equivalent Circuit Example .... 178
12.11 Caution of Using A/D Converter...................... 179
13. CRC CALCULATION ............................................ 180
14. EXPANSION FUNCTION ...................................... 182
14.1 Expansion function description................... 182
14.2 Expansion memory..................................... 183
14.3 slice RAM ................................................... 184
14.4 CRC Operation Circuit (EPG-J).................. 187
14.5 Expansion Register .................................... 200
14.6 Expansion Register Construction Composition... 240
14.7 8/4 Humming Decoder ............................... 247
14.8 24/18 Humming Decoder ........................... 248
14.9 I/O Composition of pins for Expansion Function. 250
15. PROGRAMMABLE I/O PORTS............................ 252
15.1 Port Pi Direction Register (PDi Register, i = 0 to 9) ..252
15.2 Port Pi Register (Pi Register, i = 0 to 9)...... 252
15.3 Pull-up Control Register 0 to Pull-up Control
Register 2 (PUR0 to PUR2 Registers) ....... 252
15.4 Port Control Register.................................. 252
16. ELECTRICAL CHARACTERISTICS .................... 263
17. FLASH MEMORY VERSION ................................ 279
17.1 Flash Memory Performance ....................... 279
17.2 Memory Map .............................................. 281
17.3 Boot Mode .................................................. 282
17.4 Functions To Prevent Flash Memory from Rewriting...282
17.5 CPU Rewrite Mode..................................... 284
17.6 Data Protect Function................................. 298
17.7 Status Register ........................................... 298
17.8 Full Status Check ....................................... 300
17.9 Standard Serial I/O Mode ........................... 302
17.10 Parallel I/O Mode........................................ 307
18. PACKAGE OUTLINE ............................................ 308
19. USEGE NOTES .................................................... 309
19.1 Precautions for Power Control ................... 309
19.2 Precautions for Protect............................... 309
19.3 Precautions for Interrupts ........................... 309
19.4 Precautions for DMAC................................ 313
19.5 Precautions for Timers ............................... 314
19.6 Precautions for Serial I/O (Clock-synchronous Serial I/O)... 317
19.7 Precautions for Serial I/O (UART Mode) .... 318
19.8 Precautions for A/D Converter ................... 318
19.9 Precautions for Programmable I/O Ports.... 318
19.10 Electric Characteristic Differences Between Mask ROM and
Flash Memory Version Microcomputers ........................ 318
19.11 Precautions for Flash Memory Version ...... 318
19.12 Other Notes ................................................ 323
19.13 Serial I/O (RxDi input setup time) ............... 325
19.14 Precautions for LP3 and LP4 pins .............. 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
1.3
1. DESCRIPTION
Pin Configuration
Figures 1.1 shows the pin configuration (top view).
P4_2
P4_3
P4_0
P4_1
P3_6
P3_7
P3_4
P3_5
P3_2
P3_3
VCC2
P3_1
VSS
P3_0
P2_7
P2_5
P2_6
P2_3
P2_4
P2_1
P2_2
P1_7/INT5
P2_0
P1_5/INT3
P1_6/INT4
P1_4
P1_2
P1_3
P1_0
P1_1
Pin configuration (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P0_7/AN7
81
50
P4_4
P0_6/AN6
82
49
P4_5
P0_5/AN5
83
48
P4_6
P0_4/AN4
84
47
P4_7
P0_3/AN3
85
46
P5_0
P0_2/AN2
86
45
P5_1
P5_2
P0_1/AN1
87
44
P0_0/AN0
88
43
P5_3
CVIN
89
42
P5_4
41
P5_5
VDD2
90
VCCOFF
91
VSS2
92
TEST1
LP3
M306H7FGFP/M306H7MG/MC-XXXFP
P6_2/RXD0/SCL0
AVSS
96
35
P6_3/TXD0/SDA0
M1
97
34
P6_4/CTS1/RTS1
SYNCIN
98
33
P6_5/CLK1
AVCC
99
32
P6_6/RXD1/SCL1
P97/ADTRG/SIN4
100
31
P6_7/TXD1/SDA1
Notes 1: N channel open-drain output pins.
Notes 2: When using Multi-master I2C, N channel open-drain output pins.
Figure 1.1
Pin configuration (top view)
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REJ03B0152-0210
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P7_0/TXD2/SDA2/TA0OUT(Notes 1)
P7_1/RXD2/SCL2/TA0IN/TB5IN(Notes 1)
P7_2/CLK2/TA1OUT
P7_3/CTS2/RTS2/TA1IN
P7_5/SCL3/TA2IN(Notes 2)
P7_4/SDA3/TA2OUT(Notes 2)
P7_7/TA3IN
P7_5/TA3OUT
P8_1/TA4IN
P8_0/TA4OUT
P8_2/INT0
P8_3/INT1
P8_5/NMI
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P8_4/RMTOUT/INT2
8
VCC1
7
XIN
6
VSS
5
XOUT
4
RESET
3
P8_7/XCIN
2
P8_6/XCOUT
1
CNVSS
36
STARTB
95
P9_0/TB0IN/CLK3
P6_1/CLK0
LP4
P9_1/TB1IN/SIN3
P6_0/CTS0/RTS0
37
P9_2/TB2IN/SOUT3
38
94
P9_3/TB3IN/JSTIN
93
P9_4/TB4IN/RMTIN
P5_7/CLKOUT
P9_5/ANEX0/CLK4
P5_6
39
P9_6/ANEX1/SOUT4
40
100P6S-A
M306H7MG-XXXFP/MC-XXXFP/FGFP
1.4
1. DESCRIPTION
Performance Outline
Performance outline is shown in Table 1.1.
Table 1.1
Performance outline
Item
Performance
Number of basic instructions
91 instructions
Shortest instruction execution time
Memory
capacity
I/O port
Input port
Multi function
timer
62.5 ns (f(XIN)= 16MHZ, VCC= 4.5V to 5.5V)
ROM
Refer to the Product table (Table 1.2)
RAM
Refer to the Product table (Table 1.2)
P0 to P5, P86 to P87, P9
8-bit x 7, 2-bit x 1 : VCC2 system
P6 to P7, P80 to P84
8-bit x 2, 5-bit x 1 : VCC1 system
P85
1-bit x 1 (NMI pin VCC2 level judgment) : VCC2 system
TA0, TA1, TA2, TA3, TA4
16-bit x 5 channels
TB0, TB1, TB2, TB3, TB4,
TB5
16-bit x 6 channels
3 channels
Clock synchronous serial I/O,
Clock asynchronous serial I/O,
I2C bus1., or IEBus2.
Serial I/O
2 channels
Clock synchronous serial I/O
Serial I/O
Multi-master I2C
I2C bus x 1
A/D converter
8 bits x (8 + 2) channels
DMAC
2 channels (trigger: 24 sources)
CRC calculation circuit
CRC-CCITT
Watchdog timer
15 bits x 1 (with prescaler)
Interrupt
25 internal and 8 external sources, 4 software sources,
7 levels
Clock generation circuit
2 circuits
• Main clock
• Sub-clock
(These circuits contain a built-in feedback resistor
and external crystal oscillator)
VCC1=3.00 V to VCC2, VCC2= 4.5 V to 5.5 V
(at f(XIN)=16MHZ)
VCC1=3.00 V to VCC2, VCC2= 4.00 V to 5.5 V
(at f(XIN)=16MHZ)3.
Power supply voltage
VCC1=2.90 V to VCC2, VCC2= 2.90 V to 5.5 V
(at f(XIN)=16MHZ, at divide-by-8 or 16)3.
VCC1=2.0 V to VCC2, VCC2=2.0 V to 5.5 V
(at f(XCIN)=32kHZ, only low-power consumption mode) 3.4.
Flash memory
Program/erase voltage
5.0 V ± 0.25 V
Number of program/erase
100 times
Device configuration
CMOS high performance silicon gate
Package
100-pin plastic mold QFP
Data slicer
Slice RAM
864 bytes (48 x 18 x 8-bit)
Data slicer
Corresponds to PDC, VPS, WSS, EPG-J, CC, CC2X and
ID-1
Rev.2.10
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M306H7MG-XXXFP/MC-XXXFP/FGFP
1. DESCRIPTION
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N.V. If you desire this option,
please so specify.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. If the VCC2 supply voltage is less than 4.50 V, the A/D converter, data slicer cannot be used.
4. If the VCC2 supply voltage is less than 2.60 V, be aware that only the CPU, RAM, clock timer,
interrupt, and I/O ports can be used. Other control circuits (e.g., timers A and B, serial I/O, UART)
cannot be used.
Table 1.2
Product table
Type No.
ROM capacity
RAM capacity
M306H7MG-XXXFP
256K bytes
8K bytes
M306H7MC-XXXFP
128K bytes
5K bytes
M306H7FGFP
256K bytes
8K bytes
Type No. M 3 0 6 H 7 M G
-
Remarks
Package type
Mask ROM version
100P6S-A
Mask ROM version
Flash Memory version
X X X F P
Package type:
FP : Package 100P6S-A
ROM No.
Omitted for flash memory version
ROM capacity:
G : 256K bytes
C : 128K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/6H Group
M16C Family
Figure 1.2
Type No, Memory Size, and Package
Rev.2.10
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M306H7MG-XXXFP/MC-XXXFP/FGFP
1.5
1. DESCRIPTION
Block Diagram
Figure 1.3 is a block diagram.
8
Port P0
8
Port P1
8
8
Port P2
Port P3
8
8
Port P4
Port P5
System clock generator
Expandable up to 10 channels)
XIN-XOUT
XCIN-XCOUT
Clock synchronous serial I/O
(8 bits X 2 channels)
CRC arithmetic circuit (CCITT)
(Polynomial :X16+X12+X5+1)
Slicer
2
M16C/60 series16-bit CPU core
R0L
R1L
DMAC
(2 channels)
ISP
INTB
RAM
PC
FLG
Multiplier
Block diagram
Rev.2.10
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REJ03B0152-0210
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8
Port P9
Figure 1.3
2
A0
A1
FB
ROM
USP
Port P86, P87
R2
R3
SB
Memory
<VCC2>
R0H
R1H
Port P85
Multi-master I C
Watchdog timer
(15 bits)
5
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
8
A-D converter
(8 bits X 8 channels
Port P80-P84
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
<VCC1>
<VCC1>
Internal peripheral functions
Port P6
Port P7
<VCC2>
8
M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 1.3
Pin name
VCC1, VCC2,
1. DESCRIPTION
Pin Description (1)
Signal name
I/O type Power supply
Power supply input
pin. Input condition of Vcc1 and Vcc2 are Vcc1 ≤ Vcc2. (1.)
VSS
RESET
XIN
CNVSS
Reset input
Clock input
Input
Input
VCC2
VCC2
Input
VCC2
XOUT
Clock output
Output
CNVSS
Function
Apply 2.00 V to 5.5 V to the Vcc1 and Vcc2 pins. Apply 0 V to the Vss
Connect this pin to VSS.
"L" on this input resets the microcomputer.
These are I/O pins provided for main clock oscillation circuit.
Connect ceramic resonator or crystal oscillator between pins XIN and
XOUT. To use an externally derived clock, input it to XIN pin and leave
XOUT pin open.
AVCC
Analog power supply input
This pin is a power supply input for the A/D converter. Connect this pin to VCC.
AVSS
Analog power supply input
This pin is a power supply input for the A/D converter. Connect this pin to VSS.
P00 to P07
I/O port P0
Input/output VCC2
This is an 8-bit CMOS I/O port. This port has an I/O select direction register,
allowing each pin in that port to be directed for input or output individually.
If any port is set for input, selection can be made for it in a program whether or
not to have a pull-up resistor in 4 bit units. Pins in this oprt also function as
A/D converter input pins as selected by Program.
P10 to P17
I/O port P1
Input/output VCC2
This is an 8-bit I/O port equivalent to P0. Pins P15 to P17 in this port also
functionas INT interrupt input pins as selected by software.
P20 to P27
I/O port P2
Input/output VCC2
This is an 8-bit I/O port equivalent to P0.
Note 1: In this datasheet, hereafter, VCC refers to VCC2 unless otherwise noted.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 1.4
Pin name
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
1. DESCRIPTION
Pin Description (2)
Signal name
I/O type
I/O port P3
I/O port P4
I/O port P5
Input/output
output
Input/output
I/O port P6
Input/output
I/O port P7
Input/output
Power supply
VCC2
VCC2
VCC2
VCC1
VCC1
Function
This is an 8-bit I/O port equivalent to P0.
This is an 8-bit I/O port equivalent to P0.
This is an 8-bit I/O port equivalent to P0.
The same frequency as divide-by-8, 32 of XIN from
P57 or XCIN are output by program selecting.
This is an 8-bit I/O port equivalent to P0.
These pins function as I/O pin of UART0 and UART1
by selecting it by the program.
This is an 8-bit I/O port equivalent to P0 (P70 and P71
are N channel open-drain output). This port can function
as I/O pins for timers A0 to A3 when so selected in a
program.
Furthermore, P70 to P73 function as I/O pins of UART2,
P71 function as input pin of timer B5, and P74 and P75
P80 to P84
I/O port
P80 to P84
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Input/output
Page 8 of 326
VCC1
(P80 to P84)
function as I/O pin of multi-master I2C bus.
P80 to P84, P86, and P87 are I/O ports with the same
functions as P0. When selected by a program,
P80 to P81 function as I/O pins of timer A4, P82 to P84
function input pin of INT interrupt.
And, P84 also function as output pin for remote control.
M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 1.5
Pin name
1. DESCRIPTION
Pin Description (3)
Signal name
I/O type
Power supply
VCC2 (P85
to P87)
I/O port P85
Input/output
Input/output
Input
P90 to P97
I/O port P9
Input/output
VCC2
VDD2, VSS2
Power supply
input
CVIN
Composite video
signal input 1
Composite video
signal input 2
Oscillation
selection input
Filter output 2
Filter output 3
P86,
P87,
I/O port P86
I/O port P87
P85
SYNCIN
STARTB
LP3
LP4
VCC OFF
M1
TEST1
VCC1 Power supply
input select
Mode selection
input (M1 input)
Test input
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Function
P86 and P87 that when selected in a program, both can function as I/O
pins for sub clock oscillation circuit. In that case, connect crystal
resonator between P86 (XCOUT pin) and P87 (XCIN pin).
P85 is an input-only port shared with NMI. NMI interrupt is generated
when input on this pin changes state from high to low.
NMI function cannot be disabled in a program. Pull-up resistor cannot
be set for this pin.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as SI/O3 and SI/O4 of I/O pins, Timer B0 to B4 input pins, A/D
converter input pins, A/D trigger input pins, or remote control input pins
as selected by program.
Analog power supply pin. Apply the same potential as VCC2 to the
VDD2 pin. Apply 0 V to the VSS2 pin.
Input
VCC2
This pin inputs the external composite video signal. Data-acquisition
slices this signal internally by setting.
Input
VCC2
Input
VCC2
This pin inputs the external composite video signal. Sync.-separate
circuit devides this signal internally.
This pin selects the oscillation circuit. XIN-XOUT circuit is selected when
this pin is "L"; XCIN-XCOUT circuit is selected when this pin is "H".
output
output
Input
VDD2
Input
VCC2
input "H" level.
Connect it to the VSS.In the mask ROM version, connect this pin to the
VSS or the VCC2.
Input
VCC2
This is a test pin. Connect a capacitor.
VDD2
VCC2
Page 9 of 326
This is a filter output pin 2 (for VPS).
This is a filter output pin 3 (for PDC).
Normally, please input "L" level. When VCC1 power supply is off, please
M306H7MG-XXXFP/MC-XXXFP/FGFP
1.6
1. DESCRIPTION
Memory
Figure 1.4 is a memory map of M306H7MG-XXXFP/MC-XXXFP/FCFP. The address space extends the
1M bytes from address 0000016 to FFFFF16.
The internal ROM is allocated in a lower address direction beginning with address FFFFF16. An internal
ROM of M306H7MC-XXXFP, for instance, is allocated to the addresses from E000016 to FFFFF16.
The fixed interrupt vector table is allocated to the addresses from FFFDC16 to FFFFF16. Therefore, store
the start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 0040016. An internal
RAM of M306H7MC-XXXFP, for instance, is allocated to the addresses from 0040016 to 017FF16. In
addition to storing data, the internal RAM also stores the stack used when calling subroutines and when
interrupts are generated.
SFR is allocated to the addresses from 0000016 to 003FF16. Peripheral function control registers are
located here. Of SFR, any area which has no functions allocated is reserved for future use and cannot
be used by users.
The special page vector table is allocated to the addresses from FFE0016 to FFFDB16. This vector is
used by the JMPS or JSRS instruction. For details, refer to the “M16C/60 and M16C/20 Series Software
Manual.”
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be
used by users.
0000016
SFR
0040016
Internal RAM
FFE0016
XXXXX 16
Special page
vector table
FFFDC16 Undefined instruction
Overflow
BRK instruction
Address match
Single step
Size
Internal RAM
Address XXXXX16
Size
Internal ROM
Address YYYYY16
5K bytes
17FF16
128K bytes
E000016
8K bytes
23FF16
256K bytes
C000016
Figure 1.4
Memory Map
Rev.2.10
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REJ03B0152-0210
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Watchdog timer
DBC
YYYYY16
Internal ROM
FFFFF16
FFFFF16
NMI
Reset
M306H7MG-XXXFP/MC-XXXFP/FGFP
2.
2. CENTRAL PROCESSING UNIT (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R0H(R0's high bits) R0L(R0's low bits)
R3
R1H(R1's high bits) R1L(R1's low bits)
R2
Data registers (Note)
R3
A0
b19
A1
Address registers (Note)
FB
Frame base registers (Note)
b15
b0
INTBH
INTBL
Interrupt table register
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
PC
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1
2.1
CPU registers
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32- bit data
register (R2R0). R3R1 is the same as R2R0.
2.2
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M306H7MG-XXXFP/MC-XXXFP/FGFP
2.3
2. CENTRAL PROCESSING UNIT (CPU)
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
• Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
• Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
• Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
• Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
• Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is
cleared to “0” when the interrupt request is accepted.
• Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
• Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
• Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
3.
3. RESET
Reset
There are three types of resets: a hardware reset, a software reset, and a watchdog timer reset.
3.1
Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the power supply
voltage is within the recommended operating condition, the pins are initialized (see Table 3.1).
The oscillation circuit is initialized and the main clock starts oscillating. When the input level at the RESET pin is
released from “L” to “H”, the CPU and SFR are initialized, and the program is executed starting from the address
indicated by the reset vector. The internal RAM is not initialized. If the RESET pin is pulled “L” while writing to
the internal RAM, the internal RAM becomes indeterminate.
Figure 3.1 shows the example reset circuit. Figure 3.2 shows the reset sequence. Table 3.1 shows the statuses of the
other pins while the RESET pin is “L”. Figure 3.3 shows the CPU register status after reset.
Refer to “SFR” for SFR status after reset.
1. When the power supply is stable
• When STARTB pin = “L”
(1) Apply an “L” signal to the RESET pin.
(2) Apply a clock for 20 cycles or more to the XIN pin.
(3) Apply an “H” signal to the RESET pin.
• When STARTB pin = “H”
(1) Apply an “L” signal to the RESET pin.
(2) Apply a clock for 20 cycles or more to the XCIN pin.
(3) Apply an “H” signal to the RESET pin.
2. Power on
• When STARTB pin = “L”
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply is stabilized.
(4) Apply a clock for 20 cycles or more to the XIN pin.
(5) Apply an “H” signal to the RESET pin.
• When STARTB pin = “H”
(1) Apply an “L” signal to the RESET pin.
(2) Let the power supply voltage increase until it meets the recommended operating condition.
(3) Wait td(P-R) or more until the internal power supply is stabilized.
(4) Apply a clock for 20 cycles or more to the XCIN pin.
(5) Apply an “H” signal to the RESET pin.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
3. RESET
VCC2
Recommended
operating
voltage
0V
RESET
VCC2
RESET
0V
Equal to or less
than 0.2 VCC2
Equal to or less
than 0.2 VCC2
Apply the clock of 20 cycles or more to
the td(P-R) + XIN or XCIN pin. (Note 1)
Notes 1: When the STARTB pin=L, apply the clock of 20 cycles or more to the XIN pin.
When the STARTB pin=H, apply the clock of 20 cycles or more to the XCIN pin.
Notes 2: If VCC1 ≤ VCC2, the VCC1 voltage must be lower than that of VCC2 when the power is being turned on or off.
Figure 3.1
3.2
Example Reset Circuit
Software Reset
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,
CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset vector.
Select the main clock for the CPU clock source, and set the PM03 bit to “1” with main clock oscillation
satisfactorily stable.
At software reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the PM0
register are not initialized, the processor mode remains unchanged.
3.3
Watchdog Timer Reset
Where the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer
initializes its pins, CPU and SFR if the watchdog timer underflows. Then the program is executed starting from the
address indicated by the reset vector.
At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”. Also, since the PM01 to PM00 bits in the
PM0 register are not initialized, the processor mode remains unchanged.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
3. RESET
VCC
XIN / XCIN
td(P-R)
More than
20 cycles
are needed
(Note)
RESET
BCLK
28 cycles
BCLK
Single chip
mode
FFFFC16
Content of reset vector
FFFFE16
Address
Note : When the STARTB pin= "L", apply the clock of 20 cycles or more to the XIN pin after waiting for td(P-R) until the internal power supply is stabilized.
When the STARTB pin= "H", apply the clock of 20 cycles or more to the XCIN pin after waiting for td(P-R) until the internal power supply is stabilized.
Figure 3.2
Reset Sequence
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 3.1
3. RESET
Pin Status When RESET Pin Level is “L
Status
Pin name
CNVSS = VCC (Note)
CNVSS = VSS
BYTE = VSS
BYTE = VCC
P0
Input port
Data input
Data input
P1
Input port
Data input
Input port
P2, P3, P40 to P43
Input port
Address output (undefined)
Address output (undefined)
P44
Input port
CS0 output ("H" is output)
CS0 output ("H" is output)
P45 to P47
Input port
Input port (Pulled high)
Input port (Pulled high)
P50
Input port
WR output ("H" is output)
WR output ("H" is output)
P51
Input port
BHE output (undefined)
BHE output (undefined)
P52
Input port
RD output ("H" is output)
RD output ("H" is output)
P53
Input port
BCLK output
BCLK output
P54
Input port
HLDA output (The output value HLDA output (The output value
depends on the input to the
depends on the input to the
HOLD pin)
HOLD pin)
P55
Input port
HOLD input
HOLD input
P56
Input port
ALE output ("L" is output)
ALE output ("L" is output)
P57
Input port
RDY input
RDY input
Input port
Input port
P6, P7, P80 to P84, Input port
P86, P87, P9
Note : Do not set CNVss=Vcc for this product.
b15
b0
000016
Data register(R0)
000016
Data register(R1)
000016
Data register(R2)
000016
Data register(R3)
000016
000016
Address register(A0)
Address register(A1)
000016
Frame base register(FB)
b19
b0
0000016
Interrupt table register(INTB)
Content of addresses FFFFE16 to FFFFC16
b15
Program counter(PC)
b0
000016
User stack pointer(USP)
000016
Interrupt stack pointer(ISP)
000016
Static base register(SB)
b15
b0
Flag register(FLG)
000016
b15
b8
IPL
Figure 3.3
b7
U I
b0
O B S Z D C
CPU Register Status After Reset
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M306H7MG-XXXFP/MC-XXXFP/FGFP
3.4
3. RESET
SFR
Register (Note 1)
Address
After reset
Symbol
000016
000116
000216
000316
000516
Processor mode register 0
Processor mode register 1
000616
System clock control register 0
CM0
000716
System clock control register 1
CM1
001000002
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX002
XX0000002
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
Address match interrupt register 1
RMAD1
0016
0016
X016
001E16
Processor mode register 2
PM2
XXX000002
001F 16
002016
DMA0 source pointer
SAR0
XX16
XX16
XX16
DMA0 destination pointer
DAR0
XX16
XX16
XX16
DMA0 transfer counter
TCR0
XX16
XX16
DMA0 control register
DM0CON
00000X002
DMA1 source pointer
SAR1
XX16
XX16
XX16
DMA1 destination pointer
DAR1
XX16
XX16
XX16
DMA1 transfer counter
TCR1
XX16
XX16
DMA1 control register
DM1CON
00000X002
000416
(Note 2)
PM0
PM1
000000002
000010002
010010002(the STARTB pin is "L")
011110002(the STARTB pin is "H")
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
0011 16
001216
XX16
00XXXXXX2(Note 3)
0016
0016
X016
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 3: The WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program.
X : Undefined
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Register
Address
3. RESET
Symbol
After reset
INT3IC
TB5IC
XX00X0002
XXXXX0002
XXXXX0002
004016
004116
004216
004316
004416
004516
004616
INT3 interrupt control register
Timer B5/SLICE ON interrupt control register
Timer B4/Remote control interrupt control register, UART1 BUS collision detection interrupt
control register
TB4IC, U1BCNIC
004716
Timer B3/HINT interrupt control register, UART0 BUS collision detection interrupt control register
TB3IC, U0BCNIC
004816
SI/O4 interrupt control register, INT5 interrupt control register
SI/O3 interrupt control register, INT4 interrupt control register
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
S4IC, INT5IC
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
004916
004A16
004B16
004C16
XXXXX0002
XX00X0002
XX00X0002
XXXXX0002
XXXXX0002
XXXXX0002
004D16
004E16
A/D conversion interrupt control register
004F16
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2/Clock timer interrupt control register
INT0 interrupt control register
INT1 interrupt control register
INT2 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note :The blank areas are reserved and cannot be accessed by users.
X : Undefined
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ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XX00X0002
XX00X0002
XX00X0002
M306H7MG-XXXFP/MC-XXXFP/FGFP
3. RESET
Register
Address
Symbol
After reset
008016
008116
008216
008316
008416
008516
008616
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
Flash memory control register 1
(Note 2)
FMR1
0X00XX0X2
Flash memory control register 0
Address match interrupt register 2
(Note 2)
FMR0
RMAD2
XX0000012
0016
0016
X016
XXXXXX002
0016
0016
X016
01B616
01B716
01B816
01B916
01BA16
01BB16
Address match interrupt enable register 2
01BC16
Address match interrupt register 3
AIER2
RMAD3
01BD16
01BE16
01BF16
~
~
020016
020116
Remote control transmission buffer register
RMTTMHL
0016
0016
~
~
020E16
020F16
Slice RAM address control register
SA
0016
021016
0211 16
Slice RAM data control register
SD
0016
021216
021316
021416
021516
Address control register for CRC registers
CA
0016
Data control register for CRC registers
CD
0016
021616
021716
Address control register for extended registers
DA
0016
021816
021916
Data control register for extended registers
DD
0016
021A16
021B16
Humming 8/4 register
HM8
0016
021C16
021D16
Humming 24/18 register 0
HM0
0016
021E16
021F16
Humming 24/18 register 1
HM1
0016
025016
~
~
025916
025A16
025B16
025C16
025D16
025E16
Peripheral clock select register
PCLKR
00000011 2
025F16
~
~
02D616
I2C0 interrupt control register
02D716
Reserved register
EXTIICINT
EXTREG02D7
0016
0016
02E016
I 2C data shift register
I 2C address register
I 2C states register
I 2C control register
I 2C clock control register
Reserved register
I 2C transmit buffer register
IIC0S0
IIC0S0D
IIC0S1
IIC0S1D
IIC0S2
REVREG02E5
IIC0S0S
Undefined
0016
~
02E116
02E216
02E316
02E416
02E516
02E616
~
0330 16
0331 16
0332 16
0333 16
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: This register is included in the flash memory version.
X : Undefined
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0001000?2
0016
0016
00?000002
Undefined
M306H7MG-XXXFP/MC-XXXFP/FGFP
Timer B3, 4, 5 count start flag
Register
Symbol
TBSR
Timer B3 register
TB3
Timer B4 register
TB4
Timer B5 register
TB5
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
Interrupt cause select register 2
Interrupt cause select register
SI/O3 transmit/receive register
TB3MR
TB4MR
TB5MR
IFSR2A
IFSR
S3TRR
00XX00002
00XX00002
00XX00002
00XXXXXX2
0016
XX16
SI/O3 control register
SI/O3 bit rate generator register
SI/O4 transmit/receive register
S3C
S3BRG
S4TRR
010000002
XX16
XX16
SI/O4 control register
SI/O4 bit rate generator register
S4C
S4BRG
010000002
XX16
UART0 special mode register 4
UART0 special mode register 3
UART0 special mode register 2
UART0 special mode register
UART1 special mode register 4
UART1 special mode register 3
UART1 special mode register 2
UART1 special mode register
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
UART2 transmit buffer register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
0016
000X0X0X2
X00000002
X00000002
0016
000X0X0X2
X00000002
X00000002
0016
000X0X0X2
X00000002
X00000002
0016
XX16
XXXXXXXX2
XXXXXXXX2
000010002
000000102
XXXXXXXX2
XXXXXXXX2
Address
034016
3. RESET
After reset
000XXXXX2
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B 16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
XX16
XX16
XX16
XX16
XX16
XX16
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Note : The blank areas are reserved and cannot be accessed by users.
X : Undefined
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Register
3. RESET
Count start flag
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After reset
0016
0XXXXXXX2
0016
0016
0016
Timer A0 register
TA0
Timer A1 register
TA1
Timer A2 register
TA2
Timer A3 register
TA3
Timer A4 register
TA4
Timer B0 register
TB0
Timer B1 register
TB1
Timer B2 register
TB2
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
00XX00002
00XX00002
00XX00002
03A016
UART0 transmit/receive mode register
03A116
UART0 bit rate generator register
UART0 transmit buffer register
U0MR
U0BRG
U0TB
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03AD16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
03AE16
UART1 receive buffer register
U1C0
U1C1
U1RB
UART transmit/receive control register 2
UCON
0016
XX16
XXXXXXXX2
XXXXXXXX2
000010002
000000102
XXXXXXXX2
XXXXXXXX2
0016
XX16
XXXXXXXX2
XXXXXXXX2
000010002
000000102
XXXXXXXX2
XXXXXXXX2
X00000002
DMA0 request cause select register
DM0SL
0016
DMA1 request cause select register
DM1SL
0016
CRC data register
CRCD
CRC input register
CRCIN
XX16
XX16
XX16
03A216
03A316
03A416
03A516
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
03A616
UART0 receive buffer register
U0C0
U0C1
U0RB
03A716
03A816
UART1 transmit/receive mode register
03A916
UART1 bit rate generator
UART1 transmit buffer register
03AA16
U1MR
U1BRG
U1TB
03AB16
03AC16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Note : The blank areas are reserved and cannot be accessed by users.
X : Undefined
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Address
03C016
Register
3. RESET
A/D register 0
Symbol
AD0
After reset
XXXXXXXX2
A/D register 1
AD1
XXXXXXXX2
A/D register 2
AD2
XXXXXXXX2
A/D register 3
AD3
XXXXXXXX2
A/D register 4
AD4
XXXXXXXX2
A/D register 5
AD5
XXXXXXXX2
A/D register 6
AD6
XXXXXXXX2
A/D register 7
AD7
XXXXXXXX2
A/D control register 2
ADCON2
0016
A/D control register 0
A/D control register 1
ADCON0
ADCON1
00000XXX2
0016
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
Port P4 register
Port P5 register
Port P4 direction register
Port P5 direction register
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
P7
PD6
PD7
P8
P9
PD8
PD9
P10
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
0016
0016
XX16
XX16
00X000002
0016
XX16
Pull-up control register 0
PUR0
0016
Pull-up control register 1
PUR1
000000002
Pull-up control register 2
Port control register
PUR2
PCR
0016
0016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Note 1: The blank areas are reserved and cannot be accessed by users.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
3. RESET
Processor mode register 0 (Note 1)
Symbol
PM0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
Address
000416
Bit symbol
PM00
After reset
000000002 (CNVSS pin = "L")
Bit name
Processor mode bit
PM01
(b2)
Reserved bit
PM03
Software reset bit
(b7-b4)
Reserved bits
Function
RW
b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
RW
Must set to "0".
RW
Setting this bit to “1” resets the
microcomputer. When read, its content
is "0".
Must set to "0".
RW
RW
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Figure 3.4
PM0 Register
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M306H7MG-XXXFP/MC-XXXFP/FGFP
3. RESET
Processor mode register 1 (Note 1)
b7
b6
b5
b4
b3
b2
0 0 0 0
b1
b0
0
0
Symbol
PM1
Address
000516
Bit symbol
Bit name
(b1-b0)
Reserved bit
After reset
0X0010002
Function
Must set to "0".
PM12
Watchdog timer function
select bit
0 : Watchdog timer interrupt
1 : Watchdog timer reset (Note 2)
(b6-b3)
Reserved bit
Must set to "0".
PM17
Wait bit (Note 3)
0 : No wait state
1 : With wait state (1 wait)
RW
RW
RW
RW
RW
Note 1: Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).
Note 2: PM12 bit is set to “1” by writing a “1” in a program. (Writing a “0” has no effect.)
Note 3: When PM17 bit is set to “1” (with wait state), one wait state is inserted when accessing internal RAM or
internal ROM.
Figure 3.5
PM1 Register
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4.
4. CLOCK GENERATION CIRCUIT
Clock Generation Circuit
The clock generation circuit contains two oscillator circuits as follows:
(1) Main clock oscillation circuit
(2) Sub clock oscillation circuit
Table 4.1 lists the clock generation circuit specifications. Figure 4.1 shows the clock generation circuit.
Figures 4.2 to 4.4 show the clock-related registers.
Table 4.1
CPU registers
Main clock
oscillation circuit
Use of clock
Sub clock
oscillation circuit
• CPU clock source •CPU clock source
• Peripheral function • Timer A, B's clock
source
clock source
Clock frequency
0 to 16 MHz
(Note 3)
32.768 kHz
Usable oscillator
• Ceramic oscillator
• Crystal oscillator
(Note 2)
• Crystal oscillator
Pins to connect
oscillator
XIN, XOUT
XCIN, XCOUT
Oscillation stop,
restart function
Presence
Presence
Item
Oscillator status Oscillating
after reset (Note1)
Other
Stopped
Externally derived clock can be input
Note 1. The state that the STARTB pin is held "L" after reset is shown.
The state that the STARTB pin is held "H" after reset is following.
Main clock oscillation circuit: Stopped
Sub clock oscillation circuit: Oscillating
Note 2. If you use "14 Expansion Function (Data acquisition)", be sure to connect a crystal oscillator
between the XIN and XOUT pins.
Note 3. If you use "14 Expansion Function (Data acquisition)", connect a crystal of 10MHz, 12MHz,
14MHz, or 16MHz.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
CM01–CM00=002
Sub-clock
generating circuit
XCIN
I/O ports
PM01–PM00=002, CM01–CM00=012
CLKOUT
PM01–PM00=002,
CM01–CM00=11 2
PM01–PM00=002, CM01–CM00=102
XCOUT
1/32
CM04
fC32
f1
PCLK0=1
Sub-clock
f2
PCLK0=0
fC
f8
START
f32
S Q
fAD
R
f1SIO
PCLK1=1
CM07
f2SIO
Main clock
CM06
CM10=1(stop mode)
PCLK1=0
f8SIO
S Q
XIN
XOUT
f32SIO
e b c
R
a
CM05
CM07=0
d
Divider
CPU clock
fC
Main clock
generating circuit
BCLK
CM07=1
CM02
S
WAIT instruction
Q
R
e
a
RESET
c
b
1/2
1/2
1/2
1/2
1/32
1/2
1/4
1/8
Software reset
CM06=1
CM06=0
CM17–CM16=102
Interrupt request level judgment output
CM02, CM04, CM05, CM06 and CM07: CM0 register bits
CM10, CM11, CM16 and CM17: CM1 register bits
PCLK0, PCLK1: PCLK register bits
Clock Generation Circuit
Page 26 of 326
d
CM06=0
CM17–CM16=012
CM06=0
CM17–CM16=002
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1/16
CM06=0
CM17–CM16=11 2
NMI
Figure 4.1
1/2
Details of divider
M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
System clock control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CM0
Bit symbol
Address
000616
After reset (Note 14)
011110002 (STARTB pin = Vcc)
010010002 (STARTB pin = Vss)
Bit name
Function
RW
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P57
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
CM02
WAIT peripheral function
clock stop bit (Note 10)
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8) RW
CM03
XCIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
RW
Port XC select bit
(Note 2)
Main clock stop bit
(Notes 3, 10, 12, 13)
0 : I/O port P86, P87
1 : XCIN-XCOUT generation function(Note 9)
RW
0 : On
1 : Off (Note 4, Note5)
RW
CM06
Main clock division select
bit 0 (Notes 7, 13)
0 : CM16 and CM17 valid
1 : Division by 8 mode
RW
CM07
System clock select bit
(Notes 6, 10, 11, 12)
0 : Main clock
1 : Sub-clock
RW
CM00
CM01
CM04
CM05
RW
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: The CM03 bit is set to “1” (high) when the CM04 bit is set to “0” (I/O port) or the microcomputer goes to a stop mode.
Note 3: This bit is provided to stop the main clock when the low power dissipation mode is selected. This bit cannot be used for
detection as to whether the main clock stopped or not. To stop the main clock, the following setting is required:
(1) Set the CM07 bit to “1” (Sub-clock select) with the sub-clock stably oscillating.
(2) Set the CM05 bit to “1” (Stop).
Note 4: During external clock input, only the clock oscillation buffer is turned off and clock input is accepted if the sub clock is not
chosen as a CPU clock.
Note 5: When CM05 bit is set to “1, the XOUT pin goes “H”. Furthermore, because the internal feedback resistor remains connected,
the XIN pin is pulled “H” to the same level as XOUT via the feedback resistor.
Note 6: After setting the CM04 bit to “1” (X CIN-XCOUT oscillator function), wait until the sub-clock oscillates stably before switching
the CM07 bit from “0” to “1” (sub-clock).
Note 7: When entering stop mode from high or middle speed mode, the CM06 bit is set to “1” (divide-by-8 mode).
Note 8: The fC32 clock does not stop. During low speed or low power dissipation mode, do not set this bit to “1” (peripheral clock
turned off when in wait mode).
Note 9: To use a sub-clock, set this bit to “1”. Also make sure ports P8 6 and P87 are directed for input, with no pull-ups.
Note 10: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM02, CM05, and CM07 bits has
no effect.
Note 11: If the PM21 bit needs to be set to “1”, set the CM07 bit to “0”(main clock) before setting it.
Note 12: To use the main clock as the clock source for the CPU clock, follow the procedure below.
(1) Set the CM05 bit to “0” (oscillate).
(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.
(3) Set the CM07 bit all to “0”.
Note 13: When the CM05 bit is set to “1” (main clock turned off), the CM06 bit is fixed to “1” (divide-by-8 mode) and the
CM15 bit is fixed to “1” (drive capability high).
Note 14: Keep in mind that the values after reset differ by the input voltage at the STARTB pin.
Figure 4.2
CM0 Register
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
System clock control register 1 (Note 1)
b7
b6
b5
b4
b3
0 0
b2
b1
b0
0 0
Symbol
CM1
Bit symbol
Address
000716
Bit
name
All clock stop control bit
After reset
001000002
Function
RW
(Notes 4, 5)
0 : Clock on
1 : All clocks off (stop mode)
RW
(b4-b1)
Reserved bit
Must set to “0”
RW
CM15
XIN-XOUT drive capacity
select bit (Note 2)
0 : LOW
1 : HIGH
RW
CM10
b7 b6
CM16
Main clock division
select bit 1 (Note 3)
CM17
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
RW
RW
Note 1: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Note 2: When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low
speed mode, the CM15 bit is set to “1” (drive capability high).
Note 3: Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).
Note 4: If the CM10 bit is “1” (stop mode), XOUT goes “H” and the internal feedback resistor is disconnected. The XCIN and XCOUT
pins are placed in the high-impedance state.
Note 5: When the PM21 bit of PM2 register is set to “1” (clock modification disable), writing to the CM10 bits has no effect.
Figure 4.3
CM1 Register
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
Peripheral clock select register (Note)
b7
b6
b5
b4
b3
b2
b1
b0
0 0 0 0 0 0
Symbol
PCLKR
Address
025E16
When reset
00000011 2
Bit symbol
Bit name
PCLK0
Timers A, B clock select bit
(Clock source for the
timers A and B
0 : f2
1 : f1
RW
SI/O clock select bit
(Clock source for UART0
to UART2, SI/O3, SI/O4)
0 : f2SIO
1 : f1SIO
RW
Reserved bit
Must set to “0”
PCLK1
(b7-b2)
Function
RW
RW
Note: Write to this register after setting the PRC0 bit of PRCR register to “1” (write enable).
Processor mode register 2 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Symbol
PM2
Bit symbol
(b0)
PM21
(b4-b2)
(b7-b5)
Address
001E16
Bit name
Reserved bit
System clock protective
bit
(Note 2, Note 3)
Reserved bit
After reset
XXX000002
Function
Must set to “0”
0 : Clock is protected by PRCR
register
1 : Clock modification disabled
Must set to “0”
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
Note 1: Write to this register after setting the PRC1 bit of PRCR register to “1” (write enable).
Note 2: Once this bit is set to “1”, it cannot be cleared to “0” in a program.
Note 3: If the PM21 bit is set to “1,” writing to the following bits has no effect.
CM02 bit of CM0 register
CM05 bit of CM0 register (main clock is not halted)
CM07 bit of CM0 register (CPU clock source does not change)
CM10 bit of CM1 register (stop mode is not entered)
Figure 4.4
PCLKR Register and PM2 Register
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RW
RW
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
4.1
4. CLOCK GENERATION CIRCUIT
Oscillator Circuit
The following describes the clocks generated by the clock generation circuit.
Two oscillation circuits are built in the clock generating circuit, and a main clock or a sub clock can be chosen as a
CPU clock by setup of the STARTB pin after reset.
4.1.1
Main Clock
This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator
circuit is configured by connecting a resonator between the XIN and XOUT pins. The main clock oscillator
circuit contains a feedback resistor, which is disconnected from the oscillator circuit during stop mode in order
to reduce the amount of power consumed in the chip. The main clock oscillator circuit may also be configured
by feeding an externally generated clock to the X IN pin. Figure 4.5 shows the examples of main clock
connection circuit.
When the level on the STARTB pin is “L”, the main clock divided by 8 is selected for the CPU clock (Sub
clock turned off) after reset.
The power consumption in the chip can be reduced by setting the CM05 bit of CM0 register to “1” (main clock
oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock. In this case,
XOUT goes “H”. Furthermore, because the internal feedback resistor remains on, XIN is pulled “H” to XOUT via
the feedback resistor. Note that if an externally generated clock is fed into the XIN pin, the main clock cannot be
turned off by setting the CM05 bit to “1” without selecting sub clock for the CPU clock. If necessary, use an
external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to “power control”.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XIN
XIN
XOUT
XOUT
Open
(Note)
Rd
Externally derived clock
CIN
COUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 4.5
Examples of Main Clock Connection Circuit
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4.1.2
4. CLOCK GENERATION CIRCUIT
Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the
CPU clock, as well as the timer A and timer B count sources. In addition, an fc clock with the same frequency
as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT
pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator
circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock oscillator
circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 4.6 shows the examples of sub clock connection circuit.
When the level on the STARTB pin is “L ”, the sub clock is turned off after reset. At this time, the feedback
resistor is disconnected from the oscillator circuit.
To use the sub clock for the CPU clock, set the CM07 bit of CM0 register to “1 ” (sub clock) after the sub clock
becomes oscillating stably.
When a STARTB pin is “H ”, the sub clock (XCIN) divided by 8 becomes the CPU clock after reset (the main
clock stops). When you use a main clock after this, please shift according to the procedure shown in Fig. 4.7.
During stop mode, all clocks including the sub clock are turned off. Refer to “power control”.
Microcomputer
Microcomputer
(Built-in feedback resistor)
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
(Note)
RCd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 4.6
Examples of Sub Clock Connection Circuit
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
Using the main clock from the sub clock as CPU clock
source.
Set the CM07 bit to “1” (sub clock).
Set the CM05 bit to “0” (oscillating).
Waits until the main clock becomes stable.
Set the CM07 bit to “0” (main clock). (note1)
Set the main clock division ratio.
Set the CM17 to the CM16 bits to “002,” set the CM06 bit to
“0.” (CM16 bit and CM17 bit are effective) (notes 2.)
END
Note 1: Change After the oscillation of the main clock becomes stable enough.
Note 2: Setting No division of the main clock is shown.
Change CM06 after changing CM17 and CM16.
Figure 4.7
Procedure to Use the Main Clock from the Sub Clock as CPU Clock Source
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4.2
4. CLOCK GENERATION CIRCUIT
CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions.
4.2.1
CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock or sub clock.
If the main clock is selected as the clock source for the CPU clock, the selected clock source can be divided by
1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in CM0 register and the CM17 to
CM16 bits in CM1 register to select the divide-by-n value.
When the level on the STARTB pin is “H”, the main clock divided by 8 provides the CPU clock after reset.
When the level on the STARTB pin is “L”, the sub clock of frequency divided by 8 provides the CPU clock
after reset.
At this time, the CM04 bit and the CM05 bit of CM0 register become “1” .
Note that when entering stop mode from high or middle speed mode, or when the CM05 bit of CM0 register is
set to “1” (main clock turned off) in low-speed mode, the CM06 bit of CM0 register is set to “1” (divide-by-8
mode).
4.2.2
Peripheral Function Clock(f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)
These are operating clocks for the peripheral functions.
Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock by dividing them by i. The clock fi is used
for timers A and B, and fiSIO is used for serial I/O. The f8 and f32 clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, and is used for the A/D converter.
When the WAIT instruction is executed after setting the CM02 bit of CM0 register to “1” (peripheral function
clock turned off during wait mode), or when the microcomputer is in low power dissipation mode, the fi, fiSIO
and fAD clocks are turned off.
The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can be used when the
sub clock is on.
4.3
Clock Output Function
During single-chip mode, the f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00 bits of
CM0 register to select.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4.4
4. CLOCK GENERATION CIRCUIT
Power Control
There are three power control modes. For convenience’ sake, all modes other than wait and stop modes are referred
to as normal operation mode here.
4.4.1
Normal Operation Mode
Normal operation mode is further classified into four modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the CPU and
the peripheral functions are operating. Power control is exercised by controlling the CPU clock frequency. The
higher the CPU clock frequency, the greater the processing capability. The lower the CPU clock frequency, the
smaller the power consumption in the chip. If the unnecessary oscillator circuits are turned off, the power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched must
be oscillating stably. If the new clock source is the main clock or sub clock, allow a sufficient wait time in a
program until it becomes oscillating stably.
• High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the count
source for timers A and B.
• Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used as the
count source for timers A and B.
• Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral function
clock.
The fC32 clock can be used as the count source for timers A and B.
• Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides the
CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit of CM0 register becomes “1” (divided by 8 mode).
In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium speed (divided by
8) mode is to be selected when the main clock is operated next.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4.4.2
4. CLOCK GENERATION CIRCUIT
Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. Because the main clock and sub clock are on, the peripheral functions using these clocks keep
operating.
• Peripheral Function Clock Stop Function
If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO, f8SIO,
f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced that much.
However, fC32 remains on.
• Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
• Pin Status During Wait Mode
Pin Status During Wait Mode is shown in Table 4.2.
• Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral function
interrupt.
If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before executing the
WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If CM02 bit is “0” (peripheral function clocks
not turned off during wait mode), all peripheral function interrupts can be used to exit wait mode. If CM02 bit
is “1” (peripheral function clocks turned off during wait mode), the peripheral functions using the peripheral
function clocks stop operating, so that only the peripheral functions clocked by external signals can be used to
exit wait mode.
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Table 4.2
4. CLOCK GENERATION CIRCUIT
Pin Status During Wait Mode
Pin
Single-chip mode
_______
_______
A0 to A19, D0 to D15, CS0 to CS3,
________
BHE
_____
______
________
_________
RD, WR, WRL, WRH
__________
HLDA,BCLK
ALE
I/O ports
Retains status before wait mode
CLKOUT
Table 4.3
When fC selected
When f8, f32 selected
Does not stop
Does not stop when the CM02
bit is “0”.
When the CM02 bit is “1”, the
status immediately prior to
entering wait mode is maintained.
Interrupts to Exit Wait Mode
Interrupt
CM02=0
CM02=1
NMI interrupt
Can be used
Can be used
Serial I/O interrupt
Can be used when operating
with internal or external clock
Can be used when operating
with external clock
A-D conversion
interrupt
Can be used in one-shot mode
or single sweep mode
Timer A interrupt
Timer B interrupt
Can be used in all modes
Can be used in event counter
mode or when the count
source is fC32
INT interrupt
Can be used
Can be used
(Do not use)
Table 4.3 lists the interrupts to exit wait mode.
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the following
before executing the WAIT instruction.
(1) In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral
function interrupt to be used to exit wait mode. Also, for all of the peripheral function interrupts not used to
exit wait mode, set the ILVL2 to ILVL0 bits to “0002” (interrupt disable).
(2) Set the I flag to “1”.
(3) Enable the peripheral function whose interrupt is to be used to exit wait mode. In this case, when an
interrupt request is generated and the CPU clock is thereby turned on, an interrupt routine is executed.
The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU clock that
was on when the WAIT instruction was executed.
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4.4.3
4. CLOCK GENERATION CIRCUIT
Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of
power is consumed in this mode. If the voltage applied to Vcc pins is VRAM or more, the internal RAM is
retained.
However, the peripheral functions clocked by external signals keep operating. The following interrupts can be
used to exit stop mode.
• NMI interrupt
• INT interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
The internal oscillator circuit of expansion function (Data acquisition / humming function) stops oscillation
when expansion register XTAL_VCO, PDC_VCO_ON, VPS_VCO_ON = "L".
• Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit of CM1 register to “1” (all clocks turned
off). At the same time, the CM06 bit of CM0 register is set to “1” (divide-by-8 mode) and the CM15 bit of
CM1 register is set to “1” (main clock oscillator circuit drive capability high).
• Pin Status in Stop Mode
Table 4.4 lists pin status during stop mode
• Exiting Stop Mode
The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral function
interrupt.
If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the peripheral
function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the CM10 bit to
“1”.
If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the following
before setting the CM10 bit to “1”.
(1) In the ILVL2 to ILVL0 bits of interrupt control register, set the interrupt priority level of the peripheral
function interrupt to be used to exit stop mode.
Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0 bits to
“0002”.
(2) Set the I flag to “1”.
(3) Enable the peripheral function whose interrupt is to be used to exit stop mode.
In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an interrupt
service routine is executed.
Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is determined
by the CPU clock that was on when the microcomputer was placed into stop mode as follows:
If the CPU clock before entering stop mode was derived from the sub clock: sub clock
If the CPU clock before entering stop mode was derived from the main clock: main clock divide-by-8
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Table 4.4
4. CLOCK GENERATION CIRCUIT
Pin Status in Stop Mode
Pin
_______
Single-chip mode
_______
A0 to A19, D0 to D15, CS0 to CS3,
________
BHE
_____
______
________
_________
RD, WR, WRL, WRH
__________
HLDA, BCLK
ALE
I/O ports
CLKOUT
When fc selected
When f8, f32 selected
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Retains status before stop mode
“H”
Retains status before stop mode
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M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
Figure 4.8 shows the state transition from normal operation mode to stop mode and wait mode.
Figure 4.9 shows the state transition in normal operation mode.
Reset
All oscillators stopped
WAIT
instruction
CM10=1
Medium-speed mode
(divided-by-8 mode)
Stop mode
Interrupt
Interrupt
CM07=0
CM06=1
CM05=0
CM10=1
(Note 2)
High-speed, mediumspeed mode
Stop mode
CM10=1
CM10=1
Stop mode
Interrupt
Low-speed, low power
dissipation mode
Normal mode
State Transition to Stop Mode and Wait Mode
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Wait mode
Interrupt
WAIT
instruction
When
low power When
dissipation lowmode
speed
mode
Figure 4.8
CPU operation stopped
Page 39 of 326
Wait mode
Interrupt
WAIT
instruction
Interrupt
Wait mode
M306H7MG-XXXFP/MC-XXXFP/FGFP
4. CLOCK GENERATION CIRCUIT
Main clock oscillation
High-speed mode
CPU clock: f(XIN)
Middle-speed mode
(divide by 2)
CPU clock: f(XIN)/2
Middle-speed mode
(divide by 4)
CPU clock: f(XIN)/4
CM07=0
CM07=0
CM07=0
CM06=0
CM06=0
CM06=0
CM17=0
CM17=0
CM17=1
CM16=0
CM16=1
CM16=0
Middle-speed mode Middle-speed mode
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/8
CPU clock: f(XIN)
Middle-speed mode
(divide by 2)
CM17=1
CM16=1
CPU clock: f(XIN)/2
Middle-speed mode
(divide by 4)
Middle-speed mode Middle-speed mode
(divide by 8)
(divide by 16)
CPU clock: f(XIN)/4
CPU clock: f(XIN)/8
CM07=0
CM07=0
CM07=0
CM06=0
CM06=0
CM06=0
CM17=0
CM17=0
CM17=1
CM16=0
CM16=1
CM16=0
CM06=1
CM07=0
(Note 1, Note 3)
Low-speed mode
CM07=0
CM05=1
CM05=0
Low power dissipation mode
CPU clock: f(XCIN)
CM07=0
CM06=1
CM15=1
Sub clock oscillation
Notes:
1: Switch clock after oscillation of main clock is sufficiently stable.
2: Switch clock after oscillation of sub-clock is sufficiently stable.
3: Change CM17 and CM16 before changing CM06.
4: Transit in accordance with arrow.
State Transition in Normal Mode
Page 40 of 326
CPU clock: f(XIN)/16
CM07=0
CPU clock: f(XCIN)
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CM06=0
CM04=0
CM07=1
(Note 2)
Figure 4.9
CM07=0
CM06=1
CM04=1
High-speed mode
CPU clock: f(XIN)/16
CM07=0
CM07=0
CM06=0
CM17=1
CM16=1
M306H7MG-XXXFP/MC-XXXFP/FGFP
4.5
4. CLOCK GENERATION CIRCUIT
System Clock Protective Function
When the main clock is selected for the CPU clock source, this function disables the clock against modifications in
order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit of PM2 register is set to “1” (clock modification disabled), the following bits are protected against
writes:
• CM02, CM05, and CM07 bits in CM0 register
• CM10, CM11 bits in CM1 register
Before the system clock protective function can be used, the following register settings must be made while the
CM05 bit of CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for the CPU
clock source):
(1) Set the PRC1 bit of PRCR register to “1” (enable writes to PM2 register).
(2) Set the PM21 bit of PM2 register to “1” (disable clock modification).
(3) Set the PRC1 bit of PRCR register to “0” (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is “1”.
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5.
5. PROTECTION
Protection
In the event that a program runs out of control, this function protects the important registers so that they will not be
rewritten easily. Figure 5.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
• Registers protected by PRC0 bit: CM0, CM1 and PCLKR registers
• Registers protected by PRC1 bit: PM0, PM1 and PM2 registers
• Registers protected by PRC2 bit: PD9, S3C and S4C registers
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write
protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit
to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to “1”
and the next instruction. The PRC0 and PRC1 bits are not automatically cleared to “0” by writing to any address. They
can only be cleared in a program.
Protect register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PRCR
Address
000A16
Bit symbol
Bit name
0 0 0
PRC0
Protect bit 0
After reset
XX0000002
Function
Enable write to CM0, CM1 and
PCLKR registers
0 : Write protected
1 : Write enabled
PRC1
Protect bit 1
Protect bit 2
Enable write to PD9, S3C and
S4C registers
0 : Write protected
1 : Write enabled
(b5-b3)
(b7-b6)
Reserved bit
RW
Enable write to PM0, PM1 and
PM2 registers
0 : Write protected
1 : Write enabled
PRC2
RW
Must set to “0”
RW
RW
RW
Nothing is assigned. When write, set to “0”. When read, its
content is interdeterminate.
Note: The PRC2 bit is set to “0” by writing to any address after setting it to “1”. Other bits are not set to “0”
by writing to any address, and must therefore be set in a program.
Figure 5.1
PRCR Register
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6.
6. INTERRUPTS
Interrupts
6.1
Type of Interrupts
Figure 6.1 shows types of interrupts.
Software
(Non-maskable interrupt)
Interrupt
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
_______
NMI
________
Hardware
Special
(Non-maskable interrupt)
DBC (Note 2)
Watchdog timer
Single step (Note 2)
Address match
Peripheral function (Note 1)
(Maskable interrupt)
Note 1: Peripheral function interrupts are generated by the microcomputer's internal functions.
Note 2: Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
Figure 6.1
Interrupts
• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose
interrupt priority can be changed by priority level.
• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or
whose interrupt priority cannot be changed by priority level.
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6.2
6. INTERRUPTS
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
• Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation
resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can
be specified for the INT instruction. Because software interrupt Nos. 4 to 31 are assigned to peripheral
function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by
executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is cleared to
“0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when
returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state
during instruction execution, and the SP then selected is used.
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6.3
6. INTERRUPTS
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
• Special Interrupts
Special interrupts are non-maskable interrupts.
(1) NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details about
the NMI interrupt, refer to the section "NMI interrupt".
(2) DBC Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support tools.
(3) Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the
watchdog timer. For details about the watchdog timer, refer to the section "watchdog timer".
(4) Single-step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support tools.
(5) Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address indicated
by the RMAD0 to RMAD3 register that corresponds to one of the AIER register’s AIER0 or AIER1 bit or the
AIER2 register’s AIER20 or AIER21 bit which is "1" (address match interrupt enabled). For details about the
address match interrupt, refer to the section "address match interrupt".
• Peripheral Function Interrupts
Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal
functions. The interrupt sources for peripheral function interrupts are listed in Table 6.2. For details about the
peripheral functions, refer to the description of each peripheral function in this manual.
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6.4
6. INTERRUPTS
Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt
vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt
vector. Figure 6.2 shows the interrupt vector.
MSB
Vector address (L)
LSB
Low address
Mid address
Vector address (H)
Figure 6.2
0000
High address
0000
0000
Interrupt Vector
• Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 6.1 lists the fixed
vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are
used by the ID code check function. For details, refer to the section "flash memory rewrite disabling function".
Table 6.1
Fixed Vector Tables
Interrupt source
Vector table addresses
Address (L) to address (H)
Undefined instruction FFFDC16 to FFFDF16
Overflow
FFFE016 to FFFE3 16
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the contents of address
FFFE716 is FF16, program execution starts from the address
shown by the vector in the
relocatable vector table.
Reference
M16C/60, M16C/20
series software
manual
BRK instruction
FFFE416 to FFFE7 16
Address match
FFFE816 to FFFEB16
Address match interrupt
Single step (Note)
Watchdog timer
________
DBC (Note)
FFFEC16 to FFFEF 16
FFFF016 to FFFF3 16
FFFF416 to FFFF7 16
Watchdog timer
NMI
FFFF816 to FFFFB 16
_______
NMI interrupt
Reset
FFFFC16 to FFFFF 16
Reset
Note: Do not normally use this interrupt because it is provided exclusively for use by development support tools.
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6. INTERRUPTS
• Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table
area. Table 6.2 lists the relocatable vector tables. Setting an even address in the INTB register results in the
interrupt sequence being executed faster than in the case of odd addresses.
Table 6.2
Relocatable Vector Tables
Interrupt source
BRK instruction (Note 5)
Vector address (Note 1)
Address (L) to address (H)
Software interrupt
number
+0 to +3 (000016 to 000316)
0
1 to 3
(Reserved)
Reference
M16C/60, M16C/20
series software
manual
+16 to +19 (001016 to 001316)
4
INT interrupt
+20 to +23 (001416 to 001716)
5
Timer
Timer B4/Remote control, UART1 bus
collision detect (Note 4, Note 6, Note 7)
+24 to +27 (001816 to 001B16)
6
Timer B3/HINT, UART0 bus collision
detect (Note 4, Note 6, Note 7)
+28 to +31 (001C16 to 001F16)
7
INT3
Timer B5/SLICE ON (Note 7)
Timer
Serial I/O
SI/O4, INT5
(Note 2)
+32 to +35 (002016 to 002316)
8
SI/O3, INT4
(Note 2)
+36 to +39 (002416 to 002716)
9
INT interrupt
Serial I/O
+40 to +43 (002816 to 002B16)
10
Serial I/O
DMA0
+44 to +47 (002C16 to 002F16)
11
DMA1
+48 to +51 (003016 to 003316)
12
A/D
+56 to +59 (003816 to 003B16)
14
UART2 transmit, NACK2 (Note 3)
+60 to +63 (003C16 to 003F16)
15
UART 2 bus collision detection
UART2 receive, ACK2 (Note 3)
+64 to +67 (004016 to 004316)
16
UART0 transmit, NACK0 (Note 3)
+68 to +71 (004416 to 004716)
17
UART0 receive, ACK0 (Note 3)
+72 to +75 (004816 to 004B16)
18
UART1 transmit, NACK1(Note 3)
+76 to +79 (004C16 to 004F16)
19
UART1 receive, ACK1 (Note 3)
+80 to +83 (005016 to 005316)
20
Timer A0
+84 to +87 (005416 to 005716)
21
Timer A1
+88 to +91 (005816 to 005B16)
22
Timer A2
+92 to +95 (005C16 to 005F16)
23
+96 to +99 (006016 to 006316)
24
+100 to +103 (006416 to 006716)
25
Timer B0
+104 to +107 (006816 to 006B16)
26
Timer B1
+108 to +111 (006C16 to 006F16)
27
Timer B2/Clock timer (Note 7)
+112 to +115 (007016 to 007316)
28
INT0
+116 to +119 (007416 to 007716)
29
INT1
+120 to +123 (007816 to 007B16)
30
INT2/Remote control transmission (Note 8) +124 to +127 (007C16 to 007F16)
31
+128 to +131 (008016 to 008316)
32
to
63
Timer A3
Timer A4/Multi-master I 2 C (Note 9)
Software interrupt (Note 5)
to
+252 to +255 (00FC16 to 00FF16)
DMAC
A/D converter
Serial I/O
Timer
INT interrupt
M16C/60, M16C/20
series software
manual
Notes 1: Address relative to address in INTB.
Notes 2: Use the IFSR register's IFSR6 and IFSR7 bits to select.
Notes 3: During I2C mode, NACK and ACK interrupts comprise the interrupt source.
Notes 4: Use the IFSR2A register’s IFSR26 and IFSR27 bits to select.
Notes 5: These interrupts cannot be disabled using the I flag.
Notes 6: Bus collision detection : During IE mode, this bus collision detection constitutes the cause of an interrupt.
During I2C mode, however, a start condition or a stop condition detection
constitutes the cause of an interrupt.
Notes 7: When you use SLICEON, remote control, HINT and clock timer interruption, refer to address 3616 expansion
register of “14. Expansion Function”
Notes 8: Please refer to address 3E16 of the expansion register of “14. Expansion Function” when you use the remote
control transmission interrupt.
Notes 9: Please refer to the I2C0 interrupt control register of “11 multi-master I2C-BUS interface” (address 02D616) when
you use multi master I2C interrupt.
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6.5
6. INTERRUPTS
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order
they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable the
maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register.
Figure 6.3 shows the interrupt control registers.
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6. INTERRUPTS
Interrupt control register (Note 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TB5IC
TB4IC/U1BCNIC (Note 3)
TB3IC/U0BCNIC (Note 3)
BCNIC
DM0IC, DM1IC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Bit symbol
ILVL0
Address
004516
004616
004716
004A16
004B16, 004C16
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
005A16 to 005C16
Bit name
Function
Interrupt priority level
select bit
ILVL1
ILVL2
IR
After reset
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
XXXXX0002
Interrupt request bit
b2 b1 b0
000:
001:
010:
011:
100:
101:
110:
111:
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0 : Interrupt not requested
1 : Interrupt requested
RW
RW
RW
RW
RW
(Note 1)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
(b7-b4)
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: Use the IFSR2A register to select.
b7
b6
b5
b4
b3
0
b2
b1
b0
Symbol
INT3IC
S4IC/INT5IC
S3IC/INT4IC
INT0IC to INT2IC
Bit symbol
ILVL0
Address
004416
004816
0049 16
005D16 to 005F16
Bit name
Interrupt priority level
select bit
ILVL1
ILVL2
IR
POL
After reset
XX00X0002
XX00X0002
XX00X0002
XX00X0002
Function
RW
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
RW
b2 b1 b0
RW
RW
Interrupt request bit
0: Interrupt not requested
1: Interrupt requested
Polarity select bit
0 : Selects falling edge (Notes 3, 4)
1 : Selects rising edge
RW
Must always be set to “0”
RW
Reserved bit
(b7-b6)
No functions are assigned.
When writing to these bits, write “0”. The values in these bits
when read are indeterminate.
RW
(Note 1)
RW
Note 1: This bit can only be reset by writing "0" (Do not write "1").
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that
register. For details, see the precautions for interrupts.
Note 3: If the IFSR register’s IFSRi bit (i = 0 to 5) is "1" (both edges), set the INTiIC register’s POL bit to "0 "(falling
edge).
Note 4: Set the S3IC or S4IC register’s POL bit to "0" (falling edge) when the IFSR register’s IFSR6 bit = 0 (SI/O3
selected) or IFSR7 bit = 0 (SI/O4 selected), respectively
.
Figure 6.3
Interrupt Control Registers
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6.6
6. INTERRUPTS
I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable
interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.
6.7
IR Bit
The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is cleared to “0” (=
interrupt not requested).
The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.
6.8
ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 6.3 shows the settings of interrupt priority levels and Table 6.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
• I flag = “1”
• IR bit = “1”
• interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one another.
Table 6.3
Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 bits
Interrupt priority
level
0002
Level 0 (interrupt disabled)
0012
Level 1
0102
Priority
order
Table 6.4
IPL
Interrupt Priority Levels Enabled
by IPL
Enabled interrupt priority levels
0002
Interrupt levels 1 and above are enabled
0012
Interrupt levels 2 and above are enabled
Level 2
0102
Interrupt levels 3 and above are enabled
0112
Level 3
0112
Interrupt levels 4 and above are enabled
1002
Level 4
1002
Interrupt levels 5 and above are enabled
1012
Level 5
1012
Interrupt levels 6 and above are enabled
1102
Level 6
1102
Interrupt levels 7 and above are enabled
Level 7
1112
All maskable interrupts are disabled
1112
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High
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6.9
6. INTERRUPTS
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant
the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of
the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt
occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily
suspends the instruction being executed, and transfers control to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 6.4 shows time required for executing
the interrupt sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading the
address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not requested).
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal temporary
register(Note 1).
(3) The I, D and U flags in the FLG register become as follows:
The I flag is cleared to “0” (interrupts disabled).
The D flag is cleared to “0” (single-step interrupt disabled).
The U flag is cleared to “0” (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is executed.
(4) The CPU’s internal temporary register (Note 1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the accepted interrupt is set in the IPL.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, the processor resumes executing instructions from the start address of
the interrupt routine.
Note: This register cannot be used by user.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address
000016
Address bus
Interrupt
information
Data bus
RD
WR
Indeterminate (Note 1)
Indeterminate (Note 1)
SP-2
SP-4
SP-2
contents
SP-4
contents
vec
vec
contents
vec+2
PC
vec+2
contents
Indeterminate (Note 1)
(Note 2)
Note 1 : The indeterminate state depends on the instruction queue buffer. A read cycle occurs when
the instruction queue buffer is ready to accept instructions.
Note 2 : The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 6.4
Time Required for Executing Interrupt Sequence
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6.10
6. INTERRUPTS
Interrupt Response Time
Figure 6.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time
from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.
Specifically, it consists of a time from when an interrupt request is generated till when the instruction then
executing is completed ((a) in Figure 6.5) and a time during which the interrupt sequence is executed ((b) in Figure
6.5).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
Interrupt sequence
(a)
Instruction in
interrupt routine
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address SP value 16-Bit bus, without wait
Figure 6.5
6.11
8-Bit bus, without wait
Even
Even
18 cycles
20 cycles
Even
Odd
19 cycles
20 cycles
Odd
Even
19 cycles
20 cycles
Odd
Odd
20 cycles
20 cycles
Interrupt response time
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed in Table
6.5 is set in the IPL. Shown in Table 6.5 are the IPL values of software and special interrupts when they are
accepted.
Table 6.5
IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Interrupt sources
Watchdog timer, NMI
Software, address match, DBC, single-step
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Level that is set to IPL
7
Not changed
M306H7MG-XXXFP/MC-XXXFP/FGFP
6.12
6. INTERRUPTS
Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits of the FLG register, 16
bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 6.6 shows the stack
status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use the PUSHM
instruction, and all registers except SP can be saved with a single instruction.
Stack
Address
MSB
Stack
m–4
m–4
PC L
m–3
m–3
PC M
m–2
m–2
FLGL
Address
MSB
LSB
m–1
m–1
m
Content of previous stack
m+1
Content of previous stack
[SP]
SP value before
interrupt occurs
Stack status before interrupt request
is acknowledged
Figure 6.6
LSB
FLGH
[SP]
New SP value
PCH
m
Content of previous stack
m+1
Content of previous stack
Stack status after interrupt request
is acknowledged
Stack Status Before and After Acceptance of Interrupt Request
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6. INTERRUPTS
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(Note), at the
time of acceptance of an interrupt request, is even or odd. If the stack pointer (Note) is even, the FLG register and the
PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 6.7 shows the operation
of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated by the U
flag. Otherwise, it is the ISP.
(1) SP contains even number
Address
Sequence in which order
registers are saved
Stack
[SP] – 5 (Odd)
[SP] – 4 (Even)
PCL
[SP] – 3(Odd)
PCM
[SP] – 2 (Even)
FLGL
[SP] – 1(Odd)
[SP]
FLGH
(2)Saved simultaneously,
all 16 bits
PCH
(1)Saved simultaneously,
all 16 bits
(Even)
Finished saving registers
in two operations.
(2) SP contains odd number
Address
Stack
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
PCL
(3)
[SP] – 3 (Even)
PCM
(4)
[SP] – 2(Odd)
FLGL
Saved, 8 bits at a time
[SP] – 1 (Even)
[SP]
FLGH
(1)
PCH
(2)
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the SP when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 6.7
Operation of Saving Register
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6.13
6. INTERRUPTS
Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are
restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar instruction
before executing the REIT instruction
6.14
Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that has the
highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to ILVL0
bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority is resolved by
hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 6.8 shows the
priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset
High
NMI
DBC
Watchdog timer
Peripheral function
Single step
Address match
Figure 6.8
6.15
Low
Hardware Interrupt Priority
Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 6.9 shows the circuit that judges the interrupt priority level.
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Priority level of each interrupt
6. INTERRUPTS
Level 0 (initial value)
INT1
Timer B2/Clock Timer
High
Timer B0
Timer A3
Timer A1
Timer B4/Remote control,
UART1 bus collision
INT3
INT2/Remote control transmission
INT0
Timer B1
Timer A4/Multi-master I 2 C
Timer A2
Timer B3/HINT, UART0 bus collision
Timer B5/SLICEON
UART1 reception, ACK1
UART0 reception, ACK0
Priority of peripheral function interrupts
(if priority levels are same)
UART2 reception, ACK2
A/D conversion
DMA1
UART 2 bus collision
SI/O4, INT5
Timer A0
UART1 transmission, NACK1
UART0 transmission, NACK0
UART2 transmission, NACK2
DMA0
Low
SI/O3, INT4
IPL
Interrupt request level resolution output
to clock generating circuit (Fig.4.1)
I flag
Interrupt
request
accepted
Address match
Watchdog timer
DBC
NMI
Figure 6.9
Interrupts Priority Select Circuit
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6.16
6. INTERRUPTS
INT Interrupt
INTi interrupt (i = 0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR
register's IFSRi bit.
INT4 and INT5 share the interrupt vector and interrupt control register with SI/O3 and SI/O4, respectively.
To use the INT4 interrupt, set the IFSR register’s IFSR6 bit to “1” (= INT4). To use the INT5 interrupt, set the IFSR
register’s IFSR7 bit to “1” (= INT5).
After modifying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to “0” (= interrupt not requested) before
enabling the interrupt.
INT2 and the remote control transmission, the vector and the interrupt control register are shared. (Please refer to
“14. Expansion Function” for details. )
Figure 6.10 shows the IFSR and IFSR2A registers.
Interrupt request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR
Address
035F16
Bit name
Bit symbol
IFSR0
After reset
0016
Function
RW
INT0 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
INT1 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
INT2 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
INT3 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR4
INT4 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR5
INT5 interrupt polarity
switching bit
0 : One edge
1 : Both edges
(Note 1)
RW
IFSR6
Interrupt request cause
select bit
0 : SI/O3
1 : INT4
(Note 2)
IFSR7
Interrupt request cause
select bit
0 : SI/O4
1 : INT5
(Note 2)
IFSR1
IFSR2
IFSR3
RW
RW
Note 1: When setting this bit to “1” (= both edges), make sure the INT0IC to INT5IC register’s POL bit
is set to “0” (= falling edge).
Note 2: When setting this bit to “0” (= SI/O3, SI/O4), make sure the S3IC and S4IC registers’ POL bit is
set to “0” (= falling edge).
Interrupt request cause select register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
IFSR2A
Bit name
Bit symbol
(b5-b0)
IFSR26
IFSR27
Address
035E16
After reset
00XXXXXX2
Function
RW
Nothing is assigned. When write, set to “0”.
When read, their contents are indeterminate.
Interrupt request cause
select bit (Note 1)
0 : Timer B3/HINT
1 : UART0 bus collision
detection
RW
Interrupt request cause
select bit (Note 2)
0 : Timer B4/Remote control
1 : UART1 bus collision
detection
RW
Note 1: Timer B3/HINT and UART0 bus collision detection share the vector and interrupt control register. When using
the timer B3/HINT interrupt, clear the IFSR26 bit to “0” (timer B3/HINT). When using UART0 bus collision
detection, set the IFSR26 bit to “1”.
Note 2: Timer B4/Remote control and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4/Remote control interrupt, clear the IFSR27 bit to “0” (timer B4/Remote control).
When using UART1 bus collision detection, set the IFSR27 bit to “1”.
Figure 6.10
IFSR Register and IFSR2A Register
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6.17
6. INTERRUPTS
NMI Interrupt
An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a
non-maskable interrupt.
The input level of this NMI interrupt input pin can be read by accessing the P8 register’s P8_5 bit.
This pin cannot be used as an input port.
6.18
Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the address
indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register. Use the
AIER register’s AIER0 and AIER1 bits and the AIER2 register’s AIER20 and AIER21 bits to enable or disable the
interrupt. Note that the address match interrupt is unaffected by the I flag and IPL.
For address match interrupts, the value of the PC that is saved to the stack area varies depending on the instruction
being executed (refer to “Saving Registers”).
(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one of the
methods described below to return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or similar other
instruction and then use a jump instruction to return.
Table 6.6 shows the value of the PC that is saved to the stack area when an address match interrupt request is
accepted.
Note that when using the external bus in 8 bits width, no address match interrupts can be used for externa areas.
Figure 6.11 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 6.6
Instruction Just Before Execution and Address Stored in Stack When There Occurs
Interrupts
Value of the PC that is
saved to the stack area
Instruction at the address indicated by the RMADi register
• 16-bit op-code instruction
• Instruction shown below among 8-bit operation code instructions
ADD.B:S
#IMM8,dest
SUB.B:S
#IMM8,dest
AND.B:S #IMM8,dest
OR.B:S
#IMM8,dest
MOV.B:S
#IMM8,dest
STZ.B:S
#IMM8,dest
STNZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
CMP.B:S
#IMM8,dest
PUSHM
src
POPM dest
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S
#IMM,dest (However, dest=A0 or A1)
The address
indicated by the
RMADi register +2
The address
indicated by the
RMADi register +1
Instructions other than the above
Value of the PC that is saved to the stack area : Refer to “Saving Registers”.
Table 6.7
Relationship Between Address Match Interrupt Sources and Associated Registers
Address match interrupt sources Address match interrupt enable bit
Address match interrupt register
Address match interrupt 0
AIER0
RMAD0
Address match interrupt 1
AIER1
RMAD1
Address match interrupt 2
AIER20
RMAD2
Address match interrupt 3
AIER21
RMAD3
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6. INTERRUPTS
Address match interrupt enable register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER
Bit symbol
Address
000916
After reset
XXXXXX002
Bit name
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
Address match interrupt 1
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
(b7-b2)
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
AIER0
Function
RW
RW
Address match interrupt enable register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
AIER2
Address
01BB16
After reset
XXXXXX002
Bit symbol
Bit name
AIER20
Address match interrupt 2
enable bit
0 : Interrupt disable
1 : Interrupt enabled
RW
AIER21
Address match interrupt 3
enable bit
0 : Interrupt disabled
1 : Interrupt enable
RW
(b7-b2)
Function
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Address match interrupt register i (i = 0 to 3)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address
001216 to 001016
001616 to 001416
01BA16 to 01B816
01BE16 to 01BC16
Function
Address setting register for address match interrupt
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned.
When write, set to “0”.
When read, their contents are indeterminate.
Figure 6.11
AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers
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After reset
X0000016
X0000016
X0000016
X0000016
M306H7MG-XXXFP/MC-XXXFP/FGFP
7.
7. WATCHDOG TIMER
Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using
the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts
down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog timer interrupt
request or apply a watchdog timer reset as an operation to be performed when the watchdog timer underflows after
reaching the terminal count can be selected using the PM12 bit of PM1 register. The PM12 bit can only be set to “1”
(reset). Once this bit is set to “1”, it cannot be set to “0” (watchdog timer interrupt) in a program.
Refer to “Watchdog Timer Reset” for the details of watchdog timer reset.
When the main clock is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to be 16 or 128
using the WDC7 bit of WDC register. If a sub-clock is selected for CPU clock, the divide-by- N value for the prescaler
is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as given below. The
period of watchdog timer is, however, subject to an error due to the prescaler.
With main clock chosen for CPU clock
Watchdog timer period = Prescaler dividing (16 or 128) X Watchdog timer count (32768)
CPU clock
With sub-clock chosen for CPU clock
Watchdog timer period = Prescaler dividing (2) X Watchdog timer count (32768)
CPU clock
For example, when CPU clock = 10 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer period
is approx. 52.4 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to
start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is resumed from the
held value when the modes or state are released.
Figure 7.1 shows the block diagram of the watchdog timer. Figure 7.2 shows the watchdog timer-related registers.
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7. WATCHDOG TIMER
Prescaler
CM07 = 0
WDC7 = 0
PM12 = 0
1/16
CPU
clock
1/128
Watchdog timer
interrupt request
CM07 = 0
WDC7 = 1
Watchdog timer
HOLD
PM12 = 1
CM07 = 1
1/2
Reset
Set to
“7FFF16”
Write to WDTS register
RESET
Figure 7.1
Watchdog Timer Block Diagram
Watchdog timer control register
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol
WDC
Address
After reset
000F16 00XXXXXX2(Note2)
Bit symbol
Function
Bit name
RW
(b4-b0)
High-order bit of watchdog timer
RO
WDC5
Cold start / warm start
0 : Cold start
discrimination flag (Note 1) 1 : Warm start
RW
Reserved bit
Must set to “0”
RW
0 : Divided by 16
1 : Divided by 128
RW
(b6)
WDC7
Prescaler select bit
Note 1: The WDC5 bit is always “1” (warm start) no matter how it is set by writing a “0” or “1”.
Note 2: The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program.
Watchdog timer start register (Note)
b7
b0
Symbol
WDTS
Address
000E16
After reset
Indeterminate
Function
RW
The watchdog timer is initialized and starts counting after a write instruction to
WO
this register. The watchdog timer value is always initialized to “7FFF16”
regardless of whatever value is written.
Note : Write to the WDTS register after the watchdog timer interrupt occurs.
Figure 7.2
WDC Register and WDTS Register
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8.
8. DMAC
DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data from
the source address to the destination address. The DMAC uses the same data bus as used by the CPU. Because the
DMAC has higher priority of bus control than the CPU and because it makes use of a cycle steal method, it can transfer
one word (16 bits) or one byte (8 bits) of data within a very short time after a DMA request is generated. Figure 8.1
shows the block diagram of the DMAC.
Table 8.1 shows the DMAC specifications. Figures 8.2 to 8.4 show the DMAC-related registers.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016)
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
(addresses 002916, 002816)
DMA0 transfer counter TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016)
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003916, 003816)
DMA1 transfer counter TCR1 (16)
DMA latch high-order bits
DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 8.1
DMAC Block Diagram
A DMA request is generated by a write to the DMiSL register (i = 0 to 1)’s DSR bit, as well as by an interrupt request
which is generated by any function specified by the DMiSL register’s DMS and DSEL3 to DSEL0 bits. However,
unlike in the case of interrupt requests, DMA requests are not affected by the I flag and the interrupt control register, so
that even when interrupt requests are disabled and no interrupt request can be accepted, DMA requests are always
accepted. Furthermore, because the DMAC does not affect interrupts, the interrupt control register’s IR bit does not
change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMiCON register’s DMAE bit = “1”
(DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA transfer cycle, the
number of transfer requests generated and the number of times data is transferred may not match. For details, refer to
“DMA Requests”.
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Table 8.1
8. DMAC
DMAC Specifications
Item
No. of channels
Transfer memory space
Maximum No. of bytes transferred
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
DMA request factors
(Note 1, Note 2)
Channel priority
Transfer unit
Transfer address direction
Transfer mode •Single transfer
•Repeat transfer
DMA interrupt request generation timing
DMA startup
DMA shutdown •Single transfer
•Repeat transfer
Reload timing for forward
address pointer and transfer
counter
________
Falling edge of
INT0 or
INT1
________
________
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrpt requests
A/D conversion interrupt requests
Software triggers
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer is completed when the DMAi transfer counter (i = 0–1)
underflows after reaching the terminal count.
When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is continued with it.
When the DMAi transfer counter underflowed
Data transfer is initiated each time a DMA request is generated when the
DMAiCON register’s DMAE bit = “1” (enabled).
• When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
When the DMAE bit is set to “0” (disabled)
When a data transfer is started after setting the DMAE bit to “1”
(enabled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
Notes:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.
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8. DMAC
DMA0 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0SL
Address
03B816
Bit symbol
DSEL0
DSEL1
After reset
0016
Function
Bit name
DMA request cause
select bit
Refer to note
RW
DSEL3
DMS
RW
RW
DSEL2
(b5-b4)
RW
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of requestt
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
RW
DSR
Note 1: The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 02
0 0 0 12
0 0 1 02
0 0 1 12
0 1 0 02
0 1 0 12
0 1 1 02
0 1 1 12
1 0 0 02
1 0 0 12
1 0 1 02
1 0 1 12
1 1 0 02
1 1 0 12
1 1 1 02
1 1 1 12
DMS=0 (basic cause of request)
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4 (Note 4)
Timer B0
Timer B1
Timer B2 (Note 3)
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A-D conversion
UART1 transmit
DMS=1 (extended cause of request)
–
–
–
–
–
–
Two edges of INT0 pin
Timer B3
Timer B4
Timer B5
–
–
–
–
–
–
Note 2: In VINTi, INTRMTi, and HINTi (i = 0 to 3) of address 3616 expansion register of expansion function, when use
them by the following setup, DMA request cause extension select bit = "1" (extended cause of request) cannot be used.
• VINTi = 10112
• INTRMTi = 10102
• HINTi = 10012
(i = 0 to 3)
Note 3: Please change SECINTi (i = 0 to 3) in address 3616 expansion registers of the expansion feature to the following settings
when you use the DMA forwarding by timer B2 interrupt request.
• SECINTi = 00002
The DMA forwarding by the clock timer interrupt request cannot be used.
Note 4: Please change EXTIICINTi (i = 0 to 3) in address 02D616 I2C0 interrupt control register to the following settings when you
use the DMA forwarding by timer A4 interrupt request.
• EXTIICINTi = 00002
The DMA forwarding by the Multi-master I2C interrupt request cannot be used.
Figure 8.2
DM0SL Register
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8. DMAC
DMA1 request cause select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM1SL
Address
03BA16
DSEL1
DSEL2
Function
Bit name
Bit symbol
DSEL0
After reset
0016
DMA request cause
select bit
RW
RW
DSEL3
(b5-b4)
DMS
RW
RW
Refer to note
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
DMA request cause
expansion select bit
0: Basic cause of request
1: Extended cause of request
RW
Software DMA
request bit
A DMA request is generated by
setting this bit to “1” when the DMS
bit is “0” (basic cause) and the
DSEL3 to DSEL0 bits are “00012”
(software trigger).
The value of this bit when read is “0” .
RW
DSR
Note 1: The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the
manner described below.
DSEL3 to DSEL0
0 0 0 02
0 0 0 12
0 0 1 02
0 0 1 12
0 1 0 02
0 1 0 12
0 1 1 02
0 1 1 12
1 0 0 02
1 0 0 12
1 0 1 02
1 0 1 12
1 1 0 02
1 1 0 12
1 1 1 02
1 1 1 12
DMS=0(basic cause of request)
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4 (Note 3)
Timer B0
Timer B1
Timer B2 (Note 2)
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A/D conversion
UART1 receive/ACK1
DMS=1(extended cause of request)
–
–
–
–
–
SI/O3
SI/O4
Two edges of INT1
–
–
–
–
–
–
–
–
Note 2: Please change SECINTi (i = 0 to 3) in address 3616 enhancing registers of the enhanced feature to the following settings
when you use the DMA forwarding by timer B2 interrupt request.
• SECINTi = 00002
The DMA forwarding by the clock timer interrupt request cannot be used.
Note 3: Please change EXTIICINTi (i = 0 to 3) in address 02D616 I2C0 interrupt control register to the following settings when you
use the DMA forwarding by timer A4 interrupt request.
• EXTIICINTi = 00002
The DMA forwarding by the Multi-master I2C interrupt request cannot be used.
DMAi control register (i = 0,1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
DM0CON
DM1CON
Address
002C16
003C16
Bit symbol
After reset
00000X002
00000X002
Bit name
Function
RW
DMBIT
Transfer unit bit select bit
0 : 16 bits
1 : 8 bits
RW
DMASL
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
RW
DMAS
DMA request bit
0 : DMA not requested
1 : DMA requested
DMAE
DMA enable bit
0 : Disabled
1 : Enabled
RW
DSD
Source address direction
select bit (Note 2)
0 : Fixed
1 : Forward
RW
DAD
Destination address
0 : Fixed
direction select bit (Note 2) 1 : Forward
RW
(b7-b6)
Nothing is assigned. When write, set to “0”. When
read, its content is “0”.
RW
(Note 1)
Note 1: The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).
Note 2: At least one of the DAD and DSD bits must be “0” (address direction fixed).
Figure 8.3
DM1SL Register, DM0CON Register, and DM1CON Registers
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8. DMAC
DMAi source pointer (i = 0, 1) (Note)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
Function
Set the source address of transfer
After reset
Indeterminate
Indeterminate
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DSD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0” (DMA disabled).
If the DSD bit is “1” (forward direction), this register can be written to at any time.
If the DSD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi destination pointer (i = 0, 1)(Note)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
Function
Set the destination address of transfer
After reset
Indeterminate
Indeterminate
Setting range
RW
0000016 to FFFFF16
RW
Nothing is assigned. When write, set “0”. When read, these contents
are “0”.
Note: If the DAD bit of DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit of
DMiCON register is “0”(DMA disabled).
If the DAD bit is “1” (forward direction), this register can be written to at any time.
If the DAD bit is “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
Function
Set the transfer count minus 1. The written value
is stored in the DMAi transfer counter reload
register, and when the DMAE bit of DMiCON
register is set to “1” (DMA enabled) or the DMAi
transfer counter underflows when the DMASL bit
of DMiCON register is “1” (repeat transfer), the
value of the DMAi transfer counter reload register
is transferred to the DMAi transfer counter.
When read, the DMAi transfer counter is read.
Figure 8.4
SAR0, SAR1, DAR0, DAR1, TCR0, and TCR1 Registers
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After reset
Indeterminate
Indeterminate
Setting range
RW
000016 to FFFF16
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
8.1
8. DMAC
Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus
cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer.
(a) Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd address,
the source read cycle consists of one more bus cycle than when the source address of transfer begins with an
even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins with
an odd address, the destination write cycle consists of one more bus cycle than when the destination address of
transfer begins with an even address.
(b) Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus cycles
required for that access increases by an amount equal to software wait states.
Figure 8.5 shows the example of the cycles for a source read. For convenience, the destination write cycle is shown
as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle
is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When
calculating transfer cycles, take into consideration each condition for the source read and the destination write
cycle, respectively. For example, when data is transferred in 16 bit units using an 8-bit bus ((2) in Figure 8.5), two
source read bus cycles and two destination write bus cycles are required.
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8. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
CPU use
Dummy
cycle
Destination
Source
CPU use
RD signal
WR signal
Data
bus
CPU use
Dummy
cycle
Destination
Source
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source + 1
Source
Destination
Dummy
cycle
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Address
bus
Destination
Source
CPU use
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
Source
CPU use
Destination
Dummy
cycle
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
RD signal
WR signal
Data
bus
CPU use
Source
Source + 1
Destination
Dummy
cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source
.
Figure 8.5
Transfer Cycles for Source Read
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8.2
8. DMAC
Number of DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible. Table 8.2 shows the number of DMA
transfer cycles. Table 8.3 shows the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 8.2
Number of DMA Transfer Cycles
Single-chip mode
Transfer unit
Bus width
Access address
8-bit transfers
16-bit
Even
1
(DMBIT= “1”)
(BYTE= “L”)
Odd
1
1
16-bit
Even
1
1
(BYTE = “L”)
Odd
2
2
16-bit transfers
(DMBIT= “0”)
Table 8.3
Coefficient j, k
Internal area
Internal ROM, RAM
SFR
No wait
With wait
j
1
2
2
k
1
2
2
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No. of read No. of write
cycles
cycles
1
M306H7MG-XXXFP/MC-XXXFP/FGFP
8.3
8. DMAC
DMA Enable
When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the DMAC
operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in DMiCON register is “1”
(forward) or the DARi register value when the DAD bit of DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However, if a
DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
8.4
DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS and
DSEL3 to DSEL0 bits of DMiSL register (i = 0, 1) on either channel. Table 8.4 shows the timing at which the
DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether or not
the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set to “0”
(DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a program (it can
only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore, always be
sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the DMAS bit
in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the DMAC is enabled.
Table 8.4
Timing at Which the DMAS Bit Changes State
DMA factor
DMAS bit of the DMiCON register
Timing at which the bit is set to “1” Timing at which the bit is set to “0”
Software trigger
When the DSR bit of DMiSL
register is set to “1”
Peripheral function
When the interrupt control register
for the peripheral function that is
selected by the DSEL3 to DSEL0
and DMS bits of DMiSL register
has its IR bit set to “1”
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• Immediately before a data transfer starts
• When set by writing “0” in a program
M306H7MG-XXXFP/MC-XXXFP/FGFP
8.5
8. DMAC
Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected
active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS
bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA requests are arbitrated
according to the channel priority, DMA0 > DMA1. The following describes DMAC operation when DMA0 and
DMA1 requests are detected active in the same sampling period.
Figure 8.6 shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request are
generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the CPU. When
the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, the bus
arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when DMA
requests, as DMA1 in Figure 8.6, occurs more than one time, the DMAS bit is set to “0” as soon as getting the bus
arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
An example where DMA requests for external causes are detected active at the same
BCLK
DMA0
Bus
arbitration
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 8.6
DMA Transfer by External Factors
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9.
9. TIMERS
Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either
timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer operations as
counting, reloading, etc. Figures 9.1 and 9.2 show block diagrams of timer A and timer B configuration, respectively.
1/2
• Main clock
f2 PCLK0 bit = 0
Clock prescaler
f1 or f2
f1
f8
1/8
1/4
f1 or f2 f8 f32 fC32
1/32
XCIN
PCLK0 bit = 1
f32
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
fC32
Reset
• Timer mode
• One-shot timer mode
• Pulse Width Modulation (PWM) mode
Timer A0 interrupt
Noise
filter
TA0 IN
Timer A0
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Noise
filter
TA1 IN
Timer A1 interrupt
Timer A1
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A2 interrupt
Noise
filter
TA2 IN
Timer A2
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A3 interrupt
Noise
filter
TA3 IN
Timer A3
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A4 interrupt
Noise
filter
TA4 IN
Timer A4
• Event counter mode
Timer B2 overflow or underflow
Note: Be aware that TA0 IN shares the pin with RxD2 and TB5IN.
Figure 9.1
Timer A Configuration
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1/2
• Main clock
9. TIMERS
f2 PCLK0 bit = 0
Clock prescaler
f1 or f2
f1
f8
1/8
1/4
f32
fC32
1/32
XCIN
PCLK0 bit = 1
Set the CPSR bit of CPSRF
register to “1” (= prescaler
reset)
Reset
f1 or f2 f8 f32 fC32
Timer B2 overflow or underflow ( to Timer A count source)
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB0IN
Timer B0 interrupt
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB1IN
Timer B1 interrupt
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB2IN
Timer B2 interrupt
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB3IN
Timer B3 interrupt
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB4IN
Timer B4 interrupt
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode,
pulse period measuring mode
Noise
filter
TB5IN
Timer B5
• Event counter mode
Note: Be aware that TB5IN shares the pin with RxD2 and TA0 IN.
Figure 9.2
Timer B Configuration
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Timer B5 interrupt
M306H7MG-XXXFP/MC-XXXFP/FGFP
9.1
9. TIMERS
Timer A
Figure 9.3 shows a block diagram of the timer A. Figures 9.4 to 9.6 show registers related to the timer A.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same
function. Use the TMOD1 to TMOD0 bits of TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows and underflows of other
timers.
• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count “000016.”
• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f1 or f2
f8
f32
fC32
Low-order
8 bits
• Timer
(gate function)
High-order
8 bits
Reload register
Clock selection
• Event counter
Counter
Polarity
selection
Up-count/down-count
TAiIN
(i = 0 to 4)
Always counts down except
in event counter mode
TABSR register
Clock selection
TAi
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
(Note)
TB2 overflow
To external
trigger circuit
(Note)
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
Down count
Addresses
038716 038616
038916 038816
038B16 038A16
038D16 038C16
038F16 038E16
TAj
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
TAk
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
UDF register
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Note: Overflow or underflow
Figure 9.3
Timer A Block Diagram
Timer Ai mode register (i=0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
Address
039616 to 039A16
Bit name
Operation mode select bit
TMOD1
MR0
MR1
After reset
0016
Function
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
RW
Function varies with each
operation mode
RW
Function varies with each
operation mode
RW
MR2
MR3
TCK0
Count source select bit
TCK1
Figure 9.4
TA0MR to TA4MR Registers
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b1 b0
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M306H7MG-XXXFP/MC-XXXFP/FGFP
9. TIMERS
Timer Ai register (i= 0 to 4) (Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
TA2
TA3
TA4
Address
038716, 038616
038916, 038816
038B16, 038A16
038D16, 038C16
038F16, 038E16
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting range
RW
Timer
mode
Event
counter
mode
Divide the count source by n + 1 where n =
set value
000016 to FFFF16
RW
Divide the count source by FFFF16 – n + 1
where n = set value when counting up or
by n + 1 when counting down (Note 5)
000016 to FFFF16
One-shot
timer mode
Divide the count source by n where n = set
value and cause the timer to stop
000016 to FFFF16
(Notes 2, 4)
Mode
Function
Pulse width Modify the pulse width as follows:
modulation PWM period: (216 – 1) / fj
High level PWM pulse width: n / fj
mode
(16-bit PWM) where n = set value, fj = count source
frequency
Pulse width Modify the pulse width as follows:
modulation PWM period: (28 – 1) x (m + 1)/ fj
mode
High level PWM pulse width: (m + 1)n / fj
(8-bit PWM) where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
RW
WO
000016 to FFFE16
(Note 3, 4)
WO
0016 to FE16
(High-order address)
0016 to FF16
(Low-order address) WO
(Note 3, 4)
Note 1: The register must be accessed in 16 bit units.
Note 2: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt
requests are not generated either. Furthermore, if “pulse output” is selected, no pulses are
output from the TAiOUT pin.
Note 3: If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output
level on the TAiOUT pin remains low, and timer Ai interrupt requests are not generated
either. The same applies when the 8 high-order bits of the timer TAi register are set to ‘001
6’ while operating as an 8-bit pulse width modulator.
Note 4: Use the MOV instruction to write to the TAi register.
Note 5: The timer counts pulses from an external device or overflows or underflows in other timers.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TABSR
Bit symbol
Address
038016
After reset
0016
Bit name
Function
RW
RW
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
0 : Stops counting
1 : Starts counting
RW
Up/down flag (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UDF
Bit symbol
Address
038416
Bit name
TA0UD
Timer A0 up/down flag
TA1UD
Timer A1 up/down flag
TA2UD
Timer A2 up/down flag
TA3UD
Timer A3 up/down flag
TA4UD
Timer A4 up/down flag
TA2P
TA3P
TA4P
After reset
0016
Function
0 : Down count
1 : Up count
Enabled by setting the TAiMR
register’s MR2 bit to “0”
(= switching source in UDF
register) during event counter
mode.
RW
RW
RW
RW
RW
RW
Timer A2 two-phase pulse 0 : two-phase pulse signal
WO
processing disabled
signal processing select bit
1 : two-phase pulse signal
processing enabled
Timer A3 two-phase pulse
WO
(Notes 2, 3)
signal processing select bit
Timer A4 two-phase pulse
signal processing select bit
WO
Note 1: Use MOV instruction to write to this register.
Note 2: Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set
to “0” (input mode).
Note 3: When not using the two-phase pulse signal processing function, set the bit corresponding to
timer .A2 to timer A4 to “0”
Figure 9.5
TA0 to TA4 Registers, TABSR Register, and UDF Register
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One-shot start flag
b7
b6
b5
b4
b3
b2
b1
9. TIMERS
Symbol
ONSF
b0
Address
038216
After reset
0016
0
Bit symbol
Bit name
Function
RW
TA0OS
Timer A0 one-shot start flag
RW
TA1OS
Timer A1 one-shot start flag
TA2OS
Timer A2 one-shot start flag
TA3OS
Timer A3 one-shot start flag
TA4OS
Timer A4 one-shot start flag
The timer starts counting by setting
this bit to “1” while the TMOD1 to
TMOD0 bits of TAiMR register (i =
0 to 4) = ‘102’ (= one-shot timer
mode) and the MR2 bit of TAiMR
register = “0” (=TAiOS bit enabled).
When read, its content is “0”.
Reserved bit
Must be set to “0”
RW
Timer A0 event/trigger
select bit
RW
0 0 : Input on TA0IN is selected (Note 1)
(Note
2)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected (Note 2) RW
1 1 : TA1 overflow is selected (Note 2)
(b5)
TA0TGL
TA0TGH
RW
RW
RW
RW
b7 b6
Note 1: Make sure the PD7_1 bit of PD7 register is set to “0” (= input mode).
Note 2: Overflow or underflow
Trigger select register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TRGSR
Bit symbol
TA1TGL
Address
038316
Bit name
Timer A1 event/trigger
select bit
TA1TGH
TA2TGL
Timer A2 event/trigger
select bit
TA2TGH
TA3TGL
Timer A3 event/trigger
select bit
TA3TGH
TA4TGL
Timer A4 event/trigger
select bit
TA4TGH
After reset
0016
Function
RW
0 0 : Input on TA1IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA0 is selected
1 1 : TA2 is selected
RW
b1 b0
b3 b2
0 0 : Input on TA2IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA1 is selected
1 1 : TA3 is selected
RW
RW
RW
b5 b4
0 0 : Input on TA3IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA2 is selected
1 1 : TA4 is selected
b7 b6
0 0 : Input on TA4IN is selected (Note 1)
0 1 : TB2 is selected
1 0 : TA3 is selected
1 1 : TA0 is selected
RW
RW
RW
RW
Note 1: Make sure the port direction bits for the TA1IN to TA4IN pins are set to “0” (= input mode).
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Bit symbol
Figure 9.6
Address
038116
After reset
0XXXXXXX2
(b6-b0)
Bit name
Function
Nothing is assigned.
When write, set to “0”. When read, their contents are
indeterminate.
CPSR
Clock prescaler reset flag
Setting this bit to “1” initializes the
prescaler for the timekeeping clock.
(When read, its content is “0”.)
ONSF Register, TRGSR Register, and CPSRF Register
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9.1.1
9. TIMERS
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 9.1). Figure 9.7 shows TAiMR
register in timer mode.
Table 9.1
Specifications in Timer Mode
Item
Specification
Count source
Count operation
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and continues counting
1/(n+1) n: set value of TAi register (i= 0 to 4)
000016 to FFFF16
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Timer underflow
I/O port or gate input
I/O port or pulse output
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Gate function
Select function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When not counting, the pin outputs a low.
Timer Ai mode register (i=0 to 4)
b7
b6
b5
b4
b3
0
b2
b1
b0
0 0
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
TMOD1
MR0
MR1
Address
039616 to 039A16
Bit name
Operation mode
select bit
MR3
Function
b1 b0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
Gate function select bit
b4 b3
MR2
TCK0
After reset
0016
0 0 : Gate function not available
01:
(TAiIN pin functions as I/O port)
1 0 : Counts while input on the TAiIN pin
is low (Note 2)
1 1 : Counts while input on the TAiIN pin
is high (Note 2)
Must be set to “0” in timer mode
Count source select bit
TCK1
Timer Ai Mode Register in Timer Mode
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b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 9.7
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M306H7MG-XXXFP/MC-XXXFP/FGFP
9.1.2
9. TIMERS
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other
timers. Timers A2, A3 and A4 can count two-phase external signals. Table 9.2 lists specifications in event
counter mode (when not processing two-phase pulse signal). Table 9.3 lists specifications in event counter
mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Figure 9.8 shows TAiMR
register in event counter mode (when not processing two-phase pulse signal). Figure 9.9 shows TA2MR to
TA4MR registers in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and
A4).
Table 9.2
Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Count source
Specification
• External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected
in program)
• Timer B2 overflows or underflows,
timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,
timer Ak (k=i+1, except k=0 if i=4) overflows or underflows
Count operation
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
Divided ratio
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of TAi register 000016 to FFFF16
Count start condition
Set TAiS bit of TABSR register to “1” (= start counting)
Count stop condition
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing Timer overflow or underflow
TAiIN pin function
I/O port or count source input
TAiOUT pin function
I/O port, pulse output, or up/down-count select input
Read from timer
Count value can be read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Write to timer
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is
not reloaded to it
• Pulse output function
Whenever the timer overflows or underflows, the output polarity of TAiOUT
pin is inverted . When not counting, the pin outputs a low.
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9. TIMERS
Timer Ai mode register (i=0 to 4)
(When not using two-phase pulse signal processing)
b7
b6
b5
0
b4
b3
b2
b1
b0
Symbol
TA0MR to TA4MR
0 1
Address
039616 to 039A16
Bit symbol
Bit name
TMOD0
Operation mode select bit
Function
b1 b0
0 1 : Event counter mode (Note 1)
TMOD1
MR0
After reset
0016
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output (Note 2)
RW
R
W
RW
RW
RW
(TAiOUT pin functions as pulse output pin)
MR1
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge RW
1 : Counts external signal's rising edge
MR2
Up/down switching
cause select bit
0 : UDF register
1 : Input signal to TAiOUT pin (Note 4)
MR3
Must be set to “0” in event counter mode
RW
TCK0
Count operation type
select bit
RW
TCK1
Can be “0” or “1” when not using two-phase pulse signal
processing
0 : Reload type
1 : Free-run type
RW
RW
Note 1: During event counter mode, the count source can be selected using the ONSF and TRGSR
registers.
Note 2: TA0OUT pin is N-channel open drain output.
Note 3: Effective when the TAiGH and TAiGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 4: Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port
direction bit for TAiOUT pin must be set to “0” (= input mode).
Figure 9.8
TAiMR Register in Event Counter Mode (when not using two-phase pulse signal
processing)
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9. TIMERS
The use of the event counter mode (When you use two aspect pulse signal processing with Timer A2, A3, and
A4) is shown in Table 9.3.
Figure 9.9 shows from TA2MR register to TA4MR register (When you use two aspect pulse signal processing
with timer A2, A3, and A4) at event counter mode.
Table 9.3
Specifications in Event Counter Mode (when processing two-phase pulse signal with
timers A2, A3 and A4))
Item
Count source
Count operation
Divide ratio
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register contents and continues counting. When operating in free-running mode, the
timer continues counting without reloading.
1/ (FFFF16 - n + 1) for up-count
1/ (n + 1) for down-count
Count start condition
Count stop condition
n : set value of TAi register
000016 to FFFF16
Set TAiS bit of TABSR register to “1” (= start counting)
Set TAiS bit to “0” (= stop counting)
Interrupt request generation timing
Timer overflow or underflow
TAiIN pin function
Two-phase pulse input
TAiOUT pin function
Two-phase pulse input
Read from timer
Write to timer
Count value can be read by reading timer A2, A3 or A4 register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
Select function (Note)
(Transferred to counter when reloaded next)
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN pin
when input signals on TAj OUT pin is “H”.
TAjOUT
TAjIN
(j=2,3)
Upcount
Upcount
Upcount
Downcount
Downcount
Downcount
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the
input signal on TAkOUT pin is “H”, the timer counts up rising and falling
edges on TAkOUT and TAkIN pins. If the phase relationship is such that
TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer
counts down rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count up all edges
Count down all edges
TAkIN
(k=3,4)
Count up all edges
Count down all edges
Notes:
1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to
multiply-by-4 processing operation.
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9. TIMERS
Timer Ai mode register (i=2 to 4)
(When using two-phase pulse signal processing)
b6
b5
b4
b3 b2
b1
b0
0 1 0 0 0 1
Symbol
TA2MR to TA4MR
Address
039816 to 039A16
Function
RW
0 1 : Event counter mode
RW
RW
Bit name
TMOD0
Operation mode select bit
TMOD1
MR0
After reset
0016
b1 b0
To use two-phase pulse signal processing, set this bit to “0”.
RW
To use two-phase pulse signal processing, set this bit to “0”.
RW
MR2
To use two-phase pulse signal processing, set this bit to “1”.
RW
MR3
To use two-phase pulse signal processing, set this bit to “0”.
RW
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
RW
TCK1
Two-phase pulse signal
processing operation
select bit (Note 1)(Note 2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
RW
MR1
Note 1: TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, timers A2 and A4 always operate in
normal processing mode and x4 processing mode, respectively.
Note 2: If two-phase pulse signal processing is desired, following register settings are required:
• Set the UDF register's TAiP bit to “1” (two-phase pulse signal processing function enabled) .
• Set the TRGSR register's TAiGH and TAiGL bits to “002” (TAiIN pin input).
• Set the port direction bits for TA iIN and TAiOUT to “0” (input mode).
Figure 9.9
TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase
pulsesignal processing with timer A2, A3 or A4)
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9.1.3
9. TIMERS
One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. (See Table 9.4.) When the trigger
occurs, the timer starts up and continues operating for a given period. Figure 9.10 shows the TAiMR register in
one-shot timer mode.
Table 9.4
Specifications in One-shot Timer Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the counter reaches 000016, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
1/n
n : set value of TAi register 000016 to FFFF16
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Select function
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However, the counter does not work if the divide-by-n value is set to 000016.
TAiS bit of TABSR register = “1” (start counting) and one of the following
triggers occurs.
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
• The TAiOS bit of ONSF register is set to “1” (= timer starts)
• When the counter is reloaded after reaching “000016”
• TAiS bit is set to “0” (= stop counting)
When the counter reaches “000016”
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
• Pulse output function
The timer outputs a low when not counting and a high when counting.
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9. TIMERS
Timer Ai mode register (i=0 to 4)
b7
b6
b5
0
b4
b3
b2
b1
b0
1 0
Symbol
TA0MR to TA4MR
After reset
0016
Bit name
Bit symbol
TMOD0
Address
039616 to 039A16
Function
RW
RW
Operation mode select bit
b1 b0
MR0
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
RW
1 : Pulse is output (Note 1)
(TAiOUT pin functions as a pulse output pin)
MR1
External trigger select
bit (Note 2)
0 : Falling edge of input signal to TAiIN pin (Note 3)
1 : Rising edge of input signal to TAiIN pin (Note 3) RW
MR2
Trigger select bit
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
TMOD1
1 0 : One-shot timer mode
MR3
Must be set to “0” in one-shot timer mode
TCK0
Count source select bit
TCK1
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
RW
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are ‘002’ (TAiIN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 9.10
TAiMR Register in One-shot Timer Mode
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9.1.4
9. TIMERS
Pulse Width Modulation (PWM) Mode
In PWM mode, the timer outputs pulses of a given width in succession (see Table 9.5). The counter functions as
either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 9.11 shows TAiMR register in pulse
width modulation mode. Figures 9.12 and 9.13 show examples of how a 16-bit pulse width modulator operates
and how an 8-bit pulse width modulator operates.
Table 9.5
Specifications in PWM Mode
Item
Count source
Count operation
16-bit PWM
8-bit PWM
Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
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Specification
f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new value at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs during counting
• High level width
n / fj
n : set value of TAi register (i=o to 4)
• Cycle time (216-1) / fj fixed
fj: count source frequency (f1, f2, f8, f32, fC32)
• High level width n x (m+1) / fj n : set value of TAi register high-order address
• Cycle time (28-1) x (m+1) / fj m : set value of TAi register low-order address
• TAiS bit of TABSR register is set to “1” (= start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
• Timer B2 overflow or underflow,
timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,
timer Ak (k=i+1, except k=0 if i=4) overflow or underflow
TAiS bit is set to “0” (= stop counting)
PWM pulse goes “L”
I/O port or trigger input
Pulse output
An indeterminate value is read by reading TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to only reload register
(Transferred to counter when reloaded next)
Page 84 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
9. TIMERS
Timer Ai mode register (i= 0 to 4)
b7
b6
b5
b4
b3
b2
b1
b0
1 1 1
Symbol
TA0MR to TA4MR
Bit symbol
TMOD0
TMOD1
Address
039616 to 039A16
After reset
0016
Bit name
Operation mode
select bit
RW
Function
RW
b1 b0
1 1 : PWM mode
(Note 1) RW
RW
MR0
Must be set to “1” in PWM mode
MR1
External trigger select
bit (Note 2)
0: Falling edge of input signal to TAiIN pin(Note 3)
RW
1: Rising edge of input signal to TAiIN pin(Note 3)
MR2
Trigger select bit
0 : Write “1” to TAiS bit in the TABSR register
1 : Selected by TAiTGH to TAiTGL bits
RW
MR3
16/8-bit PWM mode
select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
RW
b7 b6
TCK0
Count source select bit
TCK1
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
Note 1: TA0OUT pin is N-channel open drain output.
Note 2: Effective when the TAiTGH and TAiTGL bits of ONSF or TRGSR register are “00”2 (TAi IN pin input).
Note 3: The port direction bit for the TAiIN pin must be set to “0” (= input mode).
Figure 9.11
TAiMR Register in PWM Mode
Rev.2.10
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M306H7MG-XXXFP/MC-XXXFP/FGFP
9. TIMERS
1 / fi X (2
16
– 1)
Count source
Input signal to
TAiIN pin
“H”
“L”
Trigger is not generated by this signal
1 / fj X n
PWM pulse output
from TAiOUT pin
“H”
IR bit of TAiIC
register
“1”
“L”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
Set to “0” upon accepting an interrupt request or by writing in program
i = 0 to 4
Note 1: n = 000016 to FFFE16.
Note 2: This timing diagram is for the case where the TAi register is ‘000316,’ the TAiTGH and TAiTGL bits of ONSF
or TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 1 (rising edge), and the MR2
bit of TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 9.12
Example of 16-bit Pulse Width Modulator Operation
1 / fj X (m+ 1) X (2 8 – 1)
Count source (Note1)
Input signal to
TAiIN pin
“H”
“L”
1 / fj X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2) “L”
1 / fj X (m + 1) X n
PWM pulse output
from TAiOUT pin
IR bit of TAiIC
register
“H”
“L”
“1”
“0”
fj : Frequency of count source
(f1, f2, f8, f32, fC32)
i = 0 to 4
Set to “0” upon accepting an interrupt request or by writing in program
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16.
Note 4: This timing diagram is for the case where the TAi register is ‘020216,’ the TAiTGH and TAiTGL bits of ONSF or
TRGSR register = ‘002’ (TAiIN pin input), the MR1 bit of TAiMR register = 0 (falling edge), and the MR2 bit of
TAiMR register = 1 (trigger selected by TAiTGH and TAiTGL bits).
Figure 9.13
Example of 8-bit Pulse Width Modulator Operation
Rev.2.10
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M306H7MG-XXXFP/MC-XXXFP/FGFP
9.2
9. TIMERS
Timer B
Figure 9.14 shows a block diagram of the timer B. Figures 9.15 and 9.16 show registers related to the timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to 5) to
select the desired mode.
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external device or overflows or underflows of other
timers.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Reload register
Clock selection
Counter
• Event counter
TABSR register
TBSR register
Polarity switching,
edge pulse
TBiIN
(i = 0 to 5)
Low-order 8 bits
• Timer
• Pulse period measurement,
pulse width measurement
f1 or f2
f8
f32
fC32
Counter reset circuit
Can be selected in only
event counter mode
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
TBj overflow (Note)
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Note: Overflow or underflow.
Figure 9.14
Address
039116 039016
039316 039216
039516 039416
035116 035016
035316 035216
035516 035416
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Timer B Block Diagram
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
After reset
00XX00002
00XX00002
Function
Bit name
Operation mode select bit
TMOD1
MR0
MR1
b1 b0
RW
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
RW
Function varies with each operation
mode
RW
RW
RW
MR2
RW
(Note 1)
(Note 2)
RO
MR3
TCK0
Count source select bit
TCK1
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 9.15
TB0MR to TB5MR Registers
Rev.2.10
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Function varies with each operation
mode
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
9. TIMERS
Timer Bi register (i=0 to 5)(Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
039116, 039016
039316, 039216
039516, 039416
035116, 035016
035316, 035216
035516, 035416
Function
After reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Setting range
RW
Timer mode
Divide the count source by n + 1
where n = set value
000016 to FFFF16
RW
Event counter
mode
Divide the count source by n + 1
where n = set value (Note 2)
000016 to FFFF16
RW
Mode
Pulse period
Measures a pulse period or width
modulation mode,
Pulse width
modulation mode
RO
Note 1: The register must be accessed in 16 bit units.
Note 2: The timer counts pulses from an external device or overflows or underflows of other timers.
Count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Address
038016
Symbol
TABSR
After reset
0016
Bit name
Bit symbol
Function
RW
TA0S
Timer A0 count start flag
TA1S
Timer A1 count start flag
TA2S
Timer A2 count start flag
RW
TA3S
Timer A3 count start flag
RW
TA4S
Timer A4 count start flag
RW
TB0S
Timer B0 count start flag
RW
TB1S
Timer B1 count start flag
RW
TB2S
Timer B2 count start flag
RW
0 : Stops counting
1 : Starts counting
RW
RW
Timer B3, B4, B5 count start flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
TBSR
Address
034016
Bit symbol
After reset
000XXXXX2
Bit name
Function
RW
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
(b4-b0)
TB3S
Timer B3 count start flag
TB4S
Timer B4 count start flag
TB5S
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
RW
RW
RW
Clock prescaler reset flag
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
CPSRF
Address
038116
Bit symbol
Bit name
Figure 9.16
Function
RW
Nothing is assigned. When write, set to “0”. When read, their
contents are indeterminate.
(b6-b0)
CPSR
After reset
0XXXXXXX2
Clock prescaler reset flag Setting this bit to “1” initializes the
RW
prescaler for the timekeeping clock.
(When read, the value of this bit is “0”.)
TB0 to TB5 Registers, TABSR Register, TBSR Register, CPSRF Register
Rev.2.10
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M306H7MG-XXXFP/MC-XXXFP/FGFP
9.2.1
9. TIMERS
Timer Mode
In timer mode, the timer counts a count source generated internally (see Table 9.6). Figure 9.17 shows TBiMR
register in timer mode.
Table 9.6
Specifications in Timer Mode
Item
Count source
Specification
f1, f2, f8, f32, fC32
Count operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
Divide ratio
Count start condition
Count stop condition
Interrupt request generation timing
TBiIN pin function
Read from timer
Write to timer
continues counting
1/(n+1) n: set value of TBi register (i= 0 to 5)
Set TBiS bit(Note) to “1” (= start counting)
Set TBiS bit to “0” (= stop counting)
Timer underflow
I/O port
Count value can be read by reading TBi register
000016 to FFFF16
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Note : The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i= 0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Operation mode select bit
TMOD1
MR0
MR1
MR2
After reset
00XX00002
00XX00002
Bit name
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
Function
b1 b0
0 0 : Timer mode
RW
RW
RW
RW
Has no effect in timer mode
Can be set to “0” or “1”
RW
TB0MR, TB3MR registers
Must be set to “0” in timer mode
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate
MR3
When write in timer mode, set to “0”. When read in timer mode, its
content is indeterminate.
TCK0
Count source select bit
TCK1
Figure 9.17
TBiMR Register in Timer Mode
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 89 of 326
RO
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
9.2.2
9. TIMERS
Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of other
timers (see Table 9.7) . Figure 9.18 shows TBiMR register in event counter mode.
Table 9.7
Specifications in Event Counter Mode
Item
Count source
Specification
• External signals input to TBiIN pin (i=0 to 5) (effective edge can be selected
in program)
• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0, j=5 if i=3)
Count operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide ratio
1/(n+1)
n: set value of TBi register
000016 to FFFF16
Count start condition
Set TBiS bit1 to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing Timer underflow
TBiIN pin function
Count source input
Read from timer
Count value can be read by reading TBi register
Write to timer
• When not counting and until the 1st count source is input after counting start
Value written to TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TBi register is written to only reload register
(Transferred to counter when reloaded next)
Notes:
1. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode select bit
TMOD1
MR0
Count polarity select
bit (Note 1)
MR1
MR2
After reset
00XX00002
00XX00002
Function
b1 b0
0 1 : Event counter mode
RW
RW
RW
b3 b2
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set
TB0MR, TB3MR registers
Must be set to “0” in event count mode
RW
RW
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its
content is indeterminate.
MR3
When write in event counter mode, set to “0”. When read in event
counter mode, its content is indeterminate.
RO
TCK0
Has no effect in event counter mode.
Can be set to “0” or “1”.
RW
TCK1
Event clock select
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow or underflow
(j = i – 1, except j = 2 if i = 0,
j = 5 if i = 3)
RW
Note 1: Effective when the TCK1 bit = “0” (input from TBiIN pin). If the TCK1 bit = “1” (TBj overflow or underflow), these
bits can be set to “0” or “1”.
Note 2: The port direction bit for the TBiIN pin must be set to “0” (= input mode).
Figure 9.18
TBiMR Register in Event Counter Mode
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M306H7MG-XXXFP/MC-XXXFP/FGFP
9.2.3
9. TIMERS
Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal (see Table 9.8). Figure 9.19 shows TBiMR register in pulse period and pulse width measurement
mode. Figure 9.20 shows the operation timing when measuring a pulse period. Figure 9.21 shows the operation
timing when measuring a pulse width.
Table 9.8
Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count source
Count operation
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of mea-
surement pulse. The counter value is set to “000016” to continue counting.
Count start condition
Set TBiS (i=0 to 5) bit3 to “1” (= start counting)
Count stop condition
Set TBiS bit to “0” (= stop counting)
Interrupt request generation timing • When an effective edge of measurement pulse is input1
• Timer overflow. When an overflow occurs, MR3 bit of TBiMR register is set
to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no overflow) by
writing to TBiMR register at the next count timing or later after MR3 bit was
set to “1”. At this time, make sure TBiS bit is set to “1” (start counting).
TBiIN pin function
Measurement pulse input
Read from timer
Contents of the reload register (measurement result) can be read by reading TBi register2
Write to timer
Value written to TBi register is written to neither reload register nor counter
Notes:
1. Interrupt request is not generated when the first effective edge is input after the timer started counting.
2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.
3. The TB0S to TB2S bits are assigned to the TABSR register bit 5 to bit 7, and the TB3S to TB5S bits are assigned
to the TBSR register bit 5 to bit 7.
Timer Bi mode register (i=0 to 5)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Bit symbol
TMOD0
TMOD1
MR0
Address
039B16 to 039D16
035B16 to 035D16
Bit name
Operation mode
select bit
Measurement mode
select bit
MR1
MR2
MR3
TCK0
After reset
00XX00002
00XX00002
Function
b1 b0
1 0 : Pulse period / pulse width
measurement mode
TCK1
RW
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Must not be set.
TB0MR and TB3MR registers
Must be set to “0” in pulse period and pulse width measurement mode
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to “0”. When read, its content turns out to be
indeterminate.
Timer Bi overflow
0 : Timer did not overflow
flag ( Note)
1 : Timer has overflowed
Count source
select bit
RW
RW
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
RW
RO
RW
RW
Note: This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is cleared to “0” (no overflow) by writing
to the TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to
“1” in a program. The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits are
assigned to the TBSR register's bit 5 to bit 7.
Figure 9.19
TBiMR Register in Pulse Period and Pulse Width Measurement Mode
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M306H7MG-XXXFP/MC-XXXFP/FGFP
9. TIMERS
Count source
“H”
Measurement pulse
Reload register
transfer timing
“L”
Transfer
(indeterminate value)
Transfer
(measured value)
counter
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
TBiS bit
“0”
TBiIC register's
IR bit
“1”
TBiMR register's
MR3 bit
“1”
“0”
Set to “0” upon accepting an interrupt request or by writing in
program
“0”
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
i = 0 to 5
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “002” (measure the interval
from falling edge to falling edge of the measurement pulse).
Figure 9.20
Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
Reload register
transfer timing
“L”
counter
Transfer
(indeterminate
value)
(Note 1)
Transfer
(measured value)
(Note 1)
Transfer
(measured
value)
(Note 1)
Transfer
(measured value)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016”
“1”
TBiS bit
“0”
“1”
TBiIC register's
IR bit
“0”
“1”
TBiMR register's
MR3 bit
i = 0 to 5
Set to “0” upon accepting an interrupt request or by
writing in program
“0”
The TB0S to TB2S bits are assigned to the TABSR register's bit 5 to bit 7, and the TB3S to TB5S bits
are assigned to the TBSR register's bit 5 to bit 7.
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Note 3: This timing diagram is for the case where the TBiMR register's MR1 to MR0 bits are “102” (measure the interval
from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of the
measurement pulse).
Figure 9.21
Operation timing when measuring a pulse width
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
10. Serial I/O
Serial I/O is configured with five channels: UART0 to UART2, SI/O3 and SI/O4.
10.1
UARTi (i=0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figure 10.1 shows the block diagram of UARTi. Figures 10.2 shows the block diagram of the UARTi transmit/
receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode) : UART0, UART1
• Special mode 4 (SIM mode) : UART2
Figures 10.3 to 10.8 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
1/2
f2SIO
PCLK1=0
f1SIO or f2SIO
f1SIO
Main clock
PCLK1=1
1/8
f8SIO
1/4
(UART0)
f32SIO
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD0
Clock source selection
f1SIO or f2SIO
f8SIO
f32SIO
UART reception
1/16
CLK1 to CLK0
002
Internal CKDIR=0
012
102
Reception
control circuit
Clock synchronous
type
U0BRG
register
1 / (n0+1)
1/16
UART transmission
Transmission control
Clock synchronous
circuit
type
Clock synchronous type
(when internal clock is selected)
1/2
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
External
TxD0
Receive
clock
Transmit
clock
Transmit/
receive
unit
CKDIR=1
CKPOL
CLK
polarity
reversing
circuit
CLK0
CTS/RTS selected
CRS=1
CTS0 / RTS0
CTS/RTS disabled
RTS0
“H”
CRS=0
CTS/RTS disabled
CRD=1
RCSP=0
CTS0
CRD=0
CTS0 from UART1
RCSP=1
(UART1)
Clock source selection
CLK1 to CLK0
002
f1SIO or f2SIO
Internal CKDIR=0
012
f8SIO
102
f32SIO
External
UART reception
1/16
1 / (n1+1)
Transmission
control circuit
Clock synchronous
type
CLKMD0=0
TxD1
Receive
clock
Transmit/
receive
unit
Transmit
clock
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLKMD0=1
Clock output
pin select
CLKMD1=1
CTS1 / RTS1/
CTS0/ CLKS1
UART transmission
1/16
CKDIR=1
CLK
polarity
reversing
circuit
CLK1
Reception
control circuit
Clock synchronous
type
U1BRG
register
CKPOL
CTS/RTS selected
CRS=1
CLKMD1=0
CRS=0
CTS/RTS disabled
RTS1
“H”
CTS/RTS disabled
RCSP=0
CRD=1
CTS1
CRD=0
CTS0 from UART0
RCSP=1
(UART2)
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD2
Clock source selection
CLK1 to CLK0
002
f1SIO or f2SIO
012
Internal CKDIR=0
f8SIO
102
f32SIO
External
CLK2
1 / (n2+1)
UART reception
Clock synchronous
type
1/16
CTS/RTS
selected
CRS=1
CRS=0
Clock synchronous
type
CTS/RTS disabled
RTS2
“H”
CTS/RTS disabled
CRD=1
CTS2
CRD=0
i = 0 to 2
ni: Values set to the UiBRG register
SMD2 to SMD0, CKDIR: UiMR register's bits
CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits
CLKMD0, CLKMD1, RCSP: UCON register's bits
Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.
UARTi Block Diagram
Rev.2.10
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Reception
control circuit
UART transmission
Clock synchronous type
1/2 (when internal clock is selected)
CKDIR=0
Clock synchronous type
(when external clock is selected)
CKDIR=1
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CTS2 / RTS2
1/16
U2BRG
register
CKDIR=1
CKPOL
Figure 10.1
TxD
polarity
reversing
circuit
RxD polarity
reversing circuit
RxD1
Transmission
control circuit
Receive
clock
Transmit
clock
(Note)
Transmit/
receive
unit
TxD2
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
No reverse
IOPOL=0
RxD data
reverse circuit
RxDi
Reverse IOPOL=1
Clock
synchronous type
1SP
PAR
disabled
STPS= 0
PRYE=0
SP
2SP
SP
UARTi receive register
UART(7 bits)
PAR
PRYE=1
PAR
enabled
STPS= 1
0
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
0
0
0
UART
0
Clock
synchronous type
UART
(9 bits)
0
0
UART
(8 bits)
UART
(9 bits)
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D7
D8
UART
(9 bits)
D6
D5
D4
D3
D2
D1
D0
UiTB register
UART
(8 bits)
UART
(9 bits)
Clock
synchronous type
PAR
2SP STPS= 1 enabled PRYE=1 UART
SP
SP
PAR
STPS
=0
1SP
PRYE=0
PAR
disabled
“0”
Clock
synchronous
type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous type
i=0 to 2
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: UiMR register's bits
UiERE: UiC1 register's bit
Figure 10.2
UARTi Transmit/Receive Unit
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UARTi transmit register
UART(7 bits)
Error signal output
disable
UiERE=1
No reverse
IOPOL=0
UiERE=0
Error signal
output circuit
Error signal output
enable
IOPOL=1
TxD data
reverse circuit
Reverse
TxDi
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
UARTi transmit buffer register (i=0 to 2)(Note)
(b15)
b7
(b8)
b0 b7
Symbol
U0TB
U1TB
U2TB
b0
Address
03A316-03A216
03AB16-03AA16
037B16-037A16
After reset
Indeterminate
Indeterminate
Indeterminate
Function
RW
WO
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register (i=0 to 2)
(b15)
b7
(b8)
b0 b7
Symbol
U0RB
U1RB
U2RB
b0
Bit
symbol
Address
03A716-03A616
03AF16-03AE16
037F16-037E16
Function
Bit name
(b7-b0)
(b8)
(b10-b9)
After reset
Indeterminate
Indeterminate
Indeterminate
RW
Receive data (D7 to D0)
RO
Receive data (D8)
RO
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
ABT
Arbitration lost detecting
flag (Note 2)
OER
Overrun error flag (Note 1) 0 : No overrun error
1 : Overrun error found
FER
Framing error flag (Note 1)
0 : No framing error
1 : Framing error found
RO
PER
Parity error flag (Note 1)
0 : No parity error
1 : Parity error found
RO
SUM
Error sum flag (Note 1)
0 : No error
1 : Error found
RO
0 : Not detected
1 : Detected
RW
RO
Note 1: When the UiMR register’s SMD2 to SMD0 bits = “0002” (serial I/O disabled) or the UiC1 register’s RE bit = “0” (reception disabled), all of the SUM,
PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER bits = “0” (no error).
Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.
Note 2: The ABT bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.)
UARTi bit rate generator (i=0 to 2)(Notes 1, 2)
b7
Symbol
U0BRG
U1BRG
U2BRG
b0
Address
03A116
03A916
037916
After reset
Indeterminate
Indeterminate
Indeterminate
Function
Setting range
RW
Assuming that set value = n, UiBRG divides the count source
by n + 1
0016 to FF16
WO
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
Figure 10.3
U0TB to U2TB Register, U0RB to U2RB Register, and U0BRG to U2BRG Register
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
UARTi transmit/receive mode register (i=0 to 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0MR to U2MR
Bit
symbol
SMD0
Address
03A016, 03A816, 037816
After reset
0016
Function
Bit name
Serial I/O mode select bit
(Note 2)
RW
b2 b1 b0
RW
0 0 0 : Serial I/O disabled
0 0 1 : Clock synchronous serial I/O mode
(Note 3)
0 1 0 : I2C mode
1 0 0 : UART mode transfer data 7 bits long
1 0 1 : UART mode transfer data 8 bits long
1 1 0 : UART mode transfer data 9 bits long
Must not be set except above
RW
CKDIR Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 1)
RW
STPS
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
RW
PRY
Odd/even parity select bit Effective when PRYE = 1
0 : Odd parity
1 : Even parity
SMD1
SMD2
RW
RW
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
RW
IOPOL
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
RW
Note 1: Set the corresponding port direction bit for each CLKi pin to “0” (input mode).
Note 2: To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).
Note 3: Set the corresponding port direction bit for SCL and SDA pins to “0” (input mode).
UARTi transmit/receive control register 0 (i=0 to 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
U0C0 to U2C0
Bit
symbol
CLK0
Address
After reset
03A416, 03AC16, 037C16 000010002
Bit name
BRG count source
select bit
CLK1
CRS
TXEPT
CRD
CTS/RTS function
select bit
(Note 4)
Function
b1 b0
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Must not be set
Effective when CRD = 0
0 : CTS function is selected (Note 1)
1 : RTS function is selected
Transmit register empty 0 : Data present in transmit register (during transmission)
1 : No data present in transmit register
flag
(transmission completed)
CTS/RTS disable bit
RW
RW
RW
RW
RO
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60, P64 and P73 can be used as I/O ports)
RW
NCH
Data output select bit
(Note 2)
0 : TxDi/SDAi and SCLi pins are CMOS output
1 : TxDi/SDAi and SCLi pins are N-channel open-drain output
RW
CKPOL
CLK polarity select bit
0 : Transmit data is output at falling edge of transfer clock
and receive data is input at rising edge
1 : Transmit data is output at rising edge of transfer clock
and receive data is input at falling edge
RW
UFORM Transfer format select bit 0 : LSB first
(Note 3)
1 : MSB first
RW
Note 1: Set the corresponding port direction bit for each CTSi pin to “0” (input mode).
Note 2: TXD2/SDA2 and SCL2 are N-channel open-drain output. Cannot be set to the CMOS output. Set the NCH bit of the U2C0
register to “0”.
Note 3: Effective for clock synchronous serial I/O mode and UART mode transfer data 8 bits long.
Note 4: CTS1/RTS1 can be used when the UCON register’s CLKMD1 bit = “0” (only CLK1 output) and the UCON register’s RCSP bit =
“0” (CTS0/RTS0 not separated).
Figure 10.4
U0MR to U2MR Register and U0C0 to U2C0 Register
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
UARTi transmit/receive control register 1 (i=0, 1)
b7
b6
b5
b4
b3
b2
b1
Symbol
U0C1, U1C1
b0
Bit
symbol
Address
03A516,03AD16
After reset
000000102
Function
Bit name
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer
empty flag
0 : Data present in UiTB register
1 : No data present in UiTB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in UiRB register
1 : Data present in UiRB register
RO
(b5-b4)
Nothing is assigned.
When write, set “0”. When read, these contents are “0”.
UiLCH
Data logic select bit
0 : No reverse
1 : Reverse
RW
UiERE
Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
UART2 transmit/receive control register 1
b7
b6
b5
b4
b3
b2
b1
Symbol
U2C1
b0
Bit
symbol
Address
037D16
RW
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
RW
TI
Transmit buffer
empty flag
0 : Data present in U2TB register
1 : No data present in U2TB register
RO
RE
Receive enable bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive complete flag
0 : No data present in U2RB register
1 : Data present in U2RB register
RO
0 : Transmit buffer empty (TI = 1)
1 : Transmit is completed (TXEPT = 1)
RW
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
RW
U2ERE Error signal output
enable bit
0 : Output disabled
1 : Output enabled
RW
U0C1 to U2C1 Registers
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Function
Bit name
U2IRS UART2 transmit interrupt
cause select bit
Figure 10.5
After reset
000000102
Page 98 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
UART transmit/receive control register 2
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
UCON
Bit
symbol
Address
03B016
After reset
X00000002
Function
Bit
name
UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
RW
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
RW
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
CLKMD0 UART1 CLK/CLKS
select bit 0
Effective when CLKMD1 = “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
RW
CLKMD1 UART1 CLK/CLKS
select bit 1 (Note)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
RW
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
RW
U0IRS
U1IRS
Separate UART0
CTS/RTS bit
RW
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UART2 special mode register (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0SMR to U2SMR 036F16, 037316, 037716
0
Bit
symbol
After reset
X00000002
Function
Bit
name
RW
IICM
I2C mode select bit
0 : Other than I2C mode
1 : I2C mode
RW
ABC
Arbitration lost detecting
flag control bit
0 : Update per bit
1 : Update per byte
RW
BBS
Bus busy flag
0 : STOP condition detected
1 : START condition detected (busy)
RW
(Note1)
Reserved bit
Set to “0”
RW
ABSCS
Bus collision detect
sampling clock select bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj (Note 2)
RW
ACSE
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
RW
SSS
Transmit start condition
select bit
0 : Not synchronized to RxDi
1 : Synchronized to RxDi (Note 3)
RW
(b3)
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
(b7)
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to “0” (Not synchronized to RxDi)
Figure 10.6
UCON Register and U0SMR to U2SMR Registers
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
UARTi special mode register 2 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
U0SMR2 to U2SMR2 036E16, 037216, 037616
Bit
symbol
After reset
X00000002
Bit name
Function
RW
IICM2
I 2C mode select bit 2
Refer to Table 10.12
CSC
Clock-synchronous bit
0 : Disabled
1 : Enabled
RW
SWC
SCL wait output bit
0 : Disabled
1 : Enabled
RW
ALS
SDA output stop bit
0 : Disabled
1 : Enabled
RW
STAC
UARTi initialization bit
0 : Disabled
1 : Enabled
RW
SWC2
SCL wait output bit 2
0: Transfer clock
1: “L” output
RW
SDHI
SDA output disable bit
0: Enabled
1: Disabled (high impedance)
RW
RW
Nothing is assigned. When write, set “0”. When read, its content is
indeterminate.
(b7)
UARTi special mode register 3 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR3 to U2SMR3
Bit
symbol
(b0)
CKPH
(b2)
NODC
(b4)
DL0
Address
036D16, 037116, 037516
Bit name
After reset
000X0X0X2
Function
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Clock phase set bit
0 : Without clock delay
1 : With clock delay
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
Clock output select bit
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
RW
Nothing is assigned.
When write, set “0”. When read, its content is indeterminate.
SDAi digital delay
setup bit
(Note 1, Note 2)
DL1
DL2
b7 b6 b5
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : Without delay
1 : 1 to 2 cycle(s) of UiBRG count source
0 : 2 to 3 cycles of UiBRG count source
1 : 3 to 4 cycles of UiBRG count source
0 : 4 to 5 cycles of UiBRG count source
1 : 5 to 6 cycles of UiBRG count source
0 : 6 to 7 cycles of UiBRG count source
1 : 7 to 8 cycles of UiBRG count source
RW
RW
RW
Note 1 : The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode. In other than I2C
mode, set these bits to “0002” (no delay).
Note 2 : The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock, the amount of
delay increases by about 100 ns.
Figure 10.7
U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
UARTi special mode register 4 (i=0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Address
Symbol
U0SMR4 to U2SMR4 036C16, 037016, 037416
Bit
symbol
Bit name
RW
0 : Clear
1 : Start
RW
RSTAREQ Restart condition
generate bit (Note)
0 : Clear
1 : Start
RW
STPREQ
Stop condition
generate bit (Note)
0 : Clear
1 : Start
RW
STSPSEL
SCL,SDA output
select bit
0 : Start and stop conditions not output
1 : Start and stop conditions output
RW
ACKD
ACK data bit
0 : ACK
1 : NACK
RW
ACKC
ACK data output
enable bit
0 : Serial I/O data output
1 : ACK data output
RW
SCLHI
SCL output stop
enable bit
0 : Disabled
1 : Enabled
RW
SWC9
SCL wait bit 3
0 : SCL “L” hold disabled
1 : SCL “L” hold enabled
RW
Note: Set to “0” when each condition is generated.
U0SMR4 to U2SMR4 Registers
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Function
Start condition
generate bit (Note)
STAREQ
Figure 10.8
After reset
0016
Page 101 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
10.2
10. SERIAL I/O
Clock Synchronous serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 10.1 lists the
specifications of the clock synchronous serial I/O mode. Table 10.2 lists the registers used in clock synchronous
serial I/O mode and the register values set.
Table 10.1
Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
Transmission, reception control
Transmission start condition
Reception start condition
• CKDIR bit = “1” (external clock) : Input from CLKi pin
_______
_______
_______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in UiTB register)
_
If CTS function is selected, input on the CTSi pin = “L”
_______
_______
• Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of UiC1 register= 1 (reception enabled)
_
The TE bit of UiC1 register= 1 (transmission enabled)
_
Interrupt request
generation timing
The TI bit of UiC1 register= 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 3) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
Error detection
Select function
completion of reception)
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be chosen to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
• Separate CTS/RTS pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 3: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 10.2
Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
UiTB(Note3)
Bit
Function
0 to 7
Set transmission data
UiRB(Note3) 0 to 7
UiBRG
Reception data can be read
OER
Overrun error flag
0 to 7
Set a transfer rate
UiMR(Note3) SMD2 to SMD0
UiC0
10. SERIAL I/O
Set to “0012”
CKDIR
Select the internal clock or external clock
IOPOL
Set to “0”
CLK1 to CLK0
Select the count source for the UiBRG register
CRS
Select CTS or RTS to use
TXEPT
Transmit register empty flag
CRD
Enable or disable the CTS or RTS function
NCH
Select TxDi pin output mode (Note 2)
CKPOL
Select the transfer clock polarity
UFORM
Select the LSB first or MSB first
TE
Set this bit to “1” to enable transmission/reception
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 1)
Select the source of UART2 transmit interrupt
_______
_______
_______
UiC1
U2RRM (Note 1)
Set this bit to “1” to use continuous receive mode
UiLCH
Set this bit to “1” to use inverted data logic
UiERE
Set to “0”
UiSMR
0 to 7
Set to “0”
UiSMR2
0 to 7
Set to “0”
UiSMR3
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
0 to 7
Set to “0”
UiSMR4
UCON
_______
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM
Set this bit to “1” to use continuous receive mode
CLKMD0
Select the transfer clock output pin when CLKMD1 = 1
CLKMD1
Set this bit to “1” to output UART1 transfer clock from two pins
RCSP
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7
Set to “0”
_________
Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
i=0 to 2
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10. SERIAL I/O
Table 10.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 10.3 shows
pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 10.4 lists
the P64 pin functions during clock synchronous serial I/O mode. Note that for a period from when the UARTi
operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output
is selected, this pin is in a high-impedance state.)
Table 10.3
Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin name
Function
Method of selection
TxDi (i = 0 to 2) Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
CLKi
Transfer clock output
(P61, P65, P72)
Transfer clock input
UiMR register’s CKDIR bit=0
CTSi/RTSi
CTS input
(P60, P64, P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
Table 10.4
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
I/O port
UiC0 register’s CRD bit=1
P64 Pin Functions
Bit set value
Pin function
P64
CTS1
RTS1
CTS0(Note1)
CLKS1
U1C0 register
CRS
CRD
1
0
0
1
0
0
0
UCON register
RCSP CLKMD1 CLKMD0
0
0
0
0
0
0
1
0
1(Note 2)
PD6 register
PD6_4
Input: 0, Output: 1
0
0
1
Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0 enabled) and the U0
C0 register’s CRS bit to “1” (RTS0 selected).
Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the U1C0 register’s CLKPOL bit = 0
• Low if the U1C0 register’s CLKPOL bit = 1
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10. SERIAL I/O
(1) Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
“1”
“0”
Write data to the UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi
TCLK
“L”
Stopped pulsing because CTSi = “H”
Stopped pulsing because the TE bit = “0”
CLKi
TxDi
D0 D 1 D2 D3 D4 D5 D6 D7
UiC0 register
TXEPT bit
“1”
SiTIC register
IR bit
“1”
D 0 D 1 D 2 D3 D4 D 5 D 6 D 7
D 0 D 1 D 2 D 3 D 4 D 5 D6 D 7
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = TCLK = 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to UiBRG register
i: 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register CKDIR bit = 0 (internal clock)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
(2) Example of receive timing (when external clock is selected)
“1”
UiC1 register
RE bit
“0”
UiC1 register
TE bit
“0”
UiC1 register
TI bit
“1”
Write dummy data to UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
RTSi
“L”
Even if the reception is completed, the RTS
does not change. The RTS becomes “L”
when the RI bit changes to “0” from “1”.
1 / fEXT
CLKi
Receive data is taken in
D 0 D1 D 2 D3 D 4 D5 D6 D 7
RxDi
UiC1 register
RI bit
“1”
SiRIC register
IR bit
“1”
Transferred from UARTi receive register
to UiRB register
D0 D 1 D 2
D3 D 4 D 5
Read out from UiRB register
“0”
“0”
Cleared to “0” when interrupt request is
accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
Make sure the following conditions are met when input
as follows:
to the CLKi pin before receiving data is high:
• UiMR register CKDIR bit = 1 (external clock)
• UiC1 register TE bit = 1 (transmit enabled)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
• UiC1 register RE bit = 1 (Receive enabled)
• UiC0 register CKPOL bit = 0 (transmit data output at the falling edge and receive • Write dummy data to the UiTB register
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 10.9
Transmit and Receive Operation
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10.2.1
10. SERIAL I/O
CLK Polarity Select Function
Use the UiC0 register (i = 0 to 2)’s CKPOL bit to select the transfer clock polarity. Figure 10.10 shows the
polarity of the transfer clock.
(1) When the UiC0 register’s CKPOL bit = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
(Note 2)
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiC0 register’s CKPOL bit = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
(Note 3)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
R XD i
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: This applies to the case where the UiC0 register’s UFORM bit = 0
(LSB first) and UiC1 register's UiLCH bit = 0 (no reverse).
Note 2: When not transferring, the CLKi pin outputs a high signal.
Note 3: When not transferring, the CLKi pin outputs a low signal.
i = 0 to 2
Figure 10.10
10.2.2
Transfer Clock Polarity
LSB First/MSB First Select Function
Use the UiC0 register (i = 0 to 2)’s UFORM bit to select the transfer format. Figure 10.11 shows the transfer
format.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
D0
D1
D2
D3
D4
D5
D6
D7
R XD i
D0
D1
D2
D3
D4
D5
D6
D7
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
D7
D6
D5
D4
D3
D2
D1
D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock) and the UiC1 register’s
UiLCH bit = 0 (no reverse).
i = 0 to 2
Figure 10.11
Transfer Format
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10.2.3
10. SERIAL I/O
Continuous Receive Mode
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the UiC1 register’s TI bit is set to “0” (data
present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write
dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are the UCON register bit 2 and
bit 3, respectively, and the U2RRM bit is the U2C1 register bit 5.
10.2.4
Serial Data Logic Switching Function
When the UiC1 register (i = 0 to 2)’s UiLCH bit = 1 (reverse), the data written to the UiTB register has its logic
reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB
register. Figure 10.12 shows serial data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse) “L”
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(reverse)
“L”
D0
D1
D2
D3
D4
D5
D6
D7
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge and the receive data
taken in at the rising edge of the transfer clock) and the UFORM
bit = 0 (LSB first).
i = 0 to 2
Figure 10.12
10.2.5
Serial Data Logic Switching
Transfer Clock Output From Multiple Pins (UART1)
Use the UCON register’s CLKMD1 to CLKMD0 bits to select one of the two transfer clock output pins. (See
Figure 10.13.) This function can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1 (P67)
CLKS1 (P64)
CLK1 (P65)
IN
IN
CLK
CLK
Transfer enabled
when the UCON
register's
CLKMD0 bit = 0
Transfer enabled
when the UCON
register's
CLKMD0 bit = 1
Note: This applies to the case where the U1MRregister's CKDIR bit
= 0 (internal clock) and the UCON register's CLKMD1 bit = 1
(transfer clock output from multiple pins).
Figure 10.13
Transfer Clock Output From Multiple Pins
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10.2.6
10. SERIAL I/O
CTS/RTS Separate Function (UART0)
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64
pin. To use this function, set the register bits as shown below.
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
Note that when using the CTS/RTS separate function, UART1 CTS/RTS function cannot be used.
IC
Microcomputer
TXD0 (P63)
Figure 10.14
RXD0 (P62)
IN
OUT
CLK0 (P61)
CLK
RTS0 (P60)
CTS
CTS0 (P64)
RTS
CTS/RTS Separat Function
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10.3
10. SERIAL I/O
Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data
format. Tables 10.5 lists the specifications of the UART mode.
Table 10.5
UART Mode Specifications
Item
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• UiMR(i=0 to 2) register’s CKDIR bit = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLKi pin. n :Setting value of UiBRG register
0016 to FF16
_______
_______
_______ _______
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_______
_ If CTS function is selected, input on the CTSi pin = “L”
• Before reception can start, the following requirements must be met
_ The RE bit of UiC1 register= 1 (reception enabled)
_ Start bit detection
• For transmission, one of the following conditions can be selected
_ The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Select function
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of hte TXD pin output and RXD pin input. The
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
Note 1: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
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Table 10.6
10. SERIAL I/O
Registers to Be Used and Settings in UART Mode
Register
Bit
Function
UiTB
0 to 8
Set transmission data (Note 1)
UiRB
0 to 8
Reception data can be read (Note 1)
OER,FER,PER,SUM Error flag
UiBRG
0 to 7
Set a transfer rate
UiMR
SMD2 to SMD0
Set these bits to ‘1002’ when transfer data is 7 bits long
Set these bits to ‘1012’ when transfer data is 8 bits long
Set these bits to ‘1102’ when transfer data is 9 bits long
CKDIR
UiC0
Select the internal clock or external clock
STPS
Select the stop bit
PRY, PRYE
Select whether parity is included and whether odd or even
IOPOL
Select the TxD/RxD input/output polarity
CLK0, CLK1
Select the count source for the UiBRG register
CRS
Select CTS or RTS to use
TXEPT
Transmit register empty flag
CRD
Enable or disable the CTS or RTS function
NCH
Select TxDi pin output mode (Note 3)
CKPOL
Set to “0”
UFORM
LSB first or MSB first can be selected when transfer data is 8 bits long. Set this
_______
_______
_______
_______
bit to “0” when transfer data is 7 or 9 bits long.
UiC1
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 2)
Select the source of UART2 transmit interrupt
U2RRM (Note 2)
Set to “0”
UiLCH
Set this bit to “1” to use inverted data logic
UiERE
Set to “0”
UiSMR
0 to 7
Set to “0”
UiSMR2
0 to 7
Set to “0”
UiSMR3
0 to 7
Set to “0”
UiSMR4
0 to 7
Set to “0”
UCON
U0IRS, U1IRS
Select the source of UART0/UART1 transmit interrupt
U0RRM, U1RRM
Set to “0”
CLKMD0
Invalid because CLKMD1 = 0
CLKMD1
Set to “0”
RCSP
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin
7
Set to “0”
_________
Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;
bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.
Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are included in the UCON register.
Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
i=0 to 2
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10. SERIAL I/O
Table 10.7 lists the functions of the input/output pins during UART mode. Table 10.8 lists the P64 pin functions
during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer
starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance
state.)
Table 10.7
I/O Pin Functions
Pin name
Function
Method of selection
TxDi (i = 0 to 2) Serial data output
(P63, P67, P70)
(Outputs dummy data when performing reception only)
Serial data input
RxDi
(P62, P66, P71)
PD6 register’s PD6_2 bit=0, PD6_6 bit=0, PD7 register’s PD7_1 bit=0
(Can be used as an input port when performing transmission only)
CLKi
Input/output port
(P61, P65, P72)
Transfer clock input
UiMR register’s CKDIR bit=0
CTSi/RTSi
CTS input
(P60, P64, P73)
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=0
PD6 register’s PD6_0 bit=0, PD6_4 bit=0, PD7 register’s PD7_3 bit=0
Table 10.8
UiMR register’s CKDIR bit=1
PD6 register’s PD6_1 bit=0, PD6_5 bit=0, PD7 register’s PD7_2 bit=0
RTS output
UiC0 register’s CRD bit=0
UiC0 register’s CRS bit=1
Input/output port
UiC0 register’s CRD bit=1
P64 Pin Functions
Bit set value
Pin function
P64
CTS1
RTS1
CTS0 (Note)
U1C0 register
CRS
CRD
1
0
0
0
0
1
0
UCON register
RCSP CLKMD1
0
0
0
1
0
0
0
0
PD6 register
PD6_4
Input: 0, Output: 1
0
0
Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0
enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).
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10. SERIAL I/O
(1) Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to “L”.
Tc
Transfer clock
UiC1 register
TE bit
“1”
“0”
UiC1 register
TI bit
Write data to the UiTB register
“1”
“0”
Transferred from UiTB register to UARTi transmit register
“H”
CTSi
“L”
Start
bit
TxDi
UiC0 register
TXEPT bit
Stopped pulsing
because the TE bit
= “0”
Parity Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1
“1”
“0”
SiTIC register
IR bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set
as follows:
• UiMR register PRYE bit = 1 (parity enabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTS/RTS enabled), CRS bit = 0 (CTS selected)
• UiRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
i: 0 to 2
(2) Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
UiC1 register
TE bit
UiC1 register
TI bit
“1”
Write data to the UiTB register
“0”
“1”
“0”
Start
bit
TxDi
Stop Stop
bit bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
UiC0 register
TXEPT bit
“1”
SiTIC register
IR bit
“1”
Transferred from UiTB register to UARTi
transmit register
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP
ST D0 D1
“0”
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies to the case where the register bits are set
as follows:
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
• UiMR register PRYE bit = 0 (parity disabled)
fEXT : frequency of UiBRG count source (external clock)
• UiMR register STPS bit = 1 (2 stop bits)
n : value set to UiBRG
• UiC0 register CRD bit = 1 (CTS/RTS disabled)
i: 0 to 2
• UiRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON
register bit 1, and U2IRS bit is the U2C1 register bit 4
Figure 10.15
Transmit Operation
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10. SERIAL I/O
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG count
source
“1”
“0”
UiC1 register
RE bit
Stop bit
Start bit
RxDi
D7
D1
D0
Sampled “L”
Receive data taken in
Transfer clock
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
UiC1 register
RI bit
Transferred from UARTi receive
register to UiRB register
“0”
“H”
“L”
RTSi
“1”
“0”
SiRIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where the register bits are set as follows:
• UiMR register PRYE bit = 0 (parity disabled)
• UiMR register STPS bit = 0 (1 stop bit)
• UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
Figure 10.16
10.3.1
Receive Operation
LSB First/MSB First Select Function
As shown in Figure 10.17, use the UiC0 register’s UFORM bit to select the transfer format. This function is
valid when transfer data is 8 bits long.
(1) When UiC0 register's UFORM bit = 0 (LSB first)
CLKi
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When UiC0 register's UFORM bit = 1 (MSB first)
CLKi
TXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
RXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
Figure 10.17
Transfer Format
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10.3.2
10. SERIAL I/O
Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received
data has its logic reversed when read from the UiRB register. Figure 10.18 shows serial data logic.
(1) When the UiC1 register's UiLCH bit = 0 (no reverse)
Transfer clock
“H”
TxDi
“H”
(no reverse)
“L”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
D5
D6
D7
P
SP
(2) When the UiC1 register's UiLCH bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(reverse)
“L”
ST
D0
D1
D2
D3
D4
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0
(transmit data output at the falling edge of the transfer clock), the
UiC0 register's UFORM bit = 0 (LSB first), the UiMR register's
STPS bit = 0 (1 stop bit) and UiMR register's PRYE bit = 1 (parity
enabled).
Figure 10.18
10.3.3
Serial Data Logic Switching
TxD and RxD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/
output data (including the start, stop and parity bits) are inversed. Figure 10.19 shows the TXD pin output and
RXD pin input polarity inverse.
(1) When the UiMR register's IOPOL bit = 0 (no reverse)
Transfer clock
“H”
“L”
TxDi
“H”
(no reverse) “L”
RxDi
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(no reverse) “L”
(2) When the UiMR register's IOPOL bit = 1 (reverse)
Transfer clock
“H”
“L”
TxDi
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(reverse)
RxDi
(reverse)
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
Note: This applies to the case where the UiC0 register's UFORM bit = 0
(LSB first), the UiMR register's STPS bit = 0 (1 stop bit) and the
UiMR register's PRYE bit = 1 (parity enabled).
Figure 10.19
TXD and RXD I/O Polarity Inverse
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10.3.4
10. SERIAL I/O
CTS/RTS Separate Function (UART0)
This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0 from the P64
pin. To use this function, set the register bits as shown below.
• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)
• U0C0 register's CRS bit = 1 (outputs UART0 RTS)
• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)
• U1C0 register's CRS bit = 0 (inputs UART1 CTS)
• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)
• UCON register's CLKMD1 bit = 0 (CLKS1 not used)
Note that when using the CTS/RTS separate function, UART1 CTS/RTS function cannot be used.
IC
Microcomputer
TXD0 (P63)
Figure 10.20
RXD0 (P62)
IN
OUT
RTS0 (P60)
CTS
CTS0 (P64)
RTS
CTS/RTS Separate Function
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10.4
10. SERIAL I/O
Special Mode 1 (I2C mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 10.9 lists the specifications of
the I2C mode. Table 10.10 to 10.11 lists the registers used in the I2C mode and the register values set, Table 10.12
lists the I2C mode functions. Figure 10.21 shows the block diagram for I2C mode. Figure 10.22 shows SCLi timing.
As shown in Table 10.12, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to ‘0102’
and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output does not change
state until SCLi goes low and remains stably low.
Table 10.9
I2C Mode Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• During master
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• During slave
Transmission start condition
CKDIR bit = “1” (external clock) : Input from SCLi pin
• Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of UiC1 register= 1 (transmission enabled)
_
Reception start condition
The TI bit of UiC1 register = 0 (data present in UiTB register)
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_
The TE bit of UiC1 register= 1 (transmission enabled)
_
Interrupt request
generation timing
Error detection
Select function
The TI bit of UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
• Arbitration lost
Timing at which the UiRB register’s ABT bit is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change.
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10. SERIAL I/O
Start and stop condition generation block
SDAi
STSPSEL=1
Delay
circuit
SDASTSP
SCLSTSP
STSPSEL=0
ACK=1
IICM2=1
Transmission
register
ACK=0
IICM=1 and
IICM2=0
UARTi
SDHI
ACKD register
D
DMA0
(UART0, UART2)
Arbitration
Q
UARTi transmit,
NACK interrupt
request
ALS
T
Noise
Filter
DMA0, DMA1 request
(UART1: DMA0 only)
IICM2=1
Reception register
UARTi
IICM=1 and
IICM2=0
Start condition
detection
S
R
Q
Bus
busy
Stop condition
detection
NACK
D
IICM=0
R
I/O port
Q
STSPSEL=0
IICM=1 UARTi
Noise
Filter
Q
T
Falling edge
detection
SCLi
UARTi receive,
ACK interrupt request,
DMA1 request
D Q
T
Port register
(Note)
Internal clock
SWC2
STSPSEL=1 External
clock
ACK
9th bit
Start/stop condition detection
interrupt request
CLK
control
UARTi
R
S
9th bit falling edge
SWC
This diagram applies to the case where the UiMR register's SMD2 to SMD0 bits = 0102 and the UiSMR register's IICM bit = 1.
IICM
: UiSMR register bit
IICM2, SWC, ALS, SWC2, SDHI : UiSMR2 register bit
STSPSEL, ACKD, ACKC
: UiSMR4 register bit
i=0 to 2
Note: If the IICM bit = 1, the pin can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Figure 10.21
I2C Mode Block Diagram
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Table 10.10
10. SERIAL I/O
Registers to Be Used and Settings in I2C Mode (1) (Continued)
Register
Bit
UiTB
0 to 7
(Note 3)
UiRB
0 to 7
(Note 3) 8
ABT
OER
UiBRG 0 to 7
UiMR
SMD2 to SMD0
(Note 3) CKDIR
IOPOL
UiC0
CLK1, CLK0
Function
Master
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to ‘0102’
Set to “0”
Set to “0”
Select the count source for the UiBRG
register
CRS
Invalid because CRD = 1
TXEPT
Transmit buffer empty flag
CRD
Set to “1”
NCH
Set to “1” (Note 2)
CKPOL
Set to “0”
UFORM
Set to “1”
UiC1
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS (Note 1)
Invalid
U2RRM (Note 1), Set to “0”
UiLCH, UiERE
UiSMR IICM
Set to “1”
ABC
Select the timing at which arbitration-lost
is detected
BBS
Bus busy flag
3 to 7
Set to “0”
UiSMR2 IICM2
Refer to Table 11.12
CSC
Set this bit to “1” to enable clock
synchronization
SWC
Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th
bit of clock
ALS
Set this bit to “1” to have SDAi output
stopped when arbitration-lost is detected
STAC
Set to “0”
SWC2
Set this bit to “1” to have SCLi output
forcibly pulled low
SDHI
Set this bit to “1” to disable SDAi output
7
Set to “0”
UiSMR3 0, 2, 4 and NODC Set to “0”
CKPH
Refer to Table 11.12
DL2 to DL0
Set the amount of SDAi digital delay
Slave
Set transmission data
Reception data can be read
ACK or NACK is set in this bit
Invalid
Overrun error flag
Invalid
Set to ‘0102’
Set to “1”
Set to “0”
Invalid
Invalid because CRD = 1
Transmit buffer empty flag
Set to “1”
Set to “1” (Note 2)
Set to “0”
Set to “1”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
Set to “0”
Set to “1”
Invalid
Bus busy flag
Set to “0”
Refer to Table 11.12
Set to “0”
Set this bit to “1” to have SCLi output
fixed to “L” at the falling edge of the 9th
bit of clock
Set to “0”
Set this bit to “1” to initialize UARTi at
start condition detection
Set this bit to “1” to have SCLi output
forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
Set to “0”
Refer to Table 11.12
Set the amount of SDAi digital delay
i=0 to 2
Notes:
1. Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are
in the UCON register.
2. TxD2 pin is N channel open-drain output. Set the NCH bit in the U2C0 register to “0”.
3. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.
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Table 10.11
10. SERIAL I/O
Registers to Be Used and Settings in I2C Mode (2) (Continued)
Register
Bit
UiSMR4 STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
IFSR2A IFSR26, ISFR27
UCON U0IRS, U1IRS
2 to 7
Function
Master
Slave
Set this bit to “1” to generate start
Set to “0”
condition
Set this bit to “1” to generate restart
Set to “0”
condition
Set this bit to “1” to generate stop
Set to “0”
condition
Set this bit to “1” to output each condition Set to “0”
Select ACK or NACK
Select ACK or NACK
Set this bit to “1” to output ACK data
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCLi output
Set to “0”
stopped when stop condition is detected
Set to “0”
Set this bit to “1” to set the SCLi to “L”
hold at the next falling edge of the 9th bit
of clock
Set to “1”
Set to “1”
Invalid
Invalid
Set to “0”
Set to “0”
i=0 to 2
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Table 10.12
10. SERIAL I/O
I2C Mode Functions
Function
Clock synchronous serial I/O
I2C mode (SMD2 to SMD0 = 0102, IICM = 1)
mode (SMD2 to SMD0 = 0012, IICM2 = 0
IICM2 = 1
IICM = 0)
(NACK/ACK interrupt)
(UART transmit/ receive interrupt)
CKPH = 1
CKPH = 1
CKPH = 0
CKPH = 0
(Clock delay)
(No clock delay) (Clock delay) (No clock delay)
Factor of interrupt number
6, 7 and 10 (Note 1, 5, 7)
Start condition detection or stop condition detection
(Refer to “Table 10.13. STSPSEL Bit Functions”)
Factor of interrupt number UARTi transmission
15, 17 and 19 (Note 1, 6) Transmission started or
completed (selected by UiIRS)
Factor of interrupt number UARTi reception
16, 18 and 20 (Note 1, 6) When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Timing for transferring data CKPOL = 0 (rising edge)
from the UART reception CKPOL = 1 (falling edge)
shift register to the UiRB
register
UARTi transmission output Not delayed
delay
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
Acknowledgment detection
(ACK)
Rising edge of SCLi 9th bit
Rising edge of SCLi 9th bit
UARTi transmission UARTi transmission
Falling edge of SCLi
Rising edge of
next to the 9th bit
SCLi 9th bit
UARTi reception
Falling edge of SCLi 9th bit
Falling edge of
SCLi 9th bit
Falling and rising
edges of SCLi 9th
bit
Delayed
Functions of P63, P67 and TxDi output
P70 pins
SDAi input/output
Functions of P62, P66 and RxDi input
P71 pins
SCLi input/output
(Cannot be used in I2C mode)
Functions of P61, P65 and
P72 pins
CLKi input or output selected
Noise filter width
15ns
Read RxDi and SCLi pin
levels
Always possible no matter how the corresponding port direction bit is set
Possible when the
corresponding port direction bit
=0
CKPOL = 0 (H)
The value set in the port register before setting I2C mode (Note 2)
CKPOL = 1 (L)
Initial value of TxDi and
SDAi outputs
Initial and end values of
SCLi
H
DMA1 factor (Refer to Fig
10.22)
UARTi reception
Store received data
1st to 8th bits are stored in
UiRB register bit 0 to bit 7
Read received data
200ns
UiRB register status is read
directly as is
L
Acknowledgment detection
(ACK)
1st to 8th bits are stored in
UiRB register bit 7 to bit 0
H
L
UARTi reception
Falling edge of SCLi 9th bit
1st to 7th bits are stored in UiRB register
bit 6 to bit 0, with 8th bit stored in UiRB
register bit 8
1st to 8th bits are
stored in UiRB
register bit 7 to bit 0
(Note 3)
Read UiRB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)
i = 0 to 2
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to “precautions for interrupts” of the Usage Notes Reference Book.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
Note 2: Set the initial value of SDAi output while the UiMR register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
Note 3: Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
Note 4: First data transfer to UiRB register (Falling edge of SCLi 9th bit)
Note 5: Refer to “Figure 10.13. STSPSEL Bit Functions”.
Note 6: Refer to “Figure 10.22. Transfer to UiRB Register and Interrupt Timing” .
Note 7: When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (cause of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR27 bit in the IFSR2A register to “1” (cause of interrupt: UART1 bus collision).
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10. SERIAL I/O
(1) IICM2= 0 (ACK and NACK interrupts), CKPH= 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
D3
D2
D1
UiRB register
(2) IICM2= 0, CKPH= 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
•••
b8
b7
D8
D7
b0
D6
D5
D4
D3
UiRB register
(3) IICM2= 1 (UART transmit/receive interrupt), CKPH= 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transmit interrupt
Transfer to UiRB register
b15
b9
b8
b7
b0
D0
•••
D7
D6
D5
D4
UiRB register
(4) IICM2= 1, CKPH= 1
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b15
b9
•••
b8
D0
b7
b0
D7
D6
D5
D4
D3
D2
D1
Transmit interrupt
Transfer to UiRB register
b15
b9
•••
UiRB register
i=0 to 2
This diagram applies to the case where the following condition is met.
• UiMR register CKDIR bit = 0 (Slave selected)
Figure 10.22
Transfer to UiRB Register and Interrupt Timing
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b8
b7
D8
D7
b0
D6
D5
D4
D3
D2
UiRB register
D1
D0
M306H7MG-XXXFP/MC-XXXFP/FGFP
10.4.1
10. SERIAL I/O
Detection of Start and Stop Condtion
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low
while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when the SDAi
pin changes state from low to high while the SCLi pin is in the high state.
Because the start and stop condition-detected interrupts share the interrupt control register and vector, check the
UiSMR register’s BBS bit to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up (Note)
3 to 6 cycles < duration for holding (Note)
Duration for
setting up
Duration for
holding
SCLi
SDAi
(Start condition)
SDA i
(Stop condition)
i = 0 to 2
Note: When the PCLKR register's PCLK1 bit = 1, this is the cycle number of
f1SIO, and the PCLK1 bit = 0, this is the cycle number of f2SIO.
Figure 10.23
10.4.2
Detection of Start and Stop Condition
Output of Start and Stop Condition
A start condition is generated by setting the UiSMR4 register (i = 0 to 2)’s STAREQ bit to “1” (start).
A restart condition is generated by setting the UiSMR4 register’s RSTAREQ bit to “1” (start).
A stop condition is generated by setting the UiSMR4 register’s STPREQ bit to “1” (start).
The output procedure is described below.
Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
Set the STSPSEL bit in the UiSMR4 register to “1” (output).
The function of the STSPSEL bit is shown in Table 10.13 and Figure 10.24.
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Table 10.13
10. SERIAL I/O
STSPSEL Bit Functions
Function
Output of SCLi and SDAi pins
STSPSEL = 0
Output of transfer clock and
data
Output of start/stop condition is
STSPSEL = 1
Output of a start/stop condition
according to the STAREQ,
RSTAREQ and STPREQ bit
accomplished by a program
using ports (not automatically
Start/stop condition interrupt
request generation timing
generated in hardware)
Start/stop condition detection
Finish generating start/stop condition
(1) When slave
CKDIR=1 (external clock)
STSPSEL bit 0
1st 2nd 3rd
5th 6th 7th 8th 9th bit
SCLi
SDAi
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When master
CKDIR=0 (internal clock), CKPH=1 (clock delayed)
STSPSEL bit
Set to “1” in
a program
Set to “0” in
a program
1st 2nd 3rd
SCLi
Set to “1” in
a program
Set to “0” in
a program
5th 6th 7th 8th 9th bit
SDAi
Set STAREQ=
1 (start)
Figure 10.24
10.4.3
Start condition
detection interrupt
Set STPREQ=
1 (start)
Stop condition
detection interrupt
STSPSEL Bit Functions
Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge of
SCLi. Use the UiSMR register’s ABC bit to select the timing at which the UiRB register’s ABT bit is updated.
If the ABC bit = 0 (updated bitwise), the ABT bit is set to “1” at the same time unmatching is detected during
check, and is cleared to “0” when not detected. In cases when the ABC bit is set to “1”, if unmatching is
detected even once during check, the ABT bit is set to “1” (unmatching detected) at the falling edge of the clock
pulse of 9th bit. If the ABT bit needs to be updated bytewise, clear the ABT bit to “0” (undetected) after
detecting acknowledge in the first byte, before transferring the next byte.
Setting the UiSMR2 register’s ALS bit to “1” (SDA output stop enabled) causes arbitration-lost to occur, in
which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is set to “1”
(unmatching detected).
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10.4.4
10. SERIAL I/O
Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 10.24.
The UiSMR2 register’s CSC bit is used to synchronize the internally generated clock (internal SCLi) and an
external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchronization enabled),
if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes low, at which
time the UiBRG register value is reloaded with and starts counting in the low-level interval. If the internal SCLi
changes state from low to high while the SCLi pin is low, counting stops, and when the SCLi pin goes high,
counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin
signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the
rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The UiSMR2 register’s SWC bit allows to select whether the SCLi pin should be fixed to or freed from lowlevel output at the falling edge of the 9th clock pulse.
If the UiSMR4 register’s SCLHI bit is set to “1” (enabled), SCLi output is turned off (placed in the high
impedance state) when a stop condition is detected.
Setting the UiSMR2 register’s SWC2 bit = 1 (0 output) makes it possible to forcibly output a low-level signal
from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer clock) allows
the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal.
If the UiSMR4 register’s SWC9 bit is set to “1” (SCL hold low enabled) when the UiSMR3 register’s CKPH bit
= 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the ninth. Setting the
SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
10.4.5
SDA Output
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the UiMR register’s
SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
The UiSMR3 register’s DL2 to DL0 bits allow to add no delays or a delay of 2 to 8 UiBRG count source clock
cycles to SDAi output.
Setting the UiSMR2 register’s SDHI bit = 1 (SDA output disabled) forcibly places the SDAi pin in the highimpedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer clock.
This is because the ABT bit may inadvertently be set to “1” (detected).
10.4.6
SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to bit
0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to bit
0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH bit
= 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB register after the rising edge
of the corresponding clock pulse of 9th bit.
10.4.7
ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC
bit in the UiSMR4 register is se to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is
output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of
the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising
edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
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10.4.8
10. SERIAL I/O
Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O operates as
described below.
The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit shift
register. In this way, the serial I/O starts sending data synchronously with the next clock pulse applied.
However, the UARTi output value does not change state and remains the same as when a start condition was
detected until the first bit of data is output synchronously with the input clock.
The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the next clock
pulse applied.
The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the falling
edge of the ninth clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI does not change state. Note
also that when using this function, the selected transfer clock should be an external clock.
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10.5
10. SERIAL I/O
Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable.
Table 10.14 lists the specifications of Special Mode 2. Table 10.15 lists the registers used in Special Mode 2 and the
register values set. Figure 10.25 shows communication control example for Special Mode 2.
Table 10.14
Special Mode 2 Specifications
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• Master mode
Transmit/receive control
Transmission start condition
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16
• Slave mode
CKDIR bit = “1” (external clock selected) : Input from CLKi pin
Controlled by input/output ports
• Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
• Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
Reception start condition
_
The TE bit of UiC1 register= 1 (transmission enabled)
The TI bit of UiC1 register= 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_ The UiIRS bit of UiC1 register = 0 (transmit buffer empty): when transferring data
from the UiTB register to the UARTi transmit register (at start of transmission)
_ The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
_
Interrupt request
generation timing
Error detection
Select function
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock),
the external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low
state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does
not change.
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10. SERIAL I/O
P13
P12
P93
P72(CLK2)
P72(CLK2)
P71(RxD2)
P71(RxD2)
P70(TxD2)
P70(TxD2)
Microcomputer
(Master)
Microcomputer
(Slave)
P93
P72(CLK2)
P71(RxD2)
P70(TxD2)
Microcomputer
(Slave)
Figure 10.25
Serial Bus Communication Control Example (UART2)
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Table 10.15
10. SERIAL I/O
Registers to Be Used and Settings in Special Mode 2
Register
Bit
UiTB(Note3) 0 to 7
UiRB(Note3) 0 to 7
OER
UiBRG
0 to 7
UiMR(Note3) SMD2 to SMD0
CKDIR
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS (Note 1)
U2RRM(Note 1),
U2LCH, UiERE
UiSMR
0 to 7
UiSMR2
0 to 7
UiSMR3
CKPH
NODC
0, 2, 4 to 7
UiSMR4
0 to 7
UCON
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1, RCSP, 7
Function
Set transmission data
Reception data can be read
Overrun error flag
Set a transfer rate
Set to ‘0012’
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the UiBRG register
Invalid because CRD = 1
Transmit register empty flag
Set to “1”
Select TxDi pin output format(Note 2)
Clock phases can be set in combination with the UiSMR3 register's CKPH bit
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select UART2 transmit interrupt cause
Set to “0”
Set to “0”
Set to “0”
Clock phases can be set in combination with the UiC0 register's CKPOL bit
Set to “0”
Set to “0”
Set to “0”
Select UART0 and UART1 transmit interrupt cause
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Note 1: Set the U0C0 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
i = 0 to 2
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10.5.1
10. SERIAL I/O
Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the UiSMR3 register’s
CKPH bit and the UiC0 register’s CKPOL bit.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
• Master (Internal Clock)
Figure 10.26 shows the transmission and reception timing in master (internal clock).
• Slave (External Clock)
Figure 10.27 shows the transmission and reception timing (CKPH=0) in slave (external clock) while
Figure 10.28 shows the transmission and reception timing (CKPH=1) in slave (external clock).
"H"
Clock output
(CKPOL=0, CKPH=0) "L"
"H"
Clock output
(CKPOL=1, CKPH=0) "L"
Clock output
"H"
(CKPOL=0, CKPH=1) "L"
"H"
Clock output
(CKPOL=1, CKPH=1) "L"
Data output timing
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
Data input timing
Figure 10.26
Transmission and Reception Timing in Master Mode (Internal Clock)
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10. SERIAL I/O
"H"
Slave control input
"L"
"H"
Clock input
(CKPOL=0, CKPH=0) "L"
"H"
Clock input
(CKPOL=1, CKPH=0) "L"
Data output timing
"H"
(Note)
"L"
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Indeterminate
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 10.27
Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H"
Clock input
(CKPOL=0, CKPH=1) "L"
"H"
Clock input
(CKPOL=1, CKPH=1) "L"
Data output timing
(Note)
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
Data input timing
Note :UART2 output is an N-channel open drain and must be pulled-up externally.
Figure 10.28
Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)
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10.6
10. SERIAL I/O
Special Mode 3 (IE mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 10.16 lists the registers used in IE mode and the register values set. Figure 10.29 shows the functions of bus
collision detect function related bits.
If the TxDi pin (i = 0 to 2) output level and RxDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR2A register’s IFSR26 and IFSR27 bits to enable the UART0/UART1 bus collision detect function.
Table 10.16
Registers to Be Used and Settings in IE Mode
Register
Bit
UiTB
0 to 8
UiRB(Note3) 0 to 8
OER,FER,PER,SUM
UiBRG
0 to 7
UiMR
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
UiC0
CLK1, CLK0
CRS
TXEPT
CRD
NCH
CKPOL
UFORM
UiC1
TE
TI
RE
RI
U2IRS (Note 1)
UiRRM (Note 1),
UiLCH, UiERE
UiSMR
0 to 3, 7
ABSCS
ACSE
SSS
UiSMR2
0 to 7
UiSMR3
0 to 7
UiSMR4
0 to 7
IFSR2A
IFSR26, IFSR27
UCON
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1,RCSP,7
Function
Set transmission data
Reception data can be read
Error flag
Set a transfer rate
Set to ‘1102’
Select the internal clock or external clock
Set to “0”
Invalid because PRYE=0
Set to “0”
Select the TxD/RxD input/output polarity
Select the count source for the UiBRG register
Invalid because CRD=1
Transmit register empty flag
Set to “1”
Select TxDi pin output mode (Note 2)
Set to “0”
Set to “0”
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
Set to “0”
Select the sampling timing at which to detect a bus collision
Set this bit to “1” to use the auto clear function of transmit enable bit
Select the transmit start condition
Set to “0”
Set to “0”
Set to “0”
Set to “1”
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because CLKMD1 = 0
Set to “0”
Note 1: Set the U0C0 and U1C1 registers bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits
are in the UCON register.
Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.
Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in IEmode.
i= 0 to 2
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10. SERIAL I/O
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
(i=0 to 2)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
Input to TAjIN
Timer Aj
If ABSCS=1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TxDi
RxDi
UiBCNIC register
IR bit (Note)
If ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is cleared to “0”
(transmission disabled) when
the UiBCNIC register’s IR bit = 1
(unmatching detected).
UiC1 register
TE bit
Note: BCNIC register when UART2.
(3) UiSMR register SSS bit (Transmit start condition select )
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
D6
D7
D8
SP
TxDi
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi
CLKi
ST
TxDi
D0
D1
D2
D3
D4
D5
(Note 2)
RxDi
Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL =1.
Note 2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reversed).
Figure 10.29
Bus Collision Detect Function-Related Bits
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10.7
10. SERIAL I/O
Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented,
and this mode allows to output a low from the TxD2 pin when a parity error is detected.
Tables 10.17 lists the specifications of SIM mode. Table 10.18 lists the registers used in the SIM mode and the
register values set.
Table 10.17
SIM Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
(Note 2)
Error detection
Specification
• Direct format
• Inverse format
• U2MR register’s CKDIR bit = “0” (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register
0016 to FF16
• CKDIR bit = “1” (external clock) : fEXT/16(n+1)
fEXT: Input from CLK2 pin. n: Setting value of U2BRG register
0016 to FF16
• Before transmission can start, the following requirements must be met
_ The TE bit of U2C1 register= 1 (transmission enabled)
_ The TI bit of U2C1 register = 0 (data present in U2TB register)
• Before reception can start, the following requirements must be met
_ The RE bit of U2C1 register= 1 (reception enabled)
_ Start bit detection
• For transmission
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit =1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
• Overrun error (Note 1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
During reception, if a parity error is detected, parity error signal is output from the
TxD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
Note 1: If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit of S2RIC
register does not change.
Note 2: A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM
mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.
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Table 10.18
Registers to Be Used and Settings in SIM Mode
Register
Bit
U2TB(Note) 0 to 7
U2RB(Note) 0 to 7
OER,FER,PER,SUM
U2BRG
0 to 7
U2MR
SMD2 to SMD0
CKDIR
STPS
PRY
PRYE
IOPOL
Function
Set transmission data
Reception data can be read
Error flag
Set a transfer rate
Set to ‘1012’
Select the internal clock or external clock
Set to “0”
Set this bit to “1” for direct format or “0” for inverse format
Set to “1”
Set to “0”
U2C0
Select the count source for the U2BRG register
U2C1
10. SERIAL I/O
CLK1, CLK0
CRS
Invalid because CRD=1
TXEPT
Transmit register empty flag
CRD
Set to “1”
NCH
Set to “0”
CKPOL
Set to “0”
UFORM
Set this bit to “0” for direct format or “1” for inverse format
TE
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS
Set to “1”
U2RRM
Set to “0”
U2LCH
Set this bit to “0” for direct format or “1” for inverse format
U2ERE
Set to “1”
U2SMR(Note) 0 to 3
Set to “0”
U2SMR2
0 to 7
Set to “0”
U2SMR3
0 to 7
Set to “0”
U2SMR4
0 to 7
Set to “0”
Note: Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.
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(1) Transmission
10. SERIAL I/O
Tc
Transfer clock
U2C1 register “1”
TE bit “0”
Write data to U2TB register
U2C1 register “1”
TI bit
“0”
Transferred from U2TB register to UART2 transmit register
Parity Stop
bit
bit
Start
bit
TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
Parity error signal sent
back from receiver
P
SP
An “L” level returns due to the
occurrence of a parity error.
RxD2 pin level
(Note)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P
SP
The level is detected by the
interrupt routine.
U2C0 register “1”
The level is
detected by the
interrupt routine.
TXEPT bit “0”
The IR bit is set to “1” at the
falling edge of transfer clock
S2TIC register “1”
IR bit
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where data is transferred in
the direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the TxD2 output and the parity error signal
sent back from receiver.
(1) Reception
Tc
Transfer clock
U2C1 register “1”
RE bit
“0”
ParityStop
bit bit
Start
bit
Transmitter's
transmit waveform
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P
SP
TxD2
An “L” level is output from TxD2 due to
the occurrence of a parity error
RxD2 pin level
(Note)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
ST D0 D1 D2 D3 D4 D5 D6 D7
SP
P
SP
U2C0 register “1”
RI bit
“0”
Read the U2RB register
S2RIC register “1”
IR bit
Read the U2RB register
“0”
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
The above timing diagram applies to the case where data is received in
direct format.
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of U2BRG count source (external clock)
n : value set to U2BRG
Note : Because TxD2 and RxD2 are connected, this is composite waveform consisting of the transmitter's transmit waveform and the
parity error signal received.
Figure 10.30
Transmit and Receive Timing in SIM Mode
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
Figure 10.31 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Microcomputer
SIM card
TxD2
RxD2
Figure 10.31
10.7.1
SIM Interface Connection
Parity Error Signal Output
The parity error signal is enabled by setting the U2C1 register’s U2ERE bit to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved by
pulling the TxD2 output low with the timing shown in Figure 10.32. If the U2RB register is read while
outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output is
returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse that
immediately follows the stop bit. Therefore, whether a parity signal has been returned can be determined by
reading the port that shares the RxD2 pin in a transmission-finished interrupt service routine.
Transfer
clock
“H”
RxD2
“H”
TxD2
“H”
“L”
ST
D0
D1
D2
D3
D4
D5
D6
“L”
Note: The output of microcomputer is in the high-impedance state
(pulled up externally).
Parity Error Signal Output Timing
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
P
SP
(Note)
U2C1 register “1”
RI bit “0”
This timing diagram applies to the case where the direct format is
implemented.
Figure 10.32
D7
“L”
Page 136 of 326
ST : Start bit
P : Even Parity
SP : Stop bit
M306H7MG-XXXFP/MC-XXXFP/FGFP
10.7.2
10. SERIAL I/O
Format
• Direct Format
Set the U2MR register's PRY bit to “1”, U2C0 register's UFORM bit to “0” and U2C1 register's U2LCH bit
to “0”.
• Inverse Format
Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”. Figure 10.33 shows the SIM interface
format.
(1) Direct format
Transfer
clock
“H”
TxD2
“H”
“L”
“L”
D0
D1
D2
D3
D4
D5
D6
D7
P
P : Even parity
(2) Inverse format
Transfer
clock
TxD2
“H”
“L”
“H”
“L”
D7
D6
D5
D4
D3
D2
D1
D0
P
P : Odd parity
Figure 10.33
SIM Interface Format
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10.8
10. SERIAL I/O
SI/O3 and SI/O4
SI/O3 and SI/O4 are exclusive clock-synchronous serial I/Os.
Figure 10.34 shows the block diagram of SI/O3 and SI/O4, and Figure 10.35 shows the SI/O3 and SI/O4- related
registers.
Table 10.19 shows the specifications of SI/O3 and SI/O4.
1/2
Main clock
f2SIO
Clock source select
SMi1 to SMi0
002
PCLK1=0
f1SIO
1/8
PCLK1=1
1/4
f8SIO
012
f32SIO
102
Synchronous
circuit
SMi4
CLKi
CLK
polarity
reversing
circuit
Data bus
1/(n+1)
1/2
SiBRG register
SMi3
SMi6
SMi6
SI/O counter i
SMi2
SMi3
SMi5 LSB
SOUTi
MSB
SiTRR register
SINi
8
Note: i = 3, 4.
n = A value set in the SiBRG register.
Figure 10.34
SI/O3 and SI/O4 Block Diagram
Rev.2.10
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REJ03B0152-0210
Page 138 of 326
SI/Oi
interrupt request
M306H7MG-XXXFP/MC-XXXFP/FGFP
10. SERIAL I/O
S I/Oi control register (i = 3, 4) (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3C
S4C
Bit
symbol
SMi0
Address
036216
036616
After reset
010000016
010000016
Description
Bit name
Internal synchronous
clock select bit
SMi1
b1 b0
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Must not be set.
RW
RW
RW
SMi2
SOUTi output disable bit
(Note 4)
0 : SOUTi output
1 : SOUTi output disable(high impedance)
RW
SMi3
S I/Oi port select bit
0 : Input/output port
1 : SOUTi output, CLKi function
RW
SMi4
CLK polarity select bit
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
RW
SMi5
Transfer direction select
bit
0 : LSB first
1 : MSB first
RW
SMi6
Synchronous clock
select bit
0 : External clock (Note 2)
1 : Internal clock (Note 3)
RW
SMi7
SOUTi initial value
set bit
Effective when SMi3 = 0
0 : “L” output
1 : “H” output
RW
Note 1: Make sure this register is written to by the next instruction after setting the PRCR register's PRC2 bit to “1”
(write enable).
Note 2: Set the SMi3 bit to “1” and the corresponding port direction bit to “0” (input mode).
Note 3: Set the SMi3 bit to “1” (SOUTi output, CLKi function).
Note 4: When the SMi2 bit is set to “1”, the target pin goes to a high-impedance state regardless of which function of the
pin is being used.
SI/Oi bit rate generator (i = 3, 4) (Notes 1, 2)
b7
Symbol
S3BRG
S4BRG
b0
Address
036316
036716
After reset
Indeterminate
Indeterminate
Description
Setting range
RW
0016 to FF16
WO
Assuming that set value = n, BRGi divides the count
source by n + 1
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: Use MOV instruction to write to this register.
SI/Oi transmit/receive register (i = 3, 4) (Note 1, 2)
b7
b0
Symbol
S3TRR
S4TRR
Address
036016
036416
After reset
Indeterminate
Indeterminate
Description
RW
Transmission/reception starts by writing transmit data to this register. After
transmission/reception finishes, reception data can be read by reading this register.
RW
Note 1: Write to this register while serial I/O is neither transmitting nor receiving.
Note 2: To receive data, set the corresponding port direction bit for SINi to “0” (input mode).
Figure 10.35
S3C and S4C Registers, S3BRG and S4BRG Registers, and S3TRR and S4TRR
Registers
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 10.19
10. SERIAL I/O
SI/O3 and SI/O4 Specifications
Item
Specification
Transfer data format
• Transfer data length: 8 bits
Transfer clock
• SiC (i=3, 4) register’s SMi6 bit = “1” (internal clock) : fj/ 2(n+1)
0016 to FF16.
fj = f1SIO, f8SIO, f32SIO. n=Setting value of SiBRG register
• SMi6 bit = “0” (external clock) : Input from CLKi pin (Note 1)
Transmission/reception
start condition
• Before transmission/reception can start, the following requirements must be met
Write transmit data to the SiTRR register (Notes 2, 3)
Interrupt request
• When SiC register's SMi4 bit = 0
The rising edge of the last transfer clock pulse (Note 4)
generation timing
• When SMi4 = 1
The falling edge of the last transfer clock pulse (Note 4)
CLKi pin function
SOUTi pin function
SINi pin function
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
Select function
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Function for setting an SOUTi initial value set function
When the SiC register's SMi6 bit = 0 (external clock), the SOUTi pin output level while
not transmitting can be selected
.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge of
transfer clock can be selected.
Note 1: To set the SiC register’s SMi6 bit to “0” (external clock), follow the procedure described below.
• If the SiC register’s SMi4 bit = 0, write transmit data to the SiTRR register while input on the CLKi pin is
high. The same applies when rewriting the SiC register’s SMi7 bit.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The same
applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop the
transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock automatically
stops.
Note 2: Unlike UART0 to UART2, SI/Oi (i = 3 to 4) is not separated between the transfer register and buffer. Therefore, do not write the next transmit data to the SiTRR register during transmission.
Note 3: When the SiC register’s SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period
after completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state, with the
data hold time thereby reduced.
Note 4: When the SiC register’s SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit
= 0, or stops in the low state if the SMi4 bit = 1.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10.8.1
10. SERIAL I/O
SI/Oi Operation Timing
Figure 10.36 shows the SI/Oi operation timing
1.5 cycle (max) (Note 3)
SI/Oi internal clock
"H"
"L"
CLKi output
"H"
"L"
Signal written to the
SiTRR register
"H"
"L"
(Note 2)
SOUTi output
"H"
"L"
SINi input
"H"
"L"
SiIC register
IR bit
"1"
"0"
D0
D1
D2
D3
D4
D5
D6
D7
i= 3, 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi3=1 (SOUTi output, CLKi function), SMi4=0 (transmit data output at the falling edge and receive data input at the
rising edge of the transfer clock), SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Note 3: If the SMi6 bit=0 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
Figure 10.36
10.8.2
SI/Oi Operation Timing
CLK Polarity Selection
The SiC register's SMi4 bit allows selection of the polarity of the transfer clock. Figure 10.37 shows the polarity
of the transfer clock.
(1) When SiC register's SMi4 bit = “0”
(Note 2)
CLKi
SINi
D0
D1
D2
D3
D4
D5
D6
D7
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When SiC register's SMi4 bit = “1”
(Note 3)
CLKi
SINi
D0
D1
D2
D3
D4
D5
D6
D7
SOUTi
D0
D1
D2
D3
D4
D5
D6
D7
i=3 and 4
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi5=0 (LSB first) and SMi6=1 (internal clock)
Note 2: When the SMi6 bit=1 (internal clock), a high level is output from the CLKi
pin if not transferring data.
Note 3: When the SMi6 bit=1 (internal clock), a low level is output from the CLKi
pin if not transferring data.
Figure 10.37
Polarity of Transfer Clock
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M306H7MG-XXXFP/MC-XXXFP/FGFP
10.8.3
10. SERIAL I/O
Functions for Setting an SOUTi Initial Value
If the SiC register’s SMi6 bit = 0 (external clock), the SOUTi pin output can be fixed high or low when not
transferring. Figure 10.38 shows the timing chart for setting an SOUTi initial value and how to set it.
(Example) When “H” selected for SOUTi initial value (Note 1)
Setting of the initial value of SOUTi
output and starting of transmission/
reception
Signal written to
SiTRR register
Set the SMi3 bit to “0”
(SOUTi pin functions as an I/O port)
SMi7 bit
Set the SMi7 bit to “1”
(SOUTi initial value = “H”)
SMi3 bit
D0
SOUTi (internal)
Set the SMi3 bit to “1”
(SOUTi pin functions as SOUTi output)
D0
Port output
SOUTi pin output
Initial value = “H” (Note 3)
(i = 3, 4)
Setting the SOUTi
initial value to “H”
(Note 2)
Port selection switching
(I/O port
SOUTi)
Note 1: This diagram applies to the case where the SiC register bits are set as follows:
SMi2=0 (SOUTi output), SMi5=0 (LSB first) and SMi6=0 (external clock)
Note 2: SOUTi can only be initialized when input on the CLKi pin is in the high state if the SiC
register’s SMi4 bit = 0 (transmit data output at the falling edge of the transfer clock) or
in the low state if the SMi4 bit = 1 (transmit data output at the rising edge of the
transfer clock).
Note 3: If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUT output disabled),
this output goes to the high-impedance state.
Figure 10.38
SOUTi’s Initial Value Setting
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REJ03B0152-0210
Page 142 of 326
“H” level is output
from the SOUTi pin
Write to the SiTRR register
Serial transmit/reception starts
M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I2C BUS INTERFACE
11. Multi-master I2C-BUS Interface
The multi-master I2C-BUS interface have each dedicated circuit and operate independently.
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data
transfer format. This interface i, offering both arbitration lost detection and a synchronous functions, is useful for the
multi-master serial communications.
Table 11.1 shows multi-master I2C-BUS interface functions.
This multi-master I2C-BUS interface consists of I2C address register, I2C data shift register, I2C clock control register,
I2C control register, I2C status register, I2C transmit buffer register and the other control circuits.
Table 11.1
Clock Generation Circuit Specifications
Item
Function
Format
In conformity with Philips I2C-BUS standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
Communication mode
In conformity with Philips I2C-BUS standard:
Master transmission
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (BCLK = 16 MHz)
Power supply voltage on bus line
(SCL3/SDA3) : VCC1
Note. Our company doesn't assume the responsibility of the patent of the third party who originates in the use of the
function to control the connection of I 2 C-BUS interface and ports (SCL3, SDA3) and other infringements of right.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 143 of 326
Figure 11.1
Block Diagram of Multi-master I2C-BUS interface
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 144 of 326
SCL3
SDA3
Serial
clock
(SCL)
Serial
data
(SDA)
Noise
elimination
circuit
Noise
elimination
circuit
b0
Clock
control
circuit
circuit
BB
II2C clock control register
(IICiS2)
Clock division
b0
ACK FAST
CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
b7
ACK
BCLK
10BIT
ALS
SAD
I2C control register
(IICS1D)
b7
Internal data bus
MST TRX BB PIN
b7
AL AAS AD0 LRB
b0
Bit counter
ESO BC2 B C1 BC0
b0
I2C statusregister
b0
(IICS1)
I2C data shift register (IICS0)
Interrupt request signal
(IICiRQ)
AL
b7
Address comparator
Interrupt
generating
circuit
circuit
Data
control
circuit
I2C address register (IICiS0D)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 R BW
b7
M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I2C BUS INTERFACE
11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
(1)
Reserved register
Reserved register
Symbol
RSVREG02E5
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 0
Address
02E516
0 0
Bit Symbol
Bit name
Reserved bits
Multi-master I2C-BUS
RSVREG02E52 interface enable bit
Reserved bits
Figure 11.2
Reserved register
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
When reset
00?000002
Page 145 of 326
Function
RW
Must always be set to “0”
WO
0 = Non active
1 = Active
RW
Must always be set to “0”
WO
M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I2C BUS INTERFACE
(2) I2C data shift register, I2C transmit buffer register
The I2C data shift register is an 8-bit shift register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with
the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When
data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit
data is input, the data of this register are shifted one bit to the left.
The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register is “1.” The
bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of
the I2C status register are “1,” the SCL is output by a write instruction to the I2C data shift register. Reading data
from the I2C data shift register is always enabled regardless of the ESO bit value.
The I2C transmit buffer register is a register to store transmit data (slave address) to the I2C data shift register
before RESTART condition generation. That is, in master, transmit data written to the I2C transmit buffer register
is written to the I2C data shift register simultaneously. However, the SCL is not output. The I2C transmit buffer
register can be written only when the ESO bit is “1,” reading data from the I2C transmit buffer register is disabled
regardless of the ESO bit value.
Notes 1: To write data into the I2C data shift register or the I2C transmit buffer register after the MST bit value
changes from “1” to “0” (slave mode), keep an interval of 20 BCLK or more.
2: To generate START/RESTART condition after the I2C data shift register or the I2C transmit buffer
register is written, keep an interval of 4 BCLK or more.
Rev.2.10
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11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
I2C data shift register
Symbol
IIC0S0
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
D0
Address
02E016
Bit name
Data shift register
D1
When reset
Indeterminate
Function
This is an 8-bit shift register to store
receive data and write transmit data.
RW
RW
D2
D3
D4
D5
D6
D7
Note: To write data into the I2C data shift register after setting the MST bit to “0” (slave
mode), keep an interval of 8 machine cycles or more.
Figure 11.3
I2C data shift register
I2C transmit buffer register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IIC0S0S
Bit Symbol
Bit name
S0S0
Transmit buffer register
S0S1
S0S2
S0S3
S0S4
S0S5
S0S6
S0S7
Figure 11.4
I2C transmit buffer register
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Address
02E616
Page 147 of 326
When reset
Indeterminate
Function
This is an 8-bit register to write transmit
data to I2C data shift register.
RW
WO
11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
(3) I2C address register
The I2C address register consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave
address written in this register is compared with the address data to be received immediately after the START
condition are detected.
• Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address
data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
• Bits 1 to 7: slave address (SAD0 to SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the
address data transmitted from the master is compared with the contents of these bits.
I2C address register
Symbol
IIC0S0D
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
Bit name
Function
Read/write bit
<Only in 10-bit addressing (in slave) mode>
The last significant bit of address data is
compared.
0 : Wait the first byte of slave address
after START condition
(read state)
1 : Wait the first byte of slave address
after RESTART condition
(write state)
SAD0
Slave address
<In both modes>
The address data is compared.
SAD2
SAD3
SAD4
SAD5
SAD6
I2C address register
Rev.2.10
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REJ03B0152-0210
When reset
0016
RBW
SAD1
Figure 11.5
Address
02E116
Page 148 of 326
RW
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I2C BUS INTERFACE
(4) I2C clock control register
The I2C clock control register is used to set ACK control, SCL mode and SCL frequency.
• Bits 0 to 4: SCL frequency control bits (CCR0−CCR4)
These bits control the SCL frequency.
• Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the standard clock mode is set. When the bit is set to
“1,” the high-speed clock mode is set.
• Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock∗ is generated. When this bit is set to “0,” the ACK return mode
is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to “1,” the ACK non-return
mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock.
However, when the slave address matches the address data in the reception of address data at ACK BIT = “0,” the
SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the
address data, the SDA is automatically made HIGH (ACK is not returned).
∗ACK clock: Clock for acknowledgement
• Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission.
When this bit is set to “0,” the no ACK clock mode is set. In this case, no ACK clock occurs after data
transmission. When the bit is set to “1,” the ACK clock mode is set and the master generates an ACK clock upon
completion of each 1-byte data transmission.The device for transmitting address data and control data releases the
SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data
receiving device.
Note: Do not write data into the I2C clock control register during transmission. If data is written during
transmission, the I2C clock generator is reset, so that data cannot be transmitted normally.
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11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
I2C clock control register
Symbol
IIC0S2
b7 b6 b5 b4 b3 b2 b1 b0
When reset
0016
Bit name
Bit Symbol
CCR0
Address
02E416
SCL frequency control
bits
Function
Setup value of
CCR4–CCR0
00 to 02
CCR1
CCR2
RW
Setup disabled Setup disabled
Setup disabled
04
Setup disabled
250
05
100
400 (See note)
83.3
166
:
CCR4
RW
High speed
clock mode
03
06
CCR3
Standard
clock mode
333
500/CCR value 1000/CCR value
1D
17.2
34.5
1E
16.6
33.3
1F
16.1
32.3
(at BCLK = 10 MHz, unit : kHz)
FAST MODE
ACK BIT
ACK
SCL mode specification 0 : Standard clock mode
bit
1 : High-speed clock mode
RW
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
RW
ACK clock bit
0 : No ACK clock
1 : ACK clock
RW
Note: At 400 kHz in the high-speed clock mode, the duty is as below.
“0” period : “1” period = 3 : 2
In the other cases, the duty is as below.
“0” period : “1” period = 1 : 1
Figure 11.6
I2C clock control register
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11. MULTI-MASTER I2C BUS INTERFACE
(5) I2C control register
The I2C control register controls the data communication format.
• Bits 0 to 2: bit counter (BC0−BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs
immediately after the number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and the address data is always transmitted and
received in 8 bits.
Note: When the bit counter value = “1112,” a STOP condition and START condition cannot be waited.
• Bit 3: I2C-BUS interface use enable bit (ESO)
This bit enables usage of the multimaster I2C-BUS interface i. When this bit is set to “0,” the use disable status is
provided, so the SDA and the SCL become high-impedance. When the bit is set to “1,” use of the interface is
enabled.
When ESO = “0,” the following is performed.
• PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I2C status register).
• Writing data to the I2C data shift register and the I2C transmit buffer register is disabled.
• Bit 4: data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When this bit is set to “0,” the addressing format is
selected, so that address data is recognized. When a match is found between a slave address and address data as a
result of comparison or when a general call (refer to “(6) I2C status register,” bit 1) is received, transmission
processing can be performed. When this bit is set to “1,” the free data format is selected, so that slave addresses
are not recognized.
• Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is set to “0,” the 7-bit addressing format is
selected. In this case, only the high-order 7 bits (slave address) of the I2C address register are compared with
address data. When this bit is set to “1,” the 10-bit addressing format is selected, all the bits of the I2C address
register are compared with address data.
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11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
I2C control register
Symbol
IIC0S1D
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
BC0
Address
02E316
When reset
0016
Bit name
Function
b2 b1 b0
ESO
I2C-BUS interface use
enable bit
0 : Disabled
1 : Enabled
RW
ALS
Data format selection
bit
0 : Addressing format
1 : Free data format
RW
BC1
BC2
10BIT SAD
0
0
0
0
1
1
1
1
I2C control register
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0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
:8
:7
:6
:5
:4
:3
:2
:1
Address format selection 0 : 7-bit addressing format
bit
1 : 10-bit addressing format
Nothing is assigned.
In an attempt to write to these bits, write “0.”
The value, if read, turns out to be “0.”
Figure 11.7
RW
Bit counter
(Number of
transmit/receive bits)
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
11. MULTI-MASTER I2C BUS INTERFACE
(6) I2C status register
The I2C status register controls the I2C-BUS interface status. Bits 0 to 3, 5 are read-only bits and bits 4, 6, 7 can be
read out and written to.
• Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is
returned when an ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit is set to “1.” Except
in the ACK mode, the last bit value of received data is input. The state of this bit is changed from “1” to “0” by
executing a write instruction to the I2C data shift register or the I2C transmit buffer register.
• Bit 1: general call detecting flag (AD0)
This bit is set to “1” when a general call∗ whose address data is all “0” is received in the slave mode.
By a general call of the master device, every slave device receives control data after the general call.
The AD0 bit is set to ì0î by detecting the STOP condition or START condition.
∗General call: The master transmits the general call address “0016”to all slaves.
• Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
<<In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to “1” in one of the following
conditions.>>
• The address data immediately after occurrence of a START condition matches the slave address stored in the
high-order 7 bits of the I2C address register.
• A general call is received.
<<In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to “1” with the following
condition.>>
• When the address data is compared with the I2C address register (8 bits consists of slave address and RBW),
the first bytes match.
<<The state of this bit is changed from “1” to “0” by executing a write instruction to the I2C data shift register or
the I2C transmit buffer register.>>
• Bit 3: arbitration lost∗ detecting flag (AL)
In the master transmission mode, when a device other than the microcomputer sets the SDA to “L,” arbitration is
judged to have been lost, so that this bit is set to “1.” At the same time, the TRX bit is set to “0,” so that
immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to “0.”
When arbitration is lost during slave address transmission, the TRX bit is set to “0” and the reception mode is set.
Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master
device.
<<This bit changes “1” to “0” by writing instruction to I2C data shift register or I2C transmit buffer
register.>>
∗Arbitration lost: The status in which communication as a master is disabled.
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11. MULTI-MASTER I2C BUS INTERFACE
• Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes
from “1” to “0.” At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to “0” in
synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an
interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When detecting the STOP
condition in slave, the multi-master I2C-BUS interface interrupt request bit (IR) is set to “1” (interrupt requested)
regardless of falling of PIN bit. When the PIN bit is “0,” the SCL is kept in the “0” state and clock generation is
disabled. Figure 11.9 shows an interrupt request signal generating timing chart.
The PIN bit is set to “1” in any one of the following conditions.
• Writing “1” to the PIN bit
• Executing a write instruction to the I2C data shift register or the I2C transmit buffer register (See note).
• When the ESO bit is “0”
• At reset
Note: It takes 12 BCLK cycles or more until PIN bit becomes “1” after write instructions are executed to these
registers.
The conditions in which the PIN bit is set to “0” are shown below:
• Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
• Immediately after completion of 1-byte data reception
• In the slave reception mode, with ALS = “0” and immediately after completion of slave address or general call
address reception
• In the slave reception mode, with ALS = “1” and immediately after completion of address data reception
• Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to “0,” this bus system is not busy and a
START condition can be generated. When this bit is set to “1,” this bus system is busy and the occurrence of a
START condition is disabled by the START condition duplication prevention function (See note).
This flag cannot be written with software. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the ESO bit of the I2C control register is “0” and at
reset, the BB flag is kept in the “0” state.
• Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is “0,” the reception mode is
selected and the data of a transmitting device is received. When the bit is “1,” the transmission mode is selected
and address data and control data are output into the SDA in synchronization with the clock generated on the
SCL.
When the ALS bit of the I2C control register is “0” in the slave reception mode is selected, the TRX bit is set to
“1” (transmit) if the least significant bit (R/W bit) of the address data transmitted by the master is “1.” When the
ALS bit is “0” and the R/W bit is “0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
• When arbitration lost is detected.
• When a STOP condition is detected.
• When occurrence of a START condition is disabled by the START condition duplication prevention function
(Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
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11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
• Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is “0,” the slave is specified,
so that a START condition and a STOP condition generated by the master are received, and data communication
is performed in synchronization with the clock generated by the master.
When this bit is “1,” the master is specified and a START condition and a STOP condition are generated, and also
the clocks required for data communication are generated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START condition duplication preventing function
(See note).
• At reset
Note: The START condition duplication prevention function disables the following: the START condition
generation; bit counter reset, and SCL output with the generation. This bit is valid from setting of BB flag
to the completion of 1-byte transmission/reception (occurrence of transmission/ reception interrupt
request) <IICRQ>.
I2C status register
Symbol
IIC0S1
b7 b6 b5 b4 b3 b2 b1 b0
Bit Symbol
LRB
Address
02E216
When reset
0001000?2
Bit name
Last receive bit
Function
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting
flag
AAS
Slave address comparison 0 : Address mismatch
flag
1 : Address match
(See note 1)
Arbitration lost detecting 0 : Not detected
flag
1 : Detected
(See note 1)
0 : No general call detected
1 : General call detected (See note 1)
RO
RO
I2C-BUS interface
interrupt request bit
0 : Interrupt request issued
RW
1 : No interrupt request issued (See note 2)
BB
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
MST
b7b6
0
0
1
1
0 : Slave receive mode
1 : Slave transmit mode
0 : Master receive mode
1 : Master transmit mode
Notes 1: These bits and flags can be read out, but cannot be written.
2: This bit can be written only “1.”
I2C status register
SCL
PIN
IICIRQ
Interrupt request signal generation timing
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RO
PIN
TRX
Figure 11.9
RO
(See note 1)
AD0
AL
Figure 11.8
RW
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(See note 1)
RO
RW
11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
(7) START condition generation method
When the ESO bit of the I2C control register is “1,” execute a write instruction to the I2C status register to set the
MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes
“0002” and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are
different in the standard clock mode and the high-speed clock mode. Refer to Figure 11.10 for the START
condition generation timing diagram, and Table 11.2 for the START condition/STOP condition generation timing
table.
I2Ci status register write signal
SCL
Setup
time
Hold time
SDA
Set time
for BB flag
BB flag
Figure 11.10
START condition generation timing diagram
(8) STOP condition generation method
When the ESO bit of the I2C control register is “1,” execute a write instruction to the I2C status register for setting
the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP condition will then be generated. The STOP
condition generation timing and the BB flag reset timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 11.11 for the STOP condition generation timing diagram, and Table 11.2 for
the START condition/STOP condition generation timing table.
I2Ci status register write signal
SCL
SDA
Setup
time
BB flag
Figure 11.11
Hold time
Reset time
for
BB flag
STOP condition generation timing diagram
Table 11.2
START condition/STOP condition generation timing table
Item
Standard Clock Mode
High-speed Clock Mode
Setup time (Min.)
5.6 µs
2.1 µs
Hold time (Min.)
4.8 µs
2.3 µs
Set/reset time for BB flag
3.5 µs
0.75 µs
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11. MULTI-MASTER I2C BUS INTERFACE
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(9) START/STOP condition detect conditions
The START/STOP condition detect conditions are shown in Figure 11.12 and Table 11.3.
Only when the 3 conditions of Table 11.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal <IICRQ> is
generated to the CPU.
SCL release time
SCL
SDA
Setup
time
Hold
time
Setup
time
Hold
time
(START condition)
SDA
(STOP condition)
Figure 11.12
Table 11.3
START condition/STOP condition detect timing diagram
START condition/STOP condition detect conditions
Standard Clock Mode
6.5 µs < SCL release time
High-speed Clock Mode
1.0 µs < SCL release time
3.25 µs < Setup time
0.5 µs < Setup time
3.25 µs < Hold time
0.5 µs < Hold time
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11. MULTI-MASTER I2C BUS INTERFACE
(10) Address data communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing
format. The respective address communication formats is described below.
• 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register to “0.” The first 7-bit
address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C
address register. At the time of this comparison, address comparison of the RBW bit of the I2C address register is
not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 11.13 (1)
and (2).
• 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register to “1.” An address
comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address
stored in the I2C address register. At the time of this comparison, an address comparison between the RBW bit of
the I2C address register and the R/W bit which is the last bit of the address data transmitted from the master is
made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the
direction of communication for control data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the AAS bit of the I2C status register is set to “1.”
After the second-byte address data is stored into the I2C data shift register, make an address comparison between
the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave
address, set the RBW bit of the I2C address register to “1” by software. This processing can match the 7-bit slave
address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C
address register. For the data transmission format when the 10-bit addressing format is selected, refer to Figure
11.13, (3) and (4).
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11. MULTI-MASTER I2C BUS INTERFACE
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK
return mode is shown below.
(1) Set a slave address in the high-order 7 bits of the I2C address register and “0” in the RBW bit.
(2) Set the ACK return mode and SCL = 100 kHz by setting “8516” in the I2C clock control register.
(3) Set “1016” in the I2C status register and hold the SCL at the HIGH.
(4) Set a communication enable status by setting “0816” in the I2C control register.
(5) Set the address data of the destination of transmission in the high-order 7 bits of the I2C data shift register and
set “0” in the least significant bit.
(6) Set “F016” in the I2C status register to generate a START condition. At this time, an SCL for 1 byte and an
ACK clock automatically occurs.
(7) Set transmit data in the I2C data shift register. At this time, an SCL and an ACK clock automatically occurs.
(8) When transmitting control data of more than 1 byte, repeat step (7).
(9) Set “D016” in the I2C status register. After this, if ACK is not returned or transmission ends, a STOP condition
will be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK nonreturn mode, using the addressing format, is shown below.
(1) Set a slave address in the high-order 7 bits of the I2C address register and “0” in the RBW bit.
(2) Set the no ACK clock mode and SCL = 400 kHz by setting “2516” in the I2C clock control register.
(3) Set “1016” in the I2C status register and hold the SCL at the HIGH.
(4) Set a communication enable status by setting “0816” in the I2C control register.
(5) When a START condition is received, an address comparison is made.
(6)
•When all transmitted address are“0” (general call):
AD0 of the I2C status register is set to “1”and an interrupt request signal occurs.
•When the transmitted addresses match the address set in (1):
ASS of the I2C status register is set to “1” and an interrupt request signal occurs.
•In the cases other than the above:
AD0 and AAS of the I2C status register are set to “0” and no interrupt request signal occurs.
(7) Set dummy data in the I2C data shift register.
(8) When receiving control data of more than 1 byte, repeat step (7).
(9) When a STOP condition is detected, the communication ends.
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11. MULTI-MASTER I2C BUS INTERFACE
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S
Slave address
7 bits
R/W
A
Data
A
Data
A/A
P
A
P
1 to 8 bits
1 to 8 bits
"0"
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address
R/W
7 bits
"1"
A
Data
A
1 to 8 bits
Data
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
7 bits
R/W
A
"0"
Slave address
2nd byte
A
A
Data
1 to 8 bits
8 bits
A/A
Data
P
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
7 bits
R/W
"0"
A
Slave address
2nd byte
8 bits
A
Sr
Slave address
1st 7 bits
7 bits
R/W
A
"1"
Data
1 to 8 bits
A
Data
A
P
1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
Figure 11.13
P : STOP condition
R/W :Read/Write bit
From master to slave
From slave to master
Address data communication format
(13) Precautions when using multi-master I2C-BUS interface
• BCLK operation mode
Select the no-division mode.
• Used instructions
Specify byte (.B) as data size to access multi-master I2C-BUS interface i-related registers.
• Read-modify-write instruction
The precautions when the read-modify-write instruction such as BSET, BCLR etc. is executed for each register of
the multi-master I2C-BUS interface are described below.
• I2C data shift register (IICS0)
When executing the read-modify-write instruction for this register during transfer, data may become a value
not intended.
• I2C address register (IICS0D)
When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may
become a value not intended. It is because hardware changes the read/write bit (RBW) at the above timing.
• I2C status register (IICS1)
Do not execute the read-modify-write instruction for this register because all bits of this register are changed
by hardware.
• I2C control register (IICS1D)
When the read-modify-write instruction is executed for this register at detecting the START condition or at
completing the byte transfer, data may become a value not intended. Because hardware changes the bit
counter (BC0−BC2) at the above timing.
• I2C clock control register (IICS2)
The read-modify-write instruction can be executed for this register.
• I2C port selection register (IICS2D)
Since the read value of high-order 4 bits is indeterminate, the read-modify-write instruction cannot be used.
• I2C transmit buffer register (IICS0S)
Since the value of all bits is indeterminate, the read-modify-write instruction cannot be used.
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11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
• START condition generating procedure using multi-master
FCLR
BTST
JC
BUSFREE:
MOV.B
NOP
NOP
NOP
NOP
MOV.B
FSET
BUSBUSY:
FSET
:
I
5, IICS1
BUSBUSY
(Interrupt disabled)
(BB flag confirming and branch process)
SA, IICS0
(Writing of slave address value <SA>)
(1)
#F0H, IICS1
I
:
(Trigger of START condition generating)
(Interrupt enabled)
I
:
(Interrupt enabled)
(2)
(1) Be sure to add NOP instruction × 4 between writing the slave address value and setting trigger of START
condition generating shown the above procedure example.
(2) When using multi-master system, disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts immediately.
When using single-master system, it is not necessary to disable interrupts above.
• RESTART condition generating procedure
MOV.B
NOP
NOP
MOV.B
:
SA, IICS0S
#F0H, IICS1
:
(Writing of slave address value <SA>)
(1)
(Trigger of RESTART condition generating)
(1) Use the I2C transmit buffer register to write the slave address value to the I2C data shift register.
And also, be sure to add NOP instruction × 4.
• Writing to I2C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and TRX bits to
“0” from “1” simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is
released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to “0” from
“1” simultaneously when the PIN bit is “1.” It is because it may become the same as above.
• Process of after STOP condition generating
Do not write data in the I2C data shift register (IICS0) and the I2C status register (IICS1) until the bus busy flag
BB becomes “0” after generating the STOP condition in the master mode. It is because the STOP condition
waveform might not be normally generated. Reading to the above registers do not have the problem.
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11. MULTI-MASTER I2C BUS INTERFACE
M306H7MG-XXXFP/MC-XXXFP/FGFP
I2C0 Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol
EXTIICINT
0 0
Address
02D616
Bit symbol
Reserved bits
EXTIICINT0
At reset
0016
Bit name
Function
R W
Must set to "0."
ACK interrupt control bit
(Note 1)
EXTIICINT1
0000: Interrupt prohibition (Note 2)
0101: Interrupt permission
Other: Must not be set
Please set TA4IC (Note 3) when
you use it by "Interrupt permission".
EXTIICINT2
EXTIICINT3
Notes 1: Timer A4 and multi master I2C (ACK) interrupt, the vector and the interrupt control register
are shared. Please make it to (b7, b6, b5, b4) = (0, 1, 0, 1) when you use multi-master I2C
(ACK) interrupt.
Notes 2: Please set 00002 when you use the interrupt of timer A4.
Notes 3: Please refer to "Figure 6.3 interrupt control register" of "6.5 interrupt control".
Notes 4: Please change in the part where multi-master I2C (ACK) and timer A4 interrupt request are
not generated in the I2C0 interrupt control register.
Notes 5: Please permit interrupt after making IR bit of timer A4 (TA4IC) "0" (the interrupt request none)
after EXTIICINTi (i = 0 to 3) is changed.
Reserved Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0 0
0
0
Symbol
RSVREG02D7
Address
02D716
Bit symbol
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Bit name
At reset
0016
Function
Reserved bit
Must set to "0."
Reserved bit
When use multi-master I2C-BUS interface, set this bit to "1."
Reserved bit
Must set to "0."
Reserved bit
When use multi-master I2C-BUS interface, set this bit to "1."
Reserved bits
Must set to "0."
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12. A/D CONVERTER
12. A/D Converter
The microcomputer contains one A/D converter circuit based on 8-bit successive approximation method configured
with a capacitive-coupling amplifier. The analog inputs share the pins with P00 to P07, P95 and P96. Similarly, ADTRG
input shares the pin with P97. Therefore, when using these inputs, make sure the corresponding port direction bits are
set to “0” (= input mode).
When not using the A/D converter, set the VCUT bit to “0” (= Vref unconnected), so that no current will flow from the
VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register bits for ANi pins (i = 0 to 7).
Table 12.1 shows the performance of the A/D converter. Figure 12.1 shows the block diagram of the A/D converter,
and Figures 12.2 and 12.3 show the A/D converter-related registers.
Table 12.1
Performance of A/D Converter
Item
Performance
Method of A/D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) f AD/divide-by-2 of fAD/divide-by-3 of f AD/divide-by-4 of f AD/divide-by-6 of
f AD/divide-by-12 of f AD
Resolution
8-bit
Integral nonlinearity error When AVCC = VREF = 5V
• With 8-bit resolution: ±3LSB
- ANEX0 and ANEX1 input (including mode in which external operation
amp is connected) : ±4LSB
Operating modes
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
Analog input pins
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1)
A/D conversion start condition • Software trigger
The ADCON0 register's ADST bit is set to “1” (A/D conversion starts)
• External trigger___________
(retriggerable)
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: The φAD frequency must be 10 MHz or less.
Without sample-and-hold function, limit the φAD frequency to 250kHZ or more.
With the sample and hold function, limit the φAD frequency to 1MHZ or more.
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12. A/D CONVERTER
A/D conversion rate
selection
CKS1=1
CKS2=0
1/2
fAD
1/2
1/3
φ AD
CKS0=1
CKS1=0
CKS0=0
CKS2=1
TRG=0
Software trigger
A/D trigger
ADTRG
TRG=1
VREF
(VCC2)
AV SS
Resistor ladder
VCUT=0
VCUT=1
Successive conversion register
ADCON1 register
ADCON0 register
AD register 0(8)
AD register 1(8)
AD register 2(8)
AD register 3(8)
AD register 4(8)
AD register 5(8)
AD register 6(8)
AD register 7(8)
Data bus low-order
Decoder
for A/D register
ADCON2 register
(address 03D416)
Vref
Decoder
for channel
selection
VIN
Port P0 group
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
CH2 to CH0
=0002
=0012
=0102
=011 2
=1002
=1012
=110 2
=111 2
OPA1 to OPA0=00 2
OPA1 to OPA0=11 2
ANEX0
ANEX1
Figure 12.1
OPA0=1
OPA1 to OPA0
=012
OPA1=1
OPA1=1
A/D Converter Block Diagram
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Comparator
M306H7MG-XXXFP/MC-XXXFP/FGFP
12. A/D CONVERTER
A/D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
ADCON0
Address
03D616
Bit symbol
Bit name
CH0
Analog input pin select bit
After reset
00000XXX2
Function
Function varies with each operation mode
RW
RW
CH1
RW
CH2
RW
MD0
A/D operation mode
select bit 0
MD1
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
RW
RW
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
See Note 2 for the ADCON2 register
RW
TRG
Note: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (Note 1)
b7
b6
b5
b4
b3
b2
0
b1
b0
Symbol
ADCON1
Bit symbol
Address
03D716
Bit name
A/D sweep pin select bit
After reset
0016
Function
RW
Function varies with each operation mode
SCAN0
RW
SCAN1
RW
A/D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
RW
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit 1
See Note 2 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2)
0 : Vref not connected
1 : Vref connected
RW
OPA0
External op-amp
connection mode bit
Function varies with each operation mode
MD2
(b3)
OPA1
RW
RW
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
Figure 12.2
ADCON0 to ADCON1 Registers
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12. A/D CONVERTER
A/D control register 2 (Note 1)
b7
b6
b5
b4
b3
b2
b1
0 1
b0
0
Symbol
Address
After reset
ADCON2
03D416
0016
Bit symbol
Bit name
Function
SMP
A/D conversion method
select bit
0 : Without sample and hold
1 : With sample and hold
RW
(b1)
Reserved bit
Must always be set to "0"
RW
(b2)
Reserved bit
Must always be set to "1"
RW
(b3)
Reserved bit
Must always be set to "0"
RW
CKS2
Frequency select bit 2
(Note 2)
0: Selects fAD, fAD divided by 2, or fAD
divided by 4.
RW
1: Selects fAD divided by 3, fAD divided
by 6, or fAD divided by 12.
Nothing is assigned. In an attempt to write to these bits, write "0".
The value, if read, turns out to be "0".
(b7-b5)
Note 1: If the ADCON2 register is rewritten during A-D conversion, the conversion result will be indeterminate.
Note 2: Adjust the frequency of φAD to 10MHZ or less. φAD can be selected by combining CKS0 bit of ADCON0 register,
CKS1 bit of ADCON1 register and CKS2 bit of ADCON2 register.
CKS2
CKS1
CKS0
φAD
0
0
0
0
0
1
Divide-by-4 of fAD
Divide-by-2 of fAD
0
0
1
1
1
0
0
1
0
fAD
1
1
1
0
1
1
1
0
1
Ddivide-by-12 of fAD
Divide-by-6 of fAD
Divide-by-3 of fAD
A/D register i (i=0 to 7)
b7
Symbol
b0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Address
After reset
03C0 16
03C2 16
03C4 16
03C6 16
03C8 16
03CA 16
03CC 16
03CE 16
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Function
A/D conversion result
Figure 12.3
ADCON2 Register, and AD0 to AD7 Registers
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12.1
12. A/D CONVERTER
One-shot Mode
In this mode, the input voltage on one selected pin is A/D converted once. Table 12.2 shows the specifications of
one-shot mode. Figure 12.4 shows the ADCON0 to ADCON1 registers in one-shot mode.
Table 12.2
One-shot Mode Specifications
Item
Function
Specification
The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and the ADCON1 register's OPA1 to OPA0 bits is A/D converted once.
A/D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A/D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
A/D conversion stop condition
• Completion of A/D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A/D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing Completion of A/D conversion
Analog input pin
Select one pin from AN0 to AN7, ANEX0 to ANEX1
Reading of result of A/D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
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12. A/D CONVERTER
A/D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 0
Symbol
ADCON0
Bit symbol
CH0
Address
03D616
Bit name
Analog input pin select
bit
CH1
CH2
MD0
MD1
After reset
00000XXX2
A/D operation mode
select bit 0
Function
RW
b2 b1 b0
0 0 0 : AN 0 is selected
0 0 1 : AN 1 is selected
0 1 0 : AN 2 is selected
0 1 1 : AN 3 is selected
1 0 0 : AN 4 is selected
1 0 1 : AN 5 is selected
1 1 0 : AN 6 is selected
1 1 1 : AN 7 is selected
RW
RW
(Note 2)
b4 b3
0 0 : One-shot mode
(Note 2)
RW
RW
RW
Trigger select bit
0 : Software trigger
1 : AD TRG trigger
RW
ADST
A/D conversion start flag
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
See Note 2 for the ADCON2 register
RW
TRG
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A/D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
b1
0 0
b0
Symbol
ADCON1
Bit symbol
SCAN0
Address
03D716
After reset
0016
Bit name
A/D sweep pin
select bit
Function
Invalid in one-shot mode
SCAN1
RW
RW
RW
MD2
A/D operation mode
select bit 1
Set to “0” when one-shot mode is selected
RW
(b3)
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit1
See Note 2 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2) 1 : Vref connected
OPA0
External op-amp
connection mode bit
OPA1
RW
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
RW
RW
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
Figure 12.4
ADCON0 Register and ADCON1 Register (One-shot Mode)
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12.2
12. A/D CONVERTER
Repeat mode
In this mode, the input voltage on one selected pin is A/D converted repeatedly. Table 12.3 shows the specifications
of repeat mode. Figure 12.5 shows the ADCON0 to ADCON1 registers in repeat mode.
Table 12.3
Repeat Mode Specifications
Item
Function
Specification
The input voltage on one pin selected by the ADCON0 register's CH2 to CH0
bits and the ADCON1 register's OPA1 to OPA0 bits is A/D converted
repeatedly.
A/D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A/D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
A/D conversion stop condition Set the ADST bit to “0” (A/D conversion halted)
Interrupt request generation timing None generated
Analog input pin
Select one pin from AN0 to AN7, ANEX0 to ANEX1
Reading of result of A/D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
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12. A/D CONVERTER
A/D control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
0 1
Symbol
ADCON0
Address
03D616
Bit symbol
CH0
After reset
00000XXX2
Bit name
Analog input pin
select bit
CH1
CH2
Function
RW
b2 b1 b0
0 0 0 : AN 0 is selected
0 0 1 : AN 1 is selected
0 1 0 : AN 2 is selected
0 1 1 : AN 3 is selected
1 0 0 : AN 4 is selected
1 0 1 : AN 5 is selected
1 1 0 : AN 6 is selected
1 1 1 : AN 7 is selected
RW
RW
(Note 2)
RW
RW
RW
b4 b3
MD1
A/D operation mode
select bit 0
TRG
Trigger select bit
ADST
A/D conversion start flag
0 : Software trigger
1 : AD TRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
RW
CKS0
Frequency select bit 0
See Note 2 for the ADCON2 register
RW
MD0
0 1 : Repeat mode
(Note 2)
RW
Note 1: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A/D control register 1 (Note)
b7
b6
b5
1
b4
b3
b2
b1
0 0
b0
Symbol
ADCON1
Address
03D716
Bit symbol
SCAN0
After reset
0016
Bit name
A/D sweep pin
select bit
Function
Invalid in repeat mode
SCAN1
MD2
(b3)
RW
RW
RW
A/D operation mode
select bit 1
Reserved bit
Set to “0” when this mode is selected
Must always be set to “0”
RW
RW
CKS1
Frequency select bit 1
VCUT
Vref connect bit (Note 2) 1 : Vref connected
RW
OPA0
External op-amp
connection mode bit
RW
OPA1
See Note 2 for the ADCON2 register
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
RW
RW
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
Figure 12.5
ADCON0 Register and ADCON1 Register (Repeat Mode)
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12.3
12. A/D CONVERTER
Single Sweep Mode
In this mode, the input voltages on selected pins are A/D converted, one pin at a time. Table 12.4 shows the
specifications of single sweep mode. Figure 12.6 shows the ADCON0 to ADCON1 registers in single sweep mode.
Table 12.4
Single Sweep Mode Specifications
Item
Function
Specification
The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits are A/D converted, one pin at a time.
A/D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A/D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
A/D conversion stop condition
set to “1” (A/D conversion starts)
• Completion of A/D conversion (If a software trigger is selected, the ADST bit
is cleared to “0” (A/D conversion halted).)
• Set the ADST bit to “0”
Interrupt request generation timing Completion of A/D conversion
Analog input pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins)
Reading of result of A/D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
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12. A/D CONVERTER
A/D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 0
Symbol
ADCON0
Address
03D616
Bit symbol
CH0
After reset
00000XXX2
Bit name
Analog input pin
select bit
Function
RW
Invalid in single sweep mode
RW
CH1
RW
CH2
RW
MD0
A/D operation mode
select bit 0
b4 b3
1 0 : Single sweep mode
MD1
TRG
ADST
CKS0
RW
RW
Trigger select bit
A/D conversion start flag
Frequency select bit 0
0 : Software trigger
1 : AD TRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
RW
See Note 2 for the ADCON2 register
RW
RW
Note: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
b1
0 0
b0
Symbol
ADCON1
Address
03D716
Bit symbol
Bit name
SCAN0
A/D sweep pin select bit
After reset
0016
Function
When single sweep mode is selected
RW
RW
b1 b0
0 0 : AN 0 to AN 1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins)
SCAN1
MD2
A/D operation mode
select bit 1
Set to “0” when single sweep mode is selected
RW
(b3)
Reserved bit
Must always be set to “0”
RW
CKS1
Frequency select bit 1
See Note 2 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2)
1 : Vref connected
RW
External op-amp
connection mode
bit
b7 b6
OPA0
OPA1
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
Figure 12.6
ADCON0 Register and ADCON1 Register (Single Sweep Mode)
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12.4
12. A/D CONVERTER
Repeat Sweep Mode 0
In this mode, the input voltages on selected pins are A/D converted repeatedly. Table 12.5 shows the specifications
of repeat sweep mode 0. Figure 12.7 shows the ADCON0 to ADCON1 registers in repeat sweep mode 0.
Table 12.5
Repeat Sweep Mode 0 Specifications
Item
Function
Specification
The input voltages on pins selected by the ADCON1 register's SCAN1 to
SCAN0 bits are A/D converted repeatedly.
A/D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A/D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
A/D conversion stop condition Set the ADST bit to “0” (A/D conversion halted)
Interrupt request generation timing None generated
Analog input pin
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), AN0
to AN7 (8 pins)
Reading of result of A/D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
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12. A/D CONVERTER
A/D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Address
03D616
Bit symbol
CH0
After reset
00000XXX2
Bit name
Analog input pin
select bit
Function
Invalid in repeat sweep mode 0
RW
RW
CH1
RW
CH2
RW
MD0
A/D operation mode
select bit 0
MD1
TRG
ADST
CKS0
Trigger select bit
A/D conversion start flag
Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
RW
0 : Software trigger
1 : AD TRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
RW
See Note 2 for the ADCON2 register
RW
RW
RW
Note: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
b1
0 0
b0
Symbol
ADCON1
Address
03D716
Bit symbol
SCAN0
After reset
0016
Bit name
A/D sweep pin select bit
Function
b1 b0
0 0 : AN 0, AN 1 (2 pins)
0 1 : AN 0 to AN 3 (4 pins)
1 0 : AN 0 to AN 5 (6 pins)
1 1 : AN 0 to AN 7 (8 pins)
SCAN1
MD2
(b3)
A/D operation mode
select bit 1
Reserved bit
RW
Set to “0” when repeat sweep mode 0 is
selected
RW
Must always be set to “0”
RW
Frequency select bit 1
See Note 2 for the ADCON2 register
RW
VCUT
Vref connect bit (Note 2)
1 : Vref connected
RW
External op-amp
connection mode
bit
OPA1
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
ADCON0 Register and ADCON1 Registers (Repeat Sweep Mode 0)
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CKS1
OPA0
Figure 12.7
RW
When repeat sweep mode 0 is selected
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M306H7MG-XXXFP/MC-XXXFP/FGFP
12.5
12. A/D CONVERTER
Repeat Sweep Mode 1
In this mode, the input voltages on all pins are A/D converted repeatedly, with priority given to the selected pins.
Table 12.6 shows the specifications of repeat sweep mode 1. Figure 12.8 shows the ADCON0 to ADCON1
registers in repeat sweep mode 1.
Table 12.6
Repeat Sweep Mode 1 Specifications
Item
Function
Specification
The input voltages on all selected pins are A/D converted repeatedly,with priority given to pins selected by the ADCON1 register's SCAN1 to SCAN0 bits.
Example : If AN0 selected, input voltages are A/D converted in order of
AN0
AN1
AN0
AN2
AN0
AN3, and so on.
A/D conversion start condition • When the ADCON0 register's TRG bit is “0” (software trigger)
The ADCON0 register's ADST bit is set to “1” (A/D conversion starts)
___________
• When the TRG bit is “1” (ADTRG trigger)
___________
Input on the ADTRG pin changes state from high to low after the ADST bit is
set to “1” (A/D conversion starts)
A/D conversion stop condition Set the ADST bit to “0” (A/D conversion halted)
Interrupt request generation timing None generated
Analog input pins to be given Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3
priority when A/D converted (4 pins)
Reading of result of A/D converter Read one of the AD0 to AD7 registers that corresponds to the selected pin
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M306H7MG-XXXFP/MC-XXXFP/FGFP
12. A/D CONVERTER
A/D control register 0 (Note)
b7
b6
b5
b4
b3
b2
b1
b0
1 1
Symbol
ADCON0
Address
03D616
Bit symbol
CH0
After reset
00000XXX2
Bit name
Analog input pin
select bit
Function
Invalid in repeat sweep mode 1
RW
RW
CH1
RW
CH2
RW
MD0
A/D operation mode
select bit 0
MD1
TRG
Trigger select bit
ADST
A/D conversion start flag
CKS0
Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
RW
RW
0 : Software trigger
1 : AD TRG trigger
0 : A/D conversion disabled
1 : A/D conversion started
RW
See Note 2 for the ADCON2 register
RW
RW
Note: If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D control register 1 (Note 1)
b7
b6
b5
1
b4
b3
b2
b1
0 1
b0
Symbol
ADCON1
Address
03D716
Bit symbol
Bit name
SCAN0
A/D sweep pin select bit
After reset
0016
Function
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN 0 (1 pin)
0 1 : AN 0, AN 1 (2 pins)
1 0 : AN 0 to AN 2 (3 pins)
1 1 : AN 0 to AN 3 (4 pins)
SCAN1
MD2
(b3)
A/D operation mode
select bit 1
Reserved bit
Must always be set to “0”
RW
VCUT
Vref connect bit (Note 2)
1 : Vref connected
External op-amp
connection mode
bit
b7 b6
See Note 2 for the ADCON2 register
0 0 : ANEX0 and ANEX1 are not used
0 1 : Must not be set
1 0 : Must not be set
1 1 : External op-amp connection mode
Note 1: If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
Note 2: If the VCUT bit is reset from “0” (Vref unconnected) to “1” (Vref connected), wait for 1 µs or more before starting
A/D conversion.
Figure 12.8
ADCON0 Register and ADCON1 Register (Repeat Sweep Mode 1)
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RW
RW
Frequency select bit 1
OPA1
RW
Set to “1” when repeat sweep mode 1 is
selected
CKS1
OPA0
RW
RW
RW
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
12.6
12. A/D CONVERTER
Sample and Hold
If the ADCON2 register’s SMP bit is set to “1” (with sample-and-hold), the conversion speed per pin is increased
to 28 φAD cycles for 8-bit resolution. Sample-and-hold is effective in all operation modes.
Select whether or not to use the sample-and-hold function before starting A/D conversion.
12.7
Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the ADCON1
register’s OPA1 to OPA0 bits to select whether or not use ANEX0 and ANEX1.
The A/D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers, respectively.
12.8
External Operation Amp Connection Mode
Multiple analog inputs can be amplified using a single external op-amp via the ANXE0 and ANEX1 pins.
Set the ADCON1 register’s OPA1 OPA0 bits to ‘112’ (external op-amp connection mode). The inputs from ANi (i
= 0 to 7) are output from the ANEX0 pin. Amplify this output with an external op-amp before sending it back to the
ANEX1 pin. The A/D conversion result is stored in the corresponding ADi register. The A/D conversion speed
depends on the response characteristics of the external op-amp. Note that the ANXE0 and ANEX1 pins cannot be
directly connected to each other. Figure 12.9 is an example of how to connect the pins in external operation amp.
Microcomputer
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Resistor ladder
Successive conversion
register
ANEX0
ANEX1
Comparator
External opamp
Figure 12.9
External Op-amp Connection
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M306H7MG-XXXFP/MC-XXXFP/FGFP
12.9
12. A/D CONVERTER
Current Consumption Reducing Function
When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using
the ADCON1 register’s VCUT bit. When separated, no current will flow from the VREF pin into the resistor ladder,
helping to reduce the power consumption of the chip.
To use the A/D converter, set the VCUT bit to “1” (VREF connected) and then set the ADCON0 register’s ADST bit
to “1” (A/D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (VREF unconnected) during A/D conversion.
12.10 Analog Input Pin and External Sensor Equivalent Circuit Example
Figure 12.10 shows analog input pin and external sensor equivalent circuit example.
Microcomputer
Sensor equivalent
circuit
R0
R
VIN
Sampling time
C
VC
Figure 12.10
3
fAD
2
Sample-and-hold function disabled:
fAD
Sample-and-hold function enabled:
Analog Input Pin and External Sensor Equivalent Circuit
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M306H7MG-XXXFP/MC-XXXFP/FGFP
12. A/D CONVERTER
12.11 Caution of Using A/D Converter
(1) Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode).
Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for the
ADTRG pin is set to “0” (input mode).
(2) To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi (i=0 to 7)) each and the AVSS pin.
Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 12.11 is an example connection of
each pin.
(3) If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
•When operating in one-shot or single-sweep mode
Check to see that A/D conversion is completed before reading the target ADi register. (Check the IR bit in
the ADIC register to see if A/D conversion is completed.)
•When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
(4) If A/D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit to
“0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of
ADi registers irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
Microcomputer
VCC1
VCC2
VCC1 (16 pin) AV CC
C4
VSS
C2
AV SS
VCC2
VCC2 (62 pin)
C5
C3
ANi
VSS
ANi: ANi (i=0 to 7)
Note 1: C1≥0.47µF, C2 ≥0.47µF, C3 ≥100pF, C4 ≥0.1µF, C5≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 12.11
VCC, VSS, AVCC, AVSS, VREF and ANi Connection
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M306H7MG-XXXFP/MC-XXXFP/FGFP
13. CRC CALCULATION
13. CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator
polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8 bit units.
After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte of data is
written to the CRCIN register. CRC code generation for one-byte data is finished in two cycles.
Figure 13.1 shows the block diagram of the CRC circuit. Figure 13.2 shows the CRC-related registers.
Figure 13.3 shows the calculation example using the CRC operation.
Data bus high-order
Data bus low-order
Eight low-order bits
Eight high-order bits
CRCD register
CRC code generating circuit
x16 + x12 + x5 + 1
CRCIN register
Figure 13.1
CRC Circuit Block Diagram
CRC data register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BD16 to 03BC16
After reset
Indeterminate
Setting range
Function
When data is written to the CRCIN register after setting
the initial value in the CRCD register, the CRC code can
be read out from the CRCD register.
RW
000016 to FFFF16 RW
CRC input register
b7
Symbol
CRCIN
b0
Function
Data input
Figure 13.2
CRCD Register and CRCIN Register
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Address
03BE16
After reset
Indeterminate
Setting range
RW
0016 to FF16
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
13. CRC CALCULATION
Setup procedure and CRC operation when generating CRC code “80C416”
(a) CRC operation performed by the M16C
CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is
divided by the generator polynomial
Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 00012)
(b) Setting procedure
(1) Reverse the bit positions of the value “80C416” bytewise in a program.
“8016” → “0116”, “C416” → “2316”
b15
b0
(2) Write 000016 (initial value)
CRCD register
b7
b0
(3) Write 0116
CRCIN register
Two cycles later, the CRC code for “8016,” i.e.,
918816, has its bit positions reversed to become
“118916” which is stored in the CRCD register.
b0
b15
CRCD register
118916
b7
b0
(4) Write 2316
CRCIN register
Two cycles later, the CRC code for “80C416,” i.e.,
825016, has its bit positions reversed to become
“0A4116” which is stored in the CRCD register.
b15
b0
CRCD register
0A4116
(c) Details of CRC operation
In the case of (3) above, the value written to the CRCIN register “0116 (000000012)” has its bit positions reversed to
become “100000002.” The value “1000 0000 0000 0000 0000 00002” derived from that by adding 16 digits and the
CRCD register’s initial value “000016” are added, the result of which is divided by the generator polynomial using
modulo-2 arithmetic.
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001 1000 0000 0000 0000
1000 1000 0001 0000
Generator polynomial
1000 0001 0000
1000 1000 0001
1001 0001
0000
1
1000
0000
1000
0000
0
1
1000
Data
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
CRC code
The value “0001 0001 1000 10012 (118916)” derived from the remainder “1001 0001 1000 10002 (918816)” by
reversing its bit positions may be read from the CRCD register.
If operation (4) above is performed subsequently, the value written to the CRCIN register “2316 (001000112)” has its bit
positions reversed to become “110001002. The value “1100 0100 0000 0000 0000 00002” derived from that by adding
16 digits and the remainder in (3) “1001 0001 1000 10002” which is left in the CRCD register are added, the result of
which is divided by the generator polynomial using modulo-2 arithmetic.
The value “0000 1010 0100 00012 (0A4116)” derived from the remainder by reversing its bit positions may be read
from the CRCD register.
Figure 13.3
CRC Calculation
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14. EXPANSION FUNCTION
14. Expansion Function
14.1
Expansion function description
Expansion function consists of CRC operation function, data slice function and humming decoder function. Each
function is controlled by expansion memories.
1. CRC operation function
It performs error detection of a code, and error correction.
2. Data slice function
It performs data acquisition to get such format data as below.
Hardware : TELETEXT, PDC, VPS, VBI and EPG-J
Software : WSS, CC, CC2X and ID-1
3. Humming decoder function
It performs 8/4 humming and 24/18 humming
BCLK
SYNCIN
Clock
generator
Vertical
Syncseparate
circuit
Clock
generator
Clock
generator
Syncseparate
circuit
Timing
generator
Port
control
circuit
CVIN
CRC
register
Data slicer circuit
Expansion
register
24/18
humming
8/4
humming
Data bus (16bit)
CPU block
Figure 14.1
Block diagram of expansion function
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Serial/pararell
conversion
circuit
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Slice
RAM
Arbitration
circuit
M306H7MG-XXXFP/MC-XXXFP/FGFP
14.2
14. EXPANSION FUNCTION
Expansion memory
Expansion function memory is divided by 3 patterns ; Slice RAM, CRC registers and expansion registers
(Humming decoder operates by the register placed on SFR). Data writing and read out to the Slice RAM, CRC
registers and the expansion registers are carried out per 16 bit unit by the data setting register (addresses 020E16,
021016, 021216, 021416, 021616 and 021816) placed on SFR.
Contents of each memory and data setting register are shown in Table 14.1.
Table 14.1
Expansion memory composition
Contents
Expansion memory
Data setting register
Slice RAM
This register holds acquired data.
Slice RAM address control register (020E16)
Slice RAM data control register (021016)
CRC register
This register controls a set up generation
polynomial and code data.
CRC register address control register (0212 16)
CRC register data control register (021416)
Expansion register
This register performs data slicer control and
Expansion register address control register (021616)
VBI encoder control.
Expansion register data control register (021816)
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14.3
14. EXPANSION FUNCTION
Slice RAM
Slice RAM stores 18-line slice data. There are several types of Slice data : PDC, VPS, VBI, XDS, WSS, etc. All
data are stored to addresses which corresponds to slice line (ex. 22 line' data is stored to addresses 20016 to 21716 ).
24 addresses (SR00x to SR17x) are prepared for 1 line, slice data is stored in order from LSB side. Then, slice data
type and field information are stored to the top address of each line.
Slice RAM composition is shown in Table 14.2.
Table 14.2
Slice RAM addresses
(SA9 to SA0)
00016
00116
to
01616
01716
01816
to
01F16
02016
to
03716
04016
to
1F716
20016
to
21716
22016
to
23716
Slice RAM composition
SD15 SD14 SD13 SD12 SD11 SD10 SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Remarks (Note1)
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 6th line or 318th line
SR01F SR01E SR01D SR01C SR01B SR01A SR019 SR018 SR017 SR016 SR015 SR014 SR013 SR012 SR011 SR010 slice data
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
SR16F SR16E SR16D SR16C SR16B SR16A SR169 SR168 SR167 SR166 SR165 SR164 SR163 SR162 SR161 SR160
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
Unused area
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 7th line or 319th line
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
8th line to 21th line
or 320th line to 333 line
slice data
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 22th line or 334th line
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
SR00F SR00E SR00D SR00C SR00B SR00A SR009 SR008 SR007 SR006 SR005 SR004 SR003 SR002 SR001 SR000 23th line or 335th line
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
to
slice data
SR17F SR17E SR17D SR17C SR17B SR17A SR179 SR178 SR177 SR176 SR175 SR174 SR173 SR172 SR171 SR170
Note 1. This is the line to support when the PAL video signal is sliced and setting the expansion registers to VPS_VP8 to VPS_VP0
(bits 8 to 0 in address 2916) = "416".
For accessing to Slice RAM data, set accessing address (SA9 to SA0) (shown in Table 14.2) to Slice RAM address
control register (address 020E16 ). Then read out data from Slice RAM data control register (address 021016 ).
When end the data reading, Slice RAM address control register increments address automatically. Then, next
address data reading is possible. Do not access to unused area of each character codes. Must set address to each line
because unused area has no address' automatically increment.
Slice RAM bit composition is shown in Figure 14.2, Slice RAM access registers are shown in Figure14.3 and Slice
RAM access block diagram is shown in Figure 14.4
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14. EXPANSION FUNCTION
.
Slice RAM bit composition
The each head address of the address is corresponded to slice line following slice information.
Line register 3
Line register 2
Line register 1
Other
SR00F to SR004
0
0
0
0
SR003
SR002
0
0
0
0
field*
field*
field*
field*
SR001
1
1
0
0
SR000
1
0
1
0
* field
* the first field : 1
the second field : 0
(1) PDC
In case of the PDC data, 16 bits (2 data) are stored for the 1 address from the LSB side.
Clock run-in
+ flaming code
Data1
Data2
L
S
B
Data3
M L
S S
B B
SR020
Data5
Data4
Data6
Data39
Data40
Data41
Data42
M
S
B
SR02F
SR030
SR040
SR03F
SR04F
SR150
SR15F
SR160
SR16F
Note. The expansion register is the slice data storing pattern when setting the START
(bit 1 in address 2816 bit) to "1". SR17x is the unused area.
(2) VPS
In case of the VPS data or the VBI data, 8 bits (a data) are stored for an address from the LSB side.
Low-order 8 bits hold the slice data. And, high-order 8 bits hold warning bit, when the send data is not recognized
as bi-phase type.
The case of bi-phase data ="1,0" or "0,1" (the bi-phase type) becomes "0" for this warning bit, and it becomes "1"
in bi-phase data="0,0" or "1,1" (it is not the bi-phase type).
(For example, bi-phase data of SR011 is "0,0" or "1,1", "1" is set to SR019.)
Clock run-in
+ flaming code
Data1
L
S
B
SR020
Data2
M L
S S
B B
Data3
Data4
Data11
Data12
Data13
M
S
B
SR027
SR030
SR040
SR047
SR037
SR050
SR0C0
SR057
SR0C7
SR0D0
SR0E0
SR0E7
SR0D7
Note. The expansion register is the slice data storing pattern when setting the START
(bit 1 in address 2816 bit) to "1". From SR0Fx to SR17x are the unused area.
(3) EPG-J
Clock run-in
+ flaming code
Data1
C
S
B
SR020
Data2
Data3
M L
S S
B B
SR02F
SR030
Data4
Data5
Data6
Data31
Data32
Data33
Data34
M
S
B
SR040
SR03F
SR04F
SR110
SR11F
SR120
SR12F
Note. The expansion register is the slice data storing pattern when setting the START
(bit 1 in address 2816 bit) to "1". From SR13x to SR17x are the unused area.
Figure 14.2
Slice RAM bit composition
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14. EXPANSION FUNCTION
.
Slice RAM address control register
b15
b9
b8
b7
b0
Symbol
SA
Address
020E16
When reset
000016
Setting possible value R W
Function
Specify accessing Slice RAM address
00016 to 23716
Nothing is assigned.
When write, set to “0.”
When read, its content is indeterminate.
Note 1 : When access to Slice RAM, Slice RAM address control register (020E16) should be
set at first.
Slice RAM address control register increments by accessing Slice RAM
data control register. So, it is not neccesary to setting the next Slice RAM address.
Note 2 : When read Slice RAM data by software during slicer operation, access to Slice RAM
after 1 horizontal synchronous period from the completion of a SLICEON
(refer to 14.6 Expansion Register Construction Composition for a SLICEON
period).
Slice RAM data control register
b15
b9
b8
b7
b0
Symbol
SD
Address
021016
When reset
000016
Function
RW
Read out the data of Slice RAM.
Read out data of Slice RAM which is specified by Slice RAM address control register
(address 020E16) by reading this register.
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 14.3
Slice RAM access registers.
Data bus (16-bit)
(address 020E16)
Slice RAM address control register
(10) (SA9 to SA0)
Slice RAM data control
register (16) (SD15 to SD0)
Increment automatically
after data access
Slice RAM
Figure 14.4
Slice RAM access block diagram
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(address 021016)
M306H7MG-XXXFP/MC-XXXFP/FGFP
14.4
14. EXPANSION FUNCTION
CRC Operation Circuit (EPG-J)
CRC operation circuit (EPG-J) is a circuit for performing error detection and error correction by the 272-190
shortening difference set cyclic code which is a coding system in a data multiplex broadcast.
CRC register consists of registers shown in Figure 14.5. CRC register can perform error detection and error
correction by majority logic by setting up a generator polynomial, code data, etc. CRC register composition is
shown in Table 14.3.
Table 14.3
CA3 to CA0
0016
0116
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
CD15
DAOUT15
_
CRC_66
CRC_50
CRC_34
CRC_18
CRC_02
_
REG_C81
_
_
_
_
CRC register composition
CD12
DAOUT12
_
CRC_69
CRC_53
CRC_37
CRC_21
CRC_05
_
CD11
DAOUT11
_
CRC_70
CRC_54
CRC_38
CRC_22
CRC_06
_
CD0
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
CD10
DAOUT0
DAOUT1
DAOUT2
DAOUT3
DAOUT4
DAOUT5
DAOUT6
DAOUT7
DAOUT8
DAOUT9
DAOUT10
CRC_ERR10 CRC_ERR09 CRC_ERR08 CRC_ERR07 CRC_ERR06 CRC_ERR05 CRC_ERR04 CRC_ERR03 CRC_ERR02 CRC_ERR01 CRC_ERR00
CRC_71
CRC_72
CRC_73
CRC_76
CRC_77
CRC_78
CRC_79
CRC_80
CRC_81
CRC_75
CRC_74
CRC_55
CRC_56
CRC_57
CRC_60
CRC_61
CRC_62
CRC_63
CRC_64
CRC_65
CRC_59
CRC_58
CRC_49
CRC_48
CRC_47
CRC_46
CRC_45
CRC_44
CRC_43
CRC_42
CRC_41
CRC_40
CRC_39
CRC_33
CRC_32
CRC_31
CRC_30
CRC_29
CRC_28
CRC_27
CRC_26
CRC_25
CRC_24
CRC_23
CRC_07
CRC_17
CRC_16
CRC_15
CRC_14
CRC_13
CRC_12
CRC_11
CRC_10
CRC_09
CRC_08
CRC_01
CRC_00
_
_
_
_
_
_
_
_
_
CD14
DAOUT14
_
CRC_67
CRC_51
CRC_35
CRC_19
CRC_03
_
CD13
DAOUT13
_
CRC_68
CRC_52
CRC_36
CRC_20
CRC_04
_
REG_C80
_
_
_
_
REG_C79
_
_
_
_
REG_C78
_
_
_
_
REG_C77
_
_
_
_
REG_C76
_
_
_
_
_
_
_
_
_
_
REG_C75
_
_
_
_
REG_C74
_
_
_
_
REG_C73
_
_
_
_
_
_
_
REG_C72
_
_
_
_
REG_C71
_
_
_
_
_
_
REG_C70
_
_
_
_
REG_C69
_
_
_
_
REG_C68
_
_
_
_
REG_C67
_
_
_
_
REG_C66
_
_
_
_
CRC16SEL
_
_
_
_
CRC register address control register
b15 b14 b13
b8 b7
b5 b4 b3
b0
Symbol
CA
address
021216
at Reset
000016
The value which R W
can be set up
Function
Specify accessing CRC register address.
0016 to 0D16
CRC register address automatic increment.
0: enable / 1 : disable (Notes 2)
–
Nothing is assigned.
When write, set to "0." When read, its content is determinate.
CRCLOOP 0 to 5
CRCCHANGE
– –
The number of times of a CRC
operation repetition.
0016 to 3F16
Error detection / error correction
Selection setting
–
0:error detection mode / 1: Error correction mode
CRC operation
CRCON
–
0: Stop/1 : Operation (Note 3)
Notes 1: When access to CRC register, must be set CRC register address at first, then use
CRC register data control register (021416).
Notes 2: When bit 4 = "0" setting, CRC register data control register increments by accessing
CRC register data control register, so it is not necessary to setting the next CRC
register address. When bit 4 = "1" setting, the address is fixed.
Notes 3: When bit 15 = "0" setting, the value of a CRC data register
(address (CA3 to CA0) =01 to 07) is cleared.
CRC register data control register
b15
b8b7
b0
Symbol
CD
address
021416
Function
Write and read out the data of CRC register which is
specified by CRC register address control register
(address 021216)
at Reset
000016
The value which
can be set up
000016 to FFFF16
Note: Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 14.5
Composition of CRC register access related register
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 187 of 326
RW
Remarks
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
For accessing to CRC register data, set accessing address (CA3 to CA0) (shown in Table 14.3) to CRC register
address control register (address 021216). Then write data (CD15 to CD0) by CRC register data control register
(address 0214 16 ). When end the data accessing, CRC register address control register increments address
automatically. Then, next address data writing is possible.
CRC register access registers are shown in Figure 14.5, CRC register access block diagram is shown in Figure 14.6.
The operation example of CRC operation circuit is shown in Figure 14.7. The example of program is shown in
Figure 14.8, and CRC register bit compositions are shown in p191 to p199.
Data bus (16-bit)
(address 021216)
(CA13 to CA8)
(CA4)
CRC register address control register (4)
(CA3 to CA0)
CRC register data control register (16)
(CD15 to CD0)
Increment automatically
after data access
Shift counter
Code data
shift register
Generator polynomial register
Shift control circuit
82 bit CRC operation circuit
Error correction
mode
remainder polynomial register
Error judging
circuit
CRC error detection register
(Majority circuit)
Figure 14.6
Access block diagram for CRC registers
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 188 of 326
(address 021416)
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
b81
(1) Reset of CRC
remainder bit
0 0 0 0 0 0 0
b0
•••
0 0 0 0 0 0 0 0
CRC register
CRC_81 to 00
[address 0216 to 0716]
CRC remainder bit is automatically reset by CRCON=0 (address control register for CRC registers).
b15
b0
CRC register
(2) Setting 0016
DAOUT
[address 0016]
After CRC operation end
b0
b81
CRC register
CRC_81 to 00
[address 0216 to 0716]
The CRC code is stored
The data set as the DAOUT register is shifted from the low rank side of CRC remainder bit one by one (b0).
MOJURO-2 operation is
operation that complies
with the law given below.
0+0=0
0+1=1
1+0=1
1+1=0
-1 = 1
•••
•••
1000 01
100 0011 0000 • • • 0001 0001 0000 0000 0000 0001 0000 0000 • • • 0000 0000 0000 • • • 0000 0000
1 0000 1100 • • • 0010 001
b0
b82 b81
1100 • • • 0010 0010 0000
1000
•••
0001 0001
Remainder
b81
b0
Generator polynomial shown in below is used in this circuit :
X82 + X77 + X76 + X71 + X67 + X66 + X52 + X48 + X40 + X36 + X34 + X24 + X22 + X18 + X10 + X4 + 1
Figure 14.7
Example of operation of CRC operation circuit
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 189 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
;
;
Equations (Constant definition)
;
_CRC_ADRS
.equ
00212h
; SFR address of CRC register address control register
_CRC_DATA
.equ
00214h
; SFR address of CRC register data control register
SLICE_WORD_NUM
.equ
17
; Code data length (in nuits of word)
;
;
Macro definition
;
_wait
.macro
nop
nop
nop
.endm
;
;
CRC operation routine
;
;--------- Setting of generator polynomial
mov.w
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
#0008H
, _CRC_ADRS
; Set the head address of the generator polynomial register
0000110000100011B
, _CRC_DATA
; Coefficient of generator polynomial 82nd to 66th ( x^77 +x~76 +x^71 +x^67 +x^66)
_wait
mov.w
; Wait
;------ Writing of code data ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------mov.w
#0000H
, _CRC_ADRS
; Initialization of CRC register address control register
mov.w
#9010H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Increment=ON, and CRC address=00H.
mov.w
#0000H
, A0
; Initialization of a loop variable (A0)
cmp.w
#SLICE_WORD_NUM*2
, A0
; Comparison of the loop variable
jgeu
L20
lde.w
_CrcCodeData[A0]
, _CRC_DATA
; Writing code data to the code data shift register.
add.w
#0002H
,A0
; Increment of the address storing code data.
jmp
L18
L18:
; Branch label
; Go to L20 if writing code data is finished.
; Return to the head of this loop.
L20:
; Branch label
;--------- Dummy shift --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------; After finishing writing 272-bit code data,
; shift a bit for dummy surely in error correction mode.
; Specifying 1-bit is set up by CRCLOOP=01H.
mov.w
#8100H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Increment=OFF, and CRC address=00H.
#0000H
, _CRC_DATA
; Writing data to the code data shift register for dummy shift.
_wait
mov.w
; Wait
;--------- Error detection ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------; Since the address automatic increment in dummy shift (Increment=OFF), set CRC address=01H here.
; When accessing other CRC registers, the processing shown in the following two lines is necessary.
;
mov.w
;
_wait
#9001H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Incremet=OFF and CRC address=01H.
; Wait
mov.w
_CRC_DATA
, R0
; Read of CRC error detection register.
cmp.w
#0000H
, R0
; Judgement of CRC error.
jeq
L16
; In the case of R0=0, branch to L16 since CRC error has not occurred (CRC error correction is skipped).
;--------- Error correction --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------mov.w
#0D010H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=1, CRCLOOP=10H, Increment=ON and CRC address=00H.
mov.w
#0000H
, A0
; Initialization of a loop variable (A0)
cmp.w
#SLICE_WORD_NUB
, A0
; Comparison of the loop variable
jgeu
L24
lde.w
_CrcCodeData[A0]
, _CRC_DATA
; Writing code data to the code data shift register.
jsr
_waitlong
mov.w
_CRC_DATA
, _CrcCodeData[A0]
; Read of error correction data in the address storing code data.
add.w
#0002H
, A0
; Increment of the address storing code data.
jmp
L22
_wait
; Wait
L22:
; Branch label
; Go to L24 if correction of error data is finished.
; Wait for finish of error correction.
; Return to the head of this loop.
L24:
; Branch label
;------- The check of error correction data-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------mov.w
#8111H
, _CRC_ADRS
; Set up of CRCON=1, CRCCHANGE=0, CRCLOOP=10H, Increment=ON and CRC address=00H
_CRC_DATA
, R0
; Error check after error correction. R0=000H if correction is performed.
_wait
mov.w
; Wait
L16:
;
; The function sample for weight for error correction
;
.align
.glb
_waitlong
_waitlong:
; Function label
rts
Figure 14.8
Example of program
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 190 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
1.Bit composition of a CRC register
1. Address 0016 (=CA3 to 0)
CD15
CD8CD7
CD0
Function
Bit symbol
Bit name
DAOUT0
The code data shift register
write-in bit 0
When write, data is written to "code
data shift register" (Note).
DAOUT1
The code data shift register
write-in bit 1
DAOUT2
The code data shift register
write-in bit 2
When read, data differs between in
error detection mode and in error
correction mode.
DAOUT3
The code data shift register
write-in bit 3
DAOUT4
The code data shift register
write-in bit 4
DAOUT5
The code data shift register
write-in bit 5
DAOUT6
The code data shift register
write-in bit 6
DAOUT7
The code data shift register
write-in bit 7
DAOUT8
The code data shift register
write-in bit 8
DAOUT9
The code data shift register
write-in bit 9
DAOUT10
The code data shift register
write-in bit 10
DAOUT11
The code data shift register
write-in bit 11
DAOUT12
The code data shift register
write-in bit 12
DAOUT13
The code data shift register
write-in bit 13
DAOUT14
The code data shift register
write-in bit 14
DAOUT15
The code data shift register
write-in bit 15
• In error detection mode
(CRCCHANGE=0)
000016 is read after shift end.
When read during shift operation, its
content is indeterminate.
• In error correction mode
(CRCCHANGE=1)
Corrected data is read after the
original data is written in and some
interval of data shift.
Note: Refer to Figure 14.16 Access block diagram for CRC registers.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 191 of 326
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
2. Address 0116 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
CRC_ERR00
Logical OR of the CRC remainder bits
81 to 74 (address 0216)
CRC_ERR01
The CRC bit 73 to 66 error
detection bit
Logical OR of the CRC remainder bits
73 to 66 (address 0216)
CRC_ ERR02
The CRC bit 65 to 58 error
detection bit
Logical OR of the CRC remainder bits
65 to 58 (address 0316)
CRC_ERR03
The CRC bit 57 to 50 error
detection bit
Logical OR of the CRC remainder bits
57 to 50 (address 0316)
CRC_ERR04
The CRC bit 49 to 42 error
detection bit
Logical OR of the CRC remainder bits
49 to 42 (address 0416)
CRC_ERR05
The CRC bit 41 to 34 error
detection bit
Logical OR of the CRC remainder bits
41 to 34 (address 0416)
CRC_ERR06
The CRC bit 33 to 26 error
detection bit
Logical OR of the CRC remainder bits
33 to 26 (address 0516)
CRC_ERR07
The CRC bit 25 to 18 error
detection bit
Logical OR of the CRC remainder bits
25 to 18 (address 0516)
CRC_ERR08
The CRC bit 17 to 10 error
detection bit
Logical OR of the CRC remainder bits
17 to 10 (address 0616)
CRC_ERR09
The CRC bit 09 to 02 error
detection bit
Logical OR of the CRC remainder bits
09 to 02 (address 0616)
CRC_ERR10
The CRC bit 01 to 00 error
detection bit
Logical OR of the CRC remainder bits
01 to 00 (address 0716)
Nothing is assigned.
The value is "0" when it reads.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Function
The CRC bit 81 to 74 error
detection bit
Page 192 of 326
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
3. Address 0216 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
Function
CRC_81
81th remainder polynomial
coefficient bit
CRC_80
80th remainder polynomial
coefficient bit
The coefficient of each degree of a
remainder polynomial is set up.
It is shown in below when a remainder
polynomial is made into CRC_MOD.
CRC_79
79th remainder polynomial
coefficient bit
CRC_78
78th remainder polynomial
coefficient bit
CRC_77
77th remainder polynomial
coefficient bit
CRC_76
76th remainder polynomial
coefficient bit
CRC_75
75th remainder polynomial
coefficient bit
CRC_74
74th remainder polynomial
coefficient bit
CRC_73
73th remainder polynomial
coefficient bit
CRC_72
72th remainder polynomial
coefficient bit
CRC_71
71th remainder polynomial
coefficient bit
CRC_70
70th remainder polynomial
coefficient bit
CRC_69
69th remainder polynomial
coefficient bit
CRC_68
68th remainder polynomial
coefficient bit
CRC_67
67th remainder polynomial
coefficient bit
CRC_66
66th remainder polynomial
coefficient bit
81
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 193 of 326
CRC_MOD = Σ CRC_n • X
n=0
R W
n
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
4. Address 0316 (=CA3 to 0)
CD15
CD8CD7
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
CD0
Bit symbol
Bit name
CRC_65
65th remainder polynomial
coefficient bit
CRC_64
64th remainder polynomial
coefficient bit
CRC_63
63th remainder polynomial
coefficient bit
CRC_62
62th remainder polynomial
coefficient bit
CRC_61
61th remainder polynomial
coefficient bit
CRC_60
60th remainder polynomial
coefficient bit
CRC_59
59th remainder polynomial
coefficient bit
CRC_58
58th remainder polynomial
coefficient bit
CRC_57
57th remainder polynomial
coefficient bit
CRC_56
56th remainder polynomial
coefficient bit
CRC_55
55th remainder polynomial
coefficient bit
CRC_54
54th remainder polynomial
coefficient bit
CRC_53
53th remainder polynomial
coefficient bit
CRC_52
52th remainder polynomial
coefficient bit
CRC_51
51th remainder polynomial
coefficient bit
CRC_50
50th remainder polynomial
coefficient bit
Page 194 of 326
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
5. Address 0416 (=CA3 to 0)
CD15
CD8CD7
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
CD0
Bit symbol
Bit name
CRC_49
49th remainder polynomial
coefficient bit
CRC_48
48th remainder polynomial
coefficient bit
CRC_47
47th remainder polynomial
coefficient bit
CRC_46
46th remainder polynomial
coefficient bit
CRC_45
45th remainder polynomial
coefficient bit
CRC_44
44th remainder polynomial
coefficient bit
CRC_43
43th remainder polynomial
coefficient bit
CRC_42
42th remainder polynomial
coefficient bit
CRC_41
41th remainder polynomial
coefficient bit
CRC_40
40th remainder polynomial
coefficient bit
CRC_39
39th remainder polynomial
coefficient bit
CRC_38
38th remainder polynomial
coefficient bit
CRC_37
37th remainder polynomial
coefficient bit
CRC_36
36th remainder polynomial
coefficient bit
CRC_35
35th remainder polynomial
coefficient bit
CRC_34
34th remainder polynomial
coefficient bit
Page 195 of 326
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
6. Address 0516 (=CA3 to 0)
CD15
CD8CD7
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
CD0
Bit symbol
Bit name
CRC_33
33th remainder polynomial
coefficient bit
CRC_32
32th remainder polynomial
coefficient bit
CRC_31
31th remainder polynomial
coefficient bit
CRC_30
30th remainder polynomial
coefficient bit
CRC_29
29th remainder polynomial
coefficient bit
CRC_28
28th remainder polynomial
coefficient bit
CRC_27
27th remainder polynomial
coefficient bit
CRC_26
26th remainder polynomial
coefficient bit
CRC_25
25th remainder polynomial
coefficient bit
CRC_24
24th remainder polynomial
coefficient bit
CRC_23
23th remainder polynomial
coefficient bit
CRC_22
22th remainder polynomial
coefficient bit
CRC_21
21th remainder polynomial
coefficient bit
CRC_20
20th remainder polynomial
coefficient bit
CRC_19
19th remainder polynomial
coefficient bit
CRC_18
18th remainder polynomial
coefficient bit
Page 196 of 326
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
7. Address 0616 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
CRC_17
17th remainder polynomial
coefficient bit
CRC_16
16th remainder polynomial
coefficient bit
CRC_15
15th remainder polynomial
coefficient bit
CRC_14
14th remainder polynomial
coefficient bit
CRC_13
13th remainder polynomial
coefficient bit
CRC_12
12th remainder polynomial
coefficient bit
CRC_11
11th remainder polynomial
coefficient bit
CRC_10
10th remainder polynomial
coefficient bit
CRC_09
09th remainder polynomial
coefficient bit
CRC_08
08th remainder polynomial
coefficient bit
CRC_07
07th remainder polynomial
coefficient bit
CRC_06
06th remainder polynomial
coefficient bit
CRC_05
05th remainder polynomial
coefficient bit
CRC_04
04th remainder polynomial
coefficient bit
CRC_03
03rd remainder polynomial
coefficient bit
CRC_02
02nd remainder polynomial
coefficient bit
Function
R W
Refer to CRC_81 to 66
(address 0216).
8. Address 0716 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
CRC_01
01st remainder polynomial
coefficient bit
CRC_00
00th remainder polynomial
coefficient bit
Nothing is assigned.
The value is "0" when it reads.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 197 of 326
Function
Refer to CRC_81 to 66
(address 0216).
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
9. Address 0816 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Function
Bit name
REG_C0
Coefficient bit of the 66/0th
generation polynomials
REG_C1
Coefficient bit of the 67/1th
generation polynomials
REG_C2
Coefficient bit of the 68/2th
generation polynomials
REG_C3
Coefficient bit of the 69/3th
generation polynomials
REG_C4
Coefficient bit of the 70/4th
generation polynomials
REG_C5
Coefficient bit of the 71/5th
generation polynomials
R W
The coefficient of each degree
of the generation polynomial
is set.
The coefficient from 81 to the 66th
is set for 82 bit CRC mode.
The 15th in case of 16 bit CRC
mode. The 0th coefficients are set.
When generation polynomial to
be CRC_GP,
CRC_GP = X
82
15
n+66
Σ REG_Cn · X
REG_C6
Coefficient bit of the 72/6th
generation polynomials
REG_C7
Coefficient bit of the 73/7th
generation polynomials
+X
REG_C8
Coefficient bit of the 74/8th
generation polynomials
+X
Coefficient bit of the 75/9th
generation polynomials
(For 82 bit CRC mode)
REG_C9
REG_C10
Coefficient bit of the 76/10th
generation polynomials
CRC_GP = X
REG_C11
Coefficient bit of the 77/11th
generation polynomials
REG_C12
Coefficient bit of the 78/12th
generation polynomials
REG_C13
Coefficient bit of the 79/13th
generation polynomials
REG_C14
Coefficient bit of the 80/14th
generation polynomials
REG_C15
Coefficient bit of the 81/15th
generation polynomials
n=0
+X
56
36
18
+X
+X
+X
52
34
10
+X
+X
48
24
+X
+X
40
22
4
+X +1
16
15
+ Σ RE6_Cn · X
n
n=0
(For 16 bit CRC mode)
10. Address 0916 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
Nothing is assigned.
The value is unfixed when it reads.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 198 of 326
Function
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
11. Address 0A16 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
Function
R W
Function
R W
Function
R W
Nothing is assigned.
The value is unfixed when it reads.
12. Address 0B16 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
Nothing is assigned.
The value is unfixed when it reads.
13. Address 0C16 (=CA3 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
Nothing is assigned.
The value is unfixed when it reads.
14. Address 0D16 (=CA3 to 0)
CD15
CD8CD7
CD0
0 0 0 0
Bit symbol
Reserved bit
CRC16SEL
Function
Bit name
Must set to "0."
CRC mode select bit
Selects 82 bit CRC/16 bit CRC mode
CRC16SEL
CRC mode
0
82 bit CRC
1
16 bit CRC
Nothing is assigned Indeterminate at reading
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 199 of 326
R W
LN14_EV1
LN15_EV1
LN17_EV0
LN17_EV1
LN15_OD0
LN15_OD1
DIVS1
FLC15
CHK_FLC15
0016
0116
0216
0316
0416
0516
0616
0716
0816
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
0D16
0E16
_
_
GETPEEK3
_
1216
CHK_FLC14
_
CHK_FLC15
1516
1616
Page 200 of 326
_
_
_
_
_
_
RMT_TMH(5)
_
3F16
RMT_TMH(6)
IROUT_SLICEON
RMT_TMH(7)
_
3D16
3E16
RMT_TM(5)
_
DAYCUONT13
RMT_TM(6)
RMT_TM(7)
_
DAYCUONT14
_
DAYCUONT15
3C16
_
_
3B16
_
YUKOU1(5)
SECINT1
_
_
_
SECINT2
_
_
3A16
SECJUST
_
3916
_
SECINT3
3616
3816
3516
3716
_
EXAOFF
3416
_
_
_
_
RMT_TMH(4)
_
RMT_TM(4)
DAYCUONT12
_
_
_
YUKOU1(4)
SECINT0
_
_
_
VERTX
_
_
FILDIV1(0)
_
3316
_
_
HCOUNT12
_
_
SEL_PDCH
_
_
_
WEIGHT4
_
RMTSEL
FILDIV1(1)
3216
_
_
HCOUNT13
_
DIVV_CK4
3116
_
HCOUNT14
_
_
_
_
_
_
_
_
2F16
_
_
_
_
BIFON
CHK_FLC11
FLC11
_
SLSLVL1
CHK_FLC10
FLC10
INTDA
WEIGHT2
DIVV_CK2
_
_
DIV_VPS7
DIV_PDC7
_
_
_
_
_
_
_
_
_
RMT_TMH(3)
_
RMT_TM(3)
DAYCUONT11
_
_
_
YUKOU1(3)
HINT3
_
_
FILDIV0
JSTCKON
_
_
_
HCOUNT11
_
RMT_TMH(2)
_
RMT_TM(2)
DAYCUONT10
MINOUT10
_
_
YUKOU1(2)
HINT2
PTD8
_
_
JSTCKDIV1
_
_
_
HCOUNT10
_
_
_
_
_
_
_
STBSYNCSEP SYNCSEP_ON0
_
WEIGHT3
DIVV_CK3
_
_
DIV_VPS8
DIV_PDC8
_
_
_
_
_
_
_
_
_
STB_RES
2E16
_
SEL_VPSH
_
_
_
_
_
SLSLVL1
_
CHK_FLC10
FLC10
BIFON
CHK_FLC11
FLC11
_
3016
_
HCOUNT15
2D16
_
2C16
_
_
SEL_PDEC
_
_
2A16
2B16
_
_
_
2916
_
_
_
_
_
_
_
_
_
2816
_
_
_
_
_
RMT_TMH(1)
_
RMT_TM(1)
DAYCUONT9
MINOUT9
_
_
YUKOU1(1)
HINT1
PTC8
_
FILDIV0
JSTCKDIV0
_
_
_
HCOUNT9
_
_
_
_
SLI_GO
INTAD
WEIGHT1
DIVV_CK1
_
_
DIV_VPS6
DIV_PDC6
_
LEVELA
_
_
VPS_VCO_ON
_
_
_
_
GET_HP1
SLSLVL0
CHK_FLC9
_
RMT_TMH(0)
_
RMT_TM(0)
DAYCUONT8
MINOUT8
RTCON
_
YUKOU1(0)
HINT0
HINT_LINE8
_
RMTHD1(8)
RMTHD0(8)
_
_
_
HCOUNT8
PLSNEG8
PLSPOS8
_
_
VPS_VP8
ADON
WEIGHT0
DIVV_CK0
_
_
DIV_VPS5
DIV_PDC5
_
NORMAL
_
_
PDC_VCO_R1
_
_
_
_
GET_HP0
_
CHK_FLC8
FLC8
_
FLC9
_
_
GET_HP0
_
CHK_FLC8
FLC8
_
_
_
GET_HP0
_
CHK_FLC8
_
_
GET_HP1
SLSLVL0
CHK_FLC9
FLC9
_
_
_
GET_HP1
SLSLVL0
FLC8
_
FLC9
LN8_OD1
LN8_OD0
_
_
_
CHK_FLC9
_
DD8
LN8_EV1
LN8_EV0
LN9_OD1
LN9_OD0
_
_
SLSLVL1
_
_
DD9
LN9_EV1
LN9_EV0
CHK_FLC10
FLC10
_
LN10_OD1
LN10_OD0
_
_
_
_
_
_
_
BIFON
CHK_FLC11
FLC11
_
LN11_OD1
LN11_OD0
_
_
DD10
LN10_EV1
LN10_EV0
_
HORAX_ON
DIVV_CK5
DD11
LN11_EV1
LN11_EV0
_
GETPEEK0
_
CHK_FLC12
FLC12
_
_
_
GETPEEK0
_
CHK_FLC12
FLC12
_
_
_
_
_
_
NXP
_
2716
_
2616
_
DIVV_CK6
_
_
DIVV_CK7
2516
_
2416
_
_
2316
_
_
HM84SEL
2216
2016
2116
MPAL
_
1F16
_
_
_
_
1E16
_
_
1D16
_
EXT_PDC2
_
ADSTART
1C16
_
_
SELSTART
_
FRAM
GSTTIM
_
_
_
1916
_
GETPEEK1
1B16
_
1816
CHK_FLC13
FLC13
SELVCO
SELSTART
_
GETPEEK1
_
CHK_FLC13
FLC13
SELVCO
SELSTART
_
_
GETPEEK0
_
CHK_FLC12
FLC12
_
LN12_OD1
LN12_OD0
_
_
GETPEEK1
CHK_FLC13
1A16
GETPEEK2
_
GETPEEK3
1716
FLC14
DIVS0
1416
GSTTIM
_
DIVS1
FLC15
1316
FRAM
GETPEEK2
CHK_FLC14
CHK_FLC15
1116
FLC14
DIVS0
GSTTIM
1016
0F16
FLC15
0C16
FRAM
_
_
DIVS1
0B16
0A16
_
GETPEEK2
_
GETPEEK3
0916
FLC13
SELVCO
LN13_OD1
LN13_OD0
_
_
DD12
LN12_EV1
LN12_EV0
DD7
DD6
LN16_OD1
LN17_OD1
_
_
_
_
_
_
_
_
_
_
RMT_TML(6)
RMT_TML(7)
RMTDIV(0)
DAYCUONT6
MINOUT6
_
_
MINOUT7
_
INTRMT2
HINT_LINE6
_
RMTHD1(6)
RMTHD0(6)
_
_
_
HCOUNT6
PLSNEG6
PLSPOS6
_
MASK6
VPS_VP6
SYNLVL1
DLYSEL6
_
_
RMT_TML(5)
RMCDIV(1)
DAYCUONT5
MINOUT5
SECOUT5
_
YUKOU0(5)
INTRMT1
HINT_LINE5
_
RMTHD1(5)
RMTHD0(5)
_
_
_
HCOUNT5
PLSNEG5
PLSPOS5
_
MASK5
VPS_VP5
SYNLVL0
DLYSEL5
DIVP_CK5
_
DIVP_CK6
_
RMTDIV(1)
_
DIV_VPS2
DIV_PDC2
_
DIV_VPS3
DIV_PDC3
_
_
_
_
_
RMT_TML(4)
RMCDIV(0)
DAYCUONT4
MINOUT4
SECOUT4
_
YUKOU0(4)
INTRMT0
HINT_LINE4
_
RMTHD1(4)
RMTHD0(4)
_
_
_
HCOUNT4
PLSNEG4
PLSPOS4
_
MASK4
VPS_VP4
_
DLYSEL4
DIVP_CK4
SLION_TIM
_
DIV_VPS1
DIV_PDC1
_
_
FLD1V
_
_
_
_
SLS4
_
SLS_HP4
SEKI4
CHK_FLC4
FLC4
_
SLS4
_
SLS_HP4
SEKI4
CHK_FLC4
FLC4
_
SLS4
_
SLS_HP4
SEKI4
CHK_FLC4
FLC4
_
LN4_OD1
LN4_OD0
_
_
_
_
SEPV0
DD4
LN4_EV1
LN4_EV0
_
SLS5
_
SLS_HP5
SEKI5
CHK_FLC5
FLC5
_
SLS5
_
SLS_HP5
SEKI5
CHK_FLC5
FLC5
_
SLS5
_
SLS_HP5
SEKI5
CHK_FLC5
FLC5
_
LN5_OD1
LN5_OD0
_
_
_
_
DAYCUONT7
DD5
LN5_EV1
LN5_EV0
_
PDC_VCO_ON
_
_
SLS6
_
SLS_HP6
SEKI6
CHK_FLC6
FLC6
_
INTRMT3
HINT_LINE7
_
RMTHD1(7)
RMTHD0(7)
_
_
_
HCOUNT7
PLSNEG7
PLSPOS7
_
MASK7
VPS_VP7
SYNLVL2
DLYSEL7
DIVP_CK7
_
_
DIV_VPS4
DIV_PDC4
_
_
MACRO_ON
_
PDC_VCO_R0
_
_
SLS7
_
SLS_HP7
SEKI7
CHK_FLC7
FLC7
SLS6
_
_
SLS7
SLS_HP6
SEKI6
CHK_FLC6
FLC6
_
SLS_HP7
SEKI7
CHK_FLC7
FLC7
_
SLS6
_
SLS7
SLS_HP6
SEKI6
CHK_FLC6
FLC6
_
LN6_OD1
SLS_HP7
SEKI7
CHK_FLC7
FLC7
_
LN7_OD1
LN6_OD0
LN16_OD0
LN17_OD0
LN7_OD0
LN6_EV1
LN6_EV0
LN7_EV1
LN7_EV0
DD3
DD2
_
_
_
_
PLSNEG3
_
RMTTXINT(3)
RMT_TML(3)
IRPOL(2)
DAYCUONT3
MINOUT3
SECOUT3
_
YUKOU0(3)
VINT3
HINT_LINE3
_
RMTHD1(3)
RMTHD0(3)
_
_
_
HCOUNT3
_
RMTTXINT(2)
RMT_TML(2)
IRPOL(1)
DAYCUONT2
MINOUT2
SECOUT2
_
YUKOU0(2)
VINT2
HINT_LINE2
_
RMTHD1(2)
RMTHD0(2)
_
_
_
HCOUNT2
PLSNEG2
PLSPOS2
MASK2
PLSPOS3
VPS_VP2
MASK3
_
DLYSEL2
VPS_VP3
6BITOFF
DLYSEL3
DIVP_CK2
_
DIVP_CK3
_
DIV_VPSS2
DIV_PDCS2
_
_
_
_
DIV_VPS0
DIV_PDC0
_
_
_
_
_
_
_
_
SLS2
_
SLS_HP2
SEKI2
CHK_FLC2
FLC2
_
SLS2
_
SLS_HP2
SEKI2
CHK_FLC2
FLC2
_
SLS2
_
SLS_HP2
SEKI2
CHK_FLC2
FLC2
_
LN2_OD1
LN2_OD0
_
_
LN2_EV1
LN2_EV0
_
_
SLS3
_
SLS_HP3
SEKI3
CHK_FLC3
FLC3
_
SLS3
_
SLS_HP3
SEKI3
CHK_FLC3
FLC3
_
SLS3
_
SLS_HP3
SEKI3
CHK_FLC3
FLC3
_
LN3_OD1
LN3_OD0
_
_
LN3_EV1
LN3_EV0
DD1
_
RMTTXINT(1)
RMT_TML(1)
IRPOL(0)
DAYCUONT1
MINOUT1
SECOUT1
_
YUKOU0(1)
VINT1
HINT_LINE1
_
RMTHD1(1)
RMTHD0(1)
_
_
_
HCOUNT1
PLSNEG1
PLSPOS1
_
MASK1
VPS_VP1
START
DLYSEL1
DIVP_CK1
ADON_TIM
_
DIV_VPSS1
DIV_PDCS1
_
_
_
_
_
_
_
SLS1
_
SLS_HP1
SEKI1
CHK_FLC1
FLC1
_
SLS1
_
SLS_HP1
SEKI1
CHK_FLC1
FLC1
_
SLS1
_
SLS_HP1
SEKI1
CHK_FLC1
FLC1
_
LN1_OD1
LN1_OD0
_
_
LN1_EV1
LN1_EV0
DD0
_
RMTTXINT(0)
RMT_TML(0)
RMTSTART
DAYCUONT0
MINOUT0
SECOUT0
_
YUKOU0(0)
VINT0
HINT_LINE0
_
RMTHD1(0)
RMTHD0(0)
_
_
_
HCOUNT0
PLSNEG0
PLSPOS0
_
MASK0
VPS_VP0
ADLAT
DLYSEL0
DIVP_CK0
ADSEL
_
DIV_VPSS0
DIV_PDCS0
_
_
_
_
_
_
_
SLS0
_
SLS_HP0
SEKI0
CHK_FLC0
FLC0
_
SLS0
_
SLS_HP0
SEKI0
CHK_FLC0
FLC0
_
SLS0
_
SLS_HP0
SEKI0
CHK_FLC0
FLC0
_
LN0_OD1
LN0_OD0
_
_
LN0_EV1
LN0_EV0
for read
for read
for read
Status register 3
Status register 2
Status register 1
Line register
Remarks
Table 14.4
CHK_FLC14
FLC14
DIVS0
LN14_OD1
DD13
LN13_EV1
LN13_EV0
14.5
LN14_OD0
LN16_EV1
LN16_EV0
DD14
LN14_EV0
DD15
LN15_EV0
DA5 to DA0
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
Expansion Register
Control Data slice function. Expansion register composition is shown in Table 14.4.
Expansion register composition
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
For accessing to expansion register data, set accessing address (DA5 to DA0) (shown in Table 14.4) to expansion
register address control register (address 021616). Then write data (DD15 to DD0) to expansion register data
control register (address 0218 16 ). When end the data accessing, expansion register address control register
increments address automatically. Then, next address data writing is possible. After reset, the value of expansion
register become “0” all, except for the clock timer.
Expansion register access registers are shown in Figure 14.9, expansion register access block
diagram is shown in Figure 14.10, and expansion register bit compositions are shown in p202 to p239.
Expansion register address control register
b1 5
b8
b7
b6
b0
Symbol
DA
Address
021616
Function
When reset
000016
Setting possible value
Specify accessing expansion register address
RW
0016 to 4516
Nothing is assigned.
When write, set to “0”.
When read, its content is indeterminate.
Expansion register address automatic increment
0:enable / 1:disable (Note2)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Note1 : When access to expansion register, must be set expansion register address
at first, then use expansion register data control register (021816).
Note2 : When bit 8 = “0” setting, expansion register data control register increments by
accessing expansion register data control register, so it is not necessary to
setting the next expansion register address. When bit 8 = “1” setting, the address
is fixed.
Expansion register data control register
b1 5
b8
b7
b0
Symbol
DD
Address
021816
When reset
000016
Setting possible value
Function
Write and read out the data of expansion register which is
specified by expansion register address control register
(address 021616)
000016 to FFFF16
Note : Data access must be 16-bit unit. 8-bit unit access is disable.
Figure 14.9
Expansion register access registers composition
Data bus (16-bit)
(address 021616) (DA8)
Expansion register address
control register (6) (DA5 to DA0)
Expansion register data control
register (16) (DD15 to DD0)
Increment automatically
after data access
Expansion register
Figure 14.10
Expansion register access block diagram
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 201 of 326
(address 021816)
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
Bit composition of an expansion register
1. Address 0016 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
R W
LN0_EV0
The 0th line state register
selection bit
LN1_EV0
The 1st line state register
selection bit
LN2_EV0
The 2nd line state register
selection bit
As for the slicing method of the n-th line
(Notes 1), it is chosen which set of the
state register settings of the three sets
(Notes 2) is used with the combination
of LNn_EV0 (address 0016 and 0216,
n = 0 to 17) and LNn_EV1 (address
0116 and 0316, n= 0 to 17.)
LN3_EV0
The 3rd line state register
selection bit
Four kinds of following state registers
can be chosen for every line (Notes 3.)
LN4_EV0
The 4th line state register
selection bit
LN5_EV0
The 5th line state register
selection bit
LN6_EV0
The 6th line state register
selection bit
LN7_EV0
The 7th line state register
selection bit
LN8_EV0
The 8th line state register
selection bit
LN9_EV0
The 9th line state register
selection bit
LN10_EV0
The 10th line state register
selection bit
LN11_EV0
The 11th line state register
selection bit
LN12_EV0
The 12th line state register
selection bit
LN13_EV0
The 13th line state register
selection bit
LN14_EV0
The 14th line state register
selection bit
LN15_EV0
The 15th line state register
selection bit
LNn_EV1 LNn_EV0 State register(Notes 2)
Do not set up
0
0
State register 1
1
0
State register 2
0
1
State register 3
1
1
Notes 1. The n-th line: The number of lines after a slice start.
Please refer to the supplement (3) of 15.6 expansion register composition
(P229) for details.
Notes 2. 06h to 0Ch address: State register 1
0Dh to 13h address: State register 2
14h to 1Ah address: State register 3
Notes 3. The example of a setting.
V after sync separation
The 0th line The 1st line The 2nd line
H after sync separation
line 1
line 2
•••
line n
line (n+1)
line (n+2)
LN0_EV1=0 LN1_EV1=0 LN2_EV1=1
LN0_EV0=1 LN1_EV0=1 LN2_EV0=0
slice
slice
slice
processing by processing by processing by
setup of the
setup of the
setup of the
state register 1. state register 1. state register 2.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 202 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
2. Address 0116 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Bit name
LN0_EV1
The 0th line state register
selection bit
LN1_EV1
The 1st line state register
selection bit
LN2_EV1
The 2nd line state register
selection bit
LN3_EV1
The 3rd line state register
selection bit
LN4_EV1
The 4th line state register
selection bit
LN5_EV1
The 5th line state register
selection bit
LN6_EV1
The 6th line state register
selection bit
LN7_EV1
The 7th line state register
selection bit
LN8_EV1
The 8th line state register
selection bit
LN9_EV1
The 9th line state register
selection bit
LN10_EV1
The 10th line state register
selection bit
LN11_EV1
The 11th line state register
selection bit
LN12_EV1
The 12th line state register
selection bit
LN13_EV1
The 13th line state register
selection bit
LN14_EV1
The 14th line state register
selection bit
LN15_EV1
The 15th line state register
selection bit
Page 203 of 326
Function
Refer to LNn_EV0 (address 0016)
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
3. Address 0216 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
Function
R W
× ×
Nothing is assigned.
LN16_OD0
The 16th line state register
selection bit
LN17_OD0
The 17th line state register
selection bit
Refer to LNn_OD0 (address 0416)
× ×
Nothing is assigned.
LN16_EV0
The 16th line state register
selection bit
LN17_EV0
The 17th line state register
selection bit
Refer to LNn_EV0 (address 0016)
4. Address 0316 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
Function
× ×
Nothing is assigned.
LN16_OD1
The 16th line state register
selection bit
LN17_OD1
The 17th line state register
selection bit
Refer to LNn_OD0 (address 0416)
× ×
Nothing is assigned.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
LN16_EV1
The 16th line state register
selection bit
LN17_EV1
The 17th line state register
selection bit
Page 204 of 326
R W
Refer to LNn_EV0 (address 0016)
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
5. Address 0416 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
R W
LN0_OD0
The 0th line state register
selection bit
LN1_OD0
The 1st line state register
selection bit
LN2_OD0
The 2nd line state register
selection bit
As for the slicing method of the n-th line
(Notes 1), it is chosen which set of the
state register settings of the three sets
(Notes 2) is used with the combination
of LNn_OD0 (address 0416 and 0216,
n = 0 to 17) and LNn_OD1 (address
0516 and 0316, n= 0 to 17.)
LN3_OD0
The 3rd line state register
selection bit
Four kinds of following state registers
can be chosen for every line. (Notes 3)
LN4_OD0
The 4th line state register
selection bit
LN5_OD0
The 5th line state register
selection bit
LN6_OD0
The 6th line state register
selection bit
LN7_OD0
The 7th line state register
selection bit
LN8_OD0
The 8th line state register
selection bit
LN9_OD0
The 9th line state register
selection bit
LN10_OD0
The 10th line state register
selection bit
LN11_OD0
The 11th line state register
selection bit
LN12_OD0
The 12th line state register
selection bit
LN13_OD0
The 13th line state register
selection bit
LN14_OD0
The 14th line state register
selection bit
LN15_OD0
The 15th line state register
selection bit
LNn_EV1 LNn_EV0 State register(Notes 2)
Do not set up
0
0
State register 1
1
0
State register 2
0
1
State register 3
1
1
Notes 1. The n-th line: The number of lines after a slice start.
Please refer to the supplement (3) of 14.6 expansion register composition for details.
Notes 2. 06h to 0Ch address: State register 1
0Dh to 13h address: State register 2
14h to 1Ah address: State register 3
Notes 3. The example of a setting.
V after sync separation
The 0th line The 1st line The 2nd line
H after sync separation
line 1
line 2
•••
line n
line (n+1)
line (n+2)
LN0_OD1=0 LN1_OD1=0 LN2_OD1=1
LN0_OD0=1 LN1_OD0=1 LN2_OD0=0
slice
slice
slice
processing by processing by processing by
setup of the
setup of the
setup of the
state register 1. state register 1. state register 2.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 205 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
6. Address 0516 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Bit name
LN0_OD1
The 0th line state register
selection bit
LN1_OD1
The 1st line state register
selection bit
LN2_OD1
The 2nd line state register
selection bit
LN3_OD1
The 3rd line state register
selection bit
LN4_OD1
The 4th line state register
selection bit
LN5_OD1
The 5th line state register
selection bit
LN6_OD1
The 6th line state register
selection bit
LN7_OD1
The 7th line state register
selection bit
LN8_OD1
The 8th line state register
selection bit
LN9_OD1
The 9th line state register
selection bit
LN10_OD1
The 10th line state register
selection bit
LN11_OD1
The 11th line state register
selection bit
LN12_OD1
The 12th line state register
selection bit
LN13_OD1
The 13th line state register
selection bit
LN14_OD1
The 14th line state register
selection bit
LN15_OD1
The 15th line state register
selection bit
Page 206 of 326
Function
Refer to LNn_OD0 (address 0416)
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
7. Address 0616, 0D16, 1416 (=DA5 to 0)
DD15
DD8DD7
DD0
1 1 0 0 0 0 0 0 0 0
Bit symbol
R W
Function
Bit name
Reserved bits
Must set to "0."
×
Reserved bits
Must set to "1."
×
× ×
Nothing is assigned.
SELVCO
DIVS0
The PLL selection bit for
slice
The clock division bit for slice
DIVS1
0
1
PDC
VPS
DIVS1
0
0
1
1
DIVS0
0
1
0
1
divided value
no division
divided by 2
divided by 3
divided by 5
8. Address 0716, 0E16, 1516 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
FLC0
FLC1
Function
Bit name
Framing code selection bit
R W
Framing code is set up
Clock
run-in
Framing
code
Data
Setup
FLC2
FLC3
FLC4
FLC5
FLC6
FLC7
FLC8
FLC9
FLC10
FLC11
FLC12
FLC13
FLC14
FLC15
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 207 of 326
FLC0
to
FLC15
16 bits are checked at maximum.
However, the bit of CHK_FLCn
(addresses 0816, 0F16 and 1616)
= "1" is not checked.
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
9. Address 0816, 0F16, 1616 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
CHK_FLC0
CHK_FLC1
Function
Bit name
Framing code check
selection bit
When acquiring data, it sets up whether
framing code set up by FLC 0 to 15
(addresses 0716, 0E16, and 1516) is
checked or not per bit.
Data will be acquired if the n-th bit
which is set as check is in agreement.
CHK_FLC2
CHK_FLC3
CHK_FLC4
CHK_FLC5
CHK_FLC6
CHK_FLC7
CHK_FLC8
CHK_FLC9
CHK_FLC10
CHK_FLC11
CHK_FLC12
CHK_FLC13
CHK_FLC14
CHK_FLC15
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 208 of 326
CHK_FLCn
n-th bit
0
check
1
No check
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
10. Address 0916, 1016, 1716 (=DA5 to 0)
DD8DD7
DD15
0 1
DD0
1 0
Bit symbol
Bit name
SEKI0
Data slicer control bit 1
SEKI1
Function
R W
N
SEKI1 SEKI0
5 (Note1)
0
0
4 (Note2)
1
0
6 (Note3)
0
1
8 (Note4)
1
1
N-times the digital value after SEKI7.6.
N
SEKI2
4
0
0
3
0
1
1
1
0
No differentiation
1
1
It differentiates from the digitized data
in front of N/8 cycles (clock run-in cycle)
to the digital value after SEKI0 and 1.
N
SEKI5
SEKI4
4
0
0
3
1
0
1
0
1
No differentiation
1
1
It differentiates from the digitized data
in after N/8 cycles (clock run-in cycle)
to the digital value after SEKI3 and 2.
SEKI3
SEKI2
Data slicer control bit 2
SEKI3
SEKI4
Data slicer control bit 3
SEKI5
SEKI6
SEKI6
Data slicer control bit 4
SEKI7
0
1
Leveling existence of the following
A-D convert value
Average for four clocks
It doesn't level
0
The differentiation by SEKI2, 3,
SEKI4, and 5 is differentiated by
one time the value.
1
The differentiation by SEKI2, 3,
SEKI4, and 5 is differentiated by
twice the value.
Data slicer control bit 5
Nothing is assigned.
0
SISLVL0
Slice level control bit
1
Slice level measurement
period selection bit
SISLVL1
BIFON
Data format selection bit
0
The clock line average level is used
The slice level selection bit
(0C16,1316, 1A16, and house number
SLS7?0) is used.
2 cycles of Clock run-in
1
4 cycles of Clock run-in
0
Non Return Zero
1
Bi-phase type
Reserved bit
Must set to "0."
Reserved bits
Must set to "1."
Reserved bit
Must set to "0."
Note 1. When selecting 5 times with SEKI0, 1 and twice with SEKI7, select "none" for any one
of SEKI2, 3 or SEKI4, 5.
Note 2. When selecting 8 times for SEKI0, 1, select "none" for both SEKI2, 3 and SEKI4, 5.
Note 3. When selecting 6 times for SEKI0, 1 and twice for SEKI7, select "none" for any one of
SEKI2, 3 or SEKI4, 5.
Note 4. When selecting "none" for both SEKI2, 3 and SEKI4, 5, do not select 4 times, and
select 8 times for SEKI0, 1.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 209 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
11. Address 0A16, 1116, 1816 (=DA5 to 0)
DD8DD7
DD15
DD0
0 1
Bit symbol
SLS_HP0
Function
Bit name
R W
It will become below if data slice start
position is made into SLS_HS.
Slice check start position
selection bit
7
SLS_HS = T2×Σ2n SLS_HPn
SLS_HP1
n=0
T2 : Clock run-in cycle /2
SLS_HP2
SLS_HP3
SLS_HP4
SLS_HP5
The position where framing code
begins to be checked is set up.
SLS_HP6
Setup in a 1-bit unit is possible.
SLS_HP7
GET_HP0
Phase fine-tuning bit
Slice data 0/1 judging clock is tuned
finely.
GET_HP1
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Reserved bit
Must set to "1."
5
Reserved bit
Must set to "0."
5
GETPEEK1 GETPEEK0
Clock run-in period
2
4
5
6
GETPEEK0
Peak detection period
selection bit 0
GETPEEK1
Peak detection period
selection bit 1
GETPEEK2
Peak detection period
selection bit 2
0
1
With clock compensation
With no clock compensation
GETPEEK3
Peak detection period
selection bit 3
0
1
A mountain and a valley are detected.
Page 210 of 326
0
0
1
1
0
1
0
1
Only a mountain is detected.
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
12. Address 0B16, 1216, 1916 (=DA5 to 0)
DD8DD7
DD15
DD0
0
Bit symbol
R W
Function
Bit name
X X
Nothing is assigned.
Reserved bit
Must set to "0."
The number selection bit of
framing code check bits
FRAM
0
15-bit check
1
16-bit check
X
Nothing is assigned.
X X
13. Address 0C16, 1316, 1A16 (=DA5 to 0)
DD15
0
DD8DD7
DD0
0 0 0 0 0
Bit symbol
SLS0
Bit name
Slice level selection bit
Function
R W
It will become below if a slice level is
made into SLS_LVL.
SLS_LVL
SLS1
SLS2
Data
SLS3
At the time of SLS7 = "H"
SLS4
6
SLS_LVL = Σ2n SLSn – 128
n=0
SLS5
At the time of SLS7 = "L"
6
SLS_LVL = Σ2n SLSn
SLS6
n=0
SLS7
Reserved bits
SELSTART
Slice start condition selection bit
Must set to "0."
×
Slice beginning after slice check period
0 (SLS_HP7 to 0 of addresses 0A,11 and 18)
passes
Slice beginning after standing up of clock
1 run-in after slice check period
(SLS_HP7 to 0 of addresses 0A,11 and 18)
passes
GSTTIM
Ghost correct control bit
0 Ghost correct OFF
1 Ghost correct ON
Reserved bit
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 211 of 326
Must set to "0."
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
14. Address 1B16 (=DA5 to 0)
DD8DD7
DD15
0 0 0
DD0
0 0 0 0 0 1 0 0 0 0 0 0
Bit symbol
Function
Bit name
R W
Reserved bits
Must set to "0."
×
Reserved bit
Must set to "1."
×
Reserved bits
Must set to "0."
×
× ×
Nothing is assigned.
Reserved bits
×
Must set to "0."
15. Address 1C16 (=DA5 to 0)
DD15
0
DD8DD7
0 0 0 0 0
DD0
0 0 0 0 0 0 0
Bit symbol
R W
Reserved bits
Must set to "0."
X
Reserved bit
Must set to "1" when EPG-J is acquired.
Otherwise, set to "0."
X
Reserved bits
Must set to "0."
X
EXT_PDC2
Selection of PLL divided-in-3
frequency bit for PDC
ADSTART
Page 212 of 326
0
1
no divided
divided-in-3
Must set to "0."
Reserved bit
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Function
Bit name
A/D conversion completion bit
0
Conversion completion
1
Under conversion
X
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
16. Address 1D16 (=DA5 to 0)
DD15
DD8DD7
0 0 0 0 0
DD0
0 0 0
Bit symbol
Function
Bit name
× ×
Nothing is assigned.
Reserved bits
×
Must set to "0."
PDC_VCO_ON
PDC clock oscillation
selection bit
0
1
PDC_VCO_R0
PDC clock oscillation
change bit
PDC_VCO PDC_VCO
_R1
_R0
0
0
0
1
1
0
1
1
PDC_VCO_R1
VPS clock oscillation
selection bit
VPS_VCO_ON
R W
0
1
Reserved bits
PDC clock stop
PDC clock oscillation
Select PDC clock
Select EPG-J clock
Do not set up
Do not set up
×
VPS clock stop
VPS clock oscillation
Must set to "0."
×
× ×
Nothing is assigned.
17. Address 1E16 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 0
Bit symbol
Function
Bit name
Reserved bits
R W
Must set to "0."
Nothing is assigned.
18. Address 1F16 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0
Bit symbol
Function
Bit name
Nothing is assigned.
FLD1V
Field state flag
Reserved bits
MACRO_ON
Synchronized signal search flag
Nothing is assigned.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 213 of 326
0
Even field
1
Odd field
Must set to "0."
0
normal
1
unusual
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
19. Address 2016 (=DA5 to 0)
DD8DD7
DD15
0
0 0 0
DD0
0 0 0
Bit symbol
Function
Bit name
Reserved bits
×
Must set to "0."
× ×
Nothing is assigned.
SEPV0
Vertical synchronous
separation standard selection bit
Reserved bit
NORMAL
Synchronous signal slice potential
generating control bit
LEVELA
Reserved bits
NXP
Broadcast method selection bit
MPAL
Reserved bit
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 214 of 326
0
1
Detected in L period of 15ms/22ms.
Detected in L period of 22ms.
×
Must set to "0."
Framing code check control bit
R W
0
1
Check (Data is acquired if Framing code is in agreement).
0
Synchronous signal slice potential generating circuit OFF
1
Synchronous signal slice potential generating
circuit ON
No check (All data is acquired).
×
Must set to "0."
NXP
0
0
1
1
MPAL
0
1
0
1
Must set to "0."
Broadcast method
NTSC
M-PAL
PAL
Do not set up
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
20. Address 2116 (=DA5 to 0)
DD15
DD8DD7
DD0
0 1
Bit symbol
Function
Bit name
R W
× ×
Nothing is assigned.
Reserved bit
Must set to "1."
×
Reserved bit
Must set to "0."
×
21. Address 2216 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
DIV_PDCS0
The PLL fine-tuning bit for
PDC
Function
Slice clock frequency fPDC for PDC
is adjusted.
f PDC = fDIVP ×
DIV_PDCS1
8
n
( n=0
Σ 2 DIV_PDCn
2
m-3
+Σ 2
DIV_PDCS2
DIV_PDC0
R W
m=0
The divided value selection bit
of PLL for PDC
DIV_PDCSm+2
)
f DIVP : Horizontal synchronized
signal frequency
DIV_PDC1
• When teletext (PDC) data is acquired
DIV_PDC4 to 0, DIV_PDCS2 to 0
= (00100011)2
(
DIV_PDC2
)
• When EPG-J is acquired
DIV_PDC3
(
DIV_PDC4 to 0, DIV_PDCS2 to 0
= (00010011)2
)
DIV_PDC4
× ×
Nothing is assigned.
HM84SEL
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 215 of 326
8/4 humming polarity
selection bit
0
Normal
1
The 4-bit data of 8/4 humming is
reversal-outputted.
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
22. Address 2316 (=DA5 to 0)
DD15
0 0 0
DD8DD7
DD0
0 0 0 0
Bit symbol
Function
Bit name
DIV_VPSS0 The PLL fine-tuning bit for
VPS
f VPS = f DIVV ×
DIV_VPSS1
8 n
( n=0
Σ2
2
m=0
(
)
When CC, CC2X and ID-1 are acquired
DIV_VPS4 to 0,
DIV_VPSS2 to 0
= (11010100)2
DIV_VPS3
(
DIV_VPS4
Reserved bits
Must set to "0."
Horizontal synchronized signal 0
selection bit
1
Reserved bits
Page 216 of 326
)
DIV_VPSSm + 2
When VPS is acquired
DIV_VPS4 to 0,
DIV_VPSS2 to 0
= (00100110)2
DIV_VPS2
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
DIV_VPSn
f DIVV : Horizontal synchronized
signal frequency
The divided value selection
bit of PLL for VPS
DIV_VPS1
HORAX_ON
m-3
+ Σ2
DIV_VPSS2
DIV_VPS0
R
Slice clock frequency fPDC for VPS
is adjusted.
)
×
Analog input
The digital input of HOR
Must set to "0."
×
Ω
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
23. Address 2416 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
Reserved bits
Must set to "880816" when EPG-J is acquired.
Otherwise, set to "000016."
R W
×
24. Address 2516 (=DA5 to 0)
DD15
DD8DD7
0 0 0 1 0 0 1 1 0 0 0
DD0
0 0
Bit symbol
Function
Bit name
R W
0 Normal
ADSEL
A/D conversion slice bit
ADON_TIM
A/D operation control bit
Reserved bits
SLICEON_TIM
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Slice selection bit
digital value after A/D conversion is
1 The
given from outside (with register).
0
1
Programmable
Slice period
Must set to "0."
0
1
Every line (CHECK_START)
Programmable (PRE_START)
Reserved bits
Must set to "0."
×
Reserved bits
Must set to "1."
×
Reserved bits
Must set to "0."
×
Reserved bit
Must set to "1."
×
Reserved bits
Must set to "0."
×
Page 217 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
25. Address 2616 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
DIVP_CK0
Function
Bit name
The clock division value
The divided clock used for the phase
selection bit for phase
comparison with a PDC clock is set up.
comparison with a PDC clock
DIVP_CK1
ffSC = fDIVP ×
7
n
(n=0
Σ 2 DIVS_CKn + 2)
DIVP_CK2
fDIVP: The slice clock frequency
for PDC (please refer to
DIV_PDCS0 to 2 and
DIV_PDC0 to 4
(address 2216).)
DIVP_CK3
DIVP_CK4
When teletext (PDC) data is acquired
DIVP_CK7 to 0 = (00001110)2
DIVP_CK5
When EPG-J is acquired
DIVP_CK7 to 0 = (00001001)2
DIVP_CK6
DIVP_CK7
DIVV_CK0
The clock division value
selection bit for phase
comparison with a VPS clock
The divided clock used for the phase
comparison with a VPS clock is set up.
DIVV_CK1
ffSC = fDIVV ×
DIVV_CK2
DIVV_CK4
fDIVV : The slice clock frequency
for VPS (refer to
DIV_VPSS0 to 2 and
DIV_VPS0 to 4
(address 2316).)
DIVV_CK5
When VPS is acquired
DIVV_CK7 to 0 = (00001110)2
DIVV_CK6
When CC, CC2X and ID-1 are acquired
DIVV_CK7 to 0 = (01010011)2
DIVV_CK3
DIVV_CK7
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
7
n
( n=0
Σ 2 DIVV_CKn + 2)
Page 218 of 326
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
26. Address 2716 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0
Bit symbol
DLYSEL0
Bit name
Function
Data slicer control bit5
These are the control bits of
the ghost correction circuit.
Data slicer control bit6
These are the control bits of
the ghost correction circuit.
R W
DLYSEL1
DLYSEL2
DLYSEL3
DLYSEL4
DLYSEL5
DLYSEL6
DLYSEL7
WEIGHT0
WEIGHT1
WEIGHT2
WEIGHT3
WEIGHT4
Reserved bits
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 219 of 326
Must set to "0."
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
27. Address 2816 (=DA5 to 0)
DD15
DD8DD7
0 0 0 0 0
DD0
0
Bit symbol
Function
Bit name
ADLAT
START
Data acquisition selection bit
Slice data selection bit
Turning on the output after slice RAM
of Flaming code detection position (8 bits)
and the average of the clock run-in level
(8 bits)and turning off are set (note.)
Reserved bit
Acquisition of slice data
Acquisition of A/D data
0
1
Normal
Stop by 6th bit of A/D
Must set to "1" when EPG-J is acquired.
Otherwise, set to "0."
Reserved bit
Synchronous signal slice
level control bit
SYNLVL2 SYNLVL1 SYNLVL0
ADON
Data slicer control bit
0
1
INTAD
The amplifier control bit for
data slicers
0 Always data slicer ON.
SYNLVL0
0
0
0
0
1
1
1
1
SYNLVL1
SYNLVL2
INTDA
1
The rudder resistance control 0
bit for data slicers
1
Reserved bits
0
0
1
1
0
0
1
1
SR000 to SR00F
0 : Slice data
Data1
Data2
Data3
SR010 to SR01F
SR000 to SR00F
SR020 to SR02F SR030 to SR03F
1 : Slice data
Data1
Data2
Flaming code detection location
(8 bits)
Page 220 of 326
Clock run-in average level
(8 bits)
Slice level
approx.1.10V±0.10V
approx.1.15V±0.10V
approx.1.20V±0.10V
approx.1.25V±0.10V
approx.1.30V±0.10V
approx.1.35V±0.10V
approx.1.40V±0.10V
approx.1.45V±0.10V
On 3 to 23 lines and 315 to 335 line amplifier ON.
On other line amplifier OFF
Always ladder resistance for data slicer ON.
On 3 to 23 lines and 315 to 335 line Ladder resistance
ON. On other line Ladder resistance OFF
Must set to "0."
SR030 to SR03F
SR010 to SR01F
SR020 to SR02F
0
1
0
1
0
1
0
1
×
Data slicer OFF.
(The amplifier for slicer is also turned off).
Data slicer ON (see INTAD and the INTDA
about the amplifier for slicer)
Note. Slice RAM: Refer to Figure "Slice RAM bit construction"
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
×
Must set to "0."
A/D lower bit selection bit
6BITOFF
R W
0
1
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
28. Address 2916 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0
Bit symbol
VPS_VP0
Function
Bit name
Setup of a slice start line
(Shared by the first field and
the second field)
VPS_VP1
R W
If a slice start line is made into SLI_VS
At PAL
<The first field>
n
8
SLI_VS = Σ 2 VPS_VPn + 2
n=0
VPS_VP2
<the second field>
8
n
SLI_VS = Σ 2 VPS_VPn + 315
VPS_VP3
n=0
At NTSC
<The first field>
VPS_VP4
n
8
SLI_VS = Σ 2 VPS_VPn + 5
VPS_VP5
n=0
<the second field>
8
VPS_VP6
n
SLI_VS = Σ 2 VPS_VPn + 268
n=0
The data for 18 lines is stored in
Slice RAM from the line set up by
this register.
VPS_VP7
VPS_VP8
Slice ON/OFF control bit
0
1
Slice OFF
Slice ON
SYNCSEP_ON0
Synchronous separate
selection bit
0
1
Synchronous separate circuit OFF
Synchronous separate circuit ON
STBSYNCSEP
Synchronous separate input
control bit
0
1
SYNCIN analog input
SYNCIN digital input
SLI_GO
Reserved bits
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 221 of 326
Must set to "0."
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
29. Address 2A16 (=DA5 to 0)
DD15
DD8DD7
DD0
1 0 0 0 0 0 0 0
Bit symbol
MASK0
R W
Function
Bit name
PAL
NTSC
Mask width for time bases
selection bit.
1135
910
284
MASK1
MASK2
MASK3
The position of mask release is set up
256 steps of setup can be performed in one
fourth of the periods of the back between 1H
18H
to
256H
MASK4
=
Order of 0H to 17H
MASK5
PAL
It cannot set up
MASK6
0H
to
256H
NTSC
MASK7
Usually, please make it 80H
Reserved bits
Must set to "0."
×
Reserved bit
Must set to "1."
×
30. Address 2B16 (=DA5 to 0)
DD15
0
DD8DD7
0 0 0 0
DD0
0 0 0 0 0 0 0
Bit symbol
Function
Bit name
×
Must set to "0."
Reserved bits
× ×
Nothing is assigned.
SEL_PDCH
The internal H selection bit
for data slicers
SEL_PDCH SEL_VPSH
0
0
1
1
SEL_VPSH
Reserved bit
SEL_PDEC The clock selection bit for a PLL lock
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 222 of 326
×
Must set to "0."
Reserved bits
R W
0
1
0
1
External Hsync
From PLL for VPS
From PLL for PDC
VPS or PDC
Must set to "0."
0
1
VPS and a PLL lock from Hsync.
VPS and a PLL lock from a X'tal system.
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
31. Address 2C16 (=DA5 to 0)
DD8DD7
DD15
DD0
1 0 0 0 0 0 0
Bit symbol
Function
Bit name
Slice A/D ON period
selection bit
PLSPOS0
R W
Slice A/D ON period is counted.
V
PLSPOS1
H
PLSPOS2
PLSPOS3
8
H of
PLSPOS4
n
(n=0
Σ 2 PLSPOSn)– th shot
8
PLSPOS5
H of
n
(n=0
Σ 2 PLSNEGn)– th shot
PLSPOS6
PLSPOS7
PLSPOS8
Reserved bits
Must set to "0."
×
Reserved bit
Must set to "1."
×
32. Address 2D16 (=DA5 to 0)
DD15
0 0
DD8DD7
DD0
0 0 0 0
Bit symbol
PLSNEG0
Bit name
Slice-ON period selection bit
Function
R W
Refer to PLSPOS0 to 8
(Address 2C16)
PLSNEG1
PLSNEG2
PLSNEG3
PLSNEG4
PLSNEG5
PLSNEG6
PLSNEG7
PLSNEG8
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Reserved bits
Must set to "0."
×
Reserved bit
Must set to "1" when teletext (PDC)
data is acquired.
×
Reserved bits
Must set to "0."
×
Page 223 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
33. Address 2E16 (=DA5 to 0)
DD8DD7
DD15
DD0
Bit symbol
Bit name
HCOUNT0
Synchronous detection bit
Function
R W
A horizontal synchronized signal is
counted. These bits are reset by set
the VERTX bit (address 3316) to "0."
HCOUNT1
HCOUNT2
HCOUNT3
HCOUNT4
HCOUNT5
HCOUNT6
HCOUNT7
HCOUNT8
HCOUNT9
HCOUNT10
HCOUNT11
HCOUNT12
HCOUNT13
HCOUNT14
HCOUNT15
34. Address 2F16 (=DA5 to 0)
DD15
DD8DD7
DD0
0
Bit symbol
Function
Bit name
× ×
Nothing is assigned
Reserved bit
STB_RES
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REJ03B0152-0210
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Set to "0" usually
Extended register all reset bit
R W
0
1
Normal
It resets to address 0016 to the address
2E16 extended register.
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
35. Address 3016 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
R W
× ×
Nothing is assigned
36. Address 3116 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Function
Bit name
R W
× ×
Nothing is assigned
37. Address 3216 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
RMHTD0(0)
Remote control header length
selection bit
Function
R W
In order to detect a remote control
pulse in standby mode, the header
length to the oscillation for clocks
(address 3216) is chosen.
RMHTD0(1)
Remote
control
pulse
RMHTD0(2)
B
RMHTD0(3)
A
D
C
Effective
pulse
width
Header part
RMHTD0(4)
8
n
A = TXCIN × Σ 2 RMHTD0(n)
n=0
8 n
RMHTD0(5)
C = TXCIN × Σ 2 RMHTD1(n)
n=0
5
RMHTD0(6)
B = TXCIN × FILDIV0 × Σ YUKOU0(n)
n=0
5
D = TXCIN × FILDIV0 × Σ YUKOU1(n)
RMHTD0(7)
n=0
TXCIN : XCIN pin input cycle
Division value set by FILDIV0 (bit 9 of
address 3316)
RMHTD0(8)
JSTCKDIV0
Clock division value of JUST
CLOCK filter selection bit.
JSTCKDIV1 JSTCKDIV0 Main clock divided value
0
0
1
1
JSTCKDIV1
JSTCKON
ON/OFF of JUST CLOCK
filter selection bit.
0
1
0
1
0
1
Filter OFF
Filter ON
× ×
Nothing is assigned.
RMTSEL
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Remote control header
polarity selection bit
32 divided
64 divided
128 divided
256 divided
0
No reverse
1
reverse
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
38. Address 3316 (=DA5 to 0)
DD8DD7
DD15
0
DD0
0
Bit symbol
Bit name
RMHTD1(0)
Remote control header length
selection bit
Function
R W
Refer to RMHTD0 (0) to (8)
(address 3216).
RMHTD1(1)
RMHTD1(2)
RMHTD1(3)
RMHTD1(4)
RMHTD1(5)
RMHTD1(6)
RMHTD1(7)
RMHTD1(8)
FILDIV0
Clock division value of remote Clock division value for Remote control tolerance period
measurement is selected. (Note 1)
control pulse selection bit
FILDIV0
0
1
Reserved bit
Must set to "0. "
FILON
Filter ON/OFF of remote control 0
pulse selection bit (Notes 2, 3) 1
VERTX
Synchronous detection
reset bit
Reserved bit
FILDIV1(0)
Sub clock divided value
No divided
2
0
1
OFF
ON
Reset
Horizontal synchronized signal count
Must set to "0. "
Filter of remote control clock
divide value selection bit
FILDIV1(1)
FILDIV1(1)
0
0
1
1
FILDIV1(0) Sub clock divided value
2
0
4
1
8
0
16
1
Notes 1. Refer to RMHTD0 (0) to (8) (address 3216)
Notes 2. Change these bits at initialization and do not rewrite during remote control receive.
Notes 3. The remote control pulse filter is only for the sub clock. Set it to OFF
when the sub clock is not mounted.
39. Address 3416 (=DA5 to 0)
DD15
DD8DD7
DD0
0 1 1 1 0 0 0 0
Bit symbol
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Bit name
Function
Reserved bits
Must set to "7016."
Reserved bits
Must set to "DD16" when EPG-J is
acquired.
Otherwise, set to "0016."
Page 226 of 326
R W
×
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
40. Address 3516 (=DA5 to 0)
DD15
DD8DD7
DD0
0 0 0 0 0 1 1
Bit symbol
Bit name
HINT_LINE0
H_INT interruption position
selection bit
Function
HINT_LINE1
V
HINT_LINE2
H
HINT_LINE3
R W
A period after V is inputted until
H_INT rises is counted.
H_INT
HINT_LINE4
8 n
Σ 2 HINT_LINEn
n=0
HINT_LINE5
HINT_LINE6
HINT_LINE7
HINT_LINE8
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Reserved bits
Must set to "1."
Reserved bits
Must set to "0."
Reserved bit
Must set to "0."
Page 227 of 326
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
41. Address 3616 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
VINT0
Bit name
SLICEON interruption control test bit
VINT1
Function
0000 : Interrupt disabled (Note 3)
1011 : Interrupt enabled
Others : Do not set up
When the period of data acquisition
expires, the interrupt occurs by setting
these bits to 1011.
Set up the TB5IC register (Note 4)
when use by “Interrupt enabled.”
VINT2
VINT3
Remote control interruption
control bit (Note 1)
INTRMT1
0000 : Interrupt disabled (Note 3)
1010 : Interrupt enabled
Others : Do not set up
INTRMT2
Set up the TB4IC register (Note 4)
when use by “Interrupt enabled.”
INTRMT0
R W
INTRMT3
HINT0
HINT interruption control test
bit (Note 2)
HINT1
0000 : Interrupt disabled (Note 3)
1001 : Interrupt enabled
Others : Do not set up
Set up the TB3IC register (Note 4)
when use by “Interrupt enabled.”
HINT2
HINT3
SECINT0
Clock timer interruption
control bit
0000 : Interrupt disabled (Note 3)
1000 : Interrupt enabled (Note 5)
SECINT1
Others : Do not set up
SECINT2
Set up the TB2IC register (Note 4)
when use by “Interrupt enabled.”
SECINT3
Notes 1. Refer to 15.6 Expansion Register Construction Composition.
Notes 2. Refer to the function of HINT_LINEn (Address 3516.)
Notes 3. Set these bits to 0000 when use the interrupt of Timer B2, Timer B3, Timer B4, or Timer B5.
Notes 4. Refer to Figure 6.3 Interrupt Control Registers.
Notes 5. When the second counter (Address 3916) is changed, an interrupt is generated every 1 second.
Notes 6. Please do not change data after setting initial data to address 3616 corresponding interrupt
control bit VINTi, INTRMTi, HINTi, and SECINTi (i = 0 to 3) when you use the SLICEON, remote
control, HINT, and the clock timer interrupt.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
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M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
42. Address 3716 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
YUKOU0(0)
YUKOU0(1)
Bit name
Remote control header
judging pulse length
selection bit 0
Function
R W
Refer to RMTHD0(0) to (8)
(Address 3216)
YUKOU0(2)
YUKOU0(3)
YUKOU0(4)
YUKOU0(5)
× ×
Nothing is assigned.
YUKOU1(0)
Remote control header
judging pulse length
selection bit 1
Refer to RMTHD0(0) to (8)
(Address 3216)
YUKOU1(1)
YUKOU1(2)
YUKOU1(3)
YUKOU1(4)
YUKOU1(5)
× ×
Nothing is assigned.
43. Address 3816 (=DA5 to 0)\
DD15
DD8DD7
DD0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit symbol
Reserved bit
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Bit name
Function
Must set to "0."
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
44. Address 3916 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
SECOUT0
Clock Timer Second Setting Bit
SECOUT1
Function
R W
Set seconds (0 to 59 seconds) of
clock timer.
The settable values are 0 to 59.
SECOUT2
SECOUT3
SECOUT4
SECOUT5
× ×
Nothing is assigned.
RTCON
Clock Timer Operation
Selection Bit
0
1
Clock timer stops
Clock timer operates
× ×
Nothing is assigned.
SECJUST
Second Just Setting Bit
When writing "1", less than second of
the clock timer is reset.
When reading, the value is "0".
×
45. Address 3A16 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
MINOUT0
Clock Timer Minute Setting Bit
MINOUT1
Function
R W
Set hours and minutes of the clock
timer by the minute.
The settable values are 0 to 1439
(00:00 to 23:59)
MINOUT2
MINOUT3
MINOUT4
MINOUT5
MINOUT6
MINOUT7
MINOUT8
MINOUT9
MINOUT10
Nothing is assigned.
Rev.2.10
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× ×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
46. Address 3B16 (=DA5 to 0)
DD15
DD8DD7
DD0
Bit symbol
Bit name
DAYCUONT0
Clock Timer Day Setting Bit
DAYCUONT1
DAYCUONT2
DAYCUONT3
DAYCUONT4
DAYCUONT5
DAYCUONT6
DAYCUONT7
DAYCUONT8
DAYCUONT9
DAYCUONT10
DAYCUONT11
DAYCUONT12
DAYCUONT13
DAYCUONT14
DAYCUONT15
Rev.2.10
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Function
Set days of the clock timer.
The settable value are 0 to 65535.
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
47. Address 3C16 (=DA5 to 0) (Note 1)
DD15
DD8DD7
DD0
Bit symbol
RMTSTART
IRPOL(0)
Carrier selection bit
The output mode of remote control transmission
wave form is selected.
000: External wave, Carrier and AND output.
010: External wave, Carrier and OR output.
101: Only external wave is output (carrier none.)
Additionally: Setting prohibition.
Carrier clock source
selection bit
Carrier's clock source is selected.
00: The main clock (There is not dividing frequency.)
01: 2.5 dividing of the main clock.
10: 8 dividing of the main clock.
11: Setting prohibition.
External wave clock source
selection bit
The clock source of external wave is selected.
00: The main clock (There is not dividing frequency.)
01: 8 dividing of the main clock.
10: 64 dividing of the main clock.
11: 256 dividing of the main clock.
IRPOL(1)
IRPOL(2)
RMCDIV(0)
RMCDIV(1)
RMTDIV(0)
RMTDIV(1)
RMT_TM(0)
RMT_TM(1)
Function
Bit name
Remote control transmission Start and the stop of wave form output is selected.
start bit
0: Stop
1: Start
External wave clock dividing Dividing frequency value which is selected by
RMTDIV(1, 0)
frequency value setting bit
Set RMT_TM.
7
RMT_TM(2)
RMT_TM = Σ 2n · RMT_TM0(n)
n=0
RMT_TM(3)
RMT_TM(4)
RMT_TM(5)
RMT_TM(6)
RMT_TM(7)
Note 1. Refer to 14.6 "(6) Remote control transmission function."
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
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R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
48. Address 3D16 (=DA5 to 0) (Note 1)
DD15
DD8DD7
DD0
Bit symbol
Bit name
RMT_TML(0)
Carrier L period setting bit
Function
R W
Carrier's L period is set.
7
RMT_TML = Σ 2n · RMT_TML(n)
RMT_TML(1)
n=0
RMT_TML(2)
RMT_TML(3)
RMT_TML(4)
RMT_TML(5)
RMT_TML(6)
RMT_TML(7)
RMT_TMH(0)
Carrier H period setting bit
Carrier's H period is set.
7
RMT_TMH(1)
RMT_TMH = Σ 2n · RMT_TMH(n)
n=0
RMT_TMH(2)
RMT_TMH(3)
RMT_TMH(4)
RMT_TMH(5)
RMT_TMH(6)
RMT_TMH(7)
Note 1. Refer to 14.6 "(6) Remote control transmission function."
49. Address 3E16 (=DA5 to 0) (Note 1)
DD15
DD8DD7
0
DD0
0
Bit symbol
RMTTXINT(0)
RMTTXINT(1)
Bit name
Function
R W
Remote control transmission 0000: Interrupt prohibition (Note 2)
interrupt control
0001: Interrupt permission
(Note 1, Note 4)
Additionally: Setting prohibition
Please set INT2IC register when using
it by "Interrupt permission."
RMTTXINT(2)
RMTTXINT(3)
Reserved bit
Must set to "0."
Nothing is assigned.
IROUT_SLICEON
Reserved bit
P84 output signal selection
bit 2 (Note 3)
0: Normal setting (When use P84 I/O
port or INT2 interrupt.)
1: Remote control transmission pulse
output
Must set to "0."
Notes 1. Refer to 14.6 "(6) Remote control transmission function."
Notes 2. Set and use 00002 when use INT2 interrupt.
Notes 3. Set "1" to bit b4 of port P8 direction register when use the remote control transmission
function.
Notes 4. Please do not change data after setting the initialization data to remote control
transmission interrupt control bit RMTTXINT(i) (i = 0 to 3) when you use the remote control
transmission interrupt.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
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M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
50. Address 3F16 (=DA5 to 0) (Note 1)
DD15
DD8DD7
DD0
0
Bit symbol
Bit name
Function
R W
Nothing is assigned.
Reserved bit
Must set to "0."
Note 1. Refer to 14.6 "(6) Remote control transmission function."
51. Address 4016 (=DA5 to 0)
CD15
CD8CD7
CD0
Bit symbol
FPLS_MIN0
Bit mane
Fixed length pulse lower
bound value setting bit
Function
R W
The fixed length pulse lower
bound value is set. (note 1)
FPLS_MIN1
FPLS_MIN2
FPLS_MIN3
FPLS_MIN4
FPLS_MIN5
FPLS_MIN6
FPLS_MIN7
FPLS_MAX0
Fixed length pulse upper
bound value setting bit
The fixed length pulse upper
bound value is set. (note 1)
FPLS_MAX1
FPLS_MAX2
FPLS_MAX3
FPLS_MAX4
FPLS_MAX5
FPLS_MAX6
FPLS_MAX7
*Note 1: The fixed value pulse is a pulse ("H" or "L" part) where 0/1 is not judged. It does according to enhancing register VBITPOL
(Address 4316 and bit 13) at H period of 0/1 judgments or it does at L period or it selects it.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
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M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
52. Address 4116 (=DA5 to 0)
CD15
CD8CD7
CD0
Bit symbol
DT0_MIN0
Bit name
"0" data pulse length lower
bound value setting bit
Function
"0" data pulse length lower bound
value is set.
DT0_MIN1
DT0_MIN2
DT0_MIN3
DT0_MIN4
DT0_MIN5
DT0_MIN6
DT0_MIN7
DT0_MAX0
DT0_MAX1
DT0_MAX2
DT0_MAX3
DT0_MAX4
DT0_MAX5
DT0_MAX6
DT0_MAX7
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 235 of 326
"0" data pulse elder limit value "0" data pulse elder limit value is set
setting bit
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
53. Address 4216 (=DA5 to 0)
CD15
CD8CD7
CD0
Bit symbol
DT1_MIN0
Bit name
"1" data pulse length lower
bound value setting bit
Function
"1" data pulse length lower bound
value is set.
DT1_MIN1
DT1_MIN2
DT1_MIN3
DT1_MIN4
DT1_MIN5
DT1_MIN6
DT1_MIN7
DT1_MAX0
DT1_MAX1
DT1_MAX2
DT1_MAX3
DT1_MAX4
DT1_MAX5
DT1_MAX6
DT1_MAX7
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 236 of 326
"1" data pulse elder limit value "1" data pulse elder limit value is set.
setting bit
R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
54. Address 4316 (=DA5 to 0)
CD15
CD8CD7
CD0
Bit symbol
Bit name
Function
The maximum reception
bit number setting bit
The number of maximum reception
bits is set.
Minimum reception bit
number setting bit
The number of minimum reception
bits is set.
RMTLSB
LSB/MSB reception selection
bit
0:It receives it with MSB.
1:It receives it with LSB.
VBITPOL
0/1 judgment level selection bit
0:0/1 is judged at L period.
1:0/1 is judged at H period.
INTSEL
Interrupt selection bit
MAXBIT0
R W
MAXBIT1
MAXBIT2
MAXBIT3
MAXBIT4
MAXBIT5
MINBIT0
MINBIT1
MINBIT2
MINBIT3
MINBIT4
MINBIT5
GET_DATA
Rev.2.10
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Page 237 of 326
Bit that takes data
0:After it matches it, interrupt is
generated.
1:When a reception of the data of
the 16th bit and the maximum data
are received, interrupt is generated
1:When "1" is written from the
reception buffer in the reception
register, the data of the reception
buffer is written in the reception
register.
(The value when reading it is 0. )
×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
55. Address 4416 (=DA5 to 0)
CD15
CD8CD7
CD0
Bit name
Bit symbol
DATAOL0
Number of receive data
bits
Function
R W
The number of bits of received
data is displayed.
DATAOL1
DATAOL2
×
DATAOL3
DATAOL4
DATAOL5
NU0
Number of receive data
words
16 piece nbit data was received.
(n=0,1,2)
×
NU1
INTRMTFL0
INTRMTFL1
One word reception
completion flag
Flag that received data of
number of maximum bits
0:The data of the number of maximum
bits was not received.
1:The data of the number of
maximum bits was received
×
×
INTRMTFL2
Flag that received the
data everything
0:Everything did not receive the data.
1:Everything received the data.
×
NG
NG flag bit of reception
1:There was NG while receiving it.
×
Nothing is assigned.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
The reception completion of 0/1 data
for one word (16 bits) is shown.
0:The data of the 16th bit is not
received.
1:The data of the 16th bit was received
Page 238 of 326
× ×
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
56. Address 4516 (=DA5 to 0)
CD15
CD8CD7
CD0
Bit symbol
RMTDA0
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Bit name
Reception register
Function
The received data ("H" data 0/1
judgments by the period of "L")
is stored.
R W
×
RMTDA1
×
RMTDA2
×
RMTDA3
×
RMTDA4
×
RMTDA5
×
RMTDA6
×
RMTDA7
×
RMTDA8
×
RMTDA9
×
RMTDA10
×
RMTDA11
×
RMTDA12
×
RMTDA13
×
RMTDA14
×
RMTDA15
×
Page 239 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
14.6
14. EXPANSION FUNCTION
Expansion Register Construction Composition
(1) Acquisition timing
The SLICEON signal is output in the acquisition possible period.
Vertical blanking erase period pulse
The first field
Acquisition possible period
6 2 6
2
5
2
23 6 4 62
1
2
3
4
5
6
7
8
9
1
9
20
21
22
23
24
SLICEON output period
The second field
310 311 312 313 314 315 316
317 318 319 320 321
331 332 333 334 335 336
The scanning lines number in figure is corresponds to slice RAM.
This is the line to support when the PAL video signal is sliced and setting the expansion registers to
VPS_VP8 to VPS_VP0 (bits 8 to 0 in address 2916) = "416".
Figure 14.11
Expansion register access registers composition
(2) Synchronized signal detection circuit
The number of pulses of the horizontal synchronized signal of a compound video signal is counted during a fixed
period. The horizontal synchronous number of pulses can always be read from an expansion register.
A block diagram is shown in Figure. 14.12.
Address bus
Data bus
The arbitration circuit for
expansion registers
Latch
Q
HOR
T
16bit counter
Possible to count C00016 at maximum.
Figure 14.12
Block diagram of Synchronized detection circuit
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M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
(3) Register related to Slicer
The relation between V, H signal, and the register related to slicer is shown in Figure. 14.13 and Figure. 14.14.
V after
SYNC separation
VPS_VP 0 to 8 (address 2916)
Setting the slice start line
After V input
•••
The first line The second line
The nth line The (n+1)th line The (n+17)th line
H after
SYNC separation
After slice start
The 0th line The 1th line
On the odd field
LN0_OD1
LN0_OD0
On the even field
LN0_EV1
LN0_EV0
On the odd field
LN1_OD1
LN1_OD0
On the even field
LN1_EV1
LN1_EV0
The 17th line
On the odd field
LN17_OD1
LN17_OD0
On the even field
LN17_EV1
LN17_EV0
•••
Selection of a state register (addresses 00 to 0516)
(18 lines)
Figure 14.13
Register related to slicer (1)
Clock
GETPEEK2
SELVCO, DIVS0 to 1
(Addresses 0A, 11, 1816)
(Addresses 06, 0D, 1416)
Selection of the clock
Selection of the clock for slice
GET_HP0 to 1
compensation after
HOGO2(Addresses 09, 10, 1716)
(Addresses 0A, 11, 1816)
a peak detection
Selection of the clock for
Phase adjustment
period end
data acquisition
Clock run-in
Framing code
Data
H after
sync separation
SLSLVL0 to 1(Addresses 09, 10, 1716)
Slice level measurement period selection
Fixed
6 cycles
GETPEEK3
(Addresses 0A, 11, 1816)
A mountain and valley
detection selection
SLS_HP0 to 7(Addresses 0A, 11, 1816)
Setting slice check start position
Figure 14.14
Register related to slicer (2)
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Fixed
FLC0 to 15
(Addresses 07, 0C, 1316)
Framing code selection
CHK_FLC0 to 15
(Addresses 08, 0D, 1416)
Framing code check selection
BIFON(Addresses 07, 0C, 1316)
Data formal selection
M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
(4) Remote control pattern recognition
Pattern matching of remote control is performed using a sub clock oscillation. Remote control input is input from
RMTIN terminal. Interruption is generated when pattern matching is in agreement.
4 times match noise filter is being included, in front of the pattern matching circuit. A block diagram is shown in
Figure 14.15.
The example of a waveform of pattern matching is shown in Figure.14.16. The flow of pattern matching is shown
in Figure.14.17.
Sub clock fc
divider
FILDIV1(1, 0)
bit
FILDIV0
bit
Four time
agreement
Filter
P94/TB4in
/RMTin
Polarity
selection
Header pattern
match circuit
Port 94
Input buffer
Timer B4
Timer B4/remote control
interrupt request
Interruption
Control
A period:RMTHD0
B period:YUKOU0
C period:RMTHD1
D period:YUKOU1
RMTSEL
bit
FILON
bit
Figure 14.15
divider for
B/D period
INTRMT3 to 0
bit
Timer B4 interrupt
Remote control pattern recognition block diagram
RMTIN
B
D
C
A
Header
0 data
1 data
The number of registers
At maximum check time
A
"L" check programmable
9 bit
B
Check of a rising edge
6 bit
C
"H" check programmable
9 bit
D
Check of a falling edge
6 bit
15.6 ms
3.8 ms (Note 2)
15.6 ms
3.8 ms (Note 2)
Note 1. 1bit unit 32.768kHz (a part for one clock)
Note 2. The maximum check period of B and D is the values when enhancing register FILDIV0
(Address 3316) is set to "1".
Figure 14.16
Example of waveform of pattern matching
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14. EXPANSION FUNCTION
Initial pulse waiting state
Detect a
falling edge?
No
Yes
Retain
the "L" state
during A?
No
Yes
Detect
a rising edge
during B?
No
Yes
Retain
the "H" state
during C?
No
Yes
Detect
a falling edge
during D?
No
Yes
Interruption generating
Figure 14.17
Flow of pattern matching
4 times match process operation
This is a 4 times match digital filter using the sub clock oscillation. The input signal of the RMTin pin is sampled
4 times and the output level will change only when the level matches 4 times. When using this filter, set the
FILON bit (bit11) in the expansion register 33H to "1". The signal after passing 4 times match filter is applied to
the header pattern matching circuit and timer B4 at filter ON. The sampling rate can be changed by the FILDIV1
(1, 0) bit in the expansion register 33H. Refer to the FILDIV1 bit of the expansion register 33H function
description for details. The input signal is through supplied to the latter circuit at filter OFF. (no clock
delay).Since this filter operates only with the sub clock and cannot be used for the main clock, set the filter to OFF
(FILON bit ="0") when the sub clock is not mounted.
(5) Clock timer function
The sub clock is selected as the count source and the clock timer can set and read the count value every day,
minute and second. It has the following functions.
Clock function
1.This timer is dedicated clock function which is independent from timer A and timer B.
2.The settable ranges of day, minute and second are 0 to 65535 days, 0 to 1439 minutes and 0 to 59 seconds.
3.Second just setting is available (reset the count value of less than second).
1 second interrupt
1.The interrupt request is generated when second of the clock timer is incremented.
(The interrupt request is not generated at the second just setting.)
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14. EXPANSION FUNCTION
(6) Remote control transmission function
The career is synthesized to two kinds of pulses of external wave, and the remote control transmission circuit is
output from the microcomputer pin.
The specification of the remote control transmitter is shown in Table 14.5, The remote control transmission circuit
output wave form is shown in Figure 14.18, and The remote control transmission circuit block chart is shown in
Figure 14.19.
The feature is shown below.
• Career is a continuous pulse of the arbitrary width obtained by dividing the main clock (Figure 14.18 Wave
forms 2 and 3.)
• External wave is a shape of waves generated from the transmission data buffer with reading pin output value
("H"/"L") and the pulse width one by one (Figure 14.18 Wave form 4.)
• The shape of waves that can synthesize the career to external wave is output from the pin (Figure 14.18 Wave
form 5.)
Table 14.5
Specification of remote control transmission function
Item
Specifications
Count source
Carrier: Selection from f1 (There is not XIN dividing frequency), f2.5 (XIN 2.5
dividing frequency), and f8 (XIN 8 dividing frequency.)
External wave: Selection from f1 (There is not XIN dividing frequency), f8 (XIN
8 dividing frequency), f64 (XIN 64 dividing frequency), and f256
(XIN 256 dividing frequency.)
Count operation
(carrier)
Down count
The register for “H” width setting is read by standing up about the pulse, and
it continues the count.
The register for “L” width setting is read by standing up about the pulse, and
it continues the count.
Comparing of dividing
frequency (carrier)
“H” period and “L ” period are 1 to 256.
Count operation
(external wave)
Down count
Wave form output value (“H”/“L”) and the count value are read from the
remote control transmission data buffer with stand up/fall down of the pulse,
and the port output and the count are continued.
Comparing of dividing
frequency (external
wave)
1 to 16384 (14bit)
Start of counting
condition
The remote control transmission start bit is set to “1.”
Count stop condition
The remote control transmission start bit is set to “0.”
After the untransmission data number reference bit is empty and the count
value is underflow
Interrupt generation
timing
When external wave stand up/fall down (When the value of the interrupt
setting bit read from the remote control transmission data buffer is only 1. )
Remote control
transmission mode
OR output of career and external wave
Only external wave is output (carrier none.)
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M306H7MG-XXXFP/MC-XXXFP/FGFP
14. EXPANSION FUNCTION
1) Count source
(f1/f2.5/f8)
H period
L period
2) Transportation wave form
(axis expansion of time)
3) Transportation wave form
(axis reduction of time)
4) External wave form
T0 period
5) P8-4 pins wave form
6) Interrupt request signal
Figure 14.18
Remote control transmission circuit output wave form
L period
H period
Clock
f1
f2.5
f8
Remote control
transmission pulse
Career
Career timer
External
wave
Career generation part
External wave generation part
f1
f8
f64
f256
underflow
External wave generation circuit
Interrupt
request
b15
Remote control
transmission data buffer
(FIFO 7 words)
Writing-in
counter
Reading-out selector
Writing-in selector
Data bus
Clock
.....
Number of
untransmission data
b13
External wave pulse period set bit
Interrupt setting bit
External wave output data
setting bit
Reading-out
counter
. . . Register
WR
Figure 14.19
b0
Remote control transmission circuit block chart
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14. EXPANSION FUNCTION
Remote control transmission data buffer register
DD15
DD8DD7
DD0
Symbol
RMT_TMHL
Bit symbol
RMT_TMHL (0)
RMT_TMHL (1)
Address
When reset
200 16
000016
Bit name
Function
External wave pulse period
setting/Untransmission data
number reference bit
When writing in: Set one pulse period of the remote
control transmission external wave.
When reading out: The number of data (number of
untransmission data) that remains in the remote
control transmission data buffer is read out.
Interrupt setting bit
The presence of the interrupt generation is specified at
the change of the external wave output.
0:The interrupt request signal is not generated.
1:The interrupt request signal is generated.
External wave output data
setting bit
The remote control transmission external wave data
is set.
RMT_TMHL (2)
RMT_TMHL (3)
RMT_TMHL (4)
RMT_TMHL (5)
RMT_TMHL (6)
RMT_TMHL (7)
RMT_TMHL (8)
RMT_TMHL (9)
RMT_TMHL (10)
RMT_TMHL (11)
RMT_TMHL (12)
RMT_TMHL (13)
RMT_TMHL (14)
RMT_TMHL (15)
Figure 14.20
Setting of enhancing register (Only the part related to the remote control
transmission.)
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R W
M306H7MG-XXXFP/MC-XXXFP/FGFP
14.7
14. EXPANSION FUNCTION
8/4 Humming Decoder
8/4 humming decoder operates only by written the data which is 8/4 humming- encoded to 8/4 humming register
(address 021A16). 8/4 humming register consists of 16 bits, can decode two data at once. Can obtain the decoded
result by reading 8/4 humming register, and the decoded value and error information are output. Corrects and
outputs the decoded value for single error, and outputs only error information for double error. Decoded result is
shown in Figure 14.21 and humming 8/4 register composition is shown in Figure 14.22.
Humming data (2)
Humming data (1)
LSB MSB
MSB
LSB
Writing
Address
021A16
8/4 humming register
Reading
Error information
(2)
0
0
Error information
(1)
0
0
“1” output when
single error
Decode value
(2)
MSB
LSB
Decode value
(1)
LSB
MSB
“1” output when single error
“1” output when double error
“1” output when double error
Figure 14.21
Decoded result
Humming 8/4 register
b15
b8 b7
b0
Symbol
HM8
Address
021A16
When reset
000016
Function
8/4 humming decoder operates only by written the data which 8/4 humming-decoded to 8/4
humming register. Can obtain the decoded result by reading this register, and can decode 2
couples of data at the same time.
Figure 14.22
Humming 8/4 register composition
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14.8
14. EXPANSION FUNCTION
24/18 Humming Decoder
24/18 humming decoder operates only by written the data which is 24/18 humming-encoded to 24/18 humming
register 0 (address 021C16) and 1 (address 021E16). Can obtain the decoded result by reading the same 24/18
humming register, and the decoded value and error information are output.
Decoded result is shown in Figure 14.23 and humming 24/18 register composition is shown in Figure 14.24.
Humming data M
Humming data H
Humming data L
MSB
LSB
Writing
Writing
Address
24/18 humming register 1
021E16
Reading
Reading
Error information
0
0
0
0
0
0
0
Address
021C16
24/18 humming register 0
0
0
Decode
value
MSB
Decode value
LSB
“1” output when single error
“1” output when double error
Figure 14.23
The mistake by one pile is corrected and output.
Decoded result
Humming 24/18 register 0
b15
8
7
0
Symbol
HM0
Address
021C16
When reset
000016
Function
R W
24/18 humming decoder operates by two ways : writing data low-order and middle-order 16
bits to this register and writing data high-order 8 bits to humming 24/18 register 1 (021E16).
Can obtain the decoded result by reading this register and humming 24/18 register 1.
Humming 24/18 register 1
b15
8
7
0
Symbol
HM1
Address
021E16
When reset
000016
Function
24/18 humming decoder operates by two ways : writing data low-order and middle-order 16
bits to humming 24/18 register 0 (021C16) to this register and writing data high-order 8 bits
to this register.
Can obtain the decoded result by reading this register and humming 24/18 register 0.
Figure 14.24
Humming 24/18 register composition
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14. EXPANSION FUNCTION
Continuous error correction
When uses humming 8/4 (address 021A16) at the same time as humming 24/18, can do the continuous error
correction.
Continuous error correction sequence is shown in Figure 14.25.
A
Humming data (1)
M
Humming data (1)
L
B
Humming data (2)
L
Humming data (1)
H
C
Humming data (2)
H
Humming data (2)
M
D
Humming data (3)
M
Humming data (3)
L
E
Humming data (4)
L
Humming data (3)
H
F
Humming data (4)
H
Humming data (4)
M
Figure 14.25
1. Writes data A to address 021C 16 and writes data B to address
021E 16. (Setting the humming data (1) and L of humming data (2).)
2. Reads addresses 021C16 and 021E16 data (Obtains the decoded
value and error information on the humming data (1)).
3. Writes data C to address 021A16 (Setting H and M of the humming data (2)).
4. Reads addresses 021C16 and 021E16 data (Obtains the decoded value
and error information on the humming data (2)).
5. Writes data D to address 021C16 and writes data E to 021E16 (Setting
the humming data (3) and L of humming data (4).)
6. Reads addresses 021C16 and 021E16 data (Obtains the decoded value
and error information on the humming data (3)).
7. Writes data F to address 021A16 (Setting H and M of the humming data (4)).
8. Reads addresses 021C16 and 021E16 data (Obtains the decoded value
and error information on the humming data (4)).
Continuous error correction sequence
Then, because using a part of circuit of humming 8/4 about this operation, cannot use this operation at the
same time.
When using the humming circuit, do the decoded result reading operation at once after the setting data of
humming. And do not access other memories (Including the humming circuit) before reading of the decoded
result.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
14.9
14. EXPANSION FUNCTION
I/O Composition of pins for Expansion Function
Figure 14.26 and figure 14.27 show pins for expansion function.
VCC2
CVIN1
input
for slicer
(Note 2)
VSS
SYNCIN
from internal circuit
to internal circuit
VDD2
VCC2
from internal circuit
input
(Note 2)
VSS
to internal
circuit
VSS2
VDD2
LP3, LP4
V DD2
output
from internal circuit
(Note 2)
VSS
to internal circuit
VSS2
Notes 1. Refer to expansion register composition (Address 3516.)
Notes 2.
This is a parasitic diode.
The applied voltage to each port should hot exceed VCC.
(VCC: VCC2 for CVIN1 and SYNCIN, and VDD2 for LP3 and LP4.)
Figure 14.26
Pins for expansion function (1)
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14. EXPANSION FUNCTION
VCC2
VCCOFF
to internal circuit
input
(Note 1)
VSS
VSS2
VCC2
STARTB
to internal circuit
input
VSS
Note 1.
This is a parasitic diode.
The applied voltage to each port should hot exceed VCC.
(VCC=VCC2)
Figure 14.27
Pins for expansion function (2)
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M306H7MG-XXXFP/MC-XXXFP/FGFP
15. PROGRAMMABLE I/O PORTS
15. Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 79 lines P0 toP9 (except
P85). Each port can be set for input or output every line by using a direction register, and can also be chosen to be or
not be pulled high every 4 lines. P85 is an input-only port and does not have a pull-up resistor. Port P85 shares the pin
with NMI, so that the NMI input level can be read from the P8 register P8_5 bit.
Figures 15.1 to 15.5 show the I/O ports. Figure 15.6 shows the I/O pins.
Each pin functions as an I/O port, a peripheral function input/output.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is used as
a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as an output pin for
peripheral functions is directed for output no matter how the corresponding direction bit is set.
15.1
Port Pi Direction Register (PDi Register, i = 0 to 9)
Figure 15.7 shows the direction registers.
This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one
for one to each port.
No direction register bit for P85 is available.
15.2
Port Pi Register (Pi Register, i = 0 to 9)
Figure 15.8 show the Pi registers.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register. The Pi
register consists of a port latch to hold the output data and a circuit to read the pin status. For ports set for input
mode, the input level of the pin can be read by reading the corresponding Pi register, and data can be written to the
port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data can be
written to the port latch by writing to the Pi register. The data written to the port latch is output from the pin. The
bits in the Pi register correspond one for one to each port.
15.3
Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2
Registers)
Figure 15.9 shows the PUR0 to PUR2 registers.
The PUR0 to PUR2 register bits can be used to select whether or not to pull the corresponding port high in 4 bit
units. The port chosen to be pulled high has a pull-up resistor connected to it when the direction bit is set for input
mode.
15.4
Port Control Register
Figure 15.10 shows the port control register.
When the P1 register is read after setting the PCR register’s PCR0 bit to “1”, the corresponding port latch can be
read no matter how the PD1 register is set.
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P00 to P07
(There are inside
of broken lines)
P20 to P27, P30 to P37,
P40 to P47, P50 to P54,
P56
(There is nothing inside
of broken lines)
15. PROGRAMMABLE I/O PORTS
Pull-up selection
Direction register
Port latch
Data bus
(Note 1)
Analog input
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Port latch
Data bus
(Note 1)
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction
register
P57, P60, P64, P73, P76,
P80, P81, P84, P90, P92
"1"
Output
Port latch
Data bus
(Note 1)
Input to respective peripheral functions
Note 1:
Figure 15.1
I/O Ports (1)
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symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
(VCC: VCC1 for the port P6 to P7 and P80 to P84, and VCC2 for the
port P0 to P5, P85 to P87 and P9.)
M306H7MG-XXXFP/MC-XXXFP/FGFP
15. PROGRAMMABLE I/O PORTS
Pull-up selection
Direction
register
P61, P65, P72
"1"
Output
Port latch
Data bus
Switching
between
CMOS and
Nch
(Note 1)
Input to respective peripheral functions
Pull-up selection
P82 to P83
Direction register
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P55, P77, P91, P97
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Note 1:
Figure 15.2
I/O Ports (2)
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symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
(VCC: VCC1 for the port P6 to P7 and P80 to P84, and VCC2 for the
port P0 to P5, P85 to P87 and P9.)
M306H7MG-XXXFP/MC-XXXFP/FGFP
15. PROGRAMMABLE I/O PORTS
Pull-up selection
Direction register
P62, P66
Port latch
Data bus
(Note 1)
Switching
between
CMOS and Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67, P74, P75
"1"
Port latch
Data bus
Output
(Note 1)
Switching between CMOS and Nch
P85
Data bus
NMI interrupt input
(Note 1)
Direction register
P70, P71
"1"
Output
Data bus
Port latch
(Note 2)
Input to respective peripheral functions
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
(VCC: VCC1 for the port P6 to P7 and P80 to P84, and VCC2 for the
port P0 to P5, P85 to P87 and P9.)
Note 2:
symbolizes a parasitic diode.
Figure 15.3
I/O Ports (3)
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15. PROGRAMMABLE I/O PORTS
Pull-up selection
Direction register
P93, P94
Data bus
Port latch
(Note)
Input to respective peripheral functions
Pull-up selection
Direction register
P96
"1"
Port latch
Data bus
Output
(Note)
Analog input
Pull-up selection
Direction register
P95
"1"
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Analog input
Note:
Figure 15.4
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
(VCC=VCC2)
I/O Ports (4)
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15. PROGRAMMABLE I/O PORTS
Pull-up selection
Direction register
P87
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
Rd
Direction register
P86
"1"
Data bus
Output
Port latch
(Note)
Note:
Figure 15.5
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
(VCC=VCC2)
I/O Ports (5)
(Note 2)
CNVSS
CNVSS signal input
(Note 1)
RESET
RESET signal input
(Note 1)
Note 1:
symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed Vcc.
Note 2: A parasitic diode on the VCC side is added to the mask ROM version.
Make sure the input voltage on each port will not exceed Vcc.
(Vcc=Vcc2)
Figure 15.6
I/O Pins
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15. PROGRAMMABLE I/O PORTS
Port Pi direction register (i=0 to 7 and 9) (Note 1, 2)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PD0 to PD3
PD4 to PD7
PD9
Address
03E216, 03E316, 03E616, 03E716
03EA16, 03EB16, 03EE16, 03EF16
03F316
Bit symbol
Bit name
PDi_0
PDi_1
Port Pi0 direction bit
Port Pi1 direction bit
PDi_2
Port Pi2 direction bit
PDi_3
Port Pi3 direction bit
PDi_4
Port Pi4 direction bit
PDi_5
Port Pi5 direction bit
PDi_6
PDi_7
Port Pi6 direction bit
Port Pi7 direction bit
After reset
0016
0016
0016
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
(i = 0 to 7 and 9)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: Make sure the PD9 register is written to by the next instruction after setting the PRCR
register’s PRC2 bit to “1” (write enabled).
Port P8 direction register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
03F216
PD8
Bit symbol
Bit name
After reset
00X000002
Function
PD8_0
Port P80 direction bit
PD8_1
Port P81 direction bit
PD8_2
Port P82 direction bit
PD8_3
Port P83 direction bit
PD8_4
Port P84 direction bit
Nothing is assigned. In an attempt to write to this bit, write “0”.
The value, if read, turns out to be indeterminate.
(b5)
PD8_6
Port P86 direction bit
PD8_7
Port P87 direction bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
RW
RW
RW
RW
RW
RW
RW
RW
Reserved register
b7
b6
1 1
b5
b4
1 1
b3
b2
1 1
b1
b0
1 1
Symbol
Bit symbol
(b7-b0)
Figure 15.7
PD0 to PD9 Registers
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Address
03F616
RSV03F6
Page 258 of 326
Bit name
Reserved bits
After reset
0016
Function
Must set to "1."
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
15. PROGRAMMABLE I/O PORTS
Port Pi register (i=0 to 7 and 9) (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P0 to P3
P4 to P7
P9
Address
03E016, 03E116, 03E416, 03E516
03E816, 03E916, 03EC16, 03ED16
03F116
Bit symbol
Bit name
Pi_0
Port Pi0 bit
Pi_1
Pi_2
Port Pi1 bit
Port Pi2 bit
Pi_3
Port Pi3 bit
Pi_4
Port Pi4 bit
Pi_5
Port Pi5 bit
Pi_6
Port Pi6 bit
Pi_7
Port Pi7 bit
After reset
Indeterminate
Indeterminate
Indeterminate
Function
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register
0 : “L” level
1 : “H” level (Note 1)
(i = 0 to 7 and 9)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
Port P8 register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
P8
Address
03F016
Bit symbol
After reset
Indeterminate
Bit name
P8_0
Port P80 bit
P8_1
Port P81 bit
P8_2
Port P82 bit
P8_3
Port P83 bit
P8_4
Port P84 bit
P8_5
Port P85 bit
P8_6
Port P86 bit
P8_7
Port P87 bit
Function
The pin level on any I/O port which is
set for input mode can be read by
reading the corresponding bit in this
register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register (except for P85)
0 : “L” level
1 : “H” level
RW
RW
RW
RW
RW
RW
RO
RW
RW
Reserved register
b7
b6
0 0
b5
b4
0 0
b3
b2
0 0
b1
b0
0 0
Symbol
Bit symbol
(b7-b0)
Figure 15.8
Bit name
Reserved bits
P0 to P9 Registers
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Address
03F416
RSV03F4
Page 259 of 326
After reset
Indeterminate
Function
Must set to "0."
RW
RW
M306H7MG-XXXFP/MC-XXXFP/FGFP
15. PROGRAMMABLE I/O PORTS
Pull-up control register 0 (Note 1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR0
Bit symbol
Address
03FC16
Bit name
PU00
P00 to P03 pull-up
PU01
P04 to P07 pull-up
PU02
P10 to P13 pull-up
PU03
P14 to P17 pull-up
PU04
P20 to P23 pull-up
PU05
P24 to P27 pull-up
PU06
P30 to P33 pull-up
PU07
P34 to P37 pull-up
After reset
0016
Function
0 : Not pulled high
1 : Pulled high (Note 1)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Pull-up control register 1
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
PUR1
Bit symbol
PU10
Address
03FD16
Bit name
P40 to P43 pull-up
PU11
P44 to P47 pull-up
PU12
P50 to P53 pull-up
PU13
P54 to P57 pull-up
PU14
P60 to P63 pull-up
PU15
P64 to P67 pull-up
PU16
P72 to P73 pull-up (Note 1)
PU17
P74 to P77 pull-up
After reset (Note 3)
000000002
Function
0 : Not pulled high
1 : Pulled high (Note 2)
RW
RW
RW
RW
RW
RW
RW
RW
RW
Note 1: The P70 and P71 pins do not have pull-ups.
Note 2: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Note 3: The values after hardware reset are as follows:
• 00000000 2 when input on CNVss pin is "L"
The values after software reset and watchdog timer reset are as follows:
• 00000000 2 when PM 01 to PM00 bits of PM0 register are "002" (single-chip mode)
Pull-up control register 2
b7
b6
b5
b4
b3
b2
0 0
b1
b0
Symbol
PUR2
Bit symbol
Address
03FE16
Bit name
After reset
0016
Function
PU20
P80 to P83 pull-up
PU21
PU22
P84 to P87 pull-up (Note 2)
P90 to P93 pull-up
PU23
P94 to P97 pull-up
RW
RW
RW
RW
RW
Must set to "0"
RW
(b5-b4)
0 : Not pulled high
1 : Pulled high (Note 1)
Nothing is assigned. In an attempt to write to these bits, write
"0". The value, if read, turns out to be "0".
Note 1: The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Note 2: The P85 pin does not have pull-up.
(b7-b6)
Figure 15.9
PUR0 to PUR2 Registers
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 260 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
15. PROGRAMMABLE I/O PORTS
Port control register
b7
b6
b5
b4
b3
b2
b1
b0
Symbpl
PCR
Address
03FF16
Bit symbol
PCR0
Bit name
Port P1 control bit
After reset
0016
Function
Nothing is assigned. In an attempt to write to these bits,
(b7-b1)
Figure 15.10
write “0”. The value, if read, turns out to be “0”.
PCR Register
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 261 of 326
RW
Operation performed when the P1
register is read
0: When the port is set for input,
the input levels of P10 to P17 RW
pins are read. When set for
output, the port latch is read.
1: The port latch is read
regardless of whether the port
is set for input or output.
M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 15.1
15. PROGRAMMABLE I/O PORTS
Unassigned Pin Handling in Single-chip Mode
Pin name
Connection
Ports P0 to P7, P80 to P84,
P86 to P87, P9
After setting for input mode, connect every pin to VSS via a resistor(pull-down);
or after setting for output mode, leave these pins open. (Note 1, 2 ,3)
XOUT (Note 4)
Open
NMI (P85)
Connect via resistor to VCC (pull-up)
AVCC
Connect to VCC
AVSS
Connect to VSS
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
Note 3: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 4: With external clock input to XIN pin.
Microcomputer
Port P0 to P9 (except for P85)
(Input mode)
•
•
(Input mode)
(Output mode)
•
•
Open
NMI
XOUT
Open
VCC
AVCC
AVSS
VSS
In single-chip mode
Figure 15.11
Unassigned Pins Handling
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 262 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
16. Electrical Characteristics
Table 16.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
VCC1, VCC2
Supply voltage
V CC2=AVcc
Rated value
Unit
-0.3 to 6.0
V
VCC1
Supply voltage
V CC1
-0.3 to VCC2
V
AV CC
Analog supply voltage
VCC2=AVcc
-0.3 to 6.0
V
VDD2
Analog supply voltage
VCC2=VDD2
-0.3 to 6.0
V
Input
voltage
VI
RESET, CNVSS
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P85 to P87,
P90 to P97,
XIN, M1, STARTB
-0.3 to VCC2 + 0.3
V
P60 to P67, P70 to P77, P80 to P84
-0.3 to VCC1 + 0.3
V
P70, P71
Output
voltage
VO
-0.3 to 6.0
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P86, P87, P90 to P97,
XOUT
P60 to P67, P70 to P77, P80 to P84
P70, P71
V
-0.3 to VCC2 + 0.3
V
-0.3 to VCC1 + 0.3
V
-0.3 to 6.0
V
550
mW
Operating ambient temperature
-20 to 70
C
Storage temperature
-20 to 125
C
Pd
Power dissipation
Topr
Tstg
Note: Following setting is required: VCC1 ≤ VCC2
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 263 of 326
Topr=25 C
M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 16.2
16. ELECTRICAL CHARACTERISTICS
Recommended Operating Conditions (Note 1)
Symbol
Standard
Parameter
Min.
Typ.
Max.
5.0
5.5
VCC1, VCC2
Supply voltage (VCC1 ≤ VCC2)
AVcc
V DD2
Analog supply voltage
V CC2
Analog supply voltage
V ss
Supply voltage
V CC2
0
A V ss
Analog supply voltage
HIGH input
voltage
VIH
2.0
V CC2
0.8VCC2
V CC2
V
0.8VCC1
V CC1
V
0.8VCC2
V CC2
V
P70, P71
P31 to P37, P40 to P47, P50 to P57
0.8VCC1
5.75
V
0
0.2VCC2
V
P00 to P07, P10 to P17, P20 to P27, P30
0
0.2VCC2
V
P60 to P67, P70 to P77, P80 to P84
0
0.2VCC1
V
0
0.2VCC2
V
P85 to P87, P90 to P97,
XIN, RESET, CNVSS, M1, STARTB
VCVIN
V
V
P60 to P67, P72 to P77, P80 to P84
XIN, RESET, CNVSS, M1, STARTB
V IL
V
P31 to P37, P40 to P47, P50 to P57
P00 to P07, P10 to P17, P20 to P27, P30
P85 to P87, P90 to P97
LOW input
voltage
V
V
V
0
0.8VCC2
Unit
Composite video input voltage
CVIN, SYNCIN
2VP-P
V
I OH (peak)
HIGH peak output
current (Note2, Note3)
P00 to P07,P10 to P17, P20 to P27,P30 to P37,
P40 to P47,P50 to P57, P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97
I OH (avg)
HIGH average
output current
P00 to P07,P10 to P17, P20 to P27,P30 to P37,
P40 to P47,P50 to P57, P60 to P67,P72 to P77,
P80 to P84,P86,P87,P90 to P97
- 5.0
mA
I OL (peak)
LOW peak
output current
P00 to P07,P10 to P17, P20 to P27,P30 to P37,
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
P80 to P84,P86,P87,P90 to P97
10.0
mA
I OL (avg)
LOW average
output current
P00 to P07,P10 to P17, P20 to P27,P30 to P37,
P40 to P47, P50 to P57, P60 to P67,P70 to P77,
P80 to P84,P86,P87,P90 to P97
5.0
mA
f (X I N)
Main clock input oscillation frequency
(Note 4)
VCC2=2.9 to 5.5V
16
MHz
f (X CIN)
Sub-clock oscillation frequency
VCC2=2.0 to 5.5V(Note 5)
f (BCL K )
CPU operation clock
0
32.768
0
- 10.0
mA
50
kHz
16
MHz
Note 1: Referenced to VCC = VCC1 = VCC2 = 2.0 to 5.5V at Topr = -20 to 70 ˚C unless otherwise specified.
Note 2: The mean output current is the mean value within 100ms.
Note 3: The total IOL (peak) for ports P0, P1, P2, P3, P4, P5,P86, P87, P9 must be 80mA max. The total IOL (peak)
for ports P6, P7andP80 to P84 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2 must be -40mA max.
The total IOH (peak) for ports P3, P4andP5 must be -40mA max.
Note 4: Use the VCC1 and VCC2 power supply voltage on the following conditions.
• VCC1 = 3.00V to VCC2, VCC2 = 4.00V to 5.5V (at f(XIN) = 16MHz)
• VCC1 = 2.90V to VCC2, VCC2 = 2.90V to 5.5V (at f(XIN) = 16MHz, at divide-by-8 or 16)
Note 5: Use in low power dissipation mode. When operating on low voltage (VCC = 3.0V), only single-chip mode can be used.
If the VCC2 supply voltage is less than 2.6 V, be aware that only the CPU, RAM, clock timer, interrupt, and Input/Output ports can be used.
Other control circuits (e.g., timers A and B, serial I/O, UART) cannot be used.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 264 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 16.3
16. ELECTRICAL CHARACTERISTICS
A/D Conversion Characteristics (Note 1)
Symbol
Parameter
–
Resolution
–
Absolute accuracy
Standard
Unit
Min. Typ. Max.
Measuring condition
VREF =VCC
AN0 to AN7 input
VREF= ANEX0, ANEX1 input
VCC = External operation amp
5V
tCONV
Conversion time(8bit), Sample & hold
function available
tSAMP
VREF
Sampling time
Reference voltage
VIA
Analog input voltage
8
±3
Bits
LSB
±4
LSB
µs
2.8
VREF =VCC=5V, øAD=10MHz
VCC
µs
V
VREF
V
0.3
4.5
0
Note 1: Referenced to VCC2=AVCC=VREF=4.5 to 5.5V, VSS=AVSS=0V at Topr = -20 to 70 ˚C unless otherwise specified.
Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less.
Note 3: A case without sample & hold function turn ØAD frequency into 250 kHz or more.
A case with sample & hold function turn ØAD frequency into 1 MHz or more.
Table 16.4
Flash Memory Version Electrical Characteristics (Note 1)
Symbol
Measuring condition
Parameter
Min.
Standard
Typ.
Max
Word program time
tps
30
200
Unit
µs
Block erase time
1
4
s
Lock bit program time
30
200
µs
15
µs
Flash memory circuit stabilization wait time
Note 1: Referenced to VCC2=4.75 to 5.25V at Topr = 0 to 60 ˚C unless otherwise specified.
Table 16.5
Flash Memory Version Program/Erase Voltage and Read Operation Voltage
Characteristics (Topr = 0 to 60°C
Flash program, erase voltage
Flash read operation voltage
VCC2 = 5.0 ± 0.25 V
VCC2 = 2.0 to 5.5 V
Table 16.6
Power Supply Circuit Timing Characteristics
Symbol
Parameter
td(P-R)
td(R-S)
td(W-S)
T
ime for internal power supply stabilization during powering-on
Measuring condition
STOP release time
Low power dissipation mode wait mode release time
VCC= 5.0V
Recommended operation voltage
VCC2
td(P-R)
CPU clock
(a) Interrupt for stop mode release
(b) Interrupt for wait mode release
CPU clock
(a)
td(R-S)
(b)
td(W-S)
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 265 of 326
Min.
Standard
Typ.
ax.
2
150
150
Unit
ms
µs
µs
M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 16.7
16. ELECTRICAL CHARACTERISTICS
Electrical Characteristics (1) (Note 1)
VCC1 = VCC2 = 5V
Parameter
Symbol
VOH
Measuring condition
HIGH output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P86, P87, P90 to P97
P60 to P67, P72 to P77, P80 to P84
VOH
HIGH output P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
voltage
P86, P87, P90 to P97
P60 to P67, P72 to P77, P80 to P84
VOH
VOH
VOL
HIGH output
LP3 , LP4
voltage
HIGH output
voltage
XOUT
HIGH output
voltage
XCOUT
LOW output
voltage
XOUT
LOW output
voltage
XCOUT
VT+-VT-
VT+-VT-
IIH
VCC1-2.0
VCC1
V
IOH=-200µA
VCC2-0.3
VCC2
V
IOH=-200µA
VCC1-0.3
VCC1
V
Hysteresis
3.75
V
VCC2-2.0
VCC2
VCC2-2.0
VCC2
HIGHPOWER
With no load applied
With no load applied
2.5
V
V
1.6
IOL=5mA
2.0
V
IOL=5mA
2.0
V
IOL=200µA
0.45
V
IOL=200µA
0.45
V
VCC=4.5V, I OL=0.05mA
0.4
V
HIGHPOWER
IOL=1mA
2.0
LOWPOWER
IOL=0.5mA
2.0
HIGHPOWER
With no load applied
With no load applied
LOWPOWER
Hysteresis TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, NMI,
ADTRG, CTS0 to CTS2, SCL, SDA,
CLK0 to CLK4,TA2OUT to TA4OUT,
RxD0 to RxD2, SIN3, SIN4
RESET
0
V
V
0
0.2
1.0
V
0.2
2.2
V
HIGH input P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
current
P60 to P67, P70 to P77, P80 to P87,
P90 to P97
XIN, RESET, CNVss,
M1, STARTB
VI=5V
5.0
µA
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P77, P80 to P87,
P90 to P97
XIN, RESET, CNVss,
M1, STARTB
VI=0V
-5.0
µA
P00 to P07, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P72 to P77, P80 to P84,
P86, P87, P90 to P97
VI=0V
170
kΩ
LOW input
current
I IL
RPULLUP
IOH=-5mA
IOH=-0.5mA
P60 to P67, P70 to P77, P80 to P84
VOL
V
IOH=-1mA
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P86, P87, P90 to P97
LOW output
LP3 to LP4
voltage
VCC2
LOWPOWER
LOW output P00 to P07, P10 to P17, P20 to P27,
voltage
P30 to P37, P40 to P47, P50 to P57,
P86, P87, P90 to P97
Unit
VCC2-2.0
HIGHPOWER
LOWPOWER
VOL
Standard
Typ. Max.
IOH=-5mA
VCC=4.5V, I OH=-0.05mA
P60 to P67, P70 to P77, P80 to P84
VOL
Min
Pull-up
resistance
30
50
R fXIN
Feedback resistance
XIN
1.5
MΩ
R fXCIN
Feedback resistance
XCIN
15
MΩ
V RAM
RAM retention voltage
Stop mode
2.0
V
V SYNCIN
Sync voltage amplitude
0.3
0.6
1.2
V
V dat(text)
Teletext data voltage amplitude
0.6
0.9
1.4
V
fH
Horizontal synchronous signal frequency
14.6
17.0
kHZ
15.625
Note 1: Referenced to VCC =VCC1=VCC2= 4.50 to 5.50 V, VSS=0V at Topr = -20 to 70 ˚C, f(BCLK)=16 MHz unless otherwise specified.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 266 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 16.8
16. ELECTRICAL CHARACTERISTICS
Electrical Characteristics (2) (Note)
VCC1 = VCC2 = 3V
Symbol
V OH
V OH
V OL
V OL
V T+- V TV T+- V T-
I IH
Parameter
HIGH output
voltage
Unit
V CC
V
P60 to P67, P72 to P77, P80 to P84
IOH = -1 mA
VCC1 - 0.5
V CC
V
X COUT
HIGHPOWER
IOH = -0.1 mA
VCC2 - 0.5
V CC2
LOWPOWER
IOH = -50 µA
VCC2 - 0.5
V CC2
HIGHPOWER
With no load applied
2.5
LOWPOWER
With no load applied
1.6
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67, P70 to P77,
P80 to P84, P86, P87, P90 to P97
LOW output
voltage
X OUT
LOW output
voltage
X COUT
0.5
HIGHPOWER
IOL = 0.1 mA
0.5
LOWPOWER
IOL = 50 µA
0.5
HIGHPOWER
With no load applied
0
LOWPOWER
With no load applied
0
0.2
Hysteresis
RESET
0.2
HIGH input
voltage
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67, P70 to P77,
P80 to P87, P90 to P97
X IN , RESET, CNVss, M1, STARTB
HIGH input
voltage
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67, P70 to P77,
P80 to P87, P90 to P97
X IN , RESET, CNVss, M1, STARTB
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67, P72 to P77,
P80 to P84, P86, P87, P90 to P97
V
V
I OL = 1 mA
TA0 IN to TA4IN , TB0 IN to TB5IN, INT0 to INT5
TA2 OUT to TA4OUT
Pull-up resistance
Max.
VCC2 - 0.5
HIGH output
voltage
Hysteresis
Typ.
IOH = -1 mA
X OUT
I IL
RPULLUP
Standard
Min.
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P86, P87, P90 to P97
HIGH output
voltage
LOW output
voltage
Measuring condition
V
V
V
0.8
V
1.8
V
VI = 3 V
4.0
µA
VI = 0 V
-4.0
µA
500
kΩ
VI = 0 V
50
(0.7)
100
Feedback resistance
X IN
3.0
MΩ
Feedback resistance
X CIN
25
MΩ
RfXCIN
Note : Referenced to VCC = VCC1 = VCC2 = 3.0 V, VSS = 0 V at Topr = -20 to 70 °C, f (XCIN) = 32kHz unless otherwise specified.
Use in single-chip mode and low power dissipation mode.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 16.9
16. ELECTRICAL CHARACTERISTICS
Electrical Characteristics (2) (Note 1)
Symbol
Measuring condition
Parameter
In single-chip mode, the output
pins are open and other pins are
VSS
Mask ROM
Flash memory
Flash memory
Program
Flash memory
Erase
Mask ROM
ICC
Power supply current
Flash memory
Min.
f(BCLK)=16MHz,
VCC =5.0V
f(BCLK)=16MHz,
VCC =5.0V
f(BCLK)=16MHz,
VCC =5.0V
f(BCLK)=16MHz,
VCC =5.0V
Max.
50
100
50
100
Parameter
VIN-cu
Composite video signal input clamp voltage
25
mA
25
µA
f(BCLK)=32kHz,
Low power dissipation mode,
RAM(Note 3), (Note4) Vcc=5.0V
25
µA
420
µA
7 .5
µA
Oscillation capacity High
f(BCLK)=32kHz,
Wait mode(Note 2), (Note4)
Vcc=5.0V
Oscillation capacity Low
5.0
f(BCLK)=32kHz,
Wait mode (Note 2), (Note4)
Oscillation capacity High
Vcc=3.0V
6.0
f(BCLK)=32kHz,
Wait mode(Note 2), (Note4)
Vcc=3.0V
Oscillation capacity Low
2.0
8.0
µA
Stop mode, (Note4)
Topr=25˚C
Vcc=5.0V
0 .8
5.0
µA
Measuring condition
Sync-chip voltage
Note 1: Referenced to VCC2 = 5.0 V at Topr = -20 to 70 °C unless otherwise specified.
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mA
mA
10.0
Min
Standard
Typ. Max.
1.0
µA
µA
Video signal input conditions (Note 1)
Symbol
mA
15
Note 1: Referenced to VCC1=VCC2= 5V, VSS=0V at Topr =25 ˚C, f(BCLK)=16MHz unless otherwise specified.
Note 2: With one timer operated using fC32. (Slicer operation OFF)
Note 3: This indicates the memory in which the program to be executed exists.
Note 4: • All of VDD2 is at the same potential level as VCC2.
• Extension registers (addresses 0016 through 3F16) are set to the initial state.
• Inputs to the SYNCIN and CVIN pins are disabled.
• For current consumption reducing, set the level of VSS or VCC to the ports used in input mode.
Table 16.10
Unit
f(XCIN)=32kHz,
Low power dissipation mode,
ROM(Note 3), (Note4) Vcc=5.0V
f(BCLK)=32kHz
Low power dissipation mode,
Flash memory(Note 3), (Note4)
Vcc=5.0V
f(BCLK)=32kHz,
Wait mode (Note 2), (Note4)
Mask ROM
Flash memory
Standard
Typ.
Unit
V
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 16.11
External Clock Input (XIN input)
VCC1 = VCC2 = 5V
Symbol
tc
tw(H)
tw(L)
tr
tf
Table 16.12
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
Standard
Min.
Max.
Unit
ns
62.5
30
30
15
15
ns
ns
ns
ns
Remote Control Pulse Input
VCC1 = VCC2 = 5V
Symbol
Tw(RMTH)
Tw(RMTL)
Table 16.13
Parameter
RMTIN input HIGH pulse width
RMTIN input LOW pulse width
Standard
Min.
Max.
61
61
Unit
µs
µs
JUST CLOCK Input
VCC1 = VCC2 = 5V
Symbol
Tw(JSTH)
Tw(JSTL)
Parameter
JSTIN input HIGH pulse width
JSTIN input LOW pulse width
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Standard
Min.
Max.
61
61
Unit
µs
µs
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 16.14
Timer A Input (Counter Input in Event Counter Mode)
VCC1 = VCC2 = 5V
Symbol
tc(TA)
Parameter
TAi IN input cycle time
tw(TAH)
TAi IN input HIGH pulse width
tw(TAL)
TAi IN input LOW pulse width
Table 16.15
Standard
Min.
Max.
100
40
40
Unit
ns
ns
ns
Timer A Input (Gating Input in Timer Mode)
VCC1 = VCC2 = 5V
Symbol
Parameter
tc(TA)
TAi IN input cycle time
tw(TAH)
tw(TAL)
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Table 16.16
Standard
Min.
Max.
400
200
200
Unit
ns
ns
ns
Timer A Input (External Trigger Input in One-shot Timer Mode)
VCC1 = VCC2 = 5V
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 16.17
Parameter
Standard
Max.
Min.
Unit
TAi IN input cycle time
200
ns
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
100
100
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
VCC1 = VCC2 = 5V
Symbol
tw(TAH)
tw(TAL)
Table 16.18
Parameter
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Standard
Min.
Max.
100
100
Unit
ns
ns
Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
VCC1 = VCC2 = 5V
Symbol
Parameter
tc(UP)
TAi OUT input cycle time
tw(UPH)
TAi OUT input HIGH pulse width
tw(UPL)
tsu(UP-TIN)
TAi OUT input LOW pulse width
th(TIN-UP)
TAi OUT input setup time
TAi OUT input hold time
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Standard
Min.
Max.
2000
1000
1000
400
400
Unit
ns
ns
ns
ns
ns
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 16.19
Timer B Input (Counter Input in Event Counter Mode)
VCC1 = VCC2 = 5V
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Standard
Min.
Max.
Parameter
Symbol
TBiIN input cycle time (counted on one edge)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
Table 16.20
Unit
100
ns
40
ns
ns
40
200
ns
80
ns
80
ns
Timer B Input (Pulse Period Measurement Mode))
VCC1 = VCC2 = 5V
tc(TB)
tw(TBH)
tw(TBL)
Standard
Min.
Max.
Parameter
Symbol
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 16.21
Unit
400
ns
200
200
ns
ns
Timer B Input (Pulse Width Measurement Mode))
VCC1 = VCC2 = 5V
Parameter
Symbol
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
Table 16.22
Standard
Min.
Max.
Unit
400
ns
200
200
ns
ns
A/D Trigger Input
VCC1 = VCC2 = 5V
Standard
Min.
Max.
Parameter
Symbol
tc(AD)
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
tw(ADL)
Table 16.23
1000
ns
125
ns
Serial I/O
VCC1 = VCC2 = 5V
tc(CK)
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
Parameter
Symbol
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
Table 16.24
Unit
200
ns
100
ns
ns
ns
100
80
0
30
ns
90
ns
ns
External Interrupt INTi Input
VCC1 = VCC2 = 5V
Parameter
Symbol
tw(INH)
tw(INL)
INTi input HIGH pulse width
INTi input LOW pulse width
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Standard
Min.
Max.
250
250
Unit
Unit
ns
ns
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 16.25
External Clock Input (XIN Input)
VCC1 = VCC2 = 3V
Symbol
tc
tw(H)
tw(L)
tr
tf
Parameter
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
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Standard
Min.
Max.
Unit
ns
100
40
40
18
18
ns
ns
ns
ns
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 16.26
Timer A Input (Counter Input in Event Counter Mode)
VCC1 = VCC2 = 3V
Symbol
Parameter
tc(TA)
TAi IN input cycle time
tw(TAH)
TAi IN input HIGH pulse width
tw(TAL)
TAi IN input LOW pulse width
Table 16.27
Standard
Min.
Max.
150
60
60
Unit
ns
ns
ns
Timer A Input (Gating Input in Timer Mode)
VCC1 = VCC2 = 3V
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 16.28
Parameter
TAi IN input cycle time
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Standard
Min.
Max.
600
Unit
ns
300
ns
300
ns
Timer A Input (External Trigger Input in One-shot Timer Mode)
VCC1 = VCC2 = 3V
Symbol
tc(TA)
tw(TAH)
tw(TAL)
Table 16.29
Parameter
Standard
Max.
Unit
Min.
TAi IN input cycle time
300
ns
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
150
150
ns
ns
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
VCC1 = VCC2 = 3V
Symbol
tw(TAH)
tw(TAL)
Table 16.30
Parameter
TAi IN input HIGH pulse width
TAi IN input LOW pulse width
Standard
Min.
Max.
150
150
Unit
ns
ns
Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
VCC1 = VCC2 = 3V
Symbol
tc(UP)
Parameter
TAi OUT input cycle time
tw(UPH)
TAi OUT input HIGH pulse width
tw(UPL)
TAi OUT input LOW pulse width
tsu(UP-TIN)
TAi OUT input setup time
TAi OUT input hold time
th(TIN-UP)
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Standard
Min.
Max.
3000
1500
1500
600
600
Unit
ns
ns
ns
ns
ns
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 70°C unless otherwise specified)
Table 16.31
Timer B Input (Counter Input in Event Counter Mode)
VCC1 = VCC2 = 3V
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time (counted on one edge)
150
ns
tw(TBH)
TBiIN input HIGH pulse width (counted on one edge)
60
ns
tw(TBL)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
60
300
ns
tc(TB)
tw(TBH)
TBiIN input HIGH pulse width (counted on both edges)
120
ns
tw(TBL)
TBiIN input LOW pulse width (counted on both edges)
120
ns
Table 16.32
ns
Timer B Input (Pulse Period Measurement Mode)
VCC1 = VCC2 = 3V
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
tw(TBL)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
300
300
ns
ns
Table 16.33
Timer B Input (Pulse Period Measurement Mode)
VCC1 = VCC2 = 3V
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(TB)
TBiIN input cycle time
600
ns
tw(TBH)
TBiIN input HIGH pulse width
300
ns
tw(TBL)
TBiIN input LOW pulse width
300
ns
Table 16.34
Serial I/O (Pulse Period Measurement Mode)
VCC1 = VCC2 = 3V
Symbol
Parameter
Standard
Min.
Max.
Unit
tc(CK)
CLKi input cycle time
300
ns
tw(CKH)
CLKi input HIGH pulse width
150
ns
tw(CKL)
CLKi input LOW pulse width
150
ns
td(C-Q)
TxDi output delay time
th(C-Q)
TxDi hold time
tsu(D-C)
RxDi input setup time
RxDi input hold time
th(C-D)
Table 16.35
160
ns
0
70
ns
90
ns
ns
External Interrupt INTi Input (Pulse Period Measurement Mode)
VCC1 = VCC2 = 3V
Symbol
Parameter
tw(INH)
INTi input HIGH pulse width
tw(INL)
INTi input LOW pulse width
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REJ03B0152-0210
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Standard
Min.
380
380
Max.
Unit
ns
ns
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 5V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN−UP)
(When count on falling
edge is selected)
tsu(UP−TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 16.1
Timing Diagram (1)
Rev.2.10
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M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C−Q)
TxDi
td(C−Q)
tsu(D−C)
RxDi
tw(INL)
INTi input
Figure 16.2
tw(INH)
Timing Diagram (2)
Rev.2.10
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REJ03B0152-0210
Page 276 of 326
th(C−D)
M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 3V
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
th(TIN–UP)
(When count on falling
edge is selected)
tsu(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 16.3
Timing Diagram (3)
Rev.2.10
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M306H7MG-XXXFP/MC-XXXFP/FGFP
16. ELECTRICAL CHARACTERISTICS
VCC1 = VCC2 = 3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C–Q)
TxDi
td(C–Q)
tsu(D–C)
RxDi
tw(INL)
INTi input
Figure 16.4
tw(INH)
Timing Diagram (4)
Rev.2.10
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th(C–D)
M306H7MG-XXXFP/MC-XXXFP/FGFP
17. FLASH MEMORY VERSION
17. Flash Memory Version
17.1
Flash Memory Performance
The flash memory version is functionally the same as the mask ROM version except that it internally contains flash
memory.
The flash memory version has three modes−CPU rewrite, standard serial input/output, and parallel input/output
modes−in which its internal flash memory can be operated on.
Table 17.1 shows the outline performance of flash memory version (see Table 1.1 for the items not listed in Table
17.1.).
Table 17.1
Flash Memory Version Specifications
Item
Specification
Flash memory operating mode
Erase block
3 modes (CPU rewrite, standard serial I/O, parallel I/O)
User ROM area
See Figure 17.1
Boot ROM area
1 block (4 Kbytes) (Note 1)
Method for program
In units of word
Method for erasure
Block erase
Program, erase control method
Program and erase controlled by software command
Protect method
Protected for each block by lock bit
Number of commands
7 commands
Number of program and erasure
100 times
Data Retention
10 years
ROM code protection
Parallel I/O and standard serial I/O modes are supported.
Note 1: The boot ROM area contains a standard serial I/O mode rewrite control program which is stored
in it when shipped from the factory. This area can only be rewritten in parallel input/output mode.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
Table 17.2
17. FLASH MEMORY VERSION
Flash Memory Rewrite Modes Overview
Flash memory CPU rewrite mode (Note 1)
rewrite mode
The user ROM area is rewritFunction
ten by executing software
commands from the CPU.
EW0 mode:
Can be rewritten in any
area other than the flash
memory (Note 2)
EW1 mode:
Can be rewritten in the
flash memory
Areas which User ROM area
can be rewritten
Operation
Single chip mode
mode
Boot mode (EW0 mode)
ROM
None
programmer
Standard serial I/O mode
Parallel I/O mode
The user ROM area is rewritten by using a dedicated serial programmer.
Standard serial I/O mode 1:
Clock sync serial I/O
Standard serial I/O mode 2:
UART
The boot ROM and user
ROM areas are rewritten by
using a dedicated parallel
programmer.
User ROM area
Boot mode
User ROM area
Boot ROM area
Parallel I/O mode
Serial programmer
Parallel programmer
Note 1: Bit 3 of processor mode register 1 remains set to "1" while the FMR0 register FMR01 bit = 1 (CPU
rewrite mode enabled).
Bit 3 of processor mode register 1 is reverted to its original value by clearing the FMR01 bit to "0"
(CPU rewrite mode disabled). However, if bit 3 of processor mode register 1 is changed during CPU
rewrite mode, its changed value is not reflected until after the FMR01 bit is cleared to "0".
Note 2: When in CPU rewrite mode, bit 0 and bit 3 in the PM1 register are set to "1". The rewrite
control program can only be executed in the internal RAM.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
17.2
17. FLASH MEMORY VERSION
Memory Map
The ROM in the flash memory version is separated between a user ROM area and a boot ROM area.
Figure 17.1 shows the block diagram of flash momoery.
The user ROM area is divided into several blocks, each of which can individually be protected (locked) against
programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard serial input/output,
and parallel input/output modes.
The boot ROM area is located at addresses that overlap the user ROM area, and can only be rewritten in parallel
input/output mode. After a hardware reset that is performed by applying a high-level signal to the CNVSS and P50
pins and a low-level signal to the M1 pin, the program in the boot ROM area is executed.
After a hardware reset that is performed by applying a low-level signal to the CNVSS pin, the program in the user
ROM area is executed (but the boot ROM area cannot be read).
0C000016
0F000016
Block 8 : 64K bytes
Block 5 : 32K bytes
0D000016
Block 7 : 64K bytes
0F7FFF16
0F800016
0E000016
Block 4 : 8K bytes
0F9FFF16
0FA000 16
Block 6 : 64K bytes
Block 3 : 8K bytes
0EFFFF16
0FBFFF16
0FC00016
0F000016
Block 2 : 8K bytes
Block 0 to Block 5 (32+8+8+8
+4+4)K bytes
0FDFFF16
0FE00016
0FEFFF16
0FF00016
0FFFFF16
0FFFFF16
User ROM area
Note 1: The boot ROM area can only be rewritten in parallel input/output mode.
Note 2: To specify a block, use an even address in that block.
Note 3: Shown here is a block diagram during single-chip mode.
Figure 17.1
Flash Memory Block Diagram
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Block 1 : 4K bytes
Block 0 : 4K bytes
0FF00016
0FFFFF16
4K bytes
Boot ROM area (Note 1)
M306H7MG-XXXFP/MC-XXXFP/FGFP
17.3
17. FLASH MEMORY VERSION
Boot Mode
After a hardware reset which is performed by applying a low-level signal to the M1 pin and a high-level signal to
the CNVSS and P50 pins, the microcomputer is placed in boot mode, thereby executing the program in the boot
ROM area.
During boot mode, the boot ROM and user ROM areas are switched over by the FMR05 bit in the FMR0 register.
The boot ROM area contains a standard serial input/output mode based rewrite control program which was stored
in it when shipped from the factory.
The boot ROM area can be rewritten in parallel input/output mode. Prepare an EW0 mode based rewrite control
program and write it in the boot ROM area, and the flash memory can be rewritten as suitable for the system.
17.4
Functions To Prevent Flash Memory from Rewriting
To prevent the flash memory from being read or rewritten easily, parallel input/output mode has a ROM code
protect and standard serial input/output mode has an ID code check function.
17.4.1
ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel input/
output mode. Figure 17.2 shows the ROMCP register.
The ROMCP register is located in the user ROM area. The ROMCP1 bit consists of two bits. The ROM code
protect function is enabled by clearing one or both of two ROMCP1 bits to “0” when the ROMCR bits are not
‘002,’ with the flash memory thereby protected against reading or rewriting. Conversely, when the ROMCR bits
are ‘002’ (ROM code protect removed), the flash memory can be read or rewritten. Once the ROM code protect
function is enabled, the ROMCR bits cannot be changed during parallel input/output mode. Therefore, use
standard serial input/output or other modes to rewrite the flash memory.
17.4.2
ID Code Check Function
Use this function in standard serial input/output mode. Unless the flash memory is blank, the ID codes sent
from the programmer and the ID codes written in the flash memory are compared to see if they match. If the ID
codes do not match, the commands sent from the programmer are not accepted. The ID code consists of 8-bit
data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB 16, 0FFFEF16,
0FFFF316, 0FFFF716, and 0FFFFB16. Prepare a program in which the ID codes are preset at these addresses
and write it in the flash memory.
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17. FLASH MEMORY VERSION
ROM code protect control address
b7
b6
b5
b4
b3
b2
b1
b0
1
1
1
1
Symbol
ROMCP
Address
0FFFFF16
Bit name
Bit symbol
ROMCR
ROMCP1
Value when shipped
FF16 (Note 4)
Function
RW
Reserved bit
Set this bit to "1"
RW
Reserved bit
Set this bit to "1"
RW
Reserved bit
Set this bit to "1"
RW
Reserved bit
Set this bit to "1"
RW
ROM code protect reset
bit (Note 2, Note 4)
b5 b4
ROM code protect level
1 set bit
(Note 1, Note 3, Note 4)
00: Removes protect
01:
10: Enables ROMCP1 bit
11:
}
RW
RW
b7 b6
00:
Protect enabled
01:
10:
11: Protect disabled
}
RW
RW
Note 1: If the ROMCR bits are set to other than "002" and the ROMCP1 bits are set to other than "11 2"
(ROM code protect enabled), the flash memory is disabled against reading and rewriting in
parallel input/output mode.
Note 2: If the ROMCR bits are set to "00 2," ROM code protect level 1 is removed. However, because the
ROMCR bits cannot be modified during parallel input/output mode, they need to be modified in
standard serial input/output or other modes.
Note 3: The ROMCP1 bits are effective when the ROMCR bits are "012," "10 2," or "112."
Note 4: Once any of these bits is cleared to "0", it cannot be set back to "1". If a memory block that
contains the ROMCP register is erased, the ROMCP register is set to "FF16."
Figure 17.2
ROMCP Register
Address
0FFFDF16 to 0FFFDC16 ID1
0FFFE316 to 0FFFE016
ID2
0FFFE716 to 0FFFE416
0FFFEB16 to 0FFFE816
Undefined instruction vector
Overflow vector
BRK instruction vector
ID3
0FFFEF16 to 0FFFEC16 ID4
Address match vector
Single step vector
0FFFF316 to 0FFFF016
ID5
Watchdog timer vector
0FFFF716 to 0FFFF416
ID6
DBC vector
0FFFFB16 to 0FFFF816
ID7
NMI vector
0FFFFF16 to 0FFFFC16
ROMCP Reset vector
4 bytes
Figure 17.3
Address for ID Code Stored
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17.5
17. FLASH MEMORY VERSION
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board without
having to use a ROM programmer, etc.
In CPU rewrite mode, only the user ROM area shown in Figure 17.1 can be rewritten and the boot ROM area
cannot be rewritten. Make sure the Program and the Block Erase commands are executed only on each block in the
user ROM area.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or Erase Write
1 (EW1) mode. Table 17.3 lists the differences between Erase Write 0 (EW0) and Erase Write 1 (EW1) modes.
Table 17.3
EW0 Mode and EW1 Mode
Item
Operation mode
Areas in which a
rewrite control
program can be located
Areas in which a
rewrite control
program can be executed
Areas which can be
rewritten
Software command
limitations
Modes after Program or
Erase
CPU status during Auto
Write and Auto Erase
Flash memory status
detection
EW0 mode
• Single chip mode
• Boot mode
• User ROM area
• Boot ROM area
EW1 mode
Single chip mode
User ROM area
Must be transferred to any area other Can be executed directly in the user
than the flash memory (RAM)
ROM area
before being executed (Note 2)
User ROM area
User ROM area
However, this does not include the area
in which a rewrite control program
exists
None
• Program, Block Erase command
Cannot be executed on any block in
which a rewrite control program exists
• Read Status Register command
Cannot be executed
Read Status Register mode
Read Array mode
Operating
• Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a
program
• Execute the Read Status Register
command to read the status
register's SR7, SR5, and SR4 flags.
Hold state (I/O ports retain the state in
which they were before the command
was executed)(Note 1)
Read the FMR0 register's FMR00,
FMR06, and FMR07 bits in a program
_______
Note 1: Make sure no interrupts (except NMI and watchdog timer interrupts) and DMA transfers will occur.
Note 2: When in CPU rewrite mode, bit 0 and bit 3 in the PM1 register are set to "1". The rewrite control
program can only be executed in the internal RAM.
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17.5.1
17. FLASH MEMORY VERSION
EW0 Mode
The microcomputer is placed in CPU rewrite mode by setting the FMR0 register’s FMR01 bit to “1” (CPU
rewrite mode enabled), ready to accept commands. In this case, because the FMR1 register’s FMR11 bit = 0,
EW0 mode is selected. The FMR01 bit can be set to “1” by writing “0” and then “1” in succession.
Use software commands to control program and erase operations. Read the FMR0 register or status register to
check the status of program or erase operation at completion.
17.5.2
EW1 Mode
EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting the
FMR01 bit to “1” (by writing “0” and then “1” in succession).
Read the FMR0 register to check the status of program or erase operation at completion. The status register
cannot be read during EW1 mode.
Figure 17.4 shows the FMR0 and FMR1 registers.
Registers FMR0 and FMR1 are shown in Figure 17.4.
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17. FLASH MEMORY VERSION
FMR00 Bit
This bit indicates the operating status of the flash memory. The bit is “0” when the Program, Erase, or Lock Bit
program is running; otherwise, the bit is “1”.
FMR01 Bit
The microcomputer is made ready to accept commands by setting the FMR01 bit to “1” (CPU rewrite mode).
During boot mode, make sure the FMR05 bit also is “1” (user ROM area access).
FMR02 Bit
The lock bit set for each block can be disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to the
description of the data protect function.) The lock bits set are enabled by setting the FMR02 bit to “0”.
The FMR02 bit only disables the lock bit function and does not modify the lock bit data (lock bit status flag).
However, if the Erase command is executed while the FMR02 bit is set to “1”, the lock bit data changes state
from “0” (locked) to “1” (unlocked) after Erase is completed.
FMSTP Bit
This bit is provided for initializing the flash memory control circuits, as well as for reducing the amount of
current consumed in the flash memory. The internal flash memory is disabled against access by setting the
FMSTP bit to “1”. Therefore, make sure the FMSTP bit is modified in other than the flash memory.
In the following cases, set the FMSTP bit to “1”:
• . When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to “1” (ready))
• . When entering low power mode
Figure 17.7 shows a flow chart to be followed before and after entering low power mode.
Note that when going to stop or wait mode, the FMR0 register does not need to be set because the power for the
internal flash memory is automatically turned off and is turned back on again after returning from stop or wait
mode.
FMR05 Bit
This bit switches between the boot ROM and user ROM areas during boot mode. Set this bit to “0” when
accessing the boot ROM area (for read) or “1” (user ROM access) when accessing the user ROM area (for read,
write, or erase).
FMR06 Bit
This is a read-only bit indicating the status of auto program operation. The bit is set to “1” when a program error
occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
FMR07 Bit
This is a read-only bit indicating the status of auto erase operation. The bit is set to “1” when an erase error
occurs; otherwise, it is cleared to “0”. For details, refer to the description of the full status check.
Figure 17.5 and 17.6 show the setting and resetting of EW0 mode and EW1 mode, respectively.
FMR11 Bit
Setting this bit to “1” places the microcomputer in EW1 mode.
FMR16 Bit
This is a read-only bit indicating the execution result of the Read Lock Bit Status command.
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Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After reset
FMR0
01B716
XX0000012
0
Bit name
Bit symbol
Function
RW
FMR00
RY/BY status flag
0: Busy (being written or erased)
1: Ready
FMR01
CPU rewrite mode select bit
(Note 1)
0: Disables CPU rewrite mode
1: Enables CPU rewrite mode
RW
Lock bit disable select bit
(Note 2)
0: Enables lock bit
1: Disables lock bit
RW
Flash memory stop bit
(Note 3, Note 5))
0: Enables flash memory operation
1: Stops flash memory operation
(placed in low power mode,
flash memory initialized)
FMR02
FMSTP
Reserved bit
RO
RW
Must always be set to “0”
RW
User ROM area select bit
(Note 3)
(Effective in only boot mode)
0: Boot ROM area is accessed
1: User ROM area is accessed
RW
FMR06
Program status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
FMR07
Erase status flag (Note 4)
0: Terminated normally
1: Terminated in error
RO
(b4)
FMR05
Note 1: To set this bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or DMA transfers
will occur before writing “1” after writing “0”.
Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, modify this bit in other
than the flash memory.
Note 2: To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Note 3: modify this bit in other than the flash memory.
Note 4: This flag is cleared to “0” by executing the Clear Status command.
Note 5: Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP bit
can be set to “1” by writing “1” in a program, the flash memory is neither placed in low power mode
nor initialized.
Note 6: This status includes writing or reading with the Lock Bit Program or Read Lock Bit Status command.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol
Address
After reset
FMR1
01B516
0X00XX0X2
0
Bit name
Bit symbol
(b0)
Reserved bit
Function
The value in this bit when read is
indeterminate.
0: EW0 mode
1: EW1 mode
RW
RO
FMR11
EW1 mode select bit (Note)
(b3-b2)
Reserved bit
The value in this bit when read is
indeterminate.
RO
(b5-b4)
Reserved bit
Must always be set to “0”
RW
FMR16
Lock bit status flag
0: Lock
1: Unlock
RO
Reserved bit
Must always be set to “0”
RW
(b7)
RW
Note : To set this bit to “1”, write “0” and then “1” in succession when the FMR01 bit = 1. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”. Write this bit in the state
the NMI pin = “H”. The FMR01 and FMR11 bits both are cleared to “0” by setting the FMR01 bit to “0”.
Figure 17.4
FMR0 and FMR1 Registers
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17. FLASH MEMORY VERSION
EW0 mode operation procedure
Rewrite control program
Single-chip mode, or boot mode
Set CM0, CM1, and PM1 registers (Note 1)
Transfer a rewrite control program to any area other
than the flash memory (Note 5)
Jump to the rewrite control program which has been
transferred to any area other than the flash memory
(The subsequent processing is executed by the
rewrite control program in any area other than the
flash memory)
For only boot mode
set the FMR05 bit to “1” (user ROM area access)
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled) (Note 2)
Execute software commands
Execute the Read Array command (Note 3)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
For only boot mode
Write “0” to the FMR05 bit (Boot ROM area
accessed) (Note 4)
Jump to a specified address in the flash memory
Note 1: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1 register’s CM17 to 6
bits. Also, set the PM1 register’s PM17 bit to “1” (with wait state).
Note 2: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no interrupts or no DMA
transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory. Also write only when the NMI pin is
“H” level.
Note 3: Disables the CPU rewrite mode after executing the Read Array command.
Note 4: User ROM area is accessed when the FMR05 bit is set to “1”.
Note 5: When in CPU rewrite mode, bit 0 and bit 3 in the PM1 register are set to “1”. The rewrite control
program can only be executed in the internal RAM or in an external area that is enabled for use when the
PM13 bit = 1.
Figure 17.5
Setting and Resetting of EW0 Mode
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17. FLASH MEMORY VERSION
EW1 mode operation procedure
Program in ROM
Single-chip mode (Note 1)
Set CM0, CM1, and PM1 registers (Note 2)
Set the FMR01 bit by writing “0” and then “1” (CPU
rewrite mode enabled)
Set the FMR11 bit by writing “0” and then “1” (EW1
mode) (Note 3)
Execute software commands
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Note 1: In EW1 mode, do not set the microcomputer in boot mode.
Note 2: Select 10 MHz or less for CPU clock using the CM0 register’s CM06 bit and CM1
register’s CM17 to 6 bits. Also, set the PM1 register’s PM17 bit to “1” (with wait
state).
Note 3: To set the FMR01 bit to “1”, write “0” and then “1” in succession. Make sure no
interrupts or no DMA transfers will occur before writing “1” after writing “0”.
Write to the FMR01 bit from a program in other than the flash memory. Also write
only when the NMI pin is “H” level.
Figure 17.6
Setting and Resetting of EW1 Mode
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17. FLASH MEMORY VERSION
Low power dissipation
mode program
Transfer a low power dissipation mode program
to any area other the flash memory
Jump to the low power dissipation mode program
which has been transferred to any area other the
flash memory.
(The subsequent processing is executed by a
program in any area other than the flash memory.)
Set the FMR01 bit by writing “0” and then “1”
(CPU rewrite mode enabled)
Set FMSTP bit to “1”
(flash memory stopped. Low power state)(Note 1)
Switch the clock source for CPU clock.
Turn main clock off. (Note 2)
Process of low power dissipation mode
Turn main clock on wait until oscillation stabilizes
switch the clock source for CPU clock (Note 2)
Set the FMSTP bit to “0” (flash memory operation)
Write “0” to the FMR01 bit
(CPU rewrite mode disabled)
Wait until the flash memory circuit stabilizes (tps)
(Note 3)
Jump to a specified address in the flash memory
Note 1: Set the FMSTP bit to 1 after setting the FMR01 bit to “1”.
Note 2: Before the clock source for CPU clock can be changed to
main clock or sub clock, the clock to which to be changed
must be stable.
Note 3: Insert a tps wait time in a program. The flash memory
cannot be accessed during this wait time.
Figure 17.7
Processing Before and After Low Power Dissipation Mode
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17.5.3
17. FLASH MEMORY VERSION
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.
(1) Operation Speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for BCLK using the
CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register. Also, set the PM17 bit in
the PM1 register to “1” (with wait state).
(2) Instructions to Prevent from Using
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is
referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction.
(3) Interrupts
EW0 Mode
•Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
•The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are
initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines
should be set in the fixed vector table.
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
•The address match interrupt cannot be used because the flash memory’s internal data is referenced.
EW1 Mode
•Make sure that any interrupt which has a vector in the variable vector table or address match interrupt
will not be accepted during the auto program or auto erase period.
•Avoid using watchdog timer interrupts.
•The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when this
interrupt occurs. The jump address for the interrupt service routine should be set in the fixed vector
table.
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be
executed again after exiting the interrupt service routine.
(4) How to Access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary to
ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only when
NMI pin is “H” level.
(5) Writing in the User ROM Space
EW0 Mode
•If the power supply voltage drops while rewriting any block in which the rewrite control program is
stored, a problem may occur that the rewrite control program is not correctly rewritten and,
consequently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial
I/O or parallel I/O mode should be used.
EW1 Mode
•Avoid rewriting any block in which the rewrite control program is stored.
(6) DMA Transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 registerÅfs FMR00 bit = 0
(during the auto program or auto erase period).
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17. FLASH MEMORY VERSION
(7) Writing Command and Data
Write the command code and data at even addresses.
(8) Wait Mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the
WAIT instruction.
(9) Stop Mode
When shifting to stop mode, the following settings are required:
•Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the
CM10 bit to “1” (stop mode).
•Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop
mode)
Example program
BSET
JMP.B
0, CM1
L1
; Stop mode
L1:
Program after returning from stop mode
(10) Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
•Program
•Block erase
•Lock bit program
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17.5.4
17. FLASH MEMORY VERSION
Software Commands
Software commands are described below. The command code and data must be read and written in 16-bit units,
to and from even addresses in the user ROM area. When writing command code, the 8 high order bits (D1t−D8)
are ignored.
Table 17.4
Software Commands
First bus cycle
Command
Second bus cycle
Mode
Address
Data
(D0 to D15)
Read array
Write
X
xxFF16
X
xx7016
Mode
Address
Data
(D0 to D7)
Read
X
SRD
Read status register
Write
Clear status register
Write
X
xx5016
Program
Write
WA
xx4016
Write
WA
WD
Block erase
Write
X
xx2016
Write
BA
xxD016
Lock bit program
Write
BA
xx7716
Write
BA
xxD016
Read lock bit status
Write
X
xx7116
Write
BA
xxD016
SRD: Status register data (D7 to D0)
WA: Write address (Make sure the address value specified in the the first bus cycle is the same even address
as the write address specified in the second bus cycle.)
WD: Write data (16 bits)
BA: Uppermost block address (even address, however)
X: Any even address in the user ROM area
xx: High-order 8 bits of command code (ignored)
Read Array Command (FF16)
This command reads the flash memory.
Writing ‘exxFF16’ in the first bus cycle places the microcomputer in read array mode. Enter the read address in
the next or subsequent bus cycles, and the content of the specified address can be read in 16-bit units.
Because the microcomputer remains in read array mode until another command is written, the contents of
multiple addresses can be read in succession.
Read Status Register Command (7016)
This command reads the status register.
Write ‘exx7016’ in the first bus cycle, and the status register can be read in the second bus cycle. (Refer to
“Status Register.”) When reading the status register too, specify an even address in the user ROM area.
Do not execute this command in EW1 mode.
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Clear Status Register Command
This command clears the status register to “0”.
Write ‘exx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4 to SR5 in
the status register will be cleared to “0”.
Program Command
This command writes data to the flash memory in 1 word (2 byte) units.
Write ‘exx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an auto
program operation (data program and verify) will start. Make sure the address value specified in the first bus
cycle is the same even address as the write address specified in the second bus cycle.
Check the FMR00 bit in the FMR0 register to see if auto programming has finished. The FMR00 bit is “0”
during auto programming and set to “1” when auto programming is completed.
Check the FMR06 bit in the FMR0 register after auto programming has finished, and the result of auto
programming can be known. (Refer to “Full Status Check.”)
Each block can be protected against programming by a lock bit. (Refer to “Data Protect Function.”)
Be careful not to write over the already programmed addresses.
In EW1 mode, do not execute this command on any address at which the rewrite control program is located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto programming starts,
making it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at the same time
auto programming starts, and set back to “1” when auto programming finishes. In this case, the microcomputer
remains in read status register mode until a read command is written next. The result of auto programming can
be known by reading the status register after auto programming has finished.
Start
Write the command code ‘xx4016’
to the write address
Write data to the write address
FMR00=1?
NO
YES
Full status check
Program
completed
Note: Write the command code and data at even number.
Figure 17.8
Program Command
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17. FLASH MEMORY VERSION
Block Erase
Write ‘exx2016’ in the first bus cycle and write ‘exxD016’ to the uppermost address of a block (even address,
however) in the second bus cycle, and an auto erase operation (erase and verify) will start.
Check the FMR0 register’s FMR00 bit to see if auto erasing has finished.
The FMR00 bit is “0” during auto erasing and set to “1” when auto erasing is completed.
Check the FMR0 register’s FMR07 bit after auto erasing has finished, and the result of auto erasing can be
known. (Refer to “Full Status Check.”)
Figure 17.9 shows an example of a block erase flowchart.
Each block can be protected against erasing by a lock bit. (Refer to “Data Protect Function.”) In EW1 mode, do
not execute this command on any address at which the rewrite control program is located.
In EW0 mode, the microcomputer goes to read status register mode at the same time auto erasing starts, making
it possible to read the status register. The status register bit 7 (SR7) is cleared to “0” at the same time auto
erasing starts, and set back to “1” when auto erasing finishes. In this case, the microcomputer remains in read
status register mode until the Read Array or Read Lock Bit Status command is written next.
Start
Write the command code ‘xx2016’
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
Full status check
Block erase completed
Note: Write the command code and data at even number.
Figure 17.9
Block Erase Command
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17. FLASH MEMORY VERSION
Lock Bit Program Command
This command sets the lock bit for a specified block to “0” (locked).
Write ‘exx7716’ in the first bus cycle and write ‘exxD016’ to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that is specified
in the second bus cycle.
Figure 17.10 shows an example of a lock bit program flowchart. The lock bit status (lock bit data) can be read
using the Read Lock Bit Status command.
Check the FMR0 register’s FMR00 bit to see if writing has finished.
For details about the lock bit function, and on how to set the lock bit to “1”, refer to “Data Protect Function.”
Start
Write command code ‘xx7716’ to
the uppermost block address
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
Full status check
Lock bit program completed
Note: Write the command code and data at even number.
Figure 17.10
Lock Bit Program Command
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17. FLASH MEMORY VERSION
Read Lock Bit Status Command
This command reads the lock bit status of a specified block.
Write ‘exx7116’ in the first bus cycle and write ‘exxD016’ to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit status of the specified block is stored in the FMR1 register’s
FMR16 bit. Read the FMR16 bit after the FMR0 register’s FMR00 bit is set to “1” (ready).
Figure 17.11 shows an example of a read lock bit status flowchart.
Start
Write the command code ‘xx7116’
Write ‘xxD016’ to the uppermost
block address
FMR00=1?
NO
YES
FMR16=0?
NO
YES
Locked
Not locked
Note: Write the command code and data at even number.
Figure 17.11
Read Lock Bit Status Command
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17.6
17. FLASH MEMORY VERSION
Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is effective when the FMR02 bit = 0 (lock
bit enabled). The lock bit allows each block to be individually protected (locked) against programming and erasure.
This helps to prevent data from inadvertently written to or erased from the flash memory. The following shows the
relationship between the lock bit and the block status.
• When the lock bit = 0, the block is locked (protected against programming and erasure).
• When the lock bit = 1, the block is not locked (can be programmed or erased).
The lock bit is cleared to “0” (locked) by executing the Lock Bit Program command, and is set to “1” (unlocked) by
erasing the block. The lock bit cannot be set to “1” by a command.
The lock bit status can be read using the Read Lock Bit Status command.
The lock bit function is disabled by setting the FMR02 bit to “1”, with all blocks placed in an unlocked state.
(The lock bit data itself does not change state.) Setting the FMR02 bit to “0” enables the lock bit function (lock bit
data retained).
If the Block Erase command is executed while the FMR02 bit = 1, the target block or all blocks are erased
irrespective of how the lock bit is set. The lock bit for each block is set to “1” after completion of erasure.
For details about the commands, refer to “Software Commands.”
17.7
Status Register
The status register indicates the operating status of the flash memory and whether an erase or programming
operation terminated normally or in error. The status of the status register can be known by reading the FMR0
register’s FMR00, FMR06, and FMR07 bits.
Table 17.5 shows the status register.
In EW0 mode, the status register can be read in the following cases:
(1) When a given even address in the user ROM area is read after writing the Read Status Register command
(2) When a given even address in the user ROM area is read after executing the Program, Block Erase, or Lock
Bit Program command but before executing the Read Array command.
Sequencer Status (SR7 and FMR00 Bits )
The sequence status indicates the operating status of the flash memory. SR7 = 0 (busy) during auto
programming, auto erase, and lock bit write, and is set to “1” (ready) at the same time the operation finishes.
Erase Status (SR5 and FMR07 Bits)
Refer to “Full Status Check.”
Program Status (SR4 and FMR06 Bits)
Refer to “Full Status Check.”
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Table 17.5
Status
register
bit
SR7 (D7)
17. FLASH MEMORY VERSION
Status Register
FMR0
register
bit
FMR00
SR6 (D6)
"0"
"1"
Value
after
reset
Busy
Ready
1
-
-
Contents
Status name
Sequencer status
Reserved
SR5 (D5)
FMR07
Erase status
Terminated normally
Terminated in error
0
SR4 (D4)
FMR06
Program status
Terminated normally
Terminated in error
0
SR3 (D3)
Reserved
-
-
SR2 (D2)
Reserved
-
-
SR1 (D1)
Reserved
-
-
SR0 (D0)
Reserved
-
-
• D0 to D7: Indicates the data bus which is read out when the Read Status Register command is executed.
• The FMR07 bit (SR5) and FMR06 bit (SR4) are cleared to “0” by executing the Clear Status Register command.
• When the FMR07 bit (SR5) or FMR06 bit (SR4) = 1, the Program, Block Erase, and Lock Bit Program commands
are not accepted.
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17.8
17. FLASH MEMORY VERSION
Full Status Check
When an error occurs, the FMR0 register’s FMR06 to FMR07 bits are set to “1”, indicating occurrence of each
specific error. Therefore, execution results can be verified by checking these status bits (full status check). Table
17.6 lists errors and FMR0 register status. Figure 17.12 shows a full status check flowchart and the action to be
taken when each error occurs.
Table 17.6
Errors and FMR0 Register Status
FRM00 register
(status register)
status
Error
FMR07
(SR5)
1
FMR06
(SR4)
1
1
0
Erase error
0
1
Program error
Error occurence condition
Command
• When any command is not written correctly
sequence error • When invalid data was written other than those that can be written in the second bus cycle of the Lock Bit Program or Block
Erase command (i.e., other than ‘xxD016’ or ‘xxFF16’) (Note 1)
• When the Block Erase command was executed on locked blocks
(Note 2)
• When the Block Erase command was executed on unlocked
blocks but the blocks were not automatically erased correctly
• When the Program command was executed on locked blocks
(Note 2)
• When the Program command was executed on unlocked blocks
but the blocks were not automatically programmed correctly.
• When the Lock Bit Program command was executed but not programmed correctly
Note 1: If "xxFF16" is written by the 2nd bus cycle of these commands, it will become lead array mode and
the command code written by the 1st bus cycle will become invalid simultaneously.
Note 2: When FMR02 bit is "1" (lock bit is invalid), an error is not generated on these conditions.
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17. FLASH MEMORY VERSION
Full status check
FMR06 =1
and
FMR07=1?
YES
Command
sequence error
(1) Execute the Clear Status Register command to
clear these status flags to “0”.
(2) Reexecute the command after checking that it is
entered correctly.
NO
FMR07=
0?
NO
Erase error
YES
(1) Execute the Clear Status Register command to
clear the erase status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the FMR0 register’s FMR02 bit to “1”.
(3) Reexecute the Block Erase command.
Note 1: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
FMR06=
0?
NO
Program error
YES
Full status check completed
[During programming]
(1) Execute the Clear Status Register command to
clear the program status flag to “0”.
(2) Execute the Read Lock Bit Status command to see
if the lock bit for the block in error is “0”. If so, set
the FMR0 register’s FMR02 bit to “1”.
(3) Reexecute the Program command.
Note 2: If the error still occurs, the block in error
cannot be used.
Furthermore, if the lock bit = 1 in (2) above,
the block in error cannot be used either.
[During lock bit programming]
(1) Execute the Clear Status Register command to
clear the program status flag to “0”.
(2) Set the FMR0 register’s FMR02 bit to “1”.
(3) Execute the Block Erase command to erase the
block in error.
(4) Reexecute the Lock Bit command.
Note 3: If the error still occurs, the block in error
cannot be used.
Note 4: If FMR06 or FMR07 = 1, any of the Program, Block Erase, Lock Bit Program, or
Read Lock Bit Status command is not accepted. Execute the Clear Status Register
command before executing those commands.
Figure 17.12
Full Status Check and Handling Procedure for Each Error
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17.9
17. FLASH MEMORY VERSION
Standard Serial I/O Mode
In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is mounted onboard by using a serial programmer suitable for M306H7FGFP. For more information about serial programmers,
contact the manufacturer of your serial programmer. For details on how to use, refer to the user’s manual included
with your serial programmer.
Table 17.7 lists pin functions (flash memory standard serial input/output mode). Figures 17.13 show pin
connections for serial input/output mode.
17.9.1
ID Code Check Function
This function determines whether the ID codes sent from the serial programmer and those written in the flash
memory match. (Refer to the description of the functions to inhibit rewriting flash memory version.)
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Table 17.7
Pin Functions (Flash Memory Standard Serial I/O Mode)
Pin
VCC1, VCC2, VSS
17. FLASH MEMORY VERSION
Name
Description
I/O
Input VCC1 to VCC1 pin. Input 4.75 to 5.25V to VCC2 pin. Input condition
is VCC1 ≤ VCC2.
Power input
CNVSS
CNVSS
I
Connect to VCC2 pin.
RESET
Reset input
I
Reset input pin. While RESET pin is "L" level, input a 20 cycle or
longer clock to XIN pin.
M1
Mode select
I
Connect to VSS pin.
STARTB
Oscillation selection input
I
Connect to VSS pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to X IN pin
and open XOUT pin.
AV CC, AV SS
Analog power supply input
P00 to P07
Input port P0
I
Input "H" or "L" level signal or open.
P10 to P17
Input port P1
I
Input "H" or "L" level signal or open.
Connect AVss to Vss and AVcc to VCC2, respectively
Apply VCC2 to AVcc pin and 0V to AVSS pin..
P20 to P27
Input port P2
I
Input "H" or "L" level signal or open.
P30 to P37
Input port P3
I
Input "H" or "L" level signal or open.
P40 to P47
Input port P4
I
Input "H" or "L" level signal or open.
Input port P5
I
Input "H" or "L" level signal or open.
P50
CE input
I
Input "H" level signal.
P60 to P63
Input port P6
I
Input "H" or "L" level signal or open.
P5
P51 to P57
P64/RTS1
BUSY output
O
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.
P65/CLK1
SCLK input
I
Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".
P66/RXD1
RxD input
I
Serial data input pin
P67/TXD1
TxD output
O
Serial data output pin (Note 1)
P70 to P77
Input port P7
I
Input "H" or "L" level signal or open.
P80 to P84, P86,
P87
Input port P8
I
Input "H" or "L" level signal or open.
P85/NM1
NMI input
I
Connect this pin to VCC2.
I
Input "H" or "L" level signal or open.
P6
P90 to P97
Input port P9
VDD2, Vss2
Power input
Connect VDD2 pin to VCC2 and connect VSS2 pin to VSS.
Apply VCC2 to VDD2 pin and 0V to VSS2 pin.
LP3, LP4
Filter output
O
Open
CVIN1, SYNCIN
Compound video input
I
Input "H" or "L" level signal or open.
VCCOFF
VCC1 faction power supply
input switch
I
Input "L" level signal.
___________
Note 1: When using standard serial input/output mode 1, the TxD pin must be held high while the RESET
pin is pulled low. Therefore, connect this pin to VCC1 via a resistor. Because this pin is directed for
data output after reset, adjust the pull-up resistance value in the system so that data transfers will
not be affected.
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17. FLASH MEMORY VERSION
P4_3
P4_1
P4_2
P3_7
P4_0
P3_5
P3_6
P3_2
P3_3
P3_4
VCC
VCC2
P3_1
VSS
P3_0
P2_7
P2_5
P2_6
P2_3
P2_4
P2_1
P2_2
P1_7/INT5
P2_0
P1_5/INT3
P1_6/INT4
P1_2
P1_3
P1_4
P1_0
P1_1
VSS
M306H7MG-XXXFP/MC-XXXFP/FGFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VCC
VSS
P0_7/AN7
81
50
P4_4
P0_6/AN6
82
49
P4_5
P0_5/AN5
83
48
P4_6
P0_4/AN4
84
47
P4_7
P0_3/AN3
85
46
P0_2/AN2
86
45
P5_1
P0_1/AN1
87
44
P5_2
P0_0/AN0
88
43
P5_3
CVIN
89
42
P5_4
41
P5_5
VDD2
90
VCCOFF
91
VSS2
92
TEST1
M306H7FGFP
P5_0
CE
40
P5_6
39
P5_7/CLKOUT
P6_4/CTS1/RTS1
BUSY
SYNCIN
98
33
P6_5/CLK1
SCLK
AVCC
99
32
P6_6/RXD1/SCL1
P97/ADTRG/SIN4
100
31
P6_7/TXD1/SDA1
Note 1. Connect an oscillation circuit.
Note 2. Figure is a use example for VCC1=VCC2.
The mode setting method
Signal line name
Value
CNVss
Vcc
M1
Vss
RESET
CE
Figure 17.13
Pin Connections for Serial I/O Mode
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P6_0/CTS0/RTS0
P7_0/TXD2/SDA2/TA0OUT (Note 1)
P7_2/CLK2/TA1OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN (Note 1)
P7_4/SDA3/TA2OUT
P7_3/CTS2/RTS2/TA1IN
P7_5/TA3OUT
P7_5/SCL3/TA2IN
P8_1/TA4IN
P7_7/TA3IN
P8_0/TA4OUT
P8_2/INT0
VCC
VSS
VSS
P8_3/INT1
P8_4/RMTOUT/INT2
VCC1
P8_5/NMI
XIN
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VSS
8
XOUT
7
RESET
6
(Note 1)
5
RESET
4
P8_7/XCIN
3
P8_6/XCOUT
2
VCC
1
CNVSS
P6_3/TXD0/SDA0
34
STARTB
35
97
P9_1/TB1IN/SIN3
96
M1
P9_0/TB0IN/CLK3
AVSS
P9_2/TB2IN/SOUT3
P6_2/RXD0/SCL0
P9_3/TB3IN/JSTIN
P6_1/CLK0
36
P9_4/TB4IN/RMTIN
37
95
P9_5/ANEX0/CLK4
38
94
P9_6/ANEX1/SOUT4
93
LP3
LP4
Vss→Vcc
Vcc
RxD
TxD
M306H7MG-XXXFP/MC-XXXFP/FGFP
17.9.2
17. FLASH MEMORY VERSION
Example of Circuit Application in the Standard Serial I/O Mode
Figure 17.14 and 17.15 show example of circuit application in standard serial I/O mode 1 and mode 2,
respectively. Refer to the user's manual for serial writer to handle pins controlled by a serial writer.
Microcomputer
P65/CLK1
SCLK input
P50(CE)
P67/TxD1
TxD input
M1
P64/RTS1
BUSY output
P66/RxD1
RxD output
Reset input
CNVss
RESET
User reset
signal
P85/NMI
STARTB
VCCOFF
(1) Control pins and external circuitry will vary according to programmer.
For more information, see the programmer manual.
(2) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
(3) If in standard serial input/output mode 1 there is a possibility that the user reset
signal will go low during serial input/output mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 17.14
Circuit Application in Standard Serial I/O Mode 1
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17. FLASH MEMORY VERSION
Microcomputer
P65/CLK1
P50(CE)
TxD output
P67/TxD1
M1
Monitor output
P64/RST1
RxD input
P66/RxD1
CNVss
P85/NMI
STARTB
VCCOFF
(1) In this example, modes are switched between single-chip mode and standard serial
input/output mode by controlling the CNVss input with a switch.
Figure 17.15
Circuit Application in Standard Serial I/o Mode 2
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17. FLASH MEMORY VERSION
17.10 Parallel I/O Mode
In parallel input/output mode, the user ROM and boot ROM areas can be rewritten by using a parallel programmer
suitable for M306H7FGFP. For more information about parallel programmers, contact the manufacturer of your
parallel programmer. For details on how to use, refer to the user’s manual included with your parallel programmer.
17.10.1 User ROM and Boot ROM Areas
In the boot ROM area, an erase block operation is applied to only one 4 Kbyte block. The boot ROM area
contains a standard serial input/output mode based rewrite control program which was written in it when
shipped from the factory. Therefore, when using a serial programmer, be careful not to rewrite the boot ROM
area.
When in parallel output mode, the boot ROM area is located at addresses 0FF00016 to 0FFFFF16. When
rewriting the boot ROM area, make sure that only this address range is rewritten. (Do not access other than the
addresses 0FF00016 to 0FFFFF16.)
17.10.2 ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten. (Refer to the
description of the functions to inhibit rewriting flash memory version.)
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18. PACKAGE OUTLINE
18. Package Outline
JEITA Package Code
RENESAS Code
Previous Code
MASS[Typ.]
P-QFP100-14x20-0.65
PRQP0100JB-A
100P6S-A
1.6g
HD
*1
D
80
51
81
50
HE
*2
E
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
ZE
Reference
Symbol
100
31
Dimension in Millimeters
Min
Nom
Max
D
19.8
20.0
20.2
E
13.8
14.0
14.2
2.8
A2
30
Index mark
ZD
c
F
A2
1
HD
22.5
22.8
23.1
HE
16.5
16.8
17.1
A1
0
0.1
0.2
bp
0.25
0.3
0.4
c
0.13
0.15
0.2
e
0.5
A1
A
A
L
*3
e
y
3.05
0°
bp
Detail F
10°
0.65
y
0.575
ZD
ZE
L
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0.8
0.10
0.825
0.4
0.6
0.8
M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19. USEGE NOTES
19.1
Precautions for Power Control
(1) When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock or sub clock
oscillation is stabilized.
(2) Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit of
CM1 register to “1”. When shifting to wait mode or stop mode, an instruction queue reads ahead to the next
instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit to “1” (all
clocks stopped). The next instruction may be executed before entering wait mode or stop mode, depending
on a combination of instruction and an execution timing.
(3) Wait until the main clock oscillation stabilization time, before switching the clock source for CPU clock to
the main clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the
sub clock.
(4) Suggestions to reduce power consumption
• Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current
flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait
mode or stop mode, set non-used ports to input and stabilize the potential.
• A/D converter
When A/D conversion is not performed, set the VCUT bit of ADiCON1 register to “0” (no V REF
connection). When A/D conversion is performed, start the A/D conversion at least 1 ƒÊs or longer after
setting the VCUT bit to “1” (VREF connection).
• Stopping peripheral functions
Use the CM0 register CM02 bit to stop the unnecessary peripheral functions during wait mode. However,
because the peripheral function clock (fC32) generated from the sub-clock does not stop, this measure is not
conducive to reducing the power consumption of the chip. If low speed mode or low power dissipation
mode is to be changed to wait mode, set the CM02 bit to “0” (do not peripheral function clock stopped
when in wait mode), before changing wait mode.
• Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
• External clock
When using an external clock input for the CPU clock, set the CM0 register CM05 bit to “1” (stop). Setting
the CM05 bit to “1” disables the XOUT pin from functioning, which helps to reduce the amount of current
drawn in the chip. (When using an external clock input, note that the clock remains fed into the chip
regardless of how the CM05 bit is set.)
19.2
Precautions for Protect
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0” (write
protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2
bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set
to “1” and the next instruction.
19.3
Precautions for Interrupts
19.3.1
Reading address 0000016
Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU reads
interrupt information (interrupt number and interrupt request priority level) from the address 0000016 during the
interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an unexpected
interrupt request is generated.
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19.3.2
19. USAGE NOTES
Setting the SP
Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is cleared to ‘000016’ after
reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the program may go
out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first and
only the first instruction after reset, all interrupts including NMI interrupt are disabled.
19.3.3
The NMI Interrupt
(1) The NMI interrupt cannot be disabled. If this interrupt is unused, connect the NMI pin to VCC via a
resistor (pull-up).
(2) The input level of the NMI pin can be read by accessing the P8 register’s P8_5 bit. Note that the P8_5
bit can only be read when determining the pin level in NMI interrupt routine.
(3) Stop mode cannot be entered into while input on the NMI pin is low. This is because while input on the
NMI pin is low the CM1 register’s CM10 bit is fixed to “0”.
(4) Do not go to wait mode while input on the NMI pin is low. This is because when input on the NMI pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip
does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
(5) The low and high level durations of the input signal to the NMI pin must each be 2 CPU clock cycles +
300 ns or more.
19.3.4
Changing the Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed interrupt
may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor for an
interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not requested).
“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity or
timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to clear the
IR bit for that interrupt to “0” (interrupt not requested) after making such changes.
Refer to the description of each peripheral function for details about the interrupts from peripheral
functions.
Figure 19.1 shows the procedure for changing the interrupt generate factor.
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19. USAGE NOTES
Changing the interrupt source
Disable interrupts (Note 2, Note 3)
Change the interrupt generate factor (including a mode change of peripheral function)
Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (Note 3)
Enable interrupts (Note 2, Note 3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to
be changed
Note 1: The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
Note 2: Use the I flag for the INTi interrupt (i = 0 to 5).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable interrupts
can all be disabled without causing a problem, use the I flag. Otherwise, use the corresponding
ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is to be changed.
Note 3: Refer to Section “Rewrite the Interrupt Control Register” for details about the
instructions to use and the notes to be taken for instruction execution.
Figure 19.1
19.3.5
Procedure for Changing the Interrupt Generate Factor
INT Interrupt
(1) Either an “L” level of at least tW(INL) or an “H” level of at least tW(INH) width is necessary for the
signal input to pins INT0 through INT5 regardless of the CPU operation clock.
(2) If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are
changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0
(interrupt not requested) after changing any of those register bits.
19.3.6
Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with
the instruction to be used.
• Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified occurs,
the IR bit in the register may not be set to “1” (interrupt requested), with the result that the interrupt request
is ignored. If such a situation presents a problem, use the instructions shown below to modify the register.
Usable instructions: AND, OR, BCLR, BSET
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19. USAGE NOTES
• Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not requested).
Therefore, be sure to use the MOV instruction to clear the IR bit.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue buffer.
Example 1: Using the NOP instruction to keep the program waiting until the interrupt control
register is modified
INT_SWITCH1:
FCLR
I
AND.B #00h, 0055h
NOP ;
NOP
FSET
I
; Disable interrupts.
; Set the TA0IC register to “0016”.
; Enable interrupts.
The number of NOP instruction is as follows.
PM20=1(1 wait) : 2, PM20=0(2 wait) : 3, when using HOLD function : 4.
Example 2: Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR
I
AND.B #00h, 0055h
MOV.W MEM, R0
FSET
I
; Disable interrupts.
; Set the TA0IC register to “0016”.
; Dummy read.
; Enable interrupts.
Example3: Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
AND.B #00h, 0055h
POPC
FLG
; Disable interrupts.
; Set the TA0IC register to “0016”.
; Enable interrupts.
• Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt occurs.
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19.4
19. USAGE NOTES
Precautions for DMAC
19.4.1
Write to DMAE Bit in DMiCON Register
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously (*1).
Step 2: Make sure that the DMAi is in an initial state (*2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
Notes
*1 The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set
to “0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should
be written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
*2 Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a
value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state.
(If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register 1.) If the
read value is a value in the middle of transfer, the DMAi is not in an initial state.
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19.5
19. USAGE NOTES
Precautions for Timers
Precautions for Timer A
19.5.1
Timer A
(1) Timer A (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to
4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops) regardless
whether after reset or not.
(2) While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, if the counter is read at the same time it is reloaded, the value “FFFF16” is read.
Also, if the counter is read before it starts counting after a value is set in the TAi register while not
counting, the set value is read.
19.5.2
Timer A (Event Counter Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to
4) register, the TAi register, the UDF register, the ONSF register TAZIE, TA0TGL and TA0TGH bits and
the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the UDF register, the ONSF register TAZIE, TA0TGL and
TA0TGH bits and the TRGSR register are modified while the TAiS bit remains “0” (count stops)
regardless whether after reset or not.
(2) While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, “FFFF16” can be read in underflow, while reloading, and “000016” in overflow.
When setting TAi register to a value during a counter stop, the setting value can be read before a counter
starts counting.
19.5.3
Timer A (One-shot Timer Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to
4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before
setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
(2) When setting TAiS bit to “0” (count stop), the followings occur:
•A counter stops counting and a content of reload register is reloaded.
•TAiOUT pin outputs “L”.
•After one cycle of the CPU clock, the IR bit of TAiIC register is set to “1” (interrupt request).
(3) Output in one-shot timer mode synchronizes with a count source internally generated. When an external
trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger input to
TAiIN pin and output in one-shot timer mode.
(4) The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
•Select one-shot timer mode after reset.
•Change an operation mode from timer mode to one-shot timer mode.
•Change an operation mode from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have been
made.
(5) When a trigger occurs, while counting, a counter reloads the reload register to continue counting after
generating a re-trigger and counting down once. To generate a trigger while counting, generate a second
trigger between occurring the previous trigger and operating longer than one cycle of a timer count source.
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19.5.4
19. USAGE NOTES
Timer A (Pulse Width Modulation Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to
4) register, the TAi register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR register before
setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the ONSF register TA0TGL and TA0TGH bits and the TRGSR
register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
(2) The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
•Select the PWM mode after reset.
•Change an operation mode from timer mode to PWM mode.
•Change an operation mode from event counter mode to PWM mode.
To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above listed
changes have been made.
(3) When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:
•Stop counting.
•When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
•When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.
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19. USAGE NOTES
Precautions for Timer B
19.5.5
Timer B (Timer Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i =
0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”
(count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
(2) A value of a counter, while counting, can be read in TBi register at any time. “FFFF16” is read while
reloading. Setting value is read between setting values in TBi register at count stop and starting a
counter.
19.5.6
Timer B (Event Counter Mode)
(1) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i =
0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”
(count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not.
(2) The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this
register is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi
register is read after setting a value in it while not counting but before the counter starts counting, the
read value is the one that has been set in the register.
19.5.7
Timer B (Pulse Period/pulse Width Measurement Mode)
(1) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register
before setting the TBiS bit in the TABSR or the TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)
regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register while
the TBiS bit = “1” (count starts), be sure to write the same value as previously written to the TM0D0,
TM0D1, MR0, MR1, TCK0 and TCK1 bits and a 0 to the MR2 bit.
(2) The IR bit of TBiIC register (i=0 to 5) goes to “1” (interrupt request), when an effective edge of a
measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined
by use of the MR3 bit of TBiMR register within the interrupt routine.
(3) If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input
and a timer overflow occur at the same time, use another timer to count the number of times timer B has
overflowed.
(4) To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
(5) Use the IR bit of TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
(6) When a count is started and the first effective edge is input, an indeterminate value is transferred to the
reload register. At this time, timer Bi interrupt request is not generated.
(7) A value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and timer Bi
interrupt request may be generated between a count start and an effective edge input.
(8) For pulse width measurement, pulse widths are successively measured. Use program to check whether
the measurement result is an “H” level width or an “L” level width.
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19.6
19. USAGE NOTES
Precautions for Serial I/O (Clock-synchronous Serial I/O)
19.6.1
Transmission/reception
With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L”
when the data-receivable status becomes ready, which informs the transmission side that the reception has
become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the RTSi pin is
connected to the CTSi pin on the transmission side, the circuit can transmission and reception data with
consistent timing. With the internal clock, the RTS function has no effect.
19.6.2
Transmission
When an external clock is selected, the conditions must be met while if the UiC0 register’s CKPOL bit = “0”
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register’s CKPOL bit = “1” (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
• The TE bit of UiC1 register= “1” (transmission enabled)
• The TI bit of UiC1 register = “0” (data present in UiTB register)
• If CTS function is selected, input on the CTSi pin = “L”
19.6.3
Reception
(1) In operating the clock-synchronous serial I/O, operating a transmitter generates a shift clock. Fix
settings for transmission even when using the device only for reception. Dummy data is output to the
outside from the TxDi pin when receiving data.
(2) When an internal clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 (transmission enabled)
and write dummy data to the UiTB register, and the shift clock will thereby be generated.
When an external clock is selected, set the UiC1 register (i = 0 to 2)’s TE bit to 1 and write dummy data
to the UiTB register, and the shift clock will be generated when the external clock is fed to the CLKi
input pin.
(3) When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the UiC1 register (i = 0 to 2)’s RE bit = “1” (data present in the UiRB register), an
overrun error occurs and the UiRB register OER bit is set to “1” (overrun error occurred). In this case,
because the content of the UiRB register is indeterminate, a corrective measure must be taken by
programs on the transmit and receive sides so that the valid data before the overrun error occurred will
be retransmitted. Note that when an overrun error occurred, the SiRIC register IR bit does not change
state.
(4) To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
(5) When an external clock is selected, the conditions must be met while if the CKPOL bit = “0”, the
external clock is in the high state; if the CKPOL bit = “1”, the external clock is in the low state.
•. The RE bit of UiC1 register= “1” (reception enabled)
•. The TE bit of UiC1 register= “1” (transmission enabled)
•. The TI bit of UiC1 register= “0” (data present in the UiTB register)
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19.7
19. USAGE NOTES
Precautions for Serial I/O (UART Mode)
19.7.1
Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2C1 register U2IRS bit to “1” (transmission complete)
and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be sure to clear the IR
bit to “0” (no interrupt request) after setting these bits.
19.8
Precautions for A/D Converter
(1) Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a
trigger occurs).
(2) When the VCUT bit of ADCON1 register is changed from “0” (Vref not connected) to “1” (Vref
connected), start A/D conversion after passing 1 µs or longer.
(3) To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert
capacitors between the AVCC and analog input pins (ANi (i=0 to 7)) each and the AVSS pin. Similarly,
insert a capacitor between the VCC pin and the VSS pin. Figure 19.2 is an example connection of each pin.
(4) Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode).
Also, if the ADCON0 register’s TGR bit = 1 (external trigger), make sure the port direction bit for the
ADTRG pin is set to “0” (input mode).
(5) The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency
to 250kHZ or more. With the sample and hold function, limit the φAD frequency to 1MHZ or more.
(6) When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits of ADCON0
register and the SCAN1 to SCAN0 bits of ADCON1 register.
(7) If the CPU reads the ADi register (i = 0 to 7) at the same time the conversion result is stored in the ADi
register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
• When operating in one-shot or single-sweep mode
Check to see that A/D conversion is completed before reading the target ADi register. (Check the ADIC
register’s IR bit to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
(8) If A/D conversion is forcibly terminated while in progress by setting the ADCON0 register’s ADST bit to
“0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of
ADi registers irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all ADi registers.
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19. USAGE NOTES
Microcomputer
VCC1
VCC2
VCC1 (16pin) AVCC
C4
VSS
C2
AVSS
VCC2
C3
VCC2 (62pin)
C5
ANi
VSS
ANi: ANi (i=0 to 7)
Note 1: C1≥0.47µF, C2≥0.47µF, C3≥100pF, C4≥0.1µF, C5≥0.1µF (reference)
Note 2: Use thick and shortest possible wiring to connect capacitors.
Figure 19.2
Use of capacitors to reduce noise
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19.9
19. USAGE NOTES
Precautions for Programmable I/O Ports
(1) Setting the SM32 bit in the S3C register to “1” causes the P92 pin to go to a high-impedance state.
Similarly, setting the SM42 bit in the S4C register to “1” causes the P96 pin to go to a high-impedance
state.
(2) The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the input
level at this pin is outside the range of recommended operating conditions VIH and VIL (neither “high” nor
“low”), the input level may be determined differently depending on which side−the programmable input/
output port or the peripheral function−is currently selected.
19.10 Electric Characteristic Differences Between Mask ROM and Flash Memory
Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin,
noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
When switching to the mask ROM version, conduct equivalent tests as system evaluation tests conducted in the
flush memory version.
19.11 Precautions for Flash Memory Version
19.11.1 Precautions for Functions to Inhibit Rewriting Flash Memory Rewrite
ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and
0FFFFB16. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard
serial I/O mode.
The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash memory
cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H) of
fixed vectors.
19.11.2 Precautions for Stop mode
When shifting to stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable DMA transfers before setting the CM10
bit to “1” (stop mode).
• Execute the JMP.B instruction subsequent to the instruction which sets the CM10 bit to “1” (stop mode)
Example program
BSET
0, CM
1 ; Stop mode
JMP.B
L1
L1:
Program after returning from stop mode
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19. USAGE NOTES
19.11.3 Precautions for Wait mode
When shifting to wait mode, set the FMR01 bit to “0” (CPU rewrite mode diabled) before executing the WAIT
instruction.
19.11.4 Precautions for Low power dissipation mode
If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.
• Program
• Block erase
• Lock bit program
19.11.5 Writing command and data
Write the command code and data at even addresses.
19.11.6 Precautions for Program Command
Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an auto
program operation (data program and verify) will start. Make sure the address value specified in the first bus
cycle is the same even address as the write address specified in the second bus cycle.
19.11.7 Precautions for Lock Bit Program Command
Write ‘xx7716’ in the first bus cycle and write ‘xxD016’ to the uppermost address of a block (even address,
however) in the second bus cycle, and the lock bit for the specified block is cleared to “0”.
Make sure the address value specified in the first bus cycle is the same uppermost block address that is specified
in the second bus cycle.
19.11.8 Operation speed
Before entering CPU rewrite mode (EW0 or EW1 mode), select 10 MHz or less for CPU clock using the CM0
register’s CM06 bit and CM1 register’s CM17−6 bits. Also, set the PM1 register’s PM17 bit to 1 (with wait
state).
19.11.9 Instructions inhibited against use
The following instructions cannot be used in EW0 mode because the flash memory’s internal data is referenced:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
19.11.10 Interrupts
EW0 Mode
• Any interrupt which has a vector in the variable vector table can be used providing that its vector is
transferred into the RAM area.
• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 register are
initialized when one of those interrupts occurs. The jump addresses for those interrupt service routines
should be set in the fixed vector table.
Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite
program must be executed again after exiting the interrupt service routine.
• The address match interrupt cannot be used because the flash memory’s internal data is referenced.
EW1 Mode
• Make sure that any interrupt which has a vector in the variable vector table or address match interrupt will
not be accepted during the auto program or auto erase period.
• Avoid using watchdog timer interrupts.
• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when this
interrupt occurs. The jump address for the interrupt service routine should be set in the fixed vector table.
Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be executed
again after exiting the interrupt service routine.
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19. USAGE NOTES
19.11.11 How to access
To set the FMR01, FMR02, or FMR11 bit to “1”, write “0” and then “1” in succession. This is necessary to
ensure that no interrupts or DMA transfers will occur before writing “1” after writing “0”. Also only when NMI
pin is “H” level.
19.11.12 Writing in the user ROM area
EW0 Mode
• If the power supply voltage drops while rewriting any block in which the rewrite control program is stored,
a problem may occur that the rewrite control program is not correctly rewritten and, consequently, the flash
memory becomes unable to be rewritten thereafter. In this case, standard serial I/O or parallel I/O mode
should be used.
EW1 Mode
• Avoid rewriting any block in which the rewrite control program is stored.
19.11.13 DMA transfer
In EW1 mode, make sure that no DMA transfers will occur while the FMR0 register’s FMR00 bit = 0
(during the auto program or auto erase period).
19.11.14 Regarding Programming/Erasure Times and Execution Time
As the number of programming/erasure times increases, so does the execution time for software commands
(Program, Block Erase, and Lock Bit Program). Especially when the number of programming/erasure times
exceeds 100, the software command execution time is noticeably extended.
Therefore, the software command wait time that is set must be greater than the maximum rated value of
electrical characteristics.
The software commands are aborted by hardware reset 1, NMI interrupt, and watchdog timer interrupt. If a
software command is aborted by such reset or interrupt, the block that was in process must be erased before
reexecuting the aborted command.
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M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.12 Other Notes
19.12.1 When the power is being turned on or off
Start VCC1, VCC2, VDD2 and AVCC simultaneously.
While this device is operating, set these pins to the same electric potential.
Also, turn off VCC1, VCC2, VDD2 and AVCC simultaneously when the power supply is being turned off.
When using VCC1 < VCC2, ensure voltage of VCC1 will not exceed voltage of VCC2 while the power is being
turned on or off.
Execute in the following procedure when VCC1 is turned off (VCC2 voltage is supplied).
19.12.2 Procedure of VCC1 OFF(Note 1)
(1) Disable an interrupt which uses pins related to VCC1.
(2) Stop peripheral functions related to VCC1 (Note 2).
(3) Set pins related to VCC1 to input mode.
(4) VCCOFF pin is switched from “L” to “H” .
(5) Turn off VCC1.
19.12.3 Procedure of VCC1 ON
(1) Turn on VCC1.
(2) VCCOFF pin (91-pin) is switched from “H” to “L” .
(3) Set pins VCC1, Peripheral function and Interrupt.
Note 1: Refer to the following “Additions” for details of procedures (1) to (4).
Note 2: Only when the input from pins related to VCC1 is used. Refer to the following “Additions” for details.
<Additions>
(1) Disable an affected interrupt by pins related to VCC1.
Disable an affected interrupt by pins related to VCC1 by setting the interrupt priority level selection and the
interrupt request bits in the the following interrupt control register to “0”.
In the transitional state when changing the power supply voltage including being turned on or off, ensure
each voltage of VCC1, VDD2, and VDD3 will not exceed voltage of VCC2.
TA0IC to TA4IC (timer A interrupt control register)
INT0 to INT2IC (external interrupt control register)
S0RIC to S2RIC (UART receive interrupt control register)
Even if other interrupts are disabled without any problem in software, clear the I flag and it is also possible to
execute the above interrupt disable process after the procedure (4).
(2) Stop peripheral functions related to VCC1
Stop the function when pins related to VCC1 input affect.
When pins related to VCC1 input affect as follows:
•When operating in timer A (TA0 to TA4) and the event count mode
•When the gate input function is used in the event count mode, the one-shot timer, and PWM mode.
(When the MR2 bit in the timer A mode registers TA0MR to TA4MR are set to “1”)
•When UART to UART2 reception are set
Set the following in these cases.
•Timer A
Set the timer count start flags of timers A0 to A4 (TA0S to TA4S bits in the TABSR register) to “0”.
•UART reception
Set the RE and TE bits in the U0C1 to U2C1 registers to “0”.
Rev.2.10
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REJ03B0152-0210
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M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.12.4 Precautions when sub clock starts
When a signal “H” is applied to the STARTB pin and a reset is deserted, a sub clock divided-by-8 becomes a
CPU clock.
When using in this condition, set the CM07 bit in the CM0 register to “1” and switch the CPU clock to sub
clock (no division).
19.12.5 Power supply noise and latch-up
In order to avoid power supply noise and latch-up, connect a bypass capacitor (more than 0.1µF) directly
between the VCC pin and VSS pin, VDD2 pin and VSS2 pin, AVCC pin and AVSS pin using a heavy wire.
And, connect VSS (GND) to the TEST1 pin (93 pin) via the capacitor (more than 0.1µF).
19.12.6 When oscillation circuit stop for data slicer
Expansion register XTAL_VCO, PDC_VCO_ON,VPS_VCO_ON is set at “L”, when the data slicer is not
used, and the oscillation is stopped. When starting oscillation again, set data at the folowing order.
(a) Set expansion register XTAL_VCO = “H.”
(b) Set expansion register PDC_VCO_ON, VPS_VCO_ON = “H.”
(c) 60 ms or more is a waiting state (stability period of internal oscillation circuit + data slice prepara tion).
* To operate slice RAM, set expansion register XTAL_VCO = “H.”
Access the memories after wating for 20 ms certainly when resuming synchronous oscillation from the off
state.
19.12.7 When operation start from stand-by mode (clock is stopped)
Set up an extended register as follows in standby mode.
(a) Set extended register XTAL_VCO, PDC_VCO_ON, and VPS_VCO_ON as “L.”
When you return to an oscillation state from a clock oscillation stop, set up as the notes of the oscillation circuit
stop for data slicers.
19.12.8 Notes concerning address 3616 expansion registers and address 3E16
data setting
Please do not change data after setting initial data to the corresponding addresses 3616 and 3E16 interrupt
control bits when you use the interrupt of the expansion feature (SLICEON, remote control, HINT, clock timer,
and remote control transmission interrupt).
Rev.2.10
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REJ03B0152-0210
Page 324 of 326
M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.12.9 Notes on operating with a low supply voltage (VCC = 2.0 V to 5.5 V, f(XCIN)
= 32 kHz)
When in single-chip mode, this product can operate with a low supply voltage only during low power
dissipation mode. Before operating with a low supply voltage, always be sure to set the relevant register bits to
select low power dissipation mode (BCLK : f(XCIN), main clock XIN : stop, subclock XCIN : oscillating). Then
reduce the power supply voltage VCC to 3.0 V.
Also, when returning to normal operation, raise the power supply voltage to 5.0V while in low power
consumption mode before entering normal operation mode.
When moving from any operation mode to another, make sure a state transition occurs according to the state
transition diagram (Figure 4.9) in Section 4.4, “Power control.”
The status of the power supply voltage VCC during operation mode transition is shown in Figure 19.3 below.
5V
VCC
3V
Power control
operation modes
Normal operation mode
Low power dissipation mode
Normal operation mode
Note 1: Normal operation mode refers to the high-speed, medium-speed, and low-speed modes.
Note 2: When operating with a low supply voltage (2.6 V or more), be aware that only the CPU, ROM,
RAM, input/output ports, timers (timers A and B), clock timer, and the interrupt control circuit
can be used.
All other internal resources (e.g., data slicer, DMAC and A/D ) cannot be used.
Note 3: When operating with a low supply voltage (less than 2.6 V), be aware that only the CPU, RAM, Input/Output
ports, clock timer, and interrupt control circuit can be used.
Figure 19.3
Status of the power supply voltage VCC during operation mode transition
19.13 Serial I/O (RxDi input setup time)
For the RXDi input setup time, refer to the rated values shown below, as well as Electrical Characteristics Table
16.23, “Serial I/O.”
Table 19.1
Serial I/O (VCC=5V)
Symbol
tsu(D-C)
Parameter
RxDi input setup time
Note: Refer to “Table 16.23. Serial I/O of the Electrical Characteristics.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 325 of 326
Standard
Min.
Max.
70
Unit
ns
M306H7MG-XXXFP/MC-XXXFP/FGFP
19. USAGE NOTES
19.14 Precautions for LP3 and LP4 pins
Cannect capacitors to LP3 and LP4 as shown in Figure 19.4.
LP4
2.0KΩ
47pF
0.1µF
LP3
M306H7MG-XXXFP/
MC-XXXFP/FGFP
2.0KΩ
47pF
0.1µF
Figure 19.4
Use of capacitors to reduce noise
Notes on pins CVIN, SYNCIN, and SVREF
Please connect pins CVIN, SYNCIN, and SVREF with GND when you do not use the data slicer.
Rev.2.10
Oct 25, 2006
REJ03B0152-0210
Page 326 of 326
REVISION HISTORY
M306H7MG-XXXFP/MC-XXXFP/FGFP Datasheet
Description
Rev.
Date
1.00
Sep 02, 2005
323
1.01
Sep 15, 2005
9
1.02
Oct 27, 2005
162
I2C0 Interrupt Control Register and Reserved Register are added.
2.00
Mar 31, 2006
162
Reserved Register is changed.
211
Figure of 13. Address 0C16, 1316, 1A16 is changed.
212
Figure of 15. Address 1C16 is changed.
215
Figure of 21. Address 2216 is changed.
216
Figure of 22. Address 2316 is changed.
217
Figure of 23. Address 2416 is changed.
218
Figure of 25. Address 2616 is changed.
220
Figure of 27. Address 2816 is changed.
223
Figure of 32. Address 2D16 is changed.
225
Figure of 35. Address 3016 is changed. Figure of 36. Address 3116 is
changed.
226
Figure of 39. Address 3416 is changed.
227
Figure of 40. Address 3516 is changed.
Page
Summary
First Edition issued
DESCRIPTION Table 1.5 Pin Description (3)
The polarity of STARTB was opposite --> it corrected.
232 to
Figure of 47. Assress 3C16 to 50. Assress 3F16 are changed.
234
241
F.14.14 is changed.
244 to
14.6 (6) Remote control transmission function is added.
246
2.10
Oct 25, 2006
277
Notes of T.17.2 are changed.
281
Note 2 of T.17.3 is changed.
285
Note 5 of T.17.5 is changed.
300
T.17.7 is changed.
301
F.17.13 is changed.
19
Table of register address is changed.
23
F.3.4 is changed.
36
T.4.2 is changed.
38
T.4.4 is changed.
47
T.6.2 is changed.
53
F.6.6 is changed.
56
F.6.9 is changed.
57
L9 to L10 are added.
64
Notes of F.8.2 is changed.
65
Notes of F.8.3 is changed.
143
T.11.1 is changed.
162
Figure of I2C0 Interrupt Control Register is changed.
166
Notes of F.12.3 is changed.
A-1
REVISION HISTORY
Rev.
Date
2.10
Oct 25, 2006
M306H7MG-XXXFP/MC-XXXFP/FGFP Datasheet
Description
Page
Summary
182
F.14.1 is changed.
200
T.14.4 is changed.
211
Figure of 13. Address 0C16, 1316, 1A16, is changed.
218
Figure of 25. Address 2616 is changed.
226
Figure of 38. Address 3316 is changed.
228
Figure of 41. Address 3616 is changed.
233
Figure of 49. Address 3E16 is changed.
253
F.15.1 is changed.
260
F.15.9 is changed.
262
Note of F.15.11 is delated.
267
T.16.8 is changed.
293
T.17.4 is changed.
303
T.17.7 is changed.
304
F.17.13 is changed.
305
F.17.14 is changed.
306
F.17.15 is changed.
324
19.12.8 Notes concerning address 3616 expansion registers and address
3E16 is added.
A-2
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