YMF807

YMF807
APL-3
Automobile PLayer-3
■ General Description
YMF807 is a synthesizer LSI designed with in-car use, which is for playing back high-quality operational sounds, alarm
sounds, etc. The synthesizer block includes Yamaha-original FM synthesizer and ADPCM decoder. The FM synthesizer
allows for high-quality sound creation by parameter designation with only several tens of bytes, and the ADPCM
decoder allows for a playback of voice guidance etc.
The built-in hardware sequencers allow up to four kinds of sound contents to be played back simultaneously without
giving heavy load to a host CPU. Even in the middle of a playback, its playback time and volume can be controlled by
using simple commands; therefore, it is possible to vary an alarm sound etc. in accordance with degree of risk in real
time.
In addition, a speaker amplifier with 520mW output supports direct connection of a speaker. This allows an in-car sound
system to be configured with a few components.
YMF807 Catalog
CATALOG No.: LSI-4MF807A42
2009.6
YMF807
■ Features
z
z
CPU Interface
▼
Clock-synchronized Serial Interface (SPI-compliant interface)
▼
Data Communication at up to 20MHz
Synthesizer Function
▼
FM synthesizer capable of generating up to 16 tones simultaneously, and Monaural Hybrid Synthesizer of
ADPCM Decoder
z
¾
Supports 8bitPCM / 4bitADPCM stream playback
¾
FM synthesizer supports 16-tone simultaneous playback
Sequencer Function
▼
4 sequencers: each of them plays back one sound content.
▼
1kbyte buffer for each sequencer
¾
For FM contents, basically its data size is within 1kbyte, and this allows it to be downloaded into the
buffer whole for playback.
¾
For sound contents beyond 1kbyte, it is played back while HostCPU is supplying data into the buffer by
the interrupt processing.
▼
Asynchronous overlapping playback with 4 types of sound contents
▼
Simultaneous playback / Loop playback / Stop controls of multiple sequencers
▼
Individual volume and playback time setting for each sequencer (sound contents)
Example: simultaneous playback of hazard sound, reverse sound, sonar sound, and operational sound
z
Sound Contents
▼
z
z
2
2 types: melody contents and voice contents
¾
Melody Contents : Sound Contents of FM synthesizer
¾
Voice Contents
: Sound Contents of 8bitPCM / 4bitADPCM
▼
Yamaha authoring tool realizes its creation. Hardware format for APL-3
▼
No data size limitation. Download playback of data less than 1kbyte
Audio Output
▼
16-bit monaural D/A converter
▼
Monaural Line Output
▼
Monaural Speaker Output (Built-in speaker amplifier: Max. 520mW, RL=8Ω)
Device Specification
▼
Package
: Lead-free 48-pin SQFP (Exposed stage)
▼
Supply Voltage
: 5V /3.3V single power supply (5V to 3.3V Step-down DC converter is included.)
▼
Operating Ambient Temperature: -40℃ to +105℃
YMF807
VSS
VSS
DDCFLG
VDDIO
SWO
VSS
VDDCORE
SPOUT2
SPOUT1
VSS
VSS
VSS
36
35
34
33
32
31
30
29
28
27
26
25
Pin Configuration
VSS
37
24
VSS
VSS
38
23
VSS
DVSS
39
22
SPVSS
VDSEL
40
21
SPVDD
/TST1
41
20
EQ3
/SS
42
19
EQ2
SCK
43
18
EQ1
SI
44
17
LINEOUT
SMODE
45
16
VREF
DVSS
46
15
AVSS
VSS
47
14
DVSS
VSS
48
13
VSS
1
2
3
4
5
6
7
8
9
10
11
12
VSS
VSS
VSS
TSTOUT
SO
/IRQ
XO
XI
/RST
/TST0
DVSS
VSS
YMF807
< 48-pin SQFP TOP VIEW >
3
YMF807
Pin Function List
No.
Pin Name
I/O
Power
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VSS
VSS
VSS
TSTOUT
SO
/IRQ
XO
XI
/RST
/TST0
DVSS
VSS
VSS
DVSS
AVSS
－
－
－
O
OT
O
O
I
Ish
I
－
－
－
－
－
－
－
－
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
－
－
－
－
－
16
VREF
A
VDDCORE
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
LINEOUT
EQ1
EQ2
EQ3
SPVDD
SPVSS
VSS
VSS
VSS
VSS
VSS
SPOUT1
SPOUT2
VDDCORE
VSS
SWO
VDDIO
DDCFLG
VSS
VSS
VSS
VSS
DVSS
VDSEL
/TST1
/SS
SCK
SI
SMODE
DVSS
VSS
VSS
A
A
A
A
－
－
－
－
－
－
－
A
A
－
－
A
－
O
－
－
－
－
－
I
I
I
I
I
I
－
－
－
VDDCORE
VDDCORE
VDDCORE
VDDCORE
－
－
－
－
－
－
－
SPVDD
SPVDD
－
－
－
－
VDDIO
－
－
－
－
－
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
－
－
－
I
O
OT
Ish
A
Function
Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Test Output. This pin should be NC (No Connection).
CPU Interface Serial Data Output
Interrupt Output
Clock Output Pin
Clock Input Pin
Hardware Reset Input
Test Input. This pin should be connected to VDDIO.
Digital Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Digital Ground, Heat Sink
Analog Ground, Heat Sink
Analog Reference Voltage
Connect a capacitor of 0.1μF between this pin and AVSS.
LINEOUT output pin
Equalizer pin 1
Equalizer pin 2
Equalizer pin 3
Supply Voltage for a speaker
Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Speaker Output Pin 1
Speaekr Output Pin 2
Regulator Sense Input and Supply Voltage (3.3V) for internal core
Regulator Ground
Regulator Switching Output
Supply Voltage (Typ. +5.0V or +3.3V)
Overcurrent Detection Flag Output Pin
Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
Digital Ground, Heat Sink
Supply Voltage Selection Input (L: 5V, H: 3.3V)
Test Input. This pin should be connected to VDDIO.
CPU Interface Chip Select
CPU Interface Serial Transfer Clock Input
CPU Interface Serial Data Input
CPU Interface Mode Selection
Digital Ground, Heat Sink
Ground, Heat Sink
Ground, Heat Sink
: Digital Input Pin
: Digital Output Pin
: Tri-state Output Pin
: Schmitt Input Pin
: Analog Pin
(Caution)
VSS, DVSS, AVSS, and SPVSS pins are interconnected in a device and used also as a heat sink.
Therefore, connect them on the same ground plane.
4
YMF807
Block Diagram
5
YMF807
● CPU Interface
SPI (Serial Peripheral Interface) is used as CPU interface.
The following four lines are expected to be connected to an external CPU: Chip Select (/SS), Serial
Clock (SCK), Data Input (SI), and Data Output (SO).
This is a block that controls writing and reading data according to input data from SI pin.
● I/F Register
This is the register that can be directly accessed by an external CPU.
“Control Register” described in the next paragraph is accessed through this register.
There are many registers that control various functions in it.
● Control Register
This is the register that is accessed via a sequencer.
There are registers that mainly control synthesizer block located in the latter stage in it.
Basic waveform data for FM are stored in a ROM.
● Delayed FIFO
FIFO is an abbreviation of First In First Out, which is a memory from which data can be read in the
same order of data written.
There are four FIFOs and each of them can be read through the I/F register.
This FIFO is used in the “Delayed Write Path”, which is for accessing Control Register after time
management in a sequencer. The size of an FIFO is 1024 bytes.
● Sequencer
This is the block that interprets data written into the delayed write path.
There are four sequencers and each of them supports four delayed FIFOs.
The structure of data written into the delayed write path is “Time information data + Register setting
data”. A sequencer interprets time information data to count time and makes the setting of registers after
the time elapsed.
Generally, “Music data” is written into the delayed write path.
This sequencer has a role on playing back music by interpreting music data and controlling synthesizer
block.
● Synthesizer Block
This block includes a synthesizer that is capable of simultaneous sound generation up to 16 tones in FM
and up to four tones in PCM/ADPCM.
FM synthesizer has “four operation modes in 16 tones”.
To create more complicated voices is possible because any waveforms for FM calculation can be set.
This synthesizer supports 8-bit PCM or 4-bit ADPCM data format, and this allows for stream playback.
The sampling frequency is 48 kHz.
● DAC Block
This block converts digital signals from the synthesizer block into analog signals. Its data length is 16
bits.
● Line Out Output Block
A monaural analog output is prepared for Line Out.
● EQ Amplifier Block
Adjusting registers and capacitors connected as external components allows filter characteristics and
Gain to be changed.
6
YMF807
● Speaker Amplifier Block
A speaker amplifier with max. 520mW output at SPVDD=3.3V is included.
There is a volume that controls its output level at the former stage of the amplifier.
● Clock Generation Block
A clock ranging from 2 to 27MHz should be input.
This is a block that generates clocks required for operation in LSI.
7
YMF807
■ Electrical Characteristics
Absolute Maximum Ratings
Parameter
VDDIO pin Supply Voltage
VDDIO pin Current Limit
VDDCORE pin Supply Voltage
SPVDD Supply Voltage
Analog Input Voltage
Digital Input Voltage
Power dissipation (*1)
Speaker Load Resistance
Storage Temperature
Symbol
VDDIO
VDDIOA
VDDCORE
SPVDD
VINA
VIND
Pd
RLSP
TSTG
Min.
-0.3
-0.3
-0.3
-0.3
-0.3
6.4
-50
Max.
Unit
6.0
V
4
A
4.6
V
4.6
V
VDDCORE+0.3 V
VDDIO+0.3
V
2645
mW
Ω
125
℃
Condition: VSS = 0V
(*1) Take this value as a reference because it is calculated by simulation based on a certain environment condition.
Top= 25℃, and when mounted on a glass epoxy PCB(114.3 mm×76.2 mm×1.6 mm) with the exposed bottom pad
not soldered.
When operating above Top= 25℃, the value decreases 26.5 mW per 1 ℃.
(Ref.) The table below shows the maximum power dissipation calculated by a simulation based on the following
conditions: bottom pad soldering (Soldered/Not Soldered), board wiring density, and operating ambient
temperature (Top).
Bottom Pad Wiring Density PKG Thermal Resistance Max. Power Dissipation
Soldering
Top=25℃ Top=105℃
Not Soldered
Soldered
Not Soldered
Soldered
150%
150%
200%
200%
2645mW
4545mW
2793mW
4926mW
37.8℃/W
22.0℃/W
35.8℃/W
20.3℃/W
529mW
909mW
558mW
985mW
Recommended Operating Conditions
Parameter
VDDIO operating voltage
VDDCORE operating voltage
SPVDD operating voltage
Operating ambient temperature
Conditions
VDSEL=0V
VDSEL=VDDIO
Symbol
VDDIO
VDDCORE
SPVDD
TOP
Min.
Typ.
Max.
Unit
4.75
3.0
3.0
3.0
-40
5.0
3.3
3.3
3.3
25
5.25
3.6
3.6
3.6
105
V
V
V
V
℃
Condition: VSS = 0V
(Caution)
VDSEL=0V:
Connect SWO pin to VDDCORE and SPVDD pins through an external L and C.
A 5V switching voltage outputting to SWO pin is stepped down to 3.3V through the L and C.
VDSEL=3.3V:
Connect VDDCORE, SPVDD, and VDDIO pins to a 3.3V power supply.
SWO pin should remain open.
8
YMF807
Consumption Current
● VDSEL=0V
Parameter
Conditions
Typ.
At normal operation (*) / No sound generation
VDDIO
At normal operation (*)/ SPOUT: at 8Ω load, 300mW
consumption current output
At power-down state
(*): VDDIO=5.00V, Top=25℃, Input Pins: VIL=VSS, VIH=VDDIO
● VDSEL=VDDCORE
Parameter
Conditions
Max.
Unit
20
mA
154
mA
1.4
2.0
mA
Typ.
Max.
Unit
At normal operation (*) / No sound generation
19
VDDIO+VDDCORE+
At normal operation (*)/ SPOUT: at 8Ω load, 300mW
195
SPVDD
output
consumption current
At power-down state
10
(*): VDDIO=VDDCORE=SPVDD=3.30V, Top=25℃, Input Pins: VIL=VSS, VIH=VDDIO
mA
mA
27
μA
Max.
Unit
DC Characteristics
Parameter
Input voltage “H” level ①
Input voltage “L” level ①
Input voltage “H” level ②
Input voltage “L” level ②
Output voltage “H” level
Output voltage “L” level
Schmitt Width
Input Leakage Current
Input Capacitance
Symbol
VIH
VIL
VIH
VIL
VOH
VOL
Vsh
IL
CI
Conditions
Min.
Typ.
(*1)
0.7 × VDDIO
(*1)
(*2)
0.7 × VDDIO
(*2)
(*3) IOH = -1mA 0.8 × VDDIO
(*3) IOL = +1mA
0.2 × VDDIO
0.2 × VDDIO
0.4
0.5
-1
1
10
V
V
V
V
V
V
V
μA
pF
Conditions: Top= -40 to 105℃, VDDIO=3.0 to 3.6V or 4.75 to 5.25V, Capacitor load=50pF
(*1) Target pins: /SS，SCK, SI, SMODE, /RST, VDSEL, /TST0, /TST1
(*2) Target pins: XI
(*3) Target pins: SO, /IRQ
9
YMF807
AC Characteristics
/RST, XI, and other input signals
Parameter
/RST “L” Pulse Width
/RST (undefined → “L”) Setup Time
Supply voltage Start-up Delay
XI frequency
XI rise and fall time
XI duty
Input signals other than XI rise and fall time
Symbol
Min.
TRSTW
TRSTS
TVSKW
1 / Tfreq
Trckc, Tfckc
Th / Tfreq
Tr, Tf
100
0
Typ.
2
30
50
Max.
Unit
1
27
30
70
20
μs
ms
ms
MHz
ns
%
ns
Conditions: Top=-40 to 105℃, VDDIO=4.75 to 5.50[V], Capacitor load=50pF
The measurement points are at VIH= 0.7×VDDIO, VIL=0.3×VDDIO, VOH=0.8×VDDIO, and VOL=0.2×VDDIO.
● VDSEL=0V
● VDSEL=VDDCORE
The width of a reset signal is defined from the time when VDDCORE rose up to the level of 70%.
/RST input must be already settled at “L” level when VDDIO rises up to the level of 30%.
10
YMF807
CPU Interface
Parameter
SCK Period
SCK “L” Pulse Width (*1)
SCK “H” Pulse Width (*1)
SCK Rise Time
SCK Fall Time
/SS “H” Pulse Width (*2)
/SS Rise Time
/SS Fall Time
SI Rise Time
SI Fall Time
/SS Setup Time
/SS Hold Time
SI Setup Time
SI Hold Time
SO Output Delay 1 (SMODE= “0”)
SO Output Delay 2 (SMODE= “0”)
SO Output Delay 3 (SMODE= “0”)
SO Output Delay 4 (SMODE= “1”)
SO Output Delay 5 (SMODE= “1”)
SO Output Delay 6 (SMODE= “1”)
Symbol
Min.
Tsck_period
Tsck_low
Tsck_high
Tsck_rise
Tsck_fall
Tssn_high
Tssn_rize
Tssn_fall
Tsi_rize
Tsi_fall
Tssn_setup
Tssn_hold
Tsi_setup
Tsi_hold
Tso_delay1
Tso_delay2
Tso_delay3
Tso_delay4
Tso_delay5
Tso_delay6
50
24
24
Typ.
Max.
5
5
650 / 50
5
5
5
5
15
5
15
5
12
21
12
12
21
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Conditions: TOP=-40 to 105℃, VDDIO=4.75 to 5.25[V], or VDDCORE=3.0 to 3.6[V], Capacitor load=50pF
IOH=-2.0mA, IOL=+2.0mA (S0 pin)
The measurement points are at VIH= 0.7×VDDIO, VIL=0.2×VDDIO, VOH=0.8×VDDIO, and
VOL=0.2×VDDIO
(*1) Tsck_low + Tsck_high should be more than Tsck_period(min.).
(*2) To read data from the control register by using IF Register (BANK1/#11 and #12), a pulse width of /SS (“H”)
between #11 access and #12 access is 650ns (min.). In other cases, it becomes 50ns (min.).
11
YMF807
12
YMF807
Analog Characteristics
Conditions: TOP=25℃, VDDCORE=3.3V, and VDDIO=5.0V
○ SP Amplifier
Parameter
Min.
Gain Setting (fixed)
Speaker Load Resistance (RL)
Maximum Output Voltage Amplitude (RL=8Ω)
Maximum Output Power (RL=8Ω, THD+N ≤ 1.0%)
THD + N (RL=8Ω, f=1kHz, 400mW output)
Noise in no signal condition (A-filter: weighting filter)
PSRR (f=1kHz)
Amplitude Center Voltage
Differential Output Voltage
Maximum Load Capacitance applicable to SPOUT1 and
SPOUT2 pins (*)
Typ.
±2
8
5.7
520
0.025
-90
90
0.5×SPVDD
10
Max.
Unit
50
1000
times
Ω
Vp-p
mW
%
dBV
dB
V
mV
pF
(*): This means a capacitance up to 1000pF can be connected to both SPOUT1 pin and SPOUT2 pin.
○ EQ Amplifier
Parameter
Available Gain Setting Range
Maximum Output Voltage Amplitude
THD + N (f=1kHz)
Noise in no signal condition (A-filter)
Input Impedance
Feedback Resistance between EQ2 and EQ3
Min.
Typ.
Max.
Unit
30
dB
Vp-p
%
dBV
MΩ
kΩ
3.0
0.05
-90
10
20
○ SP Volume
Parameter
Volume Setting Range
Volume Step Width
Attenuation Rate at Mute
Min.
Typ.
-30
Max.
Unit
0
dB
dB
dB
Max.
Unit
0
dB
dB
dB
kΩ
Vp-p
Ω
1
80
○ EQ Volume
Parameter
Volume Setting Range
Volume Step Width
Attenuation Rate at Mute
Minimum Load Resistance
Maximum Output Voltage Amplitude
Output Impedance
Min.
Typ.
-30
1
80
20
1.65
300
600
13
YMF807
○ LINE Volume
Parameter
Volume Setting Range
Volume Step Width
Attenuation Rate at Mute
Minimum Load Resistance
Maximum Output Voltage Amplitude
Output Impedance
Min.
Typ.
-30
Max.
Unit
0
600
dB
dB
dB
kΩ
Vp-p
Ω
Max.
Unit
1
80
20
1.65
300
○ VREF
Parameter
Min.
VREF voltage
Typ.
0.5×VDDCORE
V
○ DAC
Parameter
Resolution
Full-scale Output Voltage
THD+N (f= 1kHz)
Noise in no signal condition (A-filter)
Frequency Characteristics (f=50Hz to 20kHz)
Min.
Typ.
Max.
Unit
0.5
Bit
Vp-p
%
dBV
dB
16
1.65
-90
-3.0 (*)
+0.5
(*) This is because degradation of the high-frequency response due to aperture effect.
Step-down DC-DC Converter
○ Switching Power Supply Capacitor
Parameter
Rated Value
Rated Ripple Current Value
Min.
Typ.
Max.
Unit
15.4
3.0
22
28.6
μF
A
Min.
Typ.
Max.
Unit
0.7
3.0
1.0
1.3
μH
A
○ Switching Power Supply Inductor
Parameter
Rated Value
Rated Current Value
14
YMF807
■External Dimensions
15
YMF807
YMF807
YMF807