1/4 ◇Structure ◇Product name ◇Type ◇Applications ◇Functions Silicon Monolithic integrated circuit Audio interface + Video driver + Back up + RTC LSI BU76292AGUW DSC, etc ＜Audio part＞ ・Monaural・16 bit ΔΣCODEC ・Monaural microphone amplifier with ALC function ・Monaural line amplifier ・BTL output speaker amplifier (300mW@8Ω, THD+N=10%, VDD=3.0V) ・64-step electronic volume with ALC function ・PLL built-in（Reference clock：12MHz、24MHz、27MHz、16fs、32fs、64fs） (sampling rate：8kHz ～ 48kHz) (Master clock output) ・Four-line serial interface （power on reset function） ・Audio IF format MSB First, 2’s compliment 2 ＜ＡＤＣ＞ 16bit word lengths Left justified, I S 2 ＜DAC＞ 16bit word lengths Left, Right justified, I S ＜Video part＞ ・Sync-tip-clamp, LPF, 6dB Amplifier ・Output coupling condenser unnecessary ＜Back up part＞ ・LDO：1ch、Voltage detect circuit：2ch built-in ＜RTC part＞ ・32bit counter built-in ・64bit back up register built-in ◇Absolute maximum ratings （Ｔａ＝２５℃） Parameter Symbol Limits Unit Comment Supply voltage VDD -0.3～4.5 Ｖ AVDD、SPVDD、VVDD、DVDD LVDD Supply voltage LVDD -0.3～2.5 V LVDD UNREG Supply voltage BATT Supply voltage Input voltage VCC BATT VIN -0.3～7.0 -0.3～4.5 -0.3～supply voltage+0.3 V V Ｖ Storage temperature range Operating temperature range Power dissipation ＊１ TSTG TOPE PD -50～125 -20～85 800 ℃ ℃ ｍＷ UNREG BATT keep each limits upon ＊1：In the case of use at Ta=25℃ or more, 8mW should be reduced per 1℃. Radiation resistance design is not arranged. ◇Operating conditions （Ｔａ＝２５℃） Parameter Supply voltage LVDD Supply voltage UNREG Supply voltage BATT Supply voltage Symbol VDD LVDD VCC BATT Limits 2.7～3.3 1.62～1.98 2.65～5.5 2.0～3.3 Unit Ｖ V V V Comment AVDD、SPVDD、VVDD、DVDD LVDD UNREG BATT （note） AVDD、DVDD、SPVDD、are not needed to be same voltage. （note） Please do not set SPVDD lower than AVDD-0.3V. （note） Please do not surpass package permissible loss, when SPVDD is set. REV. B 2/4 ◇Electrical characteristics ○Audio interface + Video driver （Unless specified, Ta=25℃、AVDD=SPVDD=DVDD=VVDD= 3.0V、LVDD= 1.8V、BATT=3.1V、UNREG=4.5V B.W.=22Hz～22kHz、fs=48kHz、fin=1kHz、OSCIN=32.768kHz） Parameter Symbol MIN. Limits TYP. MAX. Unit < Current consumption > # MASTER=0 Power-down mode IDDS - 0.02 0.1 ｍＡ PDB=L Rec mode/PLL mode IDDR - 5.8 16 ｍＡ Play mode/PLL mode IDDP - 5.3 16 ｍＡ #PWAP=MDREC=MDPLL=1, MCLK=24MHz #PWAP=MDPB=MDSP=MDPLL=1, MCLK=24MHz #PWAP=PWVD=1,MDPLL=0 Video mode IDDV 8.2 18 <ＭＲＥＧ> Output voltage VOREG 0.75AVDD-0.2 0.75AVDD 0.75AVDD+0.2 <REC path （MICIN→ADOUT）> #ALC1=OFF, MGAIN=48dB Input impedance ZIN 70 100 130 Input level VIN -53 -51 -49 Distortion THD+N 43 58 ＳＮＲ SNR 59 65 ＡＬＣ１ output level DOALC -7.0 <PB path1 （DAIN→LINEOUT）> #LGAIN=+5dB Output level VO -6.5 -5.0 -3.5 Distortion THD+N 70 80 ＳＮＲ SNR 81 89 <PB path2 （DAIN→EVROUT→SPIN→SPOUT BTL 出力）> #ALC2=OFF, EVR=-6dB, RL=8Ω Output level VO 0.1 2.1 4.1 Distortion THD+N 50 60 ＳＮＲ SNR 75 82 ＡＬＣ２ output level VOALC 0.1 2.1 4.1 <Video path （VIN→VOUT）> Voltage gain GV +5.0 +6.0 +7.0 Max output level VOM 2.2 2.6 Frequency characteristic 1 GF1 -1.0 0 +0.5 Frequency characteristic 2 GF2 -20 -6 Differential Gain DG 1.0 3.0 Differential Phase DP 1.0 3.0 Y signal output S/N SNY +50 +65 - ｍＡ Ｖ kΩ dBV dB dB dBFS Condition 2.2kΩ負荷時 DOUT=0dBFS DOUT=-6dBFS@1kHz B.W.=JIS-A ALC1=ON dBV dB dB DIN=-6dBFS DIN=-6dBFS@1kHz B.W.=JIS-A dBV dB dB dBV DIN=0dBFS DIN=0dBFS@1kHz B.W.=JIS-A ALC2=ON, EVR=8dB dB Vpp dB dB % deg dB VIN=100KHz, 1.0Vpp f=10KHz, THD=1% f=4.5MHz/100KHz f=18MHz/100KHz VIN=1.0Vp-p、Standard stair step signal VIN=1.0Vp-p、Standard stair step signal Band 100k～6MHz Terminal impedance 150Ω 100% white video signal ○Back up・RTC （Unless specified, Ta=25℃、AVDD=SPVDD=DVDD=VVDD= 3.0V、LVDD= 1.8V、BATT=3.1V、UNREG=4.5V、 B.W.=22Hz～22kHz、fs=48kHz、fin=1kHz、OSCIN = 32.768kHz） Parameter < Current consumption> UNREG Current consumption BATT Current consumption <Regulator> Output voltage Output voltage <Back up SW> Change voltage Hysteresis width <Reset> Detect voltage Hysteresis width <Logic> L input voltage H input voltage L output voltage H output voltage Symbol MIN. Limits TYP. MAX. Icc - 35 80 μＡ Iｒｔｃ - 1.0 2.0 μＡ VREG VREGI 3.000 2.65 3.100 2.75 3.200 - Ｖ V VSW VShys 2.65 40 2.75 100 2.85 160 V ｍV VRST VRhys 2.65 60 2.75 100 2.85 140 V ｍV DVSS 0.7DVDD DVSS 0.8DVDD - 0.3DVDD DVDD 0.2DVDD DVDD V V V V VIL VIH VOL VOH REV. B Unit Condition UNREG=4.5V, AL31= no load AVDD=SPVDD=DVDD=VVDD=LVDD= 0V BATT=3.1V, Counter start No load UNREG=2.85V, Iout=10mA Iout=1.0mA Iout=-1.0mA 3/4 ◇Register map Address 00H 01H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 13H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 41H 42H 43H 44H 45H 46H 50H 57H Register Power control Power control Gain control Gain control Clock control Clock control Clock control ALC control ALC control ALC control Time control Volume control Filter control Volume control Volume control Volume control Video gain control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control Filter control RTC counter RTC counter RTC counter RTC counter RTC control RTC control Back up register ： Back up register D7 0 0 0 0 FMCK1 0 MASTER 0 ATMC1 RC2MC1 RINI2 0 0 DVOL7 0 0 0 DFMRP DF0M1 DF0A7 0 DF0B7 DF1M1 DF1A7 0 DF1B7 DF2M1 DF2A7 0 DF2B7 DF3M1 DF3A7 0 DF3B7 DF4M1 DF4A7 0 DF4B7 RTC７ RTC15 RTC23 RTC31 0 0 REG7 D6 PWSV COMENB 0 0 FMCK0 FRCK2 BFPD MDALC1 ATMC0 RC2MC0 RINI1 MLIM6 0 DVOL6 0 0 0 OLDFM DF0M0 DF0A6 0 DF0B6 DF1M0 DF1A6 0 DF1B6 DF2M0 DF2A6 0 DF2B6 DF3M0 DF3A6 0 DF3B6 DF4M0 DF4A6 0 DF4B6 RTC6 RTC14 RTC22 RTC30 0 0 REG6 D5 PWAP 0 ADA 0 FBCK1 FRCK1 FSSK MDEVR1 RCMC1 CVRG1 RINI0 MLIM5 0 DVOL5 EVR5 SPVOL1 0 0 DF0A13 DF0A5 DF0B13 DF0B5 DF1A13 DF1A5 DF1B13 DF1B5 DF2A13 DF2A5 DF2B13 DF2B5 DF3A13 DF3A5 DF3B13 DF3B5 DF4A13 DF4A5 DF4B13 DF4B5 RTC5 RTC13 RTC21 RTC29 0 0 REG5 D4 PWMRG 0 0 0 FBCK0 FRCK0 DLEN MDEVR0 RCMC0 CVRG0 PINI1 MLIM4 0 DVOL4 EVR4 SPVOL0 0 DFMEN4 DF0A12 DF0A4 DF0B12 DF0B4 DF1A12 DF1A4 DF1B12 DF1B4 DF2A12 DF2A4 DF2B12 DF2B4 DF3A12 DF3A4 DF3B12 DF3B4 DF4A12 DF4A4 DF4B12 DF4B4 RTC4 RTC12 RTC20 RTC28 0 0 REG4 D3 PWVD MDSP 0 MUSP DIFGS SFS1 FMCO3 0 ATSP1 RCLM PINI0 MLIM3 HPFR3 DVOL3 EVR3 0 0 DFMEN3 DF0A11 DF0A3 DF0B11 DF0B3 DF1A11 DF1A3 DF1B11 DF1B3 DF2A11 DF2A3 DF2B11 DF2B3 DF3A11 DF3A3 DF3B11 DF3B3 DF4A11 DF4A3 DF4B11 DF4B3 RTC3 RTC11 RTC19 RTC27 0 0 REG3 D2 0 MDPB LGAIN MUBSP DIF2 SFS0 MCKO 0 ATSP0 0 0 MLIM2 HPFR2 DVOL2 EVR2 BVOL2 0 DFMEN2 DF0A10 DF0A2 DF0B10 DF0B2 DF1A10 DF1A2 DF1B10 DF1B2 DF2A10 DF2A2 DF2B10 DF2B2 DF3A10 DF3A2 DF3B10 DF3B2 DF4A10 DF4A2 DF4B10 DF4B2 RTC2 RTC10 RTC18 RTC26 0 0 REG2 D1 0 MDREC MGAIN1 MULO DIF1 DIV1 0 0 RCSP1 ATTO1 DVLT MLIM1 HPFR1 DVOL1 EVR1 BVOL1 VGAIN DFMEN1 DF0A9 DF0A1 DF0B9 DF0B1 DF1A9 DF1A1 DF1B9 DF1B1 DF2A9 DF2A1 DF2B9 DF2B1 DF3A9 DF3A1 DF3B9 DF3B1 DF4A9 DF4A1 DF4B9 DF4B1 RTC1 RTC9 RTC17 RTC25 0 0 REG1 D0 0 MDPLL MGAIN0 MUDVL DIF0 DIV0 0 MDDVL RCSP0 ATTO0 EVRT MLIM0 HPFR0 DVOL0 EVR0 BVOL0 0 DFMEN0 DF0A8 DF0A0 DF0B8 DF0B0 DF1A8 DF1A0 DF1B8 DF1B0 DF2A8 DF2A0 DF2B8 DF2B0 DF3A8 DF3A0 DF3B8 DF3B0 DF4A8 DF4A0 DF4B8 DF4B0 RTC0 RTC8 RTC16 RTC24 CNTEN ERR REG0 REG63 REG62 REG61 REG60 REG59 REG58 REG57 REG56 （note） Do not write to the address except for the above. ◇Serial interface Control commands are entered on the CSB, SCLK, and SDATA pins, outputted on the SOUT pin, using 4 line 16 bit serial input (MSB first). The input cycle is started on the CSB falling edge, and each bit of data is read in on the SCLK rising edge. The data is loaded to register on the CSB rising edge. CSB SCLK SDATA “x” R/W A6 A5 A4 SOUT A3 A2 A1 A0 “x” D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Register Address : A6 - A0 Control Data R/W : D7 - D0 : READ/WRITE(“1” WRITE, “0” READ) REV. B “x” 4/4 AVSS MICIN MREG VOUT C5 A6 A5 G5 CLAMP SPIN F7 PLL C1 C3 VREF BIAS DET LDO 2.75V EVROUT MCLKO G7 1.8V B4 LINEOUT F6 LPF B6 B5 BIAS G6 MREG A7 ALC1 AVDD F4 LVDD G4 DVSS VVSS F3 DVDD VVDD VIN LNF ◇Block diagram・External dimension A4 EVR VREF C2 UNREG D1 AL31 D2 RESETIN D3 RESETOUT AL31 ADC DAC ALC2 C4 3.1V AL31 RVSS RESET 2.75V BEEP IN A3 Digital Filters BATT G2 OSCIN G1 OSCOUT E1 CKOUT F1 BVSS E5 E7 D7 D6 E6 F5 D5 C7 C6 B7 G3 E3 SCLK CSB TEST1 TEST2 Control SOUT A1 OSC SDATA SPPOS RTC PDB B2 BATT AL31 64Bit Reg. MCLK SPVDD BATT Audio Interface FCLK A2 BCLK SPVSS ADOUT B3 DAIN SPNEG E2 BATT (note) Please the capacitors for VCC、BIAS、LNF、VREF、AL31 pins close to each. Please the capacitors and X’tal for OSCIN, OSCOUT pins close to each. Figure 2 External dimension （Unit：ｍｍ） Figure 1 Block diagram PKG : VBGA048W040 Drawing No：EX873-6001 ◇Caution （１） About absolute maximum rating When the absolute maximum rating such as the applied voltage and the ranges of the operating temperature is exceeded, LSI might be destroyed. Please apply neither voltage nor the temperature that exceeds the absolute maximum rating. Please execute physical measures for safety such as fuse when it is thought to exceed the absolute maximum rating, and examine it so that the condition to exceed the absolute maximum rating is not applied to LSI. （２） About GND Voltage In any state of operation must be the lowest voltage about the voltage of the terminal GND. Please actually confirm the voltage of each terminal is not a voltage that is lower than the terminal GND including excessive phenomenon. （３） About design of overheating malfunction preventive circuit Please design overheating malfunction preventive circuit with an enough margin in consideration of a permissible loss in the state of using actually. （４） About the short between terminals and the mounting by mistake Please note the direction and the gap of position of LSI enough about LSI when you mount on the substrate. LSI might be destroyed when mounting by mistake and energizing. Moreover, LSI might be destroyed when short-circuited by entering of the foreign substances between the terminal and GND, between terminals, between the terminal and the power supply of LSI. （５） About operation in strong electromagnetic field Use in strong electromagnetic field has the possibility of malfunctioning and evaluate it enough, please. （６） Please note not to be beyond the package permissible range, When SPVDD is set. REV. B Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. 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