VC-826 LVPECL, LVDS Crystal Oscillator VC-826 Description Vectron’s VC-826 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off a 2.5 or 3.3 volt power supply in a hermetically sealed 3.2 x 2.5mm ceramic package. Features Applications • Ultra Low Jitter Performance, 3rd OT or Fundamental Crystal Design • 20MHz -170MHz Output Frequencies • Low Power • Excellent Power Supply Rejection Ratio • Enable/Disable • 3.3 or 2.5V operation • -10/70°C or -40/85°C Operation • Hermetically Sealed 3.2x2.5mm Ceramic Package • Product is compliant to RoHS directive and fully compatible with lead free assembly • Ethernet, GbE, Synchronous Ethernet • Fiber Channel • Enterprise Servers • Telecom • Clock source for A/D’s, D/A’s • Driving FPGA’s • Test and Measurement • PON • Medical • COTS Block Diagram Complementary Output Output VDD Voltage Regulator Crystal Oscillator E/D or NC E/D or NC GND Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page1 Performance Specifications Table 1. Electrical Performance, LVPECL Option Parameter Symbol Min Typical Maximum Units Voltage VDD 3.135 2.375 3.3 2.5 3.465 2.625 V V Current2, 3.3V 2.5V IDD 45 42 mA Nominal Frequency fN 170 MHz 1 Frequency 20 Stability (Ordering Option) ±25, ±50 or ±100 3 ppm Outputs Output Logic Levels2 Output Logic High Output Logic Low VOH VOL Output Rise and Fall Time2 tR/tF VDD-1.025 VDD-1.810 Load VDD-0.880 VDD-1.620 V V 500 ps 55 % 50 ohms into VDD-1.3V Duty Cycle 45 4 Phase Noise, 3.3V, 100MHz5 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 20MHz 40MHz Jitter5, 100MHz 12kHz -20MHz фJ -70 -100 -126 -140 -146 -149 -157 -157 dBc/Hz 175 fs Enable/Disable Outputs Enabled Outputs Disabled VIH VIL Disable Time tD 6 0.7*VDD Enable/Disable Leakage Current Start-Up Time tSU Operating Temp. (Ordering Option) TOP Package Size 0.3*VDD V V 200 ns ±200 uA 10 ms -10/70 or -40/85 °C 3.2 x 2.5 x 1.05 mm 1. The VC-826 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor. 2. Figure 1 defines the test circuit and Figure 2 defines these parameters. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Duty Cycle is defined as the On/Time Period. 5. Measured using an Agilent E5052 Signal Source Analyzer. 6. Outputs will be Enabled if Enable/Disable is left open. tR VDD -1.3V NC NC 1 6 2 5 3 4 50 ȍ -1.3V tF VAMP*0.8 Cross Point VAMP VAMP*0.2 On Time 50 ȍ Period Figure 1. Figure 2. Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page2 Performance Specifications Table 2. Electrical Performance, LVDS Option Parameter Symbol Min Typical Maximum Units 3.135 2.375 3.3 2.5 3.465 2.625 V V 17 14 mA Supply Voltage1 VDD Current2, 3.3V 2.5V IDD Frequency Nominal Frequency fN 20 Stability3 (Ordering Option) 170 MHz ±25, ±50 or ±100 ppm Outputs Output Logic Levels Output Logic High Output Logic Low 2 VOH VOL Output Amplitude 0.9 1.43 1.10 1.6 V V 247 350 454 mV 50 mV 1.125 1.25 1.375 V 50 mV Differential Output Error Offset Voltage Offset Voltage Error Output Leakage Current, Outputs Disabled Output Rise and Fall Time3 tR/tF Load 10 uA 500 ps 55 % 100 ohms differential Duty Cycle 45 4 Phase Noise, 3.3V, 100MHz5 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz 20MHz 40MHz Jitter5, 100MHz 12kHz - 20MHz фJ -73 -97 -124 -137 -145 -149 -154 -154 dBc/Hz 300 fs Enable/Disable Outputs Enabled Outputs Disabled VIH VIL Disable Time Enable/Disable Leakage Current 6 0.3*VDD V V tD 200 ns IE/D ±200 uA 10 ms Start-Up Time tSU Operating Temp. (Ordering Option) TOP 0.7*VDD Package Size -10/70 or -40/85 °C 3.2 x 2.5 x 1.05 mm 1. The VC-826 power supply pin should be filtered, eg, a 10uf, 0.1uf and 0.01uf capacitor. 2. Figure 2 defines these parameters and Figure 3 defines the test circuit. 3. Includes calibration tolerance, operating temperature, supply voltage variations, aging and IR reflow. 4. Duty Cycle is defined as the On/Time Period. 5. Measured using an Agilent E5052B Signal Source Analyzer 6. Outputs will be Enabled if Enable/Disable is left open. Out 50 50 0.01 uF DC 6 5 4 1 2 3 Figure 3. Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page3 Out Package Outline Drawing XXXMXX YYWW C Dimensions in mm Marking Information XXXMXX - Frequency (Example: 100M00) YY - Year of Manufacture WW - Week of the Year C - Manufacturing Location - Pin 1 Indicator Recommended Pad Layout Pin Diagram Table 3. Pinout Pin # Symbol Function 1 E/D or NC Enable/Disable or No Connection 2 E/D or NC Enable/Disable or No Connection 3 GND Electrical and Lid Ground 4 fO Output Frequency 5 CfO Complementary Output Frequency 6 VDD Supply Voltage Phase Noise (LV-PECL Output) Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page4 LVPECL Application Diagrams VDD NC NC 1 6 2 5 3 4 0.01uF 0.01uF 0.01uF 140 ȍ 140 ȍ Figure 4. Single Resistor Termination Scheme Resistor values are typically 140 ohms for 3.3V operation and 84 ohms for 2.5V operation. Figure 5. Pull-Up Pull Down Termination Resistor values shown are typical for 3.3 V opertaion. For 2.5V operation, the resistor to ground is 62 ohms and the resistor to supply is 250 ohms The VC-826 incorporates a standard PECL output scheme, which are un-terminated FET drains. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 4, or for best 50 ohm matching a pull-up/pull-down scheme as shown in Figure 5 should be used. AC coupling capacitors are optional, depending on the application and the input logic requirements of the next stage. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. LVDS Application Diagrams LVDS Driver 100ȍ LVDS Receiver Figure 6. LVDS to LVDS Connection, Internal 100ohm Resistor Some LVDS structures have an internal 100 ohm resistor on the input and do not need additional components. AC blocking capacitors can be used if the DC levels are incompatible. LVDS Driver 100ȍ Receiver Figure 7. LVDS to LVDS Connection Some input structures may not have an internal 100 ohm resistor on the input and will need an external 100ohm resistor for impedance matching. Also, the input may have an internal DC bias which may not be compatible with LVDS levels, AC blocking capacitors can be used. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Environmental and IR Compliance Table 4. Environmental Compliance Parameter Condition Mechanical Shock MIL-STD-883 Method 2002 Mechanical Vibration MIL-STD-883 Method 2007 Temperature Cycle MIL-STD-883 Method 1010 Solderability MIL-STD-883 Method 2003 Fine and Gross Leak MIL-STD-883 Method 1014 Resistance to Solvents MIL-STD-202 Method 215 Moisture Sensitivity Level MSL1 Contact Pads Gold (0.3-1.0um) over Nickel Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page5 IR Compliance S Suggested IR Profile Devices are built using lead free epoxy and can be subjected to standard lead free IR reflow conditions shown in Table 5. Contact pads are gold over nickel and lower maximum temperatures can also be used, such as 220C. Table 5. Reflow Profile Parameter Symbol Value PreHeat Time ts 200 sec Max Ramp Up RUP 3°C/sec Max Time above 217°C tL 150 sec Max Time to Peak Temperature tAMB-P 480 sec Max Time at 260°C tP 30 sec Max Time at 240°C tP2 60 sec Max Ramp down RDN 6°C/sec Max Maximum Ratings, Tape & Reel S Absolute Maximum Ratings and Handling Precautions Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Although ESD protection circuitry has been designed into the VC-826, proper precautions should be taken when handling and mounting, VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes. Table 6. Maximum Ratings Parameter Unit Storage Temperature -55 to 125 °C Junction Temperature 150 C Supply Voltage -0.5 to 5.0 V Enable Disable Voltage -0.5 to VDD+0.5 V ESD, Human Body Model 1500 V ESD, Charged Device Model 1500 V Table 7. Tape and Reel Information Tape Dimensions (mm) Reel Dimensions (mm) W F Do Po P1 A B C D N W1 W2 #/Reel 8 3.5 1.5 4 4 178 2 13 21 60 10 14 1000 Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page6 Ordering Information VC-826- E C E - K A A N - xxxMxxxxxx Frequency in MHz Product XO Package 3.2x2.5mm Voltage Options E: +3.3 Vdc ±5% H: +2.5 Vdc ±5% Other (Future Use) N: Standard Enable/Disable Pin A: Pin 1 (Pin 2 = No Connection) B: Pin 2 (Pin 1 = No Connection) Enable/Disable Logic A: Output is Enabled with a Logic High or open, Output is Disabled with a Logic Low Output C: LVPECL D: LVDS Stability F: ±25ppm K: ±50ppm S: ±100ppm Temp Range W: -10/70°C E: -40/85°C Example: VC-826-ECE-KAAN-100M000000 For Additional Information, Please Contact USA: Vectron International 267 Lowell Road Unit 102 Hudson, NH 03051 Tel: 1.888.328.7661 Fax: 1.888.329.8328 Europe: Vectron International Landstrasse, D-74924 Neckarbischofsheim, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30 Asia: VI Shanghai 68 Yin Cheng Road(C), 22nd Floor One LuJiaZui Pudong, Shanghai 200120, China Tel: 86.21.6194.6886 Fax: 86.21.6194.6699 Disclaimer Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Rev: 12/12/2014 VN Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page7 Revision History Revision Date Approved Sep 05, 2014 VN Description VC-826 Product Initial Release. Dec 12, 2014 VN Added min and max values for LVDS output amplitude. Vectron International • 267 Lowell Road, Suite 102, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page8