VC-707 LVPECL, LVDS Crystal Oscillator Data Sheet Previous Vectron Model VCC6 VC-707 Description Vectron’s VC-707 Crystal Oscillator is a quartz stabilized, differential output oscillator, operating off 3.3 volt supply, hermetically sealed 5x7 ceramic package. Features • • • • • • Applications 3.3V Operation Output Frequencies to 800MHz Differential Output Enable/Disable -10/70°C or -40/85°C Operation Hermetically Sealed 5x7 Ceramic Package • • • • • • • • • • Product is compliant to RoHS directive and fully compatible with lead free assembly Storage Area Networking Telecom Ethernet, GE, SynchE Fiber Channel PON Driving A/D’s, D/A’s, FPGA’s Test and Measurement Medical COTS Block Diagram VDD Complementary Output Output Crystal Oscillator E/D or NC PLL E/D or NC Gnd Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page1 Performance Specifications Table 1. Electrical Performance, LVPECL Option Parameter Symbol Min Typical Maximum Units 3.3 3.45 V 100 mA Supply Voltage1 VDD Current (No Load) IDD 3.15 Frequency 2 Nominal Frequency fN 270 Stability2,3 (Ordering Options) 800 MHz ±20, ±25, ±32, ±50, ±100 ppm Outputs 4 V Output Logic Levels , -10/70°C Output Logic High Output Logic Low VOH VOL VDD-1.025 VDD-1.810 VDD-0.880 VDD-1.620 Output Logic Levels4, -40/85°C Output Logic High Output Logic Low VOH VOL VDD-1.085 VDD-1.830 VDD-0.880 VDD-1.555 V Output Rise and Fall Time4 Rise Time Fall Time tR/tF 600 600 Output Load ps ps 50 ohms to VDD-1.3V 5 Duty Cycle 45 Jitter (12 kHz - 20 MHz BW)155.52MHz6 фJ Period Jitter7 RMS P/P фJ 50 55 % 2 ps 4 30 ps ps Enable/Disable 8 Output Enabled Output Disabled VIH VIL 0.7*VDD Enable/Disable Leakage Current Start-Up Time tSU Operating Temp. (Ordering Option) TOP 0.3*VDD V V ±200 uA 10 ms -10/70 or -40/85 °C Package Size 5.0 x 7.0 x 1.8 or 5.08x7.5x2.2 mm 1. The VC-707 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor. 2. See Standard Frequencies and Ordering Information for more information. 3. Includes calibration tolerance, operating temperature, supply voltage variations,, aging and IR reflow. 4. Figure 2 defines these parameters and Figure 1 defines the test circuit. 5. Duty Cycle is defines as the On/Time Period. 6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VC-706 series”. 7. Measured using a LeCroy 8600, 25K samples. 8. Outputs will be Enabled if Enable/Disable is left open. tR VDD -1.3V 1 6 2 5 tF VOH NC 50% VOL NC 3 4 50 On Time 50 -1.3V Figure 1 Period Figure 2 Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page2 Performance Specifications Table 2. Electrical Performance, LVDS Option Parameter Symbol Min Typical Maximum Units 3.3 3.45 V 60 mA Supply Voltage1 VDD Current (No Load) IDD 3.15 Frequency 2 Nominal Frequency fN 260 Stability2,3, (Ordering Options) 800.000 ±20, ±25, ±32, ±50, ±100 MHz ppm Outputs 4 V Output Logic Levels Output Logic High Output Logic Low VOH VOL Differential Output 1.6 0.9 1.40 1.10 247 330 454 mV 50 mV 1.125 1.25 1.375 V 50 mV 10 uA 600 600 ps ps 55 % Differential Output Error Offset Voltage Offset Voltage Error Output Leakage Current Output Load 100 ohms differential Output Rise and Fall Time4 Rise Time Fall Time tR/tF Duty Cycle5 45 6 Jitter (12 kHz - 20 MHz BW)155.52MHz фJ Period Jitter7 RMS P/P фJ Output Enabled8 Output Disabled VIH VIL 50 2 ps 4 30 ps ps Enable/Disable 0.7*VDD 0.3*VDD Enable/Disable Leakage Current Start-Up Time tSU Operating Temp. (Ordering Option) TOP Package Size V V ±200 uA 10 ms -10/70 or -40/85 °C 5.0 x 7.0 x 1.8 or 5.08x7.5x2.2 mm 1. The VC-707 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor. 2. See Standard Frequencies and Ordering Information for more information. 3. Includes calibration tolerance, operating temperature, supply voltage variations,, aging and IR reflow. 4. Figure 2 defines these parameters and Figure 3 defines the test circuit. 5. Duty Cycle is defines as the On/Time Period. 6. Measured using an Agilent E5052, 155.520MHz. Please see “Typical Phase Noise and Jitter Report for the VCC6 series”. 7. Measured using a LeCroy 8600, 25K samples. 8. Outputs will be Enabled if Enable/Disable is left open. Out 50 50 Out 0.01 uF 6 5 4 1 2 3 DC Figure 3 Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page3 Package and Pinout Table 3. Pinout Pin # Symbol Function 1 E/D or NC Enable Disable or No Connection 2 E/D or NC Enable Disable or No Connection 3 GND Electrical and Lid Ground 4 fO Output Frequency 5 CfO Complementary Output Frequency 6 VDD Supply Voltage 6 7.0±0.15 5 4 The Enable/Disable function is set at the factory on either pin 1 or pin 2 and is an ordering option 6 V7-XXX XXXMXX 2 4 V7-XXX Part Number Frequency XXXMXX Date Code 5.0±0.15 YYWW C 1 7.49±0.15 5 5.08±0.15 YYWW C 3 1 2 3 1.6 max 1.397 1 6 2 Bottom View 5 2.16 max 1.27 3 1.397 1 3.57 4 6 2 Bottom View 5 2.54 5.08 1.27 3 3.57 4 2.54 5.08 Figure 4 Package A Outline Drawing Figure 5 Optional Package Outline Drawing The VC-707 can be supplied in one of two package options and Figure 4 shows the primary package used. The pad layout and dimesnions are identical and a reel would include only 1 of the two options 1.96 1.78 3.66 2.54 5.08 Figure 6 Pad Layout Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page4 LVPECL Application Diagrams Figure 7 Standard PECL Output Configuration Figure 8 Single Resistor Termination Scheme Resistor values are typically 120 to 240 ohms for 3.3V operation. Resistor values are typically 82 to 120 ohms for 2.5V operation. Figure 9 Pull-Up Pull Down Termination Resistor values are typically for 3.3V operation For 2.5V operation, the resistor to ground is 62 ohms and the resistor to supply is 240 ohms The VC-707 incorporates a standard PECL output scheme, which are un-terminated emitters as shown in Figure 7. There are numerous application notes on terminating and interfacing PECL logic and the two most common methods are a single resistor to ground, Figure 8, and a pull-up/pull-down scheme as shown in Figure 9. An AC coupling capacitor is optional, depending on the application and the input logic requirements of the next stage. LVDS Application Diagrams VCC LVDS Driver 100 LVDS Driver LVDS Receiver 100 Receiver OUT+ OUT- Figure 11 LVDS to LVDS Connection, Internal 100ohm Some LVDS structures have an internal 100 ohm resistor on the input and do not need additional components. Figure 10 Standard LVDS Output Configuration Figure 12 LVDS to LVDS Connection External 100ohm and AC blocking caps Some input structures may not have an internal 100 ohm resistor on the input and will need an external 100ohm resistor for impedance matching. Also, the input may have an internal DC bias which may not be compatible with LVDS levels, AC blocking capacitors can be used. One of the most important considerations is terminating the Output and Complementary Outputs equally. An unused output should not be left un-terminated, and if it one of the two outputs is left open it will result in excessive jitter on both. PC board layout must take this and 50 ohm impedance matching into account. Load matching and power supply noise are the main contributors to jitter related problems. Environmental and IR Compliance Table 4. Environmental Compliance Parameter Condition Mechanical Shock MIL-STD-883 Method 2002 Mechanical Vibration MIL-STD-883 Method 2007 Temperature Cycle MIL-STD-883 Method 1010 Solderability MIL-STD-883 Method 2003 Fine and Gross Leak MIL-STD-883 Method 1014 Resistance to Solvents MIL-STD-883 Method 2015 Moisture Sensitivity Level MSL1 Contact Pads Gold over Nickel Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page5 S IR Compliance Table 5. Reflow Profile Parameter Symbol Value PreHeat Time ts 200 sec Max Ramp Up RUP 3°C/sec Max Time above 217°C tL 150 sec Max Time to Peak Temperature tAMB-P Time at 260°C tP 10 sec Max Time at 240°C tP2 60 sec Max Ramp down RDN 6°C/sec Max tL 260 Temperature (DegC) Suggested IR Profile Devices are built using lead free epoxy and can be subjected to standard lead free IR reflow conditions shown in Table 5. Contact pads are gold over nickel and lower maximum temperatures can also be used, such as 220C. RUP tP 217 200 RDN 150 tS tAMB-P 480 sec Max Reliability 25 Time (sec) S Maximum Ratings, Tape & Reel Absolute Maximum Ratings and Handling Precautions Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Although ESD protection circuitry has been designed into the VC-707, proper precautions should be taken when handling and mounting, VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes. Table 6. Maximum Ratings Parameter Symbol Rating Unit Storage Temperature TSTORE -55/125 °C Supply Voltage -0.5 to 5.0 V Enable Disable Voltage -0.5 to VDD+0.5 ESD, Human Body Model 1000 V ESD, Charged Device Model 1000 V Table 7. Tape and Reel Information Tape Dimensions (mm) Reel Dimensions (mm) W F Do Po P1 A B C D N W1 W2 #/Reel 16 7.5 1.5 4 8 180 2 13 21 50 17 21 200 Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page6 Table 8. Standard Frequencies (MHz) 311.040 312.000 312.500 320.000 322.2656 332.000 333.000 350.000 400.000 446.000 472.000 500.000 693.4829 693.750 600.000 622.080 625.000 644.5313 657.4219 666.5413 669.3236 669.3265 700.000 779.5686 Ordering Information VC-707- E C E - K A A N - xxxMxxxxxx Frequency in MHz Product XO Package 5x7 Voltage Options E: +3.3 Vdc ±5% Other (Future Use) N: Standard Enable/Disable Pin A: Pin 1 B: Pin 2 Enable/Disable Logic A: Enable High Output C: LVPECL D: LVDS Stability E: ±20ppm F: ±25ppm K: ±50ppm S: ±100ppm Temp Range W: -10/70°C E: -40/85°C *Note: not all combination of options are available. Other specifications may be available upon request. Example: VC-707-ECE-KAAN-622M080000 For Additional Information, Please Contact USA: Europe: Asia: Vectron International 267 Lowell Road Unit 102 Hudson, NH 03051 Tel: 1.888.328.7661 Fax: 1.888.329.8328 Vectron International Landstrasse, D-74924 Neckarbischofsheim, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30 Vectron International 68 Yin Cheng Road (C), 22nd Floor One LuJiaZui Pudong, Shanghai 200120, China Tel: 86.21.6194.6886 Fax: 86.21.6194.6699 Disclaimer Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Rev: 02/12/2014 Vectron International • 267 Lowell Road, Hudson, NH 03051 • Tel: 1-88-VECTRON-1 • http://www.vectron.com Page7