SP6013A Synchronous Rectifier Driver APPLICATION INFORMATION Predictive Timing Operation The essence of SP6013A, the predictive timing circuitry, is based on several U.S. patented technologies. This assures higher rectification efficiency by a) eliminating high cross conduction current under all operating conditions and b) significantly reducing the body diode conduction losses in the synchronous rectifier. time sets the minimum size capacitor needed. Since it is usually desirable to achieve proper operation down to essentially zero duty cycle, the capacitor minimum size can be represented as a function of frequency. VDD Decoupling Capacitor The IC is sensitive to large supply voltage ripple. If the IC drives a MOSFET with significant input capacitance, Ciss, the ripple due to gate drive energy transfer can create large ripple. Therefore, it is most suitable to add a high frequency decoupling ceramic capacitor of 0.1μF~1.0μF between Vdd to ground, and the capacitor should be placed as close proximity to the driver as possible. Cmin=2.66*10^-5/F Ramp Capacitor Selection (Cramp) The ramp capacitor selection is frequency dependent. The capacitance selection should be made in according to the plot below: 140 Frequency (kHz ) 120 100 Cmin = Icharge * dT/dV = Icharge/F/dV; Since Icharge = 80µA & dV=3.8V-0.7V, A capacitor size should be selected to meet the above criteria including the frequency tolerance and the capacitor tolerance over temperature. The criterion for the maximum suitable capacitance is less precise because it is driven by noise constraints. If a larger capacitor is chosen, the ramp voltage becomes lower and there is more jitter on the pulse width due to noise. It is usually advantageous to operate with as high a ramp voltage as possible for this reason. The minimum ramp amplitude occurs at the maximum converter operating duty cycle because this is when the MOSFET is conducting for the shortest period of time. For converters that need to be able to operate to a wider duty cycle, the capacitance should be close to the minimum calculated above to prevent noise problems. 80 60 40 20 0 8 15 20 30 40 50 Cram p (pF) Fig. 1 The ramp capacitor selection is dependant on the range of the On and OFF times of the synchronous rectifier. In most application it is necessary to work to a narrow duty cycle. The ramp capacitor voltage charges from about 0.7 volts during the ON time. The charging current is 80 μA. For proper operation of the internal timing it is necessary to limit the ramp amplitude to 3.8 volts. This voltage limits and the maximum ramp ON 2007/07/20 Ver.3 Fig. 2 Figure 2 illustrates the characteristic waveforms of a flyback converter with input voltage of 110VAC. Page 1 SP6013A Synchronous Rectifier Driver Fig. 3: Application Schematic Channel 1 indicates the SYNC voltage on the secondary side of a flyback transformer at 77 kHz, channel 3 is the SP6013A output pin, MOSG-C, connects to the gate of MOSFET, and channel 4 designates the input current (ID). Notice the timing gap between the falling edge of MOSG-C and the rising edge of SYNC is 3.5μs with no ramp capacitor connected. Figure 3 is the equivalent circuit for this particular application. For typical flyback application with 50 kHz to 120 kHz operations, a ramp capacitor value of 10 pF to 47pF is recommended. This allows the gate ON time to reach 10-12 microseconds for narrow pulse widths. Timing Adjustment The Timing pin provides adjustment of the patented dv/dt filter circuit that differentiates between the real power and ring-back no-power transformer secondary voltage positive waveform. Under light or no load conditions, the output current will be discontinuous. For that condition the transformer voltage “rings” back positive. The SP6013A detects positive transformer secondary voltage to establish power transmission, and determines the SR MOSFET turn ON time. However, it is not desirable to turn on the MOSFET during the “ring-back”. The dv/dt filter detects the true power pulse from the “ring-back”. • Fig. 4 With 33pF added to Cramp pin with respect to ground, the timing gap immediately shortens and the ON time of the gate increased from 8.2μs to 11.6μs, as shown in figure 4. Thus, the efficiency is improved by approximately 0.655%. The output for this converter is set at 5V/8A. 2007/07/20 Ver.3 Connect resistor to VDD. The first option is the nominal setting. For this condition, the Timing pin is left open or no connection. In result, the ON time of MOSG-C should be turned ON at every cycle. If not, the timing needs to be adjusted. Figure 5 illustrates an example of several ON time cycles missing: Page 2 SP6013A Synchronous Rectifier Driver Fig. 5 Fig. 7 The Timing adjustment should be performed under light load circumstance. A variable resistor, 0~100KΩ, is connected from Timing pin to VDD and adjust the variable resistor until the waveform at MOSG-C pin appears in every cycle. If this is unable to achieve, connect the variable resistor to ground and follow the same procedures. But be careful, once the correct resistor value is exceeded, more ON time cycles will appear during oscillation. It is best to eliminate these. Once the variable resistor is adjusted to the correct value, the output waveform of pin MOSG-C should be ON at every cycle as shown in Figure 6. Then measure the resistance of the variable resistor. The typical value is between 10KΩ to 30KΩ. SYNC Voltage The Sync input voltage stands between 5V and 5.5V. It is necessary to use a resistor divider if the Sync voltage is much higher than 5 volts. R4 and R5 function as a voltage divider, in which the voltage from the secondary side of the transformer might reach as high as 40V-60V. The maximum allowable voltage for this pin is 7.5 volts. When the voltage is reached above this limit, the IC may suffer permanent damage. Therefore, it is recommended to insert a 1-5KΩ resistor in between Sync, Pin 1, to ground so the voltage can be lowered. Here is another example of a 3.3V/3.69A output converter with everything adjusted at no load: Fig. 6 Fig. 8 For light load condition, the equivalent waveform with correct resistor value connected to Timing pin is demonstrated in figure 7. The output of MOSG-C pin is turned ON at every cycle. Observe during “ring-back”, the MOSFET remains OFF. The dv/dt filter will differentiate between the true power pulses from the “ring-back” pulses. In this application, the resistor for Timing pin is adjusted at 8.80KΩ to VDD and no Cramp capacitor is needed. The converter is using a green-mode PWM IC at primary side, and figure 8 demonstrates the output, MOSG-C (channel 3), during burst mode (channel 1). 2007/07/20 Ver.3 Page 3 SP6013A Synchronous Rectifier Driver Voltage Regulator ( VR ) For applications with stable operaition voltage , there will be capcaitor between VR and Gnd. In this funtaion , the VDD will be stability to work . Alternate Power Source For applications with single set of transformer output, a way to deliver power to the IC can be derived from the isolated secondary voltage via a voltage regulator KA7812 or 78L12 as shown in figure 3. KA7812 is selected in this application. An input (4.7uF) and output (10uF) capacitor is also required for the voltage regulator. This is an acceptable approach for voltages from 6.5 volts minimum ripple valley voltage to 35 volts maximum peak voltage. The goal is to keep prediction time as short as possible to keep minimum body diode conduction. The Prediction logic uses the previous cycles to control SR operation in the present cycle. The predictive turn OFF time is adjusted by the capacitance on Pred pin. When the actual prediction time is more than that set by the capacitance on Pred pin, the IC reduces the Prediction time in the next cycle. When the actual prediction time is less than that set by the capacitance on Pred pin, the IC increases the prediction time in the next cycle. (Fig.10) MOSG-C Since the output of this IC delivers a square wave of 0~VDD volts at various frequencies, a logic level MOSFET is most applicable for the Synchronous Rectifiers. R3 is recommended at 5Ω and D2 is a small signal Schottky diode, such as BAT54, 1N5817, or 1N5819 or switching diode 1N4148. Predictive timing circuit operation ( Pred ) The IC operates on the principle of “prediction”. For freewheeling (catch) control applications, the prediction time is defined as time interval from the falling edge of Vgs to the rising edge of the synchronizing signal as shown at below. Fig.10 : No Load , SYNC = 300KHZ , Vdd = +12V ( Ch1 - SYNC waveform ; Ch3 - Catch waveform ) Tpre d vs Cpre d 800 ns Tpred 600 ns 400 ns 200 ns ns 0 20 40 60 80 Cpre d (pF) Fig.11 : Tpred vs Cramp ( VDD =12V ; Frequency = 70KHZ ) 2007/07/20 Ver.3 Page 4 SP6013A Synchronous Rectifier Driver Reference Design Board Layout Fig. 12: Topt View Fig. 13: Back View SP6003A / SP6013A Demo Board 2007/07/20 Ver.3 Page 5 SP6013A Synchronous Rectifier Driver Reference Design Board To familiar with SP6013A, the reference design board should be checked by using function generator before connecting to the converter. Do not connect the MOSFET onto the reference board. Force 12 Vdd at “ +12V ” of the board, and the “ S “ which is connected to the SYNC pin of SP6013A. Step 6: Timing adjustment.(VR via) The Timing adjustment should be performed under light load circumstance.A variable resistor “ Rt “ , 0~100KΩ, is connected from Timing pin to VDD and adjust the variable resistor. Changing the resistor value will change dv/dt slope Fig.14. There are a couple of necessary steps when installing the reference design board onto an existing flyback converter: This resistor value normally is from 10Kohm to 30Kohm. The typical relation between resistor value and the Delta T is shown in Fig.15. Delta T vs. Resistor Value Step 3: Place any MOSFET with drain connecting to the output of the transformer and source to the other segment that was split from step 2. It is best if attached directly onto the PCB/converter directly. At this point, the gate should connect to source. Step 4: Try turn on the converter and it should able to generate output, even though it is using the body diode of the MOSFET to conduct. 300 250 Delta T Step 2: Find the ground connection from the output of the transformer and split it to two segments. When doing so, be as close to the transformer’s output as possible , to avoid contacts with any other components. (ns) Step 1: Short out the existing Schottky diode. 200 150 100 50 10 12 14 16 18 20 22 24(Kohm) Fig.15 Once the resistor value is adjusted correctly, the SP6013A gate will be triggered as shown in Fig.16 . Step 5: Remove the MOSFET from step 4 and place the reference design board by attaching the drain and source of the MOSFET from the reference board to the converter. Fig. 16 Step 7: Cramp selection. The size of this capacitor is frequency dependent. The recommended value ranges from 10pF to 100pF. Please refer to page 1 for more details. Fig.14 2007/07/20 Ch 1 : Drain Waveform ; Ch 3 : Output Gate Waveform Ch 4 : Drain Current Ver.3 Page 6 SP6013A Synchronous Rectifier Driver Information provided is alleged to be exact and consistent. SYNC Power Corporation presumes no responsibility for the penalties of use of such information or for any violation of patents or other rights of third parties, which may result from its use. No license is granted by allegation or otherwise under any patent or patent rights of SYNC Power Corporation. Conditions mentioned in this publication are subject to change without notice. This publication surpasses and replaces all information previously supplied. SYNC Power Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of SYNC Power Corporation. ©The SYNC Power logo is a registered trademark of SYNC Power Corporation ©2004 SYNC Power Corporation – Printed in Taiwan – All Rights Reserved SYNC Power Corporation 9F-5, No.3-2, Park Street NanKang District (NKSP), Taipei, Taiwan, 115, R.O.C Phone: 886-2-2655-8178 Fax: 886-2-2655-8468 http://www.syncpower.com 2007/07/20 Ver.3 Page 7